riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,607 Commits 140 Branches 61 Tags 15 GiB
Commit Graph

5 Commits

Author SHA1 Message Date
mo-hosni a11bbc380b Fix absolute paths in the new mag files. 2023-03-05 01:09:20 -08:00
mo-hosni e560b56db5 reharden spare_logic_block. 2023-02-27 10:37:00 -08:00
Tim Edwards e2ee74c591 Changed "simple_por" in both caravel and caravan to be an abstract 
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
 2021-11-27 11:51:30 -05:00
Tim Edwards be98da0fe6 Added spare logic block to caravel layout and verilog GL, wired 
it to the power supply, and checked top-level LVS.
 2021-11-24 16:50:22 -05:00
manarabdelaty 83e150bf25 [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00