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Modified the padframe definition to keep the vccd domain continuous 

around the entire padframe.  The vccd1 and vccd2 domains are local
to their respective pads, and any bus routing must be done inside
the padframe.  This means that all pads operate on global vddio for
3.3V as before, but also global vccd for 1.8V.  The user 1.8V voltage
domain only goes as far as the input to the GPIO control block.
This commit is contained in:
Tim Edwards 2021-11-03 10:53:09 -04:00
parent 1d359690ac
commit fe1fcbc3a5
4 changed files with 135 additions and 19 deletions
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76
verilog/rtl/chip_io.v
View File

@ -188,7 +188,7 @@ module chip_io(
`endif `endif
); );
sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclmap_pad ( sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad (
`MGMT_ABUTMENT_PINS `MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VSSD(vssd) .VSSD(vssd)
@ -218,6 +218,21 @@ module chip_io(
`endif `endif
); );
// VCCD1/VSSD1 must be routed to clamps from outside
sky130_fd_io__top_power_lvc_wpad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS
,.P_PAD(vccd1_pad),
.P_CORE(vccd1),
.SRC_BDY_LVC1(vssd1),
.SRC_BDY_LVC2(vssd1),
.DRN_LVC1(vccd1),
.DRN_LVC2(vccd1),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vccd_lvc_clamped2_pad user1_vccd_lvclamp_pad ( sky130_ef_io__vccd_lvc_clamped2_pad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
@ -226,6 +241,7 @@ module chip_io(
,.VCCD_PAD(vccd1_pad) ,.VCCD_PAD(vccd1_pad)
`endif `endif
); );
*/
sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] ( sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
@ -246,7 +262,22 @@ module chip_io(
`endif `endif
); );
sky130_ef_io__vssd_lvc_clamped2_pad user1_vssd_lvclmap_pad ( // VCCD1/VSSD1 must be routed to clamps from outside
sky130_fd_io__top_ground_lvc_wpad user1_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS
,.G_PAD(vssd1_pad),
.G_CORE(vssd1),
.SRC_BDY_LVC1(vssd1),
.SRC_BDY_LVC2(vssd1),
.DRN_LVC1(vccd1),
.DRN_LVC2(vccd1),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vssd_lvc_clamped2_pad user1_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VSSD(vssd1) .VSSD(vssd1)
@ -254,6 +285,7 @@ module chip_io(
,.VSSD_PAD(vssd1_pad) ,.VSSD_PAD(vssd1_pad)
`endif `endif
); );
*/
// Instantiate power and ground pads for user 2 domain // Instantiate power and ground pads for user 2 domain
// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp. // 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
@ -267,6 +299,21 @@ module chip_io(
`endif `endif
); );
// VCCD2/VSSD2 must be routed to clamps from outside
sky130_fd_io__top_power_lvc_wpad user2_vccd_lvclamp_pad (
`USER2_ABUTMENT_PINS
,.P_PAD(vccd2_pad),
.P_CORE(vccd2),
.SRC_BDY_LVC1(vssd2),
.SRC_BDY_LVC2(vssd2),
.DRN_LVC1(vccd2),
.DRN_LVC2(vccd2),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vccd_lvc_clamped2_pad user2_vccd_lvclamp_pad ( sky130_ef_io__vccd_lvc_clamped2_pad user2_vccd_lvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
@ -275,6 +322,7 @@ module chip_io(
,.VCCD_PAD(vccd2_pad) ,.VCCD_PAD(vccd2_pad)
`endif `endif
); );
*/
sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad ( sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
@ -285,7 +333,22 @@ module chip_io(
`endif `endif
); );
sky130_ef_io__vssd_lvc_clamped2_pad user2_vssd_lvclmap_pad ( // VCCD2/VSSD2 must be routed to clamps from outside
sky130_fd_io__top_ground_lvc_wpad user2_vssd_lvclamp_pad (
`USER2_ABUTMENT_PINS
,.G_PAD(vssd2_pad),
.G_CORE(vssd2),
.SRC_BDY_LVC1(vssd2),
.SRC_BDY_LVC2(vssd2),
.DRN_LVC1(vccd2),
.DRN_LVC2(vccd2),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vssd_lvc_clamped2_pad user2_vssd_lvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VSSD(vssd2) .VSSD(vssd2)
@ -293,6 +356,7 @@ module chip_io(
,.VSSD_PAD(vssd2_pad) ,.VSSD_PAD(vssd2_pad)
`endif `endif
); );
*/
wire [2:0] dm_all = wire [2:0] dm_all =
{gpio_mode1_core, gpio_mode1_core, gpio_mode0_core}; {gpio_mode1_core, gpio_mode1_core, gpio_mode0_core};
@ -379,7 +443,7 @@ module chip_io(
.VSSA(vssa1), .VSSA(vssa1),
.VSWITCH(vddio), .VSWITCH(vddio),
.VDDA(vdda1), .VDDA(vdda1),
.VCCD(vccd1), .VCCD(vccd),
.VCCHIB(vccd) .VCCHIB(vccd)
`else `else
.VCCHIB() .VCCHIB()
@ -413,10 +477,6 @@ module chip_io(
.vdda2(vdda2), .vdda2(vdda2),
.vssa1(vssa1), .vssa1(vssa1),
.vssa2(vssa2), .vssa2(vssa2),
.vccd1(vccd1),
.vccd2(vccd2),
.vssd1(vssd1),
.vssd2(vssd2),
.vddio_q(vddio_q), .vddio_q(vddio_q),
.vssio_q(vssio_q), .vssio_q(vssio_q),
.analog_a(analog_a), .analog_a(analog_a),

66
verilog/rtl/chip_io_alt.v
View File

@ -220,7 +220,7 @@ module chip_io_alt #(
`endif `endif
); );
sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclmap_pad ( sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad (
`MGMT_ABUTMENT_PINS `MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VSSD(vssd) .VSSD(vssd)
@ -250,6 +250,20 @@ module chip_io_alt #(
`endif `endif
); );
// VCCD1/VSSD1 must be routed to clamps from outside
sky130_fd_io__top_power_lvc_wpad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS
.P_PAD(vccd1_pad),
.P_CORE(vccd1),
.SRC_BDY_LVC1(vssd1),
.SRC_BDY_LVC2(vssd1),
.DRC_LVC1(vccd1),
.DRC_LVC2(vccd1),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vccd_lvc_clamped2_pad user1_vccd_lvclamp_pad ( sky130_ef_io__vccd_lvc_clamped2_pad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
@ -258,6 +272,7 @@ module chip_io_alt #(
,.VCCD_PAD(vccd1_pad) ,.VCCD_PAD(vccd1_pad)
`endif `endif
); );
*/
sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] ( sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
@ -277,7 +292,21 @@ module chip_io_alt #(
`endif `endif
); );
sky130_ef_io__vssd_lvc_clamped2_pad user1_vssd_lvclmap_pad ( // VCCD1/VSSD1 must be routed to clamps from outside
sky130_fd_io__top_ground_lvc_wpad user1_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS
.P_PAD(vssd1_pad),
.P_CORE(vssd1),
.SRC_BDY_LVC1(vssd1),
.SRC_BDY_LVC2(vssd1),
.DRC_LVC1(vccd1),
.DRC_LVC2(vccd1),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vssd_lvc_clamped2_pad user1_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS `USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VSSD(vssd1) .VSSD(vssd1)
@ -285,6 +314,7 @@ module chip_io_alt #(
,.VSSD_PAD(vssd1_pad) ,.VSSD_PAD(vssd1_pad)
`endif `endif
); );
*/
// Instantiate power and ground pads for user 2 domain // Instantiate power and ground pads for user 2 domain
// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp. // 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
@ -298,6 +328,20 @@ module chip_io_alt #(
`endif `endif
); );
// VCCD2/VSSD2 must be routed to clamps from outside
sky130_fd_io__top_power_lvc_wpad user2_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS
.P_PAD(vccd2_pad),
.P_CORE(vccd2),
.SRC_BDY_LVC1(vssd2),
.SRC_BDY_LVC2(vssd2),
.DRC_LVC1(vccd2),
.DRC_LVC2(vccd2),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vccd_lvc_clamped2_pad user2_vccd_lvclamp_pad ( sky130_ef_io__vccd_lvc_clamped2_pad user2_vccd_lvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
@ -306,6 +350,7 @@ module chip_io_alt #(
,.VCCD_PAD(vccd2_pad) ,.VCCD_PAD(vccd2_pad)
`endif `endif
); );
*/
sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad ( sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
@ -316,7 +361,21 @@ module chip_io_alt #(
`endif `endif
); );
sky130_ef_io__vssd_lvc_clamped2_pad user2_vssd_lvclmap_pad ( // VCCD2/VSSD2 must be routed to clamps from outside
sky130_fd_io__top_ground_lvc_wpad user2_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS
.P_PAD(vssd2_pad),
.P_CORE(vssd2),
.SRC_BDY_LVC1(vssd2),
.SRC_BDY_LVC2(vssd2),
.DRC_LVC1(vccd2),
.DRC_LVC2(vccd2),
.BDY2_B2B(vssio),
.OGC_LVC()
);
/*
//----Replaced with base pad (see above)----//
sky130_ef_io__vssd_lvc_clamped2_pad user2_vssd_lvclamp_pad (
`USER2_ABUTMENT_PINS `USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING `ifdef TOP_ROUTING
.VSSD(vssd2) .VSSD(vssd2)
@ -324,6 +383,7 @@ module chip_io_alt #(
,.VSSD_PAD(vssd2_pad) ,.VSSD_PAD(vssd2_pad)
`endif `endif
); );
*/
// Instantiate analog pads in user area 1 using the custom analog pad // Instantiate analog pads in user area 1 using the custom analog pad
sky130_ef_io__analog_pad user1_analog_pad [ANALOG_PADS_1-2:0] ( sky130_ef_io__analog_pad user1_analog_pad [ANALOG_PADS_1-2:0] (

4
verilog/rtl/mprj_io.v
View File

@ -38,10 +38,6 @@ module mprj_io #(
inout vdda2, inout vdda2,
inout vssa1, inout vssa1,
inout vssa2, inout vssa2,
inout vccd1,
inout vccd2,
inout vssd1,
inout vssd2,
input vddio_q, input vddio_q,
input vssio_q, input vssio_q,

8
verilog/rtl/pads.v
View File

@ -24,9 +24,9 @@
.VDDIO_Q(vddio_q),\ .VDDIO_Q(vddio_q),\
.VCCHIB(vccd),\ .VCCHIB(vccd),\
.VDDIO(vddio),\ .VDDIO(vddio),\
.VCCD(vccd1),\ .VCCD(vccd),\
.VSSIO(vssio),\ .VSSIO(vssio),\
.VSSD(vssd1),\ .VSSD(vssd),\
.VSSIO_Q(vssio_q) .VSSIO_Q(vssio_q)
`define USER2_ABUTMENT_PINS \ `define USER2_ABUTMENT_PINS \
@ -38,9 +38,9 @@
.VDDIO_Q(vddio_q),\ .VDDIO_Q(vddio_q),\
.VCCHIB(vccd),\ .VCCHIB(vccd),\
.VDDIO(vddio),\ .VDDIO(vddio),\
.VCCD(vccd2),\ .VCCD(vccd),\
.VSSIO(vssio),\ .VSSIO(vssio),\
.VSSD(vssd2),\ .VSSD(vssd),\
.VSSIO_Q(vssio_q) .VSSIO_Q(vssio_q)
`define MGMT_ABUTMENT_PINS \ `define MGMT_ABUTMENT_PINS \