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caravel
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merge with caravel_redesign

This commit is contained in:
M0stafaRady 2022-10-02 06:55:41 -07:00
parent f0494ef4b1 d93db4d259
commit f3792b8421
2 changed files with 2 additions and 1 deletions
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@ -17,7 +17,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
60d2384a91301fec5721953d87931193681822c4 verilog/rtl/gpio_control_block.v
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
98563c0c63ce5057e95b1901b5e97bcfe9878cb1 verilog/rtl/housekeeping.v
8dafb824eae7173e43f4e2f31c7470a6a1272c79 verilog/rtl/housekeeping.v
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
0f3db7cf4d68971ba4e286c8706b20c9252d1f98 verilog/rtl/mgmt_protect.v
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v

1
verilog/rtl/housekeeping.v
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@ -1057,6 +1057,7 @@ module housekeeping #(
serial_bb_resetn <= 1'b0;
serial_xfer <= 1'b0;
hkspi_disable <= 1'b0;
pwr_ctrl_out <= 'd0;
sram_ro_clk <= 1'b0;
sram_ro_csb <= 1'b1;