update `caravel_core` openlane configuration to fix LVS issues

openlane/caravel_core/config.json

@@ -147,7 +147,8 @@
 		"met5 3043 2082 3171.23 2167",
 		"met5 3043 1859 3171.23 1945",
 		"met4 992 -10 1071 122",
-		"met4 2648 4631 2747 4772.41"
+		"met4 2648 4631 2747 4772.41",
+		"met5 2722.055 118.380 3154.920 166.380"
 	],
 	"FP_PDN_CFG": "dir::/pdn_configuration/pdn.tcl",
 	"PDN_MACRO_CONNECTIONS": [
@@ -236,7 +237,8 @@
 	"MAGIC_DEF_LABELS": false,
 	"MAGIC_EXT_USE_GDS": true,
 	"ERROR_ON_MAGIC_DRC": false,
+	"MAGIC_WRITE_FULL_LEF": true,
 
 	"//": "netgen",
-	"ERROR_ON_LVS_ERROR": false
+	"ERROR_ON_LVS_ERROR": true
 }

openlane/caravel_core/macros-sta.json

@@ -666,7 +666,7 @@
 			],
 			"instances": {
 				"clock_ctrl": {
-					"location": [2747, 9.40],
+					"location": [2772, 9.40],
 					"orientation": "N"
 				}
 			},

openlane/caravel_core/macros.json

@@ -610,7 +610,7 @@
 			],
 			"instances": {
 				"clock_ctrl": {
-					"location": [2747, 9.40],
+					"location": [2772, 9.40],
 					"orientation": "N"
 				}
 			},

openlane/caravel_core/openlane2-command.bash

@@ -1,4 +1,4 @@
-export RUN_TAG=RUN_15
+export RUN_TAG=RUN_18
 rm -rf /home/hosni/caravel-3/caravel/openlane/caravel_core/runs/$RUN_TAG
 export DEFINE_CLOCKS=0 ; python3 -m openlane /home/hosni/caravel-3/caravel/openlane/caravel_core/config.json /home/hosni/caravel-3/caravel/openlane/caravel_core/macros.json --run-tag $RUN_TAG --to OpenROAD.CTS --log-level WARNING
 export DEFINE_CLOCKS=1 ; python3 -m openlane /home/hosni/caravel-3/caravel/openlane/caravel_core/config.json /home/hosni/caravel-3/caravel/openlane/caravel_core/macros.json --run-tag $RUN_TAG --from OpenROAD.ResizerTimingPostCTS --to OpenROAD.RCX --log-level WARNING

openlane/caravel_core/pdn_configuration/pdn.tcl

@@ -163,7 +163,7 @@ add_pdn_stripe \
         -width 4.8 \
         -pitch 120 \
         -offset 844.3 \
-        -spacing 3.2 \
+        -spacing 2 \
         -number_of_straps 1 \
         -nets "vccd1 vssd1 vccd2 vssd2 vdda1 vssa1 vdda2 vssa2" \
         -starts_with POWER
@@ -262,19 +262,19 @@ add_pdn_stripe \
         -pitch 386 \
         -offset 2641 \
         -spacing 2 \
-        -number_of_straps 2 \
-        -nets "vddio vssio" \
-        -starts_with POWER
-    add_pdn_stripe \
-        -grid stdcell_grid \
-        -layer met4 \
-        -width 4.8 \
-        -pitch 386 \
-        -offset 665 \
-        -spacing 2 \
-        -number_of_straps 2 \
+        -number_of_straps 1 \
         -nets "vddio vssio" \
         -starts_with POWER
+    # add_pdn_stripe \
+    #     -grid stdcell_grid \
+    #     -layer met4 \
+    #     -width 4.8 \
+    #     -pitch 386 \
+    #     -offset 665 \
+    #     -spacing 2 \
+    #     -number_of_straps 1 \
+    #     -nets "vddio vssio" \
+    #     -starts_with POWER
 
 ## mprj connections
 add_pdn_stripe \

openlane/caravel_core/sdc_files/base.sdc

@@ -59,7 +59,7 @@ set_input_transition -min $min_in_tran [all_inputs]
 set_input_transition -max $max_in_tran [all_inputs]
 
 # derates
-set derate 0.06
+set derate 0.065
 puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %"
 set_timing_derate -early [expr 1-$derate]
 set_timing_derate -late [expr 1+$derate]

openlane/caravel_core/sdc_files/signoff.sdc

@@ -56,8 +56,8 @@ set_multicycle_path -setup 2 -through [get_pins {mprj/wbs_stb_i}]
 set_multicycle_path -hold 1  -through [get_pins {mprj/wbs_stb_i}]
 
 # add loads for output ports (pads)
-set min_cap 0.5
-set max_cap 1.0
+set min_cap 0.1
+set max_cap 0.5
 puts "\[INFO\]: Cap load range: $min_cap : $max_cap"
 # set_load 10 [all_outputs]
 set_load -min $min_cap [all_outputs]