mirror of https://github.com/efabless/caravel.git
244 lines
7.0 KiB
JSON
244 lines
7.0 KiB
JSON
{
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"meta": {
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"version": 2,
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"flow": [
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"Yosys.JsonHeader",
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"Yosys.Synthesis",
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"OpenROAD.CheckSDCFiles",
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"OpenROAD.Floorplan",
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"Odb.SetPowerConnections",
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"Odb.ManualMacroPlacement",
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"OpenROAD.TapEndcapInsertion",
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"OpenROAD.IOPlacement",
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"Odb.ApplyDEFTemplate",
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"Odb.AddPDNObstructions",
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"OpenROAD.GeneratePDN",
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"OpenROAD.GlobalPlacement",
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"OpenROAD.RepairDesignPostGPL",
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"OpenROAD.DetailedPlacement",
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"OpenROAD.CTS",
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"OpenROAD.ResizerTimingPostCTS",
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"OpenROAD.DetailedPlacement",
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"OpenROAD.GlobalRouting",
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"OpenROAD.RepairDesignPostGRT",
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"OpenROAD.ResizerTimingPostGRT",
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"OpenROAD.GlobalPlacement",
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"OpenROAD.DetailedPlacement",
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"OpenROAD.GlobalRouting",
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"OpenROAD.RepairDesignPostGRT",
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"OpenROAD.ResizerTimingPostGRT",
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"OpenROAD.GlobalPlacement",
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"OpenROAD.DetailedPlacement",
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"Odb.HeuristicDiodeInsertion",
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"OpenROAD.RepairAntennas",
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"OpenROAD.DetailedPlacement",
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"Odb.AddRoutingObstructions",
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"OpenROAD.DetailedRouting",
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"Checker.TrDRC",
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"Odb.ReportDisconnectedPins",
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"Odb.ReportWireLength",
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"OpenROAD.CheckAntennas",
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"Checker.WireLength",
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"OpenROAD.FillInsertion",
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"OpenROAD.RCX",
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"OpenROAD.STAPostPNR",
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"Magic.StreamOut",
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"KLayout.StreamOut",
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"Magic.WriteLEF",
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"KLayout.XOR",
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"Checker.XOR",
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"Magic.DRC",
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"KLayout.DRC",
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"Checker.MagicDRC",
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"Checker.KLayoutDRC",
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"Magic.SpiceExtraction",
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"Checker.IllegalOverlap",
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"Netgen.LVS",
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"Checker.LVS"
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]
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},
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"DESIGN_NAME": "caravel_core",
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"CLOCK_PORT": "clock_core",
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"CLOCK_NET": "caravel_clk",
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"CLOCK_PERIOD": 25,
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"PNR_SDC_FILE": "dir::/sdc_files/base.sdc",
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"SIGNOFF_SDC_FILE": "dir::/sdc_files/signoff.sdc",
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"MAX_FANOUT_CONSTRAINT": 14,
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"//": "SYNTHESIS",
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"VERILOG_FILES": [
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"dir::/../../verilog/rtl/defines.v",
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"dir::/../../verilog/rtl/user_defines.v",
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"dir::/../../verilog/rtl/caravel_core.v",
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"dir::/../../verilog/rtl/mgmt_protect.v",
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"dir::/../../verilog/rtl/gpio_control_block.v",
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"dir::/../../verilog/rtl/gpio_control_block_mgmt.v"
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],
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"SYNTH_EXTRA_MAPPING_FILE": "dir::/synth_configuration/yosys_mapping.v",
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"//": "FLOORPLAN",
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"FP_PIN_ORDER_CFG": "dir::/floorplan_configuration/pin_order.cfg",
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"FP_DEF_TEMPLATE": "dir::/floorplan_configuration/io.def",
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"FP_SIZING": "absolute",
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"DIE_AREA": [0, 0, 3165, 4767],
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"CORE_AREA": [10, 10, 3155, 4757],
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"FP_IO_VEXTEND": 2,
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"FP_IO_HEXTEND": 2,
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"FP_TAPCELL_DIST": 10,
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"FP_OBSTRUCTIONS": [
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[0, 1200, 3166, 1250],
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[0, 1300, 3166, 1350],
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[0, 1400, 3166, 1450],
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[0, 1500, 3166, 1550],
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[0, 1600, 3166, 1650],
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[0, 1700, 3166, 1750],
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[0, 1800, 3166, 1850],
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[0, 1900, 3166, 1950],
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[0, 2000, 3166, 2050],
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[0, 2100, 3166, 2150],
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[0, 2200, 3166, 2250],
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[0, 2300, 3166, 2350],
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[0, 2400, 3166, 2450],
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[0, 2500, 3166, 2550],
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[0, 2600, 3166, 2650],
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[0, 2700, 3166, 2750],
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[0, 2800, 3166, 2850],
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[0, 2900, 3166, 2950],
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[0, 3000, 3166, 3050],
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[0, 3100, 3166, 3150],
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[0, 3200, 3166, 3250],
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[0, 3300, 3166, 3350],
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[0, 3400, 3166, 3450],
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[0, 3500, 3166, 3550],
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[0, 3600, 3166, 3650],
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[0, 3700, 3166, 3750],
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[0, 3800, 3166, 3850],
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[0, 3900, 3166, 3950],
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[0, 4000, 3166, 4050],
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[0, 4100, 3166, 4150],
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[0, 4200, 3166, 4250],
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[0, 4300, 3166, 4350],
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[0, 4400, 3166, 4450],
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[0, 4500, 3166, 4550],
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[78, 1033, 3085, 1072],
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[78, 1072, 121, 4592],
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[78, 4592, 3085, 4630],
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[3042, 1072, 3085, 4592],
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[2650, 4661, 2745, 4712],
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[992, 0, 1071, 34],
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[2645, 0, 3075, 258]
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],
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"FP_MACRO_HORIZONTAL_HALO": 10,
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"FP_MACRO_VERTICAL_HALO": 10,
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"//": "PDN",
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"PDN_CONNECT_MACROS_TO_GRID": true,
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"PDN_OBSTRUCTIONS": [
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"met4 77.11 1032.73 3085.99 4630.95",
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"met5 77.52 1033.73 3086.58 4629.95",
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"met5 -16 125 120 207",
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"met5 -16 1987 120 2073",
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"met5 -16 2199 120 2283",
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"met5 -16 3920 120 4005",
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"met5 -16 4344 120 4431",
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"met5 3043 4321 3171.23 4406",
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"met5 3043 3873 3171.23 3960",
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"met5 3043 2302 3171.23 2387",
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"met5 3043 2082 3171.23 2167",
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"met5 3043 1859 3171.23 1945",
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"met4 992 -10 1071 122",
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"met4 2648 4631 2747 4772.41",
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"met5 2722.055 118.380 3154.920 166.380"
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],
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"FP_PDN_CFG": "dir::/pdn_configuration/pdn.tcl",
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"PDN_MACRO_CONNECTIONS": [
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"mprj vccd1 vssd1 vccd1 vssd1",
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"user_id_value vccd vssd VPWR VGND",
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"housekeeping vccd vssd VPWR VGND",
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"mprj vccd1 vssd1 vccd1 vssd1",
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"mprj vccd2 vssd2 vccd2 vssd2",
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"mprj vdda1 vssa1 vdda1 vssa1",
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"mprj vdda2 vssa2 vdda2 vssa2",
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"soc vccd vssd VPWR VGND",
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"mgmt_buffers.mprj_logic_high_inst vccd1 vssd1 vccd1 vssd1",
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"mgmt_buffers.mprj2_logic_high_inst vccd2 vssd2 vccd2 vssd2",
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"mgmt_buffers.powergood_check vccd vssd vccd vssd",
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"mgmt_buffers.powergood_check vdda1 vssa1 vdda1 vssa1",
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"mgmt_buffers.powergood_check vdda2 vssa2 vdda2 vssa2",
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"gpio_control.* vccd1 vssd1 vccd1 vssd1",
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"spare_logic.* vccd vssd vccd vssd",
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"clock_ctrl vccd vssd VPWR VGND",
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"por vddio vssio vdd3v3 vss3v3",
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"por vccd vssd vdd1v8 vss1v8",
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"rstb_level vddio vssio VPWR VGND",
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"rstb_level vccd vssd LVPWR LVGND"
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],
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"FP_PDN_CORE_RING": true,
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"FP_PDN_SKIPTRIM": true,
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"FP_PDN_CORE_RING_VWIDTH": 10,
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"FP_PDN_CORE_RING_HWIDTH": 10,
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"FP_PDN_CORE_RING_VSPACING": 2,
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"FP_PDN_CORE_RING_HSPACING": 2,
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"FP_PDN_CORE_RING_VOFFSET": 0,
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"FP_PDN_CORE_RING_HOFFSET": 0,
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"FP_PDN_VPITCH": 264,
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"FP_PDN_HPITCH": 360,
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"FP_PDN_VSPACING": 19,
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"FP_PDN_HSPACING": 27,
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"FP_PDN_VWIDTH": 3,
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"FP_PDN_HWIDTH": 3,
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"FP_PDN_HOFFSET": 30.65,
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"FP_PDN_VOFFSET": 3.5,
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"VDD_NETS": ["vccd", "vccd1", "vccd2", "vdda1", "vdda2", "vddio"],
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"GND_NETS": ["vssd", "vssd1", "vssd2", "vssa1", "vssa2", "vssio"],
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"//": "PLACEMENT",
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"PL_TIME_DRIVEN": false,
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"PL_ROUTABILITY_DRIVEN": true,
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"PL_WIRE_LENGTH_COEF": 0.01,
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"PL_TARGET_DENSITY_PCT": 29,
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"PL_RESIZER_DESIGN_OPTIMIZATIONS": true,
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"PL_RESIZER_TIMING_OPTIMIZATIONS": true,
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"PL_RESIZER_HOLD_SLACK_MARGIN": 0.1,
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"DESIGN_REPAIR_MAX_SLEW_PCT": 10,
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"DESIGN_REPAIR_MAX_CAP_PCT": 10,
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"DESIGN_REPAIR_MAX_WIRE_LENGTH": 1200,
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"//": "CTS",
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"CTS_MAX_CAP": 0.80,
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"CTS_CLK_MAX_WIRE_LENGTH": 800,
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"CTS_SINK_CLUSTERING_SIZE": 1,
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"CTS_SINK_CLUSTERING_MAX_DIAMETER": 50,
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"CTS_CLK_BUFFERS": ["sky130_fd_sc_hd__clkbuf_8", "sky130_fd_sc_hd__clkbuf_4"],
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"//": "ROUTING",
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"RT_CLOCK_MIN_LAYER": "met3",
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"DRT_THREADS": 20,
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"GRT_ADJUSTMENT": 0.10,
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"GRT_ALLOW_CONGESTION": true,
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"GLB_RESIZER_TIMING_OPTIMIZATIONS": true,
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"GRT_RESIZER_HOLD_SLACK_MARGIN": 0.05,
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"GRT_RESIZER_SETUP_SLACK_MARGIN": 0.2,
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"GRT_DESIGN_REPAIR_MAX_WIRE_LENGTH": 3000,
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"GRT_ANTENNA_ITERS": 10,
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"ROUTING_OBSTRUCTIONS": [
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"met3 672 33 700 40",
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"met3 2648.72 150.82 2737.92 154.625",
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"met4 2655.52 147.27 2730.32 152.455"
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],
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"DEFAULT_CORNER": "max_ss_100C_1v60",
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"//": "DONT TOUCH",
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"RSZ_DONT_TOUCH_RX": "analog_io|rstb_h|porb_h|serial_clock_out|serial_load_out|ringosc|mgmt_buffers.la_data_out_core|mprj_ack_i_user|mprj_dat_i_user|user_irq_core|user_io_out|user_io_oeb",
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"//": "MAGIC",
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"MAGIC_CAPTURE_ERRORS": false,
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"MAGIC_DEF_LABELS": false,
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"MAGIC_EXT_USE_GDS": true,
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"ERROR_ON_MAGIC_DRC": false,
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"MAGIC_WRITE_FULL_LEF": true,
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"//": "netgen",
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"ERROR_ON_LVS_ERROR": true
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} |