cocotb - Add spi_rd_wr_nbyte test

verilog/dv/cocotb/caravel_tests.py

@@ -26,6 +26,7 @@ from tests.bitbang.bitbang_tests import *
 from tests.bitbang.bitbang_tests_cpu import *
 from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import *
 from tests.housekeeping.housekeeping_spi.user_pass_thru import *
+from tests.housekeeping.housekeeping_spi.spi import *
 from tests.housekeeping.general.pll import *
 from tests.housekeeping.general.sys_ctrl import *
 from tests.temp_partial_test.partial import *

verilog/dv/cocotb/tests.json

@@ -311,6 +311,12 @@
             "GL":[],
             "GL_SDF":[],
             "description":"hello world test"}
+        ,"spi_rd_wr_nbyte" :{"level":3, 
+            "SW":false,
+            "RTL":[],
+            "GL":[],
+            "GL_SDF":[],
+            "description":"try housekeeping spi Write and Read in n-byte mode "}
 
     }
 }

verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi.py

@@ -0,0 +1,42 @@
+import random
+import cocotb
+from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer
+import cocotb.log
+from interfaces.cpu import RiskV
+from interfaces.defsParser import Regs
+from cocotb.result import TestSuccess
+from tests.common_functions.test_functions import *
+from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP
+from tests.housekeeping.housekeeping_spi.spi_access_functions import *
+
+
+bit_time_ns = 0
+reg = Regs()
+
+
+@cocotb.test()
+@repot_test
+async def spi_rd_wr_nbyte(dut):
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=14833)
+    cpu = RiskV(dut)
+    cpu.cpu_force_reset()
+    cpu.cpu_release_reset()
+    cocotb.log.info (f"[TEST] start spi_rd_wr_nbyte test")
+    nbytes_limits= 8
+    #  writing to the random number(1 to 8) of bits after 0x1E (gpio_configure[4]) address  avoid changing gpio 3 
+    for j in range(3):
+        address = random.randint(0x26 , 0x67-nbytes_limits)
+        n_bytes = random.randint(1,nbytes_limits)
+        await write_reg_spi_nbytes(caravelEnv,address,[0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F],nbytes_limits)
+        await write_reg_spi_nbytes(caravelEnv,address,[0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0],n_bytes)
+        data = await read_reg_spi_nbytes(caravelEnv,address,nbytes_limits)
+        for i in range(nbytes_limits):
+            if i >= n_bytes: 
+                if data[i] != 0x1F:
+                    cocotb.log.error(f"[TEST] register {i} has returned value {data[i]} while it should return value 0x1F n_bytes = {n_bytes}")
+                else: cocotb.log.info(f"[TEST] successful read 0 from register {i} n_bytes = {n_bytes}")
+            else: 
+                if data[i] != 0: 
+                    cocotb.log.error(f"[TEST] register number {i} has returned value {data[i]} > 0 while it should return value == 0 n_bytes = {n_bytes}")
+                else: cocotb.log.info(f"[TEST] successful read {data[i]} from register {i} n_bytes = {n_bytes}")    
+    await ClockCycles(caravelEnv.clk,200)

verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py

@@ -16,6 +16,26 @@ async def read_reg_spi(caravelEnv,address):
     await caravelEnv.disable_csb()
     return data
 
+async def write_reg_spi_nbytes(caravelEnv,address,data,n_bytes):
+    write_command = 0x2 << 6 | n_bytes << 3 
+    print(f"command = {hex(write_command)}")
+    await caravelEnv.enable_csb()
+    await caravelEnv.hk_write_byte(write_command) # Write n byte command
+    await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control)
+    for byte in data:
+        await caravelEnv.hk_write_byte(byte) # Data = 0x01 (enable bit-bang mode)
+    await caravelEnv.disable_csb()
+
+
+async def read_reg_spi_nbytes(caravelEnv,address,n_bytes):
+    data =[]
+    await caravelEnv.enable_csb()
+    await caravelEnv.hk_write_byte(0x40) # read stream command
+    await caravelEnv.hk_write_byte(address) # Address 
+    for i in range(n_bytes):
+        data.append(await caravelEnv.hk_read_byte()) # Data = 0x01 (enable bit-bang mode)
+    await caravelEnv.disable_csb()
+    return data
 
 async def reg_spi_user_pass_thru(caravelEnv,command,address):
     await caravelEnv.enable_csb()

verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_rd_wr_nbyte.c

@@ -0,0 +1,10 @@
+#include <defs.h>
+#include <stub.c>
+
+// Empty C code
+
+void main()
+{
+    print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
+	return;
+}

verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py

@@ -1,4 +1,3 @@
-from email.headerregistry import Address
 import random
 import cocotb
 from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer