From d13743ae41a1a50c7b11d8d64f86f23b12753148 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 18 Oct 2022 11:43:40 -0700 Subject: [PATCH] cocotb - Add spi_rd_wr_nbyte test --- verilog/dv/cocotb/caravel_tests.py | 1 + verilog/dv/cocotb/tests.json | 6 +++ .../housekeeping/housekeeping_spi/spi.py | 42 +++++++++++++++++++ .../housekeeping_spi/spi_access_functions.py | 20 +++++++++ .../housekeeping_spi/spi_rd_wr_nbyte.c | 10 +++++ .../housekeeping_spi/user_pass_thru.py | 1 - 6 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi.py create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_rd_wr_nbyte.c diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index 0fd19184..f1aabcc4 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -26,6 +26,7 @@ from tests.bitbang.bitbang_tests import * from tests.bitbang.bitbang_tests_cpu import * from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import * from tests.housekeeping.housekeeping_spi.user_pass_thru import * +from tests.housekeeping.housekeeping_spi.spi import * from tests.housekeeping.general.pll import * from tests.housekeeping.general.sys_ctrl import * from tests.temp_partial_test.partial import * diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 8dd090fb..aba98e54 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -311,6 +311,12 @@ "GL":[], "GL_SDF":[], "description":"hello world test"} + ,"spi_rd_wr_nbyte" :{"level":3, + "SW":false, + "RTL":[], + "GL":[], + "GL_SDF":[], + "description":"try housekeeping spi Write and Read in n-byte mode "} } } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi.py new file mode 100644 index 00000000..b0731a91 --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi.py @@ -0,0 +1,42 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer +import cocotb.log +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP +from tests.housekeeping.housekeeping_spi.spi_access_functions import * + + +bit_time_ns = 0 +reg = Regs() + + +@cocotb.test() +@repot_test +async def spi_rd_wr_nbyte(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=14833) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info (f"[TEST] start spi_rd_wr_nbyte test") + nbytes_limits= 8 + # writing to the random number(1 to 8) of bits after 0x1E (gpio_configure[4]) address avoid changing gpio 3 + for j in range(3): + address = random.randint(0x26 , 0x67-nbytes_limits) + n_bytes = random.randint(1,nbytes_limits) + await write_reg_spi_nbytes(caravelEnv,address,[0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F],nbytes_limits) + await write_reg_spi_nbytes(caravelEnv,address,[0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0],n_bytes) + data = await read_reg_spi_nbytes(caravelEnv,address,nbytes_limits) + for i in range(nbytes_limits): + if i >= n_bytes: + if data[i] != 0x1F: + cocotb.log.error(f"[TEST] register {i} has returned value {data[i]} while it should return value 0x1F n_bytes = {n_bytes}") + else: cocotb.log.info(f"[TEST] successful read 0 from register {i} n_bytes = {n_bytes}") + else: + if data[i] != 0: + cocotb.log.error(f"[TEST] register number {i} has returned value {data[i]} > 0 while it should return value == 0 n_bytes = {n_bytes}") + else: cocotb.log.info(f"[TEST] successful read {data[i]} from register {i} n_bytes = {n_bytes}") + await ClockCycles(caravelEnv.clk,200) \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py index 96e2e9e1..b8c6184e 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py @@ -16,6 +16,26 @@ async def read_reg_spi(caravelEnv,address): await caravelEnv.disable_csb() return data +async def write_reg_spi_nbytes(caravelEnv,address,data,n_bytes): + write_command = 0x2 << 6 | n_bytes << 3 + print(f"command = {hex(write_command)}") + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(write_command) # Write n byte command + await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control) + for byte in data: + await caravelEnv.hk_write_byte(byte) # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + + +async def read_reg_spi_nbytes(caravelEnv,address,n_bytes): + data =[] + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x40) # read stream command + await caravelEnv.hk_write_byte(address) # Address + for i in range(n_bytes): + data.append(await caravelEnv.hk_read_byte()) # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + return data async def reg_spi_user_pass_thru(caravelEnv,command,address): await caravelEnv.enable_csb() diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_rd_wr_nbyte.c b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_rd_wr_nbyte.c new file mode 100644 index 00000000..251067b3 --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_rd_wr_nbyte.c @@ -0,0 +1,10 @@ +#include +#include + +// Empty C code + +void main() +{ + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); + return; +} diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py index 34534770..d6cf16e6 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py @@ -1,4 +1,3 @@ -from email.headerregistry import Address import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer