Final LVS run reports for caravel and caravan top levels, showing LVS

clean.  Provides the netgen report, JSON file, and run-time log of
each.  Modified the scripts to tee into the run-time log file and to
add the SPICE netlist of the simple_por.  Corrected the simple_por
netlist to make the xhigh resistors non-width-specific, since the
width-specific ID mask is not a GDS layer and cannot be reconstructed
from GDS (at least not with the current tech file in magic).

scripts/chip_io_prep.sh

@@ -10,6 +10,7 @@
 # magic layout.
 #
 # Written by Tim Edwards for MPW-7  10/11/2022
+# Updated/fixed 11/08/2022
 #-------------------------------------------------------------------
 
 echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
@@ -17,8 +18,10 @@ echo ${PDK:=sky130A} > /dev/null
 
 # Generate DEF of chip_io
 echo "Generating DEF view of chip_io"
-magic -d OGL -rcfile ${PDK_ROOT}/${PDK}/libs.tech/magic/${PDK}.magicrc << EOF
+magic -dnull -noconsole -rcfile ${PDK_ROOT}/${PDK}/libs.tech/magic/${PDK}.magicrc << EOF
 load chip_io
+select top cell
+expand
 property flatten true
 flatten -doproperty chip_io_flat
 load chip_io_flat
@@ -28,7 +31,20 @@ select top cell
 extract do local
 extract no all
 extract all
-def write chip_io
+# Declare all signals to be SPECIALNETS
+set globals(vccd) 1
+set globals(vssd) 1
+set globals(vddio) 1
+set globals(vssio) 1
+set globals(vdda1) 1
+set globals(vssa1) 1
+set globals(vccd1) 1
+set globals(vssd1) 1
+set globals(vdda2) 1
+set globals(vssa2) 1
+set globals(vccd2) 1
+set globals(vssd2) 1
+def write chip_io -units 400
 quit -noprompt
 EOF
 
@@ -36,8 +52,10 @@ rm *.ext
 
 # Generate DEF of chip_io_alt
 echo "Generating DEF view of chip_io_alt"
-magic -d OGL -rcfile ${PDK_ROOT}/${PDK}/libs.tech/magic/${PDK}.magicrc << EOF
+magic -dnull -noconsole -rcfile ${PDK_ROOT}/${PDK}/libs.tech/magic/${PDK}.magicrc << EOF
 load chip_io_alt
+select top cell
+expand
 property flatten true
 flatten -doproperty chip_io_alt_flat
 load chip_io_alt_flat
@@ -47,7 +65,20 @@ select top cell
 extract do local
 extract no all
 extract all
-def write chip_io_alt
+# Declare all signals to be SPECIALNETS
+set globals(vccd) 1
+set globals(vssd) 1
+set globals(vddio) 1
+set globals(vssio) 1
+set globals(vdda1) 1
+set globals(vssa1) 1
+set globals(vccd1) 1
+set globals(vssd1) 1
+set globals(vdda2) 1
+set globals(vssa2) 1
+set globals(vccd2) 1
+set globals(vssd2) 1
+def write chip_io_alt -units 400
 quit -noprompt
 EOF
 

scripts/run_caravan_lvs_3.sh

@@ -88,7 +88,7 @@ EOF
 rm -f *.ext
 fi
 
-cat > netgenD.tcl << EOF
+cat > netgenE.tcl << EOF
 puts stdout "Reading netlist caravan.spice"
 set circuit1 [readnet spice $CARAVEL_ROOT/spi/lvs/caravan.spice]
 puts stdout "Reading SPICE netlists of I/O"
@@ -128,11 +128,11 @@ readnet verilog $LITEX_ROOT/verilog/gl/mgmt_core_wrapper.v \$circuit2
 puts stdout "Reading top gate-level verilog module"
 readnet verilog $CARAVEL_ROOT/verilog/gl/caravan-signoff.v \$circuit2
 
-# Cells in management core wrapper (layout) are prefixed with RL_ or KF_
+# Cells in management core wrapper (layout) are prefixed with unique 2-letter prefix
 set cells1 [cells list -all \$circuit1]
 set cells2 [cells list -all \$circuit2]
 foreach cell \$cells1 {
-    if {[regexp "\\[A-Z\\]\\[A-Z\\]_(.+)" \$cell match cellname]} {
+    if {[regexp {.._(.+)} \$cell match cellname]} {
         if {([lsearch \$cells2 \$cell] < 0) && ([lsearch \$cells2 \$cellname] >= 0) && ([lsearch \$cells1 \$cellname] < 0)} {
             equate classes "\$circuit1 \$cell" "\$circuit2 \$cellname"
             puts stdout "Matching pins of \$cell in circuit 1 and \$cellname in circuit 2"
@@ -140,7 +140,7 @@ foreach cell \$cells1 {
         }
     }
     # Ignore fill cells in standard cell sets that have two-letter prefixes.
-    if {[regexp {\\[A-Z\\]\\[A-Z\\]_sky130_fd_sc_[^_]+__fill_[[:digit:]]+} \$cell match]} {
+    if {[regexp {.._sky130_fd_sc_[^_]+__fill_[[:digit:]]+} \$cell match]} {
 	ignore class "\$circuit1 \$cell"
     }
 }
@@ -152,7 +152,7 @@ EOF
 
 export NETGEN_COLUMNS=90
 export MAGIC_EXT_USE_GDS=1
-netgen -batch source netgenD.tcl >& caravan_3_lvs.log
+netgen -batch source netgenE.tcl 2>&1 | tee caravan_3_lvs.log
-rm netgenD.tcl
+rm netgenE.tcl
 
 exit 0

scripts/run_caravel_lvs_3.sh

@@ -131,7 +131,7 @@ readnet verilog $CARAVEL_ROOT/verilog/gl/caravel-signoff.v \$circuit2
 set cells1 [cells list -all \$circuit1]
 set cells2 [cells list -all \$circuit2]
 foreach cell \$cells1 {
-    if {[regexp "\\[A-Z\\]\\[A-Z\\]_(.+)" \$cell match cellname]} {
+    if {[regexp ".._(.+)" \$cell match cellname]} {
         if {([lsearch \$cells2 \$cell] < 0) && ([lsearch \$cells2 \$cellname] >= 0) && ([lsearch \$cells1 \$cellname] < 0)} {
             equate classes "\$circuit1 \$cell" "\$circuit2 \$cellname"
             puts stdout "Matching pins of \$cell in circuit 1 and \$cellname in circuit 2"
@@ -139,7 +139,7 @@ foreach cell \$cells1 {
         }
     }
     # Ignore fill cells in standard cell sets that have two-letter prefixes.
-    if {[regexp {\\[A-Z\\]\\[A-Z\\]_sky130_fd_sc_[^_]+__fill_[[:digit:]]+} \$cell match]} {
+    if {[regexp {.._sky130_fd_sc_[^_]+__fill_[[:digit:]]+} \$cell match]} {
 	ignore class "\$circuit1 \$cell"
     }
 }
@@ -151,7 +151,7 @@ EOF
 
 export NETGEN_COLUMNS=90
 export MAGIC_EXT_USE_GDS=1
-netgen -batch source netgenD.tcl >& caravel_3_lvs.log
+netgen -batch source netgenD.tcl 2>&1 | tee caravel_3_lvs.log
 rm netgenD.tcl
 
 exit 0

signoff/caravel/standalone_pvr/caravel.lvs.report

@@ -6983,6 +6983,46 @@ B
 Cell pin lists are equivalent.
 Device classes NF_sky130_fd_sc_hd__nor4b_2 and sky130_fd_sc_hd__nor4b_2 are equivalent.
 
+Circuit 1 cell sky130_fd_pr__cap_mim_m3_1 and Circuit 2 cell sky130_fd_pr__cap_mim_m3_1 are black boxes.
+Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_1 is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__cap_mim_m3_1                                                       |Circuit 2: sky130_fd_pr__cap_mim_m3_1                                                       
+--------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------
+1                                                                                           |1                                                                                           
+2                                                                                           |2                                                                                           
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__cap_mim_m3_1 and sky130_fd_pr__cap_mim_m3_1 are equivalent.
+
+Circuit 1 cell sky130_fd_pr__cap_mim_m3_2 and Circuit 2 cell sky130_fd_pr__cap_mim_m3_2 are black boxes.
+Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_2 is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_2 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__cap_mim_m3_2                                                       |Circuit 2: sky130_fd_pr__cap_mim_m3_2                                                       
+--------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------
+1                                                                                           |1                                                                                           
+2                                                                                           |2                                                                                           
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__cap_mim_m3_2 and sky130_fd_pr__cap_mim_m3_2 are equivalent.
+
+Circuit 1 cell sky130_fd_pr__res_xhigh_po and Circuit 2 cell sky130_fd_pr__res_xhigh_po are black boxes.
+Warning: Equate pins:  cell sky130_fd_pr__res_xhigh_po is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__res_xhigh_po is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__res_xhigh_po                                                       |Circuit 2: sky130_fd_pr__res_xhigh_po                                                       
+--------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------
+1                                                                                           |1                                                                                           
+2                                                                                           |2                                                                                           
+3                                                                                           |3                                                                                           
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__res_xhigh_po and sky130_fd_pr__res_xhigh_po are equivalent.
+
 Circuit 1 cell sky130_fd_pr__res_generic_pd__hv and Circuit 2 cell sky130_fd_pr__res_generic_pd__hv are black boxes.
 Warning: Equate pins:  cell sky130_fd_pr__res_generic_pd__hv is a placeholder, treated as a black box.
 Warning: Equate pins:  cell sky130_fd_pr__res_generic_pd__hv is a placeholder, treated as a black box.
@@ -18099,20 +18139,46 @@ flash_io3_di
 -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 Cell pin lists are equivalent.
 Device classes mgmt_core_wrapper and mgmt_core_wrapper are equivalent.
+Flattening unmatched subcell QJ_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB in circuit simple_por (0)(4 instances)
+Flattening unmatched subcell QJ_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE in circuit simple_por (0)(1 instance)
+Flattening unmatched subcell QJ_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC in circuit simple_por (0)(1 instance)
+Flattening unmatched subcell QJ_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM in circuit simple_por (0)(1 instance)
+Flattening unmatched subcell QJ_sky130_fd_pr__cap_mim_m3_1_WRT4AW in circuit simple_por (0)(1 instance)
+Flattening unmatched subcell QJ_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV in circuit simple_por (0)(1 instance)
+Flattening unmatched subcell QJ_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG in circuit simple_por (0)(1 instance)
+Flattening unmatched subcell QJ_sky130_fd_pr__cap_mim_m3_2_W5U4AW in circuit simple_por (0)(1 instance)
+Flattening unmatched subcell QJ_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ in circuit simple_por (0)(1 instance)
+Flattening unmatched subcell QJ_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 in circuit simple_por (0)(1 instance)
+Flattening unmatched subcell QJ_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS in circuit simple_por (0)(1 instance)
 
-Circuit 2 cell simple_por is a black box; will not flatten Circuit 1
+Class simple_por (0):  Merged 20 parallel devices.
-Warning: Equate pins:  cell simple_por is a placeholder, treated as a black box.
+Class simple_por (0):  Merged 24 series devices.
+Subcircuit summary:
+Circuit 1: simple_por                                                                       |Circuit 2: simple_por                                                                       
+--------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------
+sky130_fd_pr__pfet_g5v0d10v5 (21->8)                                                        |sky130_fd_pr__pfet_g5v0d10v5 (8)                                                            
+sky130_fd_pr__nfet_g5v0d10v5 (9->3)                                                         |sky130_fd_pr__nfet_g5v0d10v5 (3)                                                            
+sky130_fd_pr__cap_mim_m3_1 (1)                                                              |sky130_fd_pr__cap_mim_m3_1 (1)                                                              
+sky130_fd_pr__cap_mim_m3_2 (1)                                                              |sky130_fd_pr__cap_mim_m3_2 (1)                                                              
+QJ_sky130_fd_sc_hvl__buf_8 (2)                                                              |sky130_fd_sc_hvl__buf_8 (2)                                                                 
+QJ_sky130_fd_sc_hvl__inv_8 (1)                                                              |sky130_fd_sc_hvl__inv_8 (1)                                                                 
+sky130_fd_pr__res_xhigh_po (28->3)                                                          |sky130_fd_pr__res_xhigh_po (4->3)                                                           
+QJ_sky130_fd_sc_hvl__schmittbuf_1 (1)                                                       |sky130_fd_sc_hvl__schmittbuf_1 (1)                                                          
+Number of devices: 20                                                                       |Number of devices: 20                                                                       
+Number of nets: 17                                                                          |Number of nets: 17                                                                          
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Netlists match uniquely.
 
 Subcircuit pins:
 Circuit 1: simple_por                                                                       |Circuit 2: simple_por                                                                       
 --------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------
-vdd3v3                                                                                      |vdd3v3                                                                                      
-vdd1v8                                                                                      |vdd1v8                                                                                      
 porb_h                                                                                      |porb_h                                                                                      
-por_l                                                                                       |por_l                                                                                       
 porb_l                                                                                      |porb_l                                                                                      
-vss1v8                                                                                      |vss1v8                                                                                      
+por_l                                                                                       |por_l                                                                                       
 vss3v3                                                                                      |vss3v3                                                                                      
+vdd3v3                                                                                      |vdd3v3                                                                                      
+vss1v8                                                                                      |vss1v8                                                                                      
+vdd1v8                                                                                      |vdd1v8                                                                                      
 -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 Cell pin lists are equivalent.
 Device classes simple_por and simple_por are equivalent.

xschem/simple_por.spice

@@ -1,3 +1,5 @@
+# NOTE:  Hand-edited to change res_xhigh_po_0p69 resistors to res_xhigh_po resistors with W=0.69
+# because the former device does not get recognized when reading from GDS.
 .subckt simple_por vdd3v3 vss3v3 porb_h porb_l por_l vdd1v8 vss1v8
 *.iopin vdd3v3
 *.iopin vss3v3
@@ -14,14 +16,16 @@ XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((n
 XM2 net2 net3 vss3v3 vss3v3 sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
 + as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
 + nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
-XR1 net4 vdd3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
+# XR1 net4 vdd3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
+XR1 net4 vdd3v3 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=500 mult=1 m=1
 XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
 + as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
 + nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
 XM5 net3 net3 vss3v3 vss3v3 sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
 + as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
 + nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
-XR2 vss3v3 net4 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
+# XR2 vss3v3 net4 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
+XR2 vss3v3 net4 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=150 mult=1 m=1
 XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
 + as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
 + nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
@@ -43,7 +47,8 @@ XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int
 XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
 + as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
 + nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
-XR3 vss3v3 vss3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
+# XR3 vss3v3 vss3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
+XR3 vss3v3 vss3v3 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=25 mult=2 m=2
 x2 net10 vss3v3 vss3v3 vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
 x3 net10 vss1v8 vss1v8 vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
 x4 net10 vss1v8 vss1v8 vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8