Corrected an error in verilog/gl/chip_io_alt.v, which was missing

connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.

mag/run_caravan_lvs.sh

@@ -1,5 +1,6 @@
-#!/bin/sh
+#!/bin/bassh
 #
+if [ ! -f caravan.spice ]; then
 magic -dnull -noconsole -rcfile /usr/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc << EOF
 drc off
 crashbackups stop
@@ -11,6 +12,7 @@ extract all
 ext2spice lvs
 ext2spice
 EOF
+fi
 
 rm *.ext
 

mag/run_caravel_lvs.sh

@@ -1,5 +1,6 @@
-#!/bin/sh
+#!/bin/bash
 #
+if [ ! -f caravel.spice ]; then
 magic -dnull -noconsole -rcfile /usr/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc << EOF
 drc off
 crashbackups stop
@@ -11,6 +12,7 @@ extract all
 ext2spice lvs
 ext2spice
 EOF
+fi
 
 rm *.ext
 

mag/run_chip_io_alt_lvs.sh

@@ -0,0 +1,19 @@
+#!/bin/bash
+#
+if [ ! -f caravan.spice ]; then
+magic -dnull -noconsole -rcfile /usr/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc << EOF
+drc off
+crashbackups stop
+load caravan
+select top cell
+expand
+extract do local
+extract all
+ext2spice lvs
+ext2spice
+EOF
+rm *.ext
+fi
+
+export NETGEN_COLUMNS=60
+netgen -batch lvs "caravan.spice chip_io_alt" "../verilog/gl/chip_io_alt.v chip_io_alt" ./sky130A_setup.tcl comp.out

mag/run_chip_io_lvs.sh

@@ -0,0 +1,18 @@
+#!/bin/bash
+#
+if [ ! -f caravel.spice ]; then
+magic -dnull -noconsole -rcfile /usr/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc << EOF
+drc off
+crashbackups stop
+load caravel
+select top cell
+expand
+extract do local
+extract all
+ext2spice lvs
+ext2spice
+EOF
+fi
+
+export NETGEN_COLUMNS=60
+netgen -batch lvs "caravel.spice chip_io" "../verilog/gl/chip_io.v chip_io" ./sky130A_setup.tcl comp.out

verilog/gl/chip_io_alt.v

@@ -2301,6 +2301,7 @@ module chip_io_alt(vddio_pad, vddio_pad2, vssio_pad, vssio_pad2, vccd_pad, vssd_
     .AMUXBUS_A(\mprj_pads.analog_a ),
     .AMUXBUS_B(\mprj_pads.analog_b ),
     .VCCD(vccd),
+    .VCCD1(vccd1),
     .VCCD_PAD(vccd1_pad),
     .VCCHIB(vccd),
     .VDDA(vdda1),
@@ -2308,6 +2309,7 @@ module chip_io_alt(vddio_pad, vddio_pad2, vssio_pad, vssio_pad2, vccd_pad, vssd_
     .VDDIO_Q(\mprj_pads.vddio_q ),
     .VSSA(vssa1),
     .VSSD(vssd),
+    .VSSD1(vssd1),
     .VSSIO(vssio),
     .VSSIO_Q(\mprj_pads.vssio_q ),
     .VSWITCH(vddio)
@@ -2376,12 +2378,14 @@ module chip_io_alt(vddio_pad, vddio_pad2, vssio_pad, vssio_pad2, vccd_pad, vssd_
     .AMUXBUS_A(\mprj_pads.analog_a ),
     .AMUXBUS_B(\mprj_pads.analog_b ),
     .VCCD(vccd),
+    .VCCD1(vccd1),
     .VCCHIB(vccd),
     .VDDA(vdda1),
     .VDDIO(vddio),
     .VDDIO_Q(\mprj_pads.vddio_q ),
     .VSSA(vssa1),
     .VSSD(vssd),
+    .VSSD1(vssd1),
     .VSSD_PAD(vssd1_pad),
     .VSSIO(vssio),
     .VSSIO_Q(\mprj_pads.vssio_q ),
@@ -2505,6 +2509,7 @@ module chip_io_alt(vddio_pad, vddio_pad2, vssio_pad, vssio_pad2, vccd_pad, vssd_
     .AMUXBUS_A(\mprj_pads.analog_a ),
     .AMUXBUS_B(\mprj_pads.analog_b ),
     .VCCD(vccd),
+    .VCCD1(vccd2),
     .VCCD_PAD(vccd2_pad),
     .VCCHIB(vccd),
     .VDDA(vdda2),
@@ -2512,6 +2517,7 @@ module chip_io_alt(vddio_pad, vddio_pad2, vssio_pad, vssio_pad2, vccd_pad, vssd_
     .VDDIO_Q(\mprj_pads.vddio_q ),
     .VSSA(vssa2),
     .VSSD(vssd),
+    .VSSD1(vssd2),
     .VSSIO(vssio),
     .VSSIO_Q(\mprj_pads.vssio_q ),
     .VSWITCH(vddio)
@@ -2550,12 +2556,14 @@ module chip_io_alt(vddio_pad, vddio_pad2, vssio_pad, vssio_pad2, vccd_pad, vssd_
     .AMUXBUS_A(\mprj_pads.analog_a ),
     .AMUXBUS_B(\mprj_pads.analog_b ),
     .VCCD(vccd),
+    .VCCD1(vccd2),
     .VCCHIB(vccd),
     .VDDA(vdda2),
     .VDDIO(vddio),
     .VDDIO_Q(\mprj_pads.vddio_q ),
     .VSSA(vssa2),
     .VSSD(vssd),
+    .VSSD1(vssd2),
     .VSSD_PAD(vssd2_pad),
     .VSSIO(vssio),
     .VSSIO_Q(\mprj_pads.vssio_q ),