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Update caravel to force high at gpio3 at the start of test

This commit is contained in:
M0stafaRady 2022-10-11 08:30:02 -07:00
parent 9cc8ebf28a
commit bd40646465
2 changed files with 6 additions and 3 deletions
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4
verilog/dv/cocotb/interfaces/caravel.py
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@ -51,13 +51,15 @@ class Caravel_env:
"""start carvel by insert power then reset""" """start carvel by insert power then reset"""
async def start_up(self): async def start_up(self):
await self.power_up() await self.power_up()
# await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup
await self.reset() await self.reset()
await self.disable_bins() await self.disable_bins()
common.fill_macros(self.dut.macros) # get macros value common.fill_macros(self.dut.macros) # get macros value
async def disable_bins(self): async def disable_bins(self):
for i in range(38): for i in range(38):
if i ==3:
continue
common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0)
"""setup the vdd and vcc power bins""" """setup the vdd and vcc power bins"""

5
verilog/dv/cocotb/interfaces/cpu.py
View File

@ -33,10 +33,11 @@ class RiskV:
if not Macros['GL']: if not Macros['GL']:
self.cpu_hdl = dut.uut.soc.core.VexRiscv self.cpu_hdl = dut.uut.soc.core.VexRiscv
else: else:
self.cpu_hdl = dut.uut.soc.core self.cpu_hdl = dut.uut.soc
self.debug_hdl = dut.uut.mprj.debug self.debug_hdl = dut.uut.mprj.debug
self.force_reset = 0 self.force_reset = 0
cocotb.scheduler.add(self.force_reset_fun()) if not Macros['GL']:
cocotb.scheduler.add(self.force_reset_fun())
""" """ """ """