diff --git a/verilog/dv/cocotb/interfaces/caravel.py b/verilog/dv/cocotb/interfaces/caravel.py
index 74f4d2ac..54096a2d 100644
--- a/verilog/dv/cocotb/interfaces/caravel.py
+++ b/verilog/dv/cocotb/interfaces/caravel.py
@@ -51,13 +51,15 @@ class Caravel_env:
     """start carvel by insert power then reset"""
     async def start_up(self):
         await self.power_up()
-        # await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup
+        await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup
         await self.reset()
         await self.disable_bins()
         common.fill_macros(self.dut.macros) # get macros value
 
     async def disable_bins(self):
         for i in range(38):
+            if i ==3:
+                continue
             common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) 
 
     """setup the vdd and vcc power bins"""
diff --git a/verilog/dv/cocotb/interfaces/cpu.py b/verilog/dv/cocotb/interfaces/cpu.py
index 115c0f67..b2bd6885 100644
--- a/verilog/dv/cocotb/interfaces/cpu.py
+++ b/verilog/dv/cocotb/interfaces/cpu.py
@@ -33,10 +33,11 @@ class RiskV:
         if not Macros['GL']:
             self.cpu_hdl     = dut.uut.soc.core.VexRiscv
         else:
-            self.cpu_hdl     = dut.uut.soc.core
+            self.cpu_hdl     = dut.uut.soc
         self.debug_hdl   = dut.uut.mprj.debug
         self.force_reset = 0
-        cocotb.scheduler.add(self.force_reset_fun())
+        if not Macros['GL']:
+            cocotb.scheduler.add(self.force_reset_fun())
 
 
     """  """