add initial openlane configuration for `caravan_core`

openlane/caravan_core/config.tcl

@@ -0,0 +1,294 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set ::env(DESIGN_NAME) caravan_core
+set ::env(ROUTING_CORES) 36
+set ::env(DESIGN_IS_CORE) 1
+set ::env(BASE_SDC_FILE) "$::env(DESIGN_DIR)/sdc_files/base.sdc"
+set ::env(RCX_SDC_FILE) "$::env(DESIGN_DIR)/sdc_files/rcx.sdc"
+
+set ::env(VERILOG_FILES) "\
+                        $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+                        $::env(CARAVEL_ROOT)/verilog/rtl/user_defines.v \
+                        $::env(CARAVEL_ROOT)/verilog/rtl/caravan_core.v \
+                        $::env(CARAVEL_ROOT)/verilog/rtl/mgmt_protect.v \
+                        $::env(CARAVEL_ROOT)/verilog/rtl/digital_pll.v \
+                        $::env(CARAVEL_ROOT)/verilog/rtl/clock_div.v \
+                        $::env(CARAVEL_ROOT)/verilog/rtl/gpio_control_block.v \
+                        $::env(MCW_ROOT)/verilog/rtl/mgmt_core_wrapper.v \
+                        $::env(MCW_ROOT)/verilog/rtl/mgmt_core.v \
+                        $::env(MCW_ROOT)/verilog/rtl/ibex_all.v \
+                        $::env(MCW_ROOT)/verilog/rtl/picorv32.v \
+                        $::env(MCW_ROOT)/verilog/rtl/VexRiscv_MinDebugCache.v \
+                        $::env(MCW_ROOT)/verilog/rtl/RAM256.v \
+"
+                    
+set ::env(RUN_KLAYOUT) 0
+
+# clock constraints
+set ::env(CLOCK_PORT) "clock_core"
+set ::env(CLOCK_NET) "caravel_clk"
+set ::env(CLOCK_PERIOD) 25
+
+# Synthesis
+set ::env(SYNTH_STRATEGY) "DELAY 1"
+set ::env(SYNTH_DEFINES) "PnR TOP_ROUTING"
+set ::env(NO_SYNTH_CELL_LIST) $::env(DESIGN_DIR)/synth_configuration/no_synth.cells
+set ::env(DRC_EXCLUDE_CELL_LIST) $::env(DESIGN_DIR)/synth_configuration/drc_exclude.cells
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+# set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+set ::env(SYNTH_BUFFERING) 0
+set ::env(SYNTH_EXTRA_MAPPING_FILE) "$::env(DESIGN_DIR)/synth_configuration/yosys_mapping.v"
+set ::env(SYNTH_MAX_FANOUT) 12
+set ::env(SYNTH_CAP_LOAD) 52
+set ::env(SYNTH_CLOCK_TRANSITION) 0.6
+set ::env(SYNTH_CLOCK_UNCERTAINTY) 0.25
+set ::env(SYNTH_MAX_TRAN) 0.50
+set ::env(QUIT_ON_SYNTH_CHECKS) 0
+
+## Floorplan
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 3165 4767"
+set ::env(CORE_AREA) "10 10 3155 4757"
+
+set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/floorplan_configuration/io.def
+
+set ::env(FP_PDN_VERTICAL_HALO) "8"
+set ::env(FP_PDN_HORIZONTAL_HALO) "1"
+
+set ::env(FP_IO_MIN_DISTANCE) 5
+
+set ::env(FP_IO_VEXTEND) 2
+set ::env(FP_IO_HEXTEND) 2
+
+set ::env(FP_TAPCELL_DIST) 10
+set ::env(PL_MACRO_HALO) "-1 -3"
+# set ::env(CELL_PAD) 0
+
+## PDN 
+set ::env(VSRC_LOC) $::env(DESIGN_DIR)/floorplan_configuration/Vsrc.loc
+
+set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
+set ::env(FP_PDN_CFG) [glob $::env(DESIGN_DIR)/pdn_configuration/pdn.tcl]
+set ::env(FP_PDN_CHECK_NODES) 0
+
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_PDN_SKIPTRIM) 0
+
+set ::env(VDD_NETS) "vccd vccd1 vccd2 vdda1 vdda2 vddio"
+set ::env(GND_NETS) "vssd vssd1 vssd2 vssa1 vssa2 vssio"
+
+set ::env(FP_PDN_MACRO_HOOKS) {
+    user_id_value vccd vssd VPWR VGND,\
+    housekeeping vccd vssd VPWR VGND,\
+    mprj vccd1 vssd1 vccd1 vssd1,\
+    mprj vccd2 vssd2 vccd2 vssd2,\
+    mprj vdda1 vssa1 vdda1 vssa1,\
+    mprj vdda2 vssa2 vdda2 vssa2,\
+    soc.core.RAM256.BANK128\\\\\\[0\\\\\\].RAM128 vccd vssd VPWR VGND,\
+    soc.core.RAM256.BANK128\\\\\\[1\\\\\\].RAM128 vccd vssd VPWR VGND,\
+    soc.core.RAM128 vccd vssd vccd1 vssd1,\
+    mgmt_buffers.mprj_logic_high_inst vccd1 vssd1 vccd1 vssd1,\
+    mgmt_buffers.mprj2_logic_high_inst vccd2 vssd2 vccd2 vssd2,\
+    mgmt_buffers.powergood_check vccd vssd vccd vssd,\
+    mgmt_buffers.powergood_check vdda1 vssa1 vdda1 vssa1,\
+    mgmt_buffers.powergood_check vdda2 vssa2 vdda2 vssa2,\
+    gpio_control_bidir_1\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_bidir_1\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1a\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1a\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1a\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1a\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1a\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1a\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_1\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_2\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_2\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_2\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_2\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_2\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_2\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_2\\\\\\[6\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_2\\\\\\[7\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_2\\\\\\[8\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_in_2\\\\\\[9\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_bidir_2\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_bidir_2\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    gpio_control_bidir_2\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
+    spare_logic\\\\\\[0\\\\\\] vccd vssd vccd vssd,\
+    spare_logic\\\\\\[1\\\\\\] vccd vssd vccd vssd,\
+    spare_logic\\\\\\[2\\\\\\] vccd vssd vccd vssd,\
+    spare_logic\\\\\\[3\\\\\\] vccd vssd vccd vssd,\
+    clock_ctrl vccd vssd VPWR VGND,\
+    por vddio vssio vdd3v3 vss3v3,\
+    por vccd vssd vdd1v8 vss1v8,\
+    rstb_level vddio vssio VPWR VGND,\
+    rstb_level vccd vssd LVPWR LVGND\
+}
+
+set ::env(FP_PDN_CORE_RING_VWIDTH) 10
+set ::env(FP_PDN_CORE_RING_HWIDTH) 10
+set ::env(FP_PDN_CORE_RING_VSPACING) 2
+set ::env(FP_PDN_CORE_RING_VOFFSET) 1
+set ::env(FP_PDN_CORE_RING_HSPACING) 2
+set ::env(FP_PDN_CORE_RING_VOFFSET) 0
+set ::env(FP_PDN_CORE_RING_HOFFSET) 0
+set ::env(FP_PDN_VPITCH) 264
+set ::env(FP_PDN_HPITCH) 360
+set ::env(FP_PDN_VSPACING) 19
+set ::env(FP_PDN_HSPACING) 27
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
+set ::env(FP_PDN_HOFFSET) 30.65
+set ::env(FP_PDN_VOFFSET) 3.5
+
+##CTS
+set ::env(RUN_CTS) 1
+set ::env(CTS_MAX_CAP) 0.3
+set ::env(CTS_SINK_CLUSTERING_SIZE) 12
+set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) 30
+set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4}
+set ::env(CTS_CLK_MAX_WIRE_LENGTH) 1000
+
+##PLACEMENT
+set ::env(PL_ROUTABILITY_DRIVEN) 1
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_WIRELENGTH_COEF) 0.01
+set ::env(PL_TARGET_DENSITY) 0.24
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.03
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 0
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) 0.1
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 1000
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 50
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 50
+
+##ROUTING
+set ::env(GRT_ALLOW_CONGESTION) 1
+
+set ::env(GRT_ADJUSTMENT) 0.10
+##                                li1 ,met1,met2,met3,met4,met5
+# set ::env(GRT_LAYER_ADJUSTMENTS) "0.99,0.10,0.05,0.10,0.05,0.00"
+# set ::env(GRT_LAYER_ADJUSTMENTS) "0.99,0.20,0.10,0.20,0.05,0.00"
+# set ::env(GRT_OVERFLOW_ITERS) 60
+
+set ::env(GRT_ESTIMATE_PARASITICS) 1
+
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.05
+set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) 1
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) 600
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) 30
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) 30
+
+## Antenna
+set ::env(GRT_REPAIR_ANTENNAS) 1
+set ::env(RUN_HEURISTIC_DIODE_INSERTION) 1
+set ::env(HEURISTIC_ANTENNA_THRESHOLD) 80
+set ::env(DIODE_ON_PORTS) "none"
+set ::env(GRT_ANT_MARGIN) 10
+set ::env(GRT_ANT_ITERS) 12
+set ::env(GRT_MAX_DIODE_INS_ITERS) 4
+set ::env(DIODE_PADDING) 0
+
+## MACROS
+set ::env(MACRO_PLACEMENT_CFG) [glob $::env(DESIGN_DIR)/floorplan_configuration//macro_placement.cfg]
+
+set ::env(VERILOG_FILES_BLACKBOX) "\
+    $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+    $::env(CARAVEL_ROOT)/verilog/rtl/user_id_programming.v \
+    $::env(CARAVEL_ROOT)/verilog/rtl/__user_analog_project_wrapper.v \
+    $::env(CARAVEL_ROOT)/verilog/gl/housekeeping.v \
+    $::env(CARAVEL_ROOT)/verilog/rtl/simple_por.v \
+    $::env(CARAVEL_ROOT)/verilog/gl/xres_buf.v \
+    $::env(CARAVEL_ROOT)/verilog/gl/spare_logic_block.v \
+    $::env(CARAVEL_ROOT)/verilog/rtl/gpio_defaults_block.v \
+    $::env(CARAVEL_ROOT)/verilog/gl/mprj_logic_high.v \
+	$::env(CARAVEL_ROOT)/verilog/gl/mprj2_logic_high.v \
+	$::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect_hv.v \
+    $::env(CARAVEL_ROOT)/verilog/gl/gpio_logic_high.v \
+    $::env(CARAVEL_ROOT)/verilog/gl/empty_macro.v \
+    $::env(CARAVEL_ROOT)/verilog/gl/empty_macro_1.v \
+    $::env(CARAVEL_ROOT)/verilog/gl/caravel_clocking.v \
+    $::env(CARAVEL_ROOT)/verilog/gl/caravan_signal_routing.v \
+    $::env(MCW_ROOT)/verilog/gl/RAM128.v \
+"
+
+set ::env(EXTRA_LEFS) "\
+    $::env(CARAVEL_ROOT)/lef/user_id_programming.lef \
+    $::env(CARAVEL_ROOT)/lef/user_analog_project_wrapper_empty.lef \
+    $::env(CARAVEL_ROOT)/lef/housekeeping.lef \
+    $::env(CARAVEL_ROOT)/lef/simple_por.lef \
+    $::env(CARAVEL_ROOT)/lef/xres_buf.lef \
+    $::env(CARAVEL_ROOT)/lef/spare_logic_block.lef \
+    $::env(CARAVEL_ROOT)/lef/gpio_defaults_block.lef \
+    $::env(CARAVEL_ROOT)/lef/mprj_logic_high.lef \
+    $::env(CARAVEL_ROOT)/lef/mprj2_logic_high.lef \
+    $::env(CARAVEL_ROOT)/lef/mgmt_protect_hv.lef \
+    $::env(CARAVEL_ROOT)/lef/gpio_logic_high.lef \
+    $::env(CARAVEL_ROOT)/lef/empty_macro.lef \
+    $::env(CARAVEL_ROOT)/lef/empty_macro_1.lef \
+    $::env(CARAVEL_ROOT)/lef/caravel_clocking.lef \
+    $::env(CARAVEL_ROOT)/lef/caravan_signal_routing.lef \
+    $::env(MCW_ROOT)/lef/RAM128.lef \
+"
+
+set ::env(EXTRA_GDS_FILES) "\
+    $::env(CARAVEL_ROOT)/gds/user_id_programming.gds \
+    $::env(CARAVEL_ROOT)/gds/user_analog_project_wrapper_empty.gds \
+    $::env(CARAVEL_ROOT)/gds/housekeeping.gds \
+    $::env(CARAVEL_ROOT)/gds/simple_por.gds \
+    $::env(CARAVEL_ROOT)/gds/xres_buf.gds \
+    $::env(CARAVEL_ROOT)/gds/spare_logic_block.gds \
+    $::env(CARAVEL_ROOT)/gds/gpio_defaults_block.gds \
+    $::env(CARAVEL_ROOT)/gds/mprj_logic_high.gds \
+    $::env(CARAVEL_ROOT)/gds/mprj2_logic_high.gds \
+    $::env(CARAVEL_ROOT)/gds/mgmt_protect_hv.gds \
+    $::env(CARAVEL_ROOT)/gds/gpio_logic_high.gds \
+    $::env(CARAVEL_ROOT)/gds/empty_macro.gds \
+    $::env(CARAVEL_ROOT)/gds/empty_macro_1.gds \
+    $::env(CARAVEL_ROOT)/gds/caravel_clocking.gds \
+    $::env(CARAVEL_ROOT)/gds/caravan_signal_routing.gds \
+    $::env(MCW_ROOT)/gds/RAM128.gds \
+"
+
+set ::env(EXTRA_LIBS) "\
+    $::env(CARAVEL_ROOT)/lib/housekeeping.lib \
+    $::env(CARAVEL_ROOT)/lib/gpio_defaults_block.lib \
+    $::env(CARAVEL_ROOT)/lib/gpio_logic_high.lib \
+    $::env(CARAVEL_ROOT)/lib/mprj_io_buffer.lib \
+    $::env(CARAVEL_ROOT)/lib/user_project_wrapper.lib \
+    $::env(CARAVEL_ROOT)/lib/caravel_clocking.lib \
+    $::env(MCW_ROOT)/signoff/RAM128/primetime/lib/ff/RAM128.nom.lib \
+"
+
+set ::env(STA_WRITE_LIB) 0
+
+## For faster development
+set ::env(QUIT_ON_TR_DRC) 1
+set ::env(QUIT_ON_LVS_ERROR) 0
+set ::env(QUIT_ON_MAGIC_DRC) 0
+
+set ::env(MAGIC_DEF_LABELS) 0
+set ::env(MAGIC_EXT_USE_GDS) 1
+
+set ::env(RSZ_DONT_TOUCH_RX) "rstb_h|porb_h|serial_clock_out|serial_load_out|ringosc|mgmt_buffers.la_data_out_core|mprj_ack_i_user|mprj_dat_i_user|user_irq_core|3v3|clamp"

openlane/caravan_core/floorplan_configuration/Vsrc.loc

@@ -0,0 +1 @@
+9.880,191.880,48,1.8

openlane/caravan_core/floorplan_configuration/io.py

@@ -0,0 +1,536 @@
+def print_io_east(pad, offset_x, offset_y):
+    print(f'''
+    - mprj_io_in[''' + str(pad) + '''] + NET mprj_io_in[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_one[''' + str(pad) + '''] + NET mprj_io_one[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+5980), f''') N ;''')
+    print(f'''
+    - mprj_io_slow_sel[''' + str(pad) + '''] + NET mprj_io_slow_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+9200), f''') N ;''')
+    if (pad > 6) & (pad < 36):
+        print(f'''
+    - user_gpio_analog[''' + str(pad-7) + '''] + NET user_gpio_analog[''' + str(pad-7) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+12420), f''') N ;''')
+    print(f'''
+    - mprj_io_dm[''' + str(pad*3+1) + '''] + NET mprj_io_dm[''' + str(pad*3+1) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+18400), f''') N ;''')
+    if (pad > 6):
+        print(f'''
+        - user_gpio_noesd[''' + str(pad-7) + '''] + NET user_gpio_noesd[''' + str(pad-7) + '''] + DIRECTION INPUT + USE SIGNAL
+            + PORT
+            + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+            + PLACED (''', str(offset_x), str(offset_y+21620), f''') N ;''')
+    print(f'''
+    - mprj_io_analog_en[''' + str(pad) + '''] + NET mprj_io_analog_en[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+24380), f''') N ;''')
+    print(f'''
+    - mprj_io_dm[''' + str(pad*3) + '''] + NET mprj_io_dm[''' + str(pad*3) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+27600), f''') N ;''')
+    print(f'''
+    - mprj_io_analog_pol[''' + str(pad) + '''] + NET mprj_io_analog_pol[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+30820), f''') N ;''')
+    print(f'''
+    - mprj_io_inp_dis[''' + str(pad) + '''] + NET mprj_io_inp_dis[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+33580), f''') N ;''')
+    print(f'''
+    - mprj_io_analog_sel[''' + str(pad) + '''] + NET mprj_io_analog_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+46000), f''') N ;''')
+    print(f'''
+    - mprj_io_dm[''' + str(pad*3+2) + '''] + NET mprj_io_dm[''' + str(pad*3+2) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+49220), f''') N ;''')
+    print(f'''
+    - mprj_io_holdover[''' + str(pad) + '''] + NET mprj_io_holdover[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+52440), f''') N ;''')
+    print(f'''
+    - mprj_io_out[''' + str(pad) + '''] + NET mprj_io_out[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+55200), f''') N ;''')
+    print(f'''
+    - mprj_io_vtrip_sel[''' + str(pad) + '''] + NET mprj_io_vtrip_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+64400), f''') N ;''')
+    print(f'''
+    - mprj_io_ib_mode_sel[''' + str(pad) + '''] + NET mprj_io_ib_mode_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+67620), f''') N ;''')
+    print(f'''
+    - mprj_io_oeb[''' + str(pad) + '''] + NET mprj_io_oeb[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+70840), f''') N ;''')
+    print(f'''
+    - mprj_io_in_3v3[''' + str(pad) + '''] + NET mprj_io_in_3v3[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y+73600), f''') N ;''')
+
+def print_io_north(pad, offset_x, offset_y):
+    print(f'''
+    - mprj_io_in[''' + str(pad) + '''] + NET mprj_io_in[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_one[''' + str(pad) + '''] + NET mprj_io_one[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-5980), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_slow_sel[''' + str(pad) + '''] + NET mprj_io_slow_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-9200), str(offset_y), f''') N ;''')
+    if (pad > 6) & (pad < 29):
+        print(f'''
+    - user_gpio_analog[''' + str(pad-7) + '''] + NET user_gpio_analog[''' + str(pad-7) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-12420), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_dm[''' + str(pad*3+1) + '''] + NET mprj_io_dm[''' + str(pad*3+1) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-18400), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_analog_en[''' + str(pad) + '''] + NET mprj_io_analog_en[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-24380), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_dm[''' + str(pad*3) + '''] + NET mprj_io_dm[''' + str(pad*3) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-27600), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_analog_pol[''' + str(pad) + '''] + NET mprj_io_analog_pol[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-30820), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_inp_dis[''' + str(pad) + '''] + NET mprj_io_inp_dis[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-33580), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_analog_sel[''' + str(pad) + '''] + NET mprj_io_analog_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-46000), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_dm[''' + str(pad*3+2) + '''] + NET mprj_io_dm[''' + str(pad*3+2) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-49220), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_holdover[''' + str(pad) + '''] + NET mprj_io_holdover[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-52440), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_out[''' + str(pad) + '''] + NET mprj_io_out[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-55200), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_vtrip_sel[''' + str(pad) + '''] + NET mprj_io_vtrip_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-64400), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_ib_mode_sel[''' + str(pad) + '''] + NET mprj_io_ib_mode_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-67620), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_oeb[''' + str(pad) + '''] + NET mprj_io_oeb[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 2935 )
+        + PLACED (''', str(offset_x-70840), str(offset_y), f''') N ;''')
+    
+def print_io_west(pad, offset_x, offset_y):
+    print(f'''
+    - mprj_io_in[''' + str(pad) + '''] + NET mprj_io_in[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y), f''') N ;''')
+    print(f'''
+    - mprj_io_one[''' + str(pad) + '''] + NET mprj_io_one[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-5980), f''') N ;''')
+    print(f'''
+    - mprj_io_slow_sel[''' + str(pad) + '''] + NET mprj_io_slow_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-9200), f''') N ;''')
+    if (pad > 6) & (pad < 25):
+        print(f'''
+    - user_gpio_analog[''' + str(pad-7) + '''] + NET user_gpio_analog[''' + str(pad-7) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-12420), f''') N ;''')
+    print(f'''
+    - mprj_io_dm[''' + str(pad*3+1) + '''] + NET mprj_io_dm[''' + str(pad*3+1) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-18400), f''') N ;''')
+    if (pad > 6) & (pad < 25):
+        print(f'''
+    - user_gpio_noesd[''' + str(pad-7) + '''] + NET user_gpio_noesd[''' + str(pad-7) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-21620), f''') N ;''')
+    print(f'''
+    - mprj_io_analog_en[''' + str(pad) + '''] + NET mprj_io_analog_en[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-24380), f''') N ;''')
+    print(f'''
+    - mprj_io_dm[''' + str(pad*3) + '''] + NET mprj_io_dm[''' + str(pad*3) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-27600), f''') N ;''')
+    print(f'''
+    - mprj_io_analog_pol[''' + str(pad) + '''] + NET mprj_io_analog_pol[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-30820), f''') N ;''')
+    print(f'''
+    - mprj_io_inp_dis[''' + str(pad) + '''] + NET mprj_io_inp_dis[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-33580), f''') N ;''')
+    print(f'''
+    - mprj_io_analog_sel[''' + str(pad) + '''] + NET mprj_io_analog_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-46000), f''') N ;''')
+    print(f'''
+    - mprj_io_dm[''' + str(pad*3+2) + '''] + NET mprj_io_dm[''' + str(pad*3+2) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-49220), f''') N ;''')
+    print(f'''
+    - mprj_io_holdover[''' + str(pad) + '''] + NET mprj_io_holdover[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-52440), f''') N ;''')
+    print(f'''
+    - mprj_io_out[''' + str(pad) + '''] + NET mprj_io_out[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-55200), f''') N ;''')
+    print(f'''
+    - mprj_io_vtrip_sel[''' + str(pad) + '''] + NET mprj_io_vtrip_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-64400), f''') N ;''')
+    print(f'''
+    - mprj_io_ib_mode_sel[''' + str(pad) + '''] + NET mprj_io_ib_mode_sel[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-67620), f''') N ;''')
+    print(f'''
+    - mprj_io_oeb[''' + str(pad) + '''] + NET mprj_io_oeb[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3185 -300 ) ( 3000 300 )
+        + PLACED (''', str(offset_x), str(offset_y-70840), f''') N ;''')
+    print(f'''
+    - mprj_io_in_3v3[''' + str(pad) + '''] + NET mprj_io_in_3v3[''' + str(pad) + '''] + DIRECTION INPUT + USE SIGNAL
+        + PORT
+        + LAYER met3 ( -3000 -300 ) ( 3185 300 )
+        + PLACED (''', str(offset_x), str(offset_y-73600), f''') N ;''')
+
+
+print(f'''
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN caravan_core ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 3165000 4767000 ) ;
+PINS 621 ;
+    - clock_core + NET clock_core + DIRECTION INPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 725275 1000 ) N ;
+    - flash_clk_frame + NET flash_clk_frame + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 1597475 1000 ) N ;
+    - flash_clk_oeb + NET flash_clk_oeb + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 1613115 1000 ) N ;
+    - flash_csb_frame + NET flash_csb_frame + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 1323475 1000 ) N ;
+    - flash_csb_oeb + NET flash_csb_oeb + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 1339115 1000 ) N ;
+    - flash_io0_di + NET flash_io0_di + DIRECTION INPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 1816275 1000 ) N ;
+    - flash_io0_do + NET flash_io0_do + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 1871475 1000 ) N ;
+    - flash_io0_ieb + NET flash_io0_ieb + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 1849855 1000 ) N ;
+    - flash_io0_oeb + NET flash_io0_oeb + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 1887115 1000 ) N ;
+    - flash_io1_di + NET flash_io1_di + DIRECTION INPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 2090275 1000 ) N ;
+    - flash_io1_do + NET flash_io1_do + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 2145475 1000 ) N ;
+    - flash_io1_ieb + NET flash_io1_ieb + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 2123855 1000 ) N ;
+    - flash_io1_oeb + NET flash_io1_oeb + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 2161115 1000 ) N ;
+    - gpio_in_core + NET gpio_in_core + DIRECTION INPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 2364275 1000 ) N ;
+    - gpio_inenb_core + NET gpio_inenb_core + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 2397855 1000 ) N ;
+    - gpio_mode0_core + NET gpio_mode0_core + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 2391875 1000 ) N ;
+    - gpio_mode1_core + NET gpio_mode1_core + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 2413495 1000 ) N ;
+    - gpio_out_core + NET gpio_out_core + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 2419475 1000 ) N ;
+    - gpio_outenb_core + NET gpio_outenb_core + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 2435115 1000 ) N ;
+    - por_l + NET por_l + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 758855 1000 ) N ;
+    - porb_h + NET porb_h + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+        + PLACED ( 1329915 1000 ) N ;
+    - rstb_h + NET rstb_h + DIRECTION INPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -140 -11525 ) ( 140 3000 )
+        + PLACED ( 496975 1000 ) N ;
+
+    - user_analog[0] + NET user_analog[0] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -300 ) ( 1000 200 )
+        + PLACED ( 3164500 4585280 ) N ;
+    - user_analog[1] + NET user_analog[1] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 2966500 4767000 ) N ; 
+    - user_analog[2] + NET user_analog[2] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 2451500 4767000 ) N ; 
+    - user_analog[3] + NET user_analog[3] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 2194500 4767000 ) N ; 
+
+    - user_analog[4] + NET user_analog[4] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 1706500 4767000 ) N ; 
+    - user_clamp_high[0] + NET user_clamp_high[0] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 1756500 4767000 ) N ; 
+    - user_clamp_low[0] + NET user_clamp_low[0] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 1743500 4767000 ) N ; 
+
+    - user_analog[5] + NET user_analog[5] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 1287500 4767000 ) N ; 
+    - user_clamp_high[1] + NET user_clamp_high[1] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 1247500 4767000 ) N ; 
+    - user_clamp_low[1] + NET user_clamp_low[1] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 1234500 4767000 ) N ; 
+
+    - user_analog[6] + NET user_analog[6] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 1024500 4767000 ) N ; 
+    - user_clamp_high[2] + NET user_clamp_high[2] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 984500 4767000 ) N ; 
+    - user_clamp_low[2] + NET user_clamp_low[2] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 971500 4767000 ) N ;        
+
+    - user_analog[7] + NET user_analog[7] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 725500 4767000 ) N ; 
+    - user_analog[8] + NET user_analog[8] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 468500 4767000 ) N ; 
+    - user_analog[9] + NET user_analog[9] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( 0 -500 ) ( 500 500 )
+        + PLACED ( 211500 4767000 ) N ;       
+    - user_analog[10] + NET user_analog[10] + DIRECTION INOUT + USE SIGNAL
+      + PORT
+        + LAYER met3 ( -500 -300 ) ( 500 200 )
+        + PLACED ( 0 4599000 ) N ;    
+        
+        ''')
+
+## East pads
+offset_x = 3164000 
+offset_y = 294275
+pad = 0
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 226000
+pad = 1
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 225000
+pad = 2
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 226000
+pad = 3
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 225000
+pad = 4
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 225000
+pad = 5
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 226000
+pad = 6
+print_io_east(pad, offset_x, offset_y)
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 886000
+pad = 7
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 226000
+pad = 8
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 225000
+pad = 9
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 226000
+pad = 10
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 225000
+pad = 11
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 225000
+pad = 12
+print_io_east(pad, offset_x, offset_y)
+offset_y = offset_y + 446000
+pad = 13
+print_io_east(pad, offset_x, offset_y)
+
+## West pads
+offset_x = 1000
+offset_y = 4635725
+offset_y = offset_y - 849000
+pad = 14
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 15
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 16
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 17
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 18
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 19
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 20
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 638000
+pad = 21
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 22
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 23
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 24
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 25
+print_io_west(pad, offset_x, offset_y)
+offset_y = offset_y - 216000
+pad = 26
+print_io_west(pad, offset_x, offset_y)
+
+print(f'''
+END PINS
+END DESIGN''')

openlane/caravan_core/floorplan_configuration/macro_placement.cfg

@@ -0,0 +1,83 @@
+user_id_value 2962.655 129.19 N
+soc.core.RAM256.BANK128\[0\].RAM128 90.09 175 N
+soc.core.RAM256.BANK128\[1\].RAM128 581.97 175 FN
+soc.core.RAM128 1800 125 FN
+mgmt_buffers.mprj_logic_high_inst 1190.94 1020 N
+mgmt_buffers.powergood_check 1794 1020 N
+mgmt_buffers.mprj2_logic_high_inst 823 1020 FN
+por 1063.15 135 MX
+mprj 115.04 1183.09 N
+housekeeping 2650 190 N
+spare_logic\[0\] 454 778.2 N 
+spare_logic\[1\] 1054 658.2 N
+spare_logic\[2\] 1554 658.2 N 
+spare_logic\[3\] 2054 658.2 N
+gpio_defaults_block_0 3137 230 N
+gpio_defaults_block_1 3137 460 N
+gpio_defaults_block_2 3137 680 N
+gpio_defaults_block_3 3137 910 N
+gpio_defaults_block_4 3137 1130 N
+gpio_defaults_block_5 3137 1350 N
+gpio_defaults_block_6 3137 1590 N
+gpio_defaults_block_7 3137 2460 N
+gpio_defaults_block_8 3137 2700 N
+gpio_defaults_block_9 3137 2920 N
+gpio_defaults_block_10 3137 3150 N
+gpio_defaults_block_11 3137 3380 N
+gpio_defaults_block_12 3137 3600 N
+gpio_defaults_block_13 3137 4030 N
+gpio_defaults_block_25 10 3680 FN
+gpio_defaults_block_26 10 3460 FN
+gpio_defaults_block_27 10 3240 FN
+gpio_defaults_block_28 10 3030 FN
+gpio_defaults_block_29 10 2800 FN
+gpio_defaults_block_30 10 2600 FN
+gpio_defaults_block_31 10 2390 FN
+gpio_defaults_block_32 10 1740 FN
+gpio_defaults_block_33 10 1530 FN
+gpio_defaults_block_34 10 1300 FN
+gpio_defaults_block_35 10 1090 FN
+gpio_defaults_block_36 10 870 FN
+gpio_defaults_block_37 10 660 FN
+gpio_control_bidir_1\[0\].gpio_logic_high 3128.9 200 N
+gpio_control_bidir_1\[1\].gpio_logic_high 3128.9 430 N
+gpio_control_in_1a\[0\].gpio_logic_high 3128.9 650 N
+gpio_control_in_1a\[1\].gpio_logic_high 3128.9 880 N
+gpio_control_in_1a\[2\].gpio_logic_high 3128.9 1100 N
+gpio_control_in_1a\[3\].gpio_logic_high 3128.9 1320 N
+gpio_control_in_1a\[4\].gpio_logic_high 3128.9 1560 N
+gpio_control_in_1a\[5\].gpio_logic_high 3128.9 2430 N
+gpio_control_in_1\[0\].gpio_logic_high 3128.9 2670 N
+gpio_control_in_1\[1\].gpio_logic_high 3128.9 2890 N
+gpio_control_in_1\[2\].gpio_logic_high 3128.9 3120 N
+gpio_control_in_1\[3\].gpio_logic_high 3128.9 3350 N
+gpio_control_in_1\[4\].gpio_logic_high 3128.9 3570 N
+gpio_control_in_1\[5\].gpio_logic_high 3128.9 4000 N
+gpio_control_in_2\[0\].gpio_logic_high 11 3650 N
+gpio_control_in_2\[1\].gpio_logic_high 11 3430 N
+gpio_control_in_2\[2\].gpio_logic_high 11 3210 N
+gpio_control_in_2\[3\].gpio_logic_high 11 3000 N
+gpio_control_in_2\[4\].gpio_logic_high 11 2770 N
+gpio_control_in_2\[5\].gpio_logic_high 11 2570 N
+gpio_control_in_2\[6\].gpio_logic_high 11 2360 N
+gpio_control_in_2\[7\].gpio_logic_high 11 1710 N
+gpio_control_in_2\[8\].gpio_logic_high 11 1500 N
+gpio_control_in_2\[9\].gpio_logic_high 11 1270 N
+gpio_control_bidir_2\[0\].gpio_logic_high 11 1060 N
+gpio_control_bidir_2\[1\].gpio_logic_high 11 840 N
+gpio_control_bidir_2\[2\].gpio_logic_high 11 630 N
+rstb_level 683.62 26 S
+empty_macro_0 10.92 4194.6 N
+clock_ctrl 1545 183 N
+caravan_signal_routing 0 0 N
+empty_macro_1 3042 1854 N
+empty_macro_2 3042 2055 N
+empty_macro_3 3042 2231 N
+empty_macro_4 3042 3773 N
+empty_macro_5 0 1983 N
+empty_macro_6 0 2146 N
+empty_macro_7 0 3904 N
+empty_macro_8 0 4066 N
+empty_macro_9 3042 4194.6 N
+empty_macro_10 3042 4394.6 N
+empty_macro_11 3042 4594.6 N

openlane/caravan_core/floorplan_configuration/pin_order.cfg

@@ -0,0 +1,686 @@
+#BUS_SORT
+#NR
+$20
+mprj_analog_io\[8\]
+mprj_io_in\[15\]
+mprj_io_slow_sel\[15\]
+mprj_io_dm\[46\]
+mprj_io_analog_en\[15\]
+mprj_io_dm\[45\]
+mprj_io_analog_pol\[15\]
+mprj_io_inp_dis\[15\]
+mprj_io_analog_sel\[15\]
+mprj_io_dm\[47\]
+mprj_io_holdover\[15\]
+mprj_io_out\[15\]
+mprj_io_vtrip_sel\[15\]
+mprj_io_ib_mode_sel\[15\]
+mprj_io_oeb\[15\]
+mprj_io_one\[15\]
+$84
+mprj_analog_io\[9\]
+mprj_io_in\[16\]
+mprj_io_slow_sel\[16\]
+mprj_io_dm\[49\]
+mprj_io_analog_en\[16\]
+mprj_io_dm\[48\]
+mprj_io_analog_pol\[16\]
+mprj_io_inp_dis\[16\]
+mprj_io_analog_sel\[16\]
+mprj_io_dm\[50\]
+mprj_io_holdover\[16\]
+mprj_io_out\[16\]
+mprj_io_vtrip_sel\[16\]
+mprj_io_ib_mode_sel\[16\]
+mprj_io_oeb\[16\]
+mprj_io_one\[16\]
+$35
+mprj_analog_io\[10\]
+mprj_io_in\[17\]
+mprj_io_slow_sel\[17\]
+mprj_io_dm\[52\]
+mprj_io_analog_en\[17\]
+mprj_io_dm\[51\]
+mprj_io_analog_pol\[17\]
+mprj_io_inp_dis\[17\]
+mprj_io_analog_sel\[17\]
+mprj_io_dm\[53\]
+mprj_io_holdover\[17\]
+mprj_io_out\[17\]
+mprj_io_vtrip_sel\[17\]
+mprj_io_ib_mode_sel\[17\]
+mprj_io_oeb\[17\]
+mprj_io_one\[17\]
+$73
+mprj_analog_io\[11\]
+mprj_io_in\[18\]
+mprj_io_slow_sel\[18\]
+mprj_io_dm\[55\]
+mprj_io_analog_en\[18\]
+mprj_io_dm\[54\]
+mprj_io_analog_pol\[18\]
+mprj_io_inp_dis\[18\]
+mprj_io_analog_sel\[18\]
+mprj_io_dm\[56\]
+mprj_io_holdover\[18\]
+mprj_io_out\[18\]
+mprj_io_vtrip_sel\[18\]
+mprj_io_ib_mode_sel\[18\]
+mprj_io_oeb\[18\]
+mprj_io_one\[18\]
+$85
+mprj_analog_io\[12\]
+mprj_io_in\[19\]
+mprj_io_slow_sel\[19\]
+mprj_io_dm\[58\]
+mprj_io_analog_en\[19\]
+mprj_io_dm\[57\]
+mprj_io_analog_pol\[19\]
+mprj_io_inp_dis\[19\]
+mprj_io_analog_sel\[19\]
+mprj_io_dm\[59\]
+mprj_io_holdover\[19\]
+mprj_io_out\[19\]
+mprj_io_vtrip_sel\[19\]
+mprj_io_ib_mode_sel\[19\]
+mprj_io_oeb\[19\]
+mprj_io_one\[19\]
+$35
+mprj_analog_io\[13\]
+mprj_io_in\[20\]
+mprj_io_slow_sel\[20\]
+mprj_io_dm\[61\]
+mprj_io_analog_en\[20\]
+mprj_io_dm\[60\]
+mprj_io_analog_pol\[20\]
+mprj_io_inp_dis\[20\]
+mprj_io_analog_sel\[20\]
+mprj_io_dm\[62\]
+mprj_io_holdover\[20\]
+mprj_io_out\[20\]
+mprj_io_vtrip_sel\[20\]
+mprj_io_ib_mode_sel\[20\]
+mprj_io_oeb\[20\]
+mprj_io_one\[20\]
+$35
+mprj_analog_io\[14\]
+mprj_io_in\[21\]
+mprj_io_slow_sel\[21\]
+mprj_io_dm\[64\]
+mprj_io_analog_en\[21\]
+mprj_io_dm\[63\]
+mprj_io_analog_pol\[21\]
+mprj_io_inp_dis\[21\]
+mprj_io_analog_sel\[21\]
+mprj_io_dm\[65\]
+mprj_io_holdover\[21\]
+mprj_io_out\[21\]
+mprj_io_vtrip_sel\[21\]
+mprj_io_ib_mode_sel\[21\]
+mprj_io_oeb\[21\]
+mprj_io_one\[21\]
+$35
+mprj_analog_io\[15\]
+mprj_io_in\[22\]
+mprj_io_slow_sel\[22\]
+mprj_io_dm\[67\]
+mprj_io_analog_en\[22\]
+mprj_io_dm\[66\]
+mprj_io_analog_pol\[22\]
+mprj_io_inp_dis\[22\]
+mprj_io_analog_sel\[22\]
+mprj_io_dm\[68\]
+mprj_io_holdover\[22\]
+mprj_io_out\[22\]
+mprj_io_vtrip_sel\[22\]
+mprj_io_ib_mode_sel\[22\]
+mprj_io_oeb\[22\]
+mprj_io_one\[22\]
+$35
+mprj_analog_io\[16\]
+mprj_io_in\[23\]
+mprj_io_slow_sel\[23\]
+mprj_io_dm\[70\]
+mprj_io_analog_en\[23\]
+mprj_io_dm\[69\]
+mprj_io_analog_pol\[23\]
+mprj_io_inp_dis\[23\]
+mprj_io_analog_sel\[23\]
+mprj_io_dm\[71\]
+mprj_io_holdover\[23\]
+mprj_io_out\[23\]
+mprj_io_vtrip_sel\[23\]
+mprj_io_ib_mode_sel\[23\]
+mprj_io_oeb\[23\]
+mprj_io_one\[23\]
+$20
+
+#S
+$43
+rstb_h
+$21
+clock_core
+$2
+por_l
+$56
+flash_csb_frame
+$1
+flash_csb_oeb
+porb_h
+$26
+flash_clk_frame
+flash_clk_oeb
+$19
+flash_io0_di
+$2
+flash_io0_ieb
+$1
+flash_io0_do 
+$1
+flash_io0_oeb
+$19
+flash_io1_di
+$1
+flash_io1_ieb
+$1
+flash_io1_do
+flash_io1_oeb
+$19
+gpio_in_core
+$2
+gpio_mode0_core
+gpio_inenb_core
+$1
+gpio_mode1_core
+gpio_out_core
+gpio_outenb_core
+$63
+
+#E
+$40
+mprj_io_in\[0\]
+mprj_io_slow_sel\[0\]
+mprj_io_dm\[1\]
+mprj_io_analog_en\[0\]
+mprj_io_dm\[0\]
+mprj_io_analog_pol\[0\]
+mprj_io_inp_dis\[0\]
+mprj_io_analog_sel\[0\]
+mprj_io_dm\[2\]
+mprj_io_holdover\[0\]
+mprj_io_out\[0\]
+mprj_io_vtrip_sel\[0\]
+mprj_io_ib_mode_sel\[0\]
+mprj_io_oeb\[0\]
+mprj_io_one\[0\]
+$32
+mprj_io_in\[1\]
+mprj_io_slow_sel\[1\]
+mprj_io_dm\[4\]
+mprj_io_analog_en\[1\]
+mprj_io_dm\[3\]
+mprj_io_analog_pol\[1\]
+mprj_io_inp_dis\[1\]
+mprj_io_analog_sel\[1\]
+mprj_io_dm\[5\]
+mprj_io_holdover\[1\]
+mprj_io_out\[1\]
+mprj_io_vtrip_sel\[1\]
+mprj_io_ib_mode_sel\[1\]
+mprj_io_oeb\[1\]
+mprj_io_one\[1\]
+$32
+mprj_io_in\[2\]
+mprj_io_slow_sel\[2\]
+mprj_io_dm\[7\]
+mprj_io_analog_en\[2\]
+mprj_io_dm\[6\]
+mprj_io_analog_pol\[2\]
+mprj_io_inp_dis\[2\]
+mprj_io_analog_sel\[2\]
+mprj_io_dm\[8\]
+mprj_io_holdover\[2\]
+mprj_io_out\[2\]
+mprj_io_vtrip_sel\[2\]
+mprj_io_ib_mode_sel\[2\]
+mprj_io_oeb\[2\]
+mprj_io_one\[2\]
+$32
+mprj_io_in\[3\]
+mprj_io_slow_sel\[3\]
+mprj_io_dm\[10\]
+mprj_io_analog_en\[3\]
+mprj_io_dm\[9\]
+mprj_io_analog_pol\[3\]
+mprj_io_inp_dis\[3\]
+mprj_io_analog_sel\[3\]
+mprj_io_dm\[11\]
+mprj_io_holdover\[3\]
+mprj_io_out\[3\]
+mprj_io_vtrip_sel\[3\]
+mprj_io_ib_mode_sel\[3\]
+mprj_io_oeb\[3\]
+mprj_io_one\[3\]
+$32
+mprj_io_in\[4\]
+mprj_io_slow_sel\[4\]
+mprj_io_dm\[13\]
+mprj_io_analog_en\[4\]
+mprj_io_dm\[12\]
+mprj_io_analog_pol\[4\]
+mprj_io_inp_dis\[4\]
+mprj_io_analog_sel\[4\]
+mprj_io_dm\[14\]
+mprj_io_holdover\[4\]
+mprj_io_out\[4\]
+mprj_io_vtrip_sel\[4\]
+mprj_io_ib_mode_sel\[4\]
+mprj_io_oeb\[4\]
+mprj_io_one\[4\]
+$32
+mprj_io_in\[5\]
+mprj_io_slow_sel\[5\]
+mprj_io_dm\[16\]
+mprj_io_analog_en\[5\]
+mprj_io_dm\[15\]
+mprj_io_analog_pol\[5\]
+mprj_io_inp_dis\[5\]
+mprj_io_analog_sel\[5\]
+mprj_io_dm\[17\]
+mprj_io_holdover\[5\]
+mprj_io_out\[5\]
+mprj_io_vtrip_sel\[5\]
+mprj_io_ib_mode_sel\[5\]
+mprj_io_oeb\[5\]
+mprj_io_one\[5\]
+$32
+mprj_io_in\[6\]
+mprj_io_slow_sel\[6\]
+mprj_io_dm\[19\]
+mprj_io_analog_en\[6\]
+mprj_io_dm\[18\]
+mprj_io_analog_pol\[6\]
+mprj_io_inp_dis\[6\]
+mprj_io_analog_sel\[6\]
+mprj_io_dm\[20\]
+mprj_io_holdover\[6\]
+mprj_io_out\[6\]
+mprj_io_vtrip_sel\[6\]
+mprj_io_ib_mode_sel\[6\]
+mprj_io_oeb\[6\]
+mprj_io_one\[6\]
+$172
+mprj_analog_io\[0\]
+mprj_io_in\[7\]
+mprj_io_slow_sel\[7\]
+mprj_io_dm\[22\]
+mprj_io_analog_en\[7\]
+mprj_io_dm\[21\]
+mprj_io_analog_pol\[7\]
+mprj_io_inp_dis\[7\]
+mprj_io_analog_sel\[7\]
+mprj_io_dm\[23\]
+mprj_io_holdover\[7\]
+mprj_io_out\[7\]
+mprj_io_vtrip_sel\[7\]
+mprj_io_ib_mode_sel\[7\]
+mprj_io_oeb\[7\]
+mprj_io_one\[7\]
+$32
+mprj_analog_io\[1\]
+mprj_io_in\[8\]
+mprj_io_slow_sel\[8\]
+mprj_io_dm\[25\]
+mprj_io_analog_en\[8\]
+mprj_io_dm\[24\]
+mprj_io_analog_pol\[8\]
+mprj_io_inp_dis\[8\]
+mprj_io_analog_sel\[8\]
+mprj_io_dm\[26\]
+mprj_io_holdover\[8\]
+mprj_io_out\[8\]
+mprj_io_vtrip_sel\[8\]
+mprj_io_ib_mode_sel\[8\]
+mprj_io_oeb\[8\]
+mprj_io_one\[8\]
+$32
+mprj_analog_io\[2\]
+mprj_io_in\[9\]
+mprj_io_slow_sel\[9\]
+mprj_io_dm\[28\]
+mprj_io_analog_en\[9\]
+mprj_io_dm\[27\]
+mprj_io_analog_pol\[9\]
+mprj_io_inp_dis\[9\]
+mprj_io_analog_sel\[9\]
+mprj_io_dm\[29\]
+mprj_io_holdover\[9\]
+mprj_io_out\[9\]
+mprj_io_vtrip_sel\[9\]
+mprj_io_ib_mode_sel\[9\]
+mprj_io_oeb\[9\]
+mprj_io_one\[9\]
+$32
+mprj_analog_io\[3\]
+mprj_io_in\[10\]
+mprj_io_slow_sel\[10\]
+mprj_io_dm\[31\]
+mprj_io_analog_en\[10\]
+mprj_io_dm\[30\]
+mprj_io_analog_pol\[10\]
+mprj_io_inp_dis\[10\]
+mprj_io_analog_sel\[10\]
+mprj_io_dm\[32\]
+mprj_io_holdover\[10\]
+mprj_io_out\[10\]
+mprj_io_vtrip_sel\[10\]
+mprj_io_ib_mode_sel\[10\]
+mprj_io_oeb\[10\]
+mprj_io_one\[10\]
+$32
+mprj_analog_io\[4\]
+mprj_io_in\[11\]
+mprj_io_slow_sel\[11\]
+mprj_io_dm\[34\]
+mprj_io_analog_en\[11\]
+mprj_io_dm\[33\]
+mprj_io_analog_pol\[11\]
+mprj_io_inp_dis\[11\]
+mprj_io_analog_sel\[11\]
+mprj_io_dm\[35\]
+mprj_io_holdover\[11\]
+mprj_io_out\[11\]
+mprj_io_vtrip_sel\[11\]
+mprj_io_ib_mode_sel\[11\]
+mprj_io_oeb\[11\]
+mprj_io_one\[11\]
+$32
+mprj_analog_io\[5\]
+mprj_io_in\[12\]
+mprj_io_slow_sel\[12\]
+mprj_io_dm\[37\]
+mprj_io_analog_en\[12\]
+mprj_io_dm\[36\]
+mprj_io_analog_pol\[12\]
+mprj_io_inp_dis\[12\]
+mprj_io_analog_sel\[12\]
+mprj_io_dm\[38\]
+mprj_io_holdover\[12\]
+mprj_io_out\[12\]
+mprj_io_vtrip_sel\[12\]
+mprj_io_ib_mode_sel\[12\]
+mprj_io_oeb\[12\]
+mprj_io_one\[12\]
+$76
+mprj_analog_io\[6\]
+mprj_io_in\[13\]
+mprj_io_slow_sel\[13\]
+mprj_io_dm\[40\]
+mprj_io_analog_en\[13\]
+mprj_io_dm\[39\]
+mprj_io_analog_pol\[13\]
+mprj_io_inp_dis\[13\]
+mprj_io_analog_sel\[13\]
+mprj_io_dm\[41\]
+mprj_io_holdover\[13\]
+mprj_io_out\[13\]
+mprj_io_vtrip_sel\[13\]
+mprj_io_ib_mode_sel\[13\]
+mprj_io_oeb\[13\]
+mprj_io_one\[13\]
+$76
+mprj_analog_io\[7\]
+mprj_io_in\[14\]
+mprj_io_slow_sel\[14\]
+mprj_io_dm\[43\]
+mprj_io_analog_en\[14\]
+mprj_io_dm\[42\]
+mprj_io_analog_pol\[14\]
+mprj_io_inp_dis\[14\]
+mprj_io_analog_sel\[14\]
+mprj_io_dm\[44\]
+mprj_io_holdover\[14\]
+mprj_io_out\[14\]
+mprj_io_vtrip_sel\[14\]
+mprj_io_ib_mode_sel\[14\]
+mprj_io_oeb\[14\]
+mprj_io_one\[14\]
+$15
+
+#WR
+mprj_io_in\[24\]
+mprj_io_slow_sel\[24\]
+mprj_analog_io\[17\]
+mprj_io_dm\[73\]
+mprj_io_analog_en\[24\]
+mprj_io_dm\[72\]
+mprj_io_analog_pol\[24\]
+mprj_io_inp_dis\[24\]
+mprj_io_analog_sel\[24\]
+mprj_io_dm\[74\]
+mprj_io_holdover\[24\]
+mprj_io_out\[24\]
+mprj_io_vtrip_sel\[24\]
+mprj_io_ib_mode_sel\[24\]
+mprj_io_oeb\[24\]
+mprj_io_one\[24\]
+$160
+mprj_analog_io\[18\]
+mprj_io_in\[25\]
+mprj_io_slow_sel\[25\]
+mprj_io_dm\[76\]
+mprj_io_analog_en\[25\]
+mprj_io_dm\[75\]
+mprj_io_analog_pol\[25\]
+mprj_io_inp_dis\[25\]
+mprj_io_analog_sel\[25\]
+mprj_io_dm\[77\]
+mprj_io_holdover\[25\]
+mprj_io_out\[25\]
+mprj_io_vtrip_sel\[25\]
+mprj_io_ib_mode_sel\[25\]
+mprj_io_oeb\[25\]
+mprj_io_one\[25\]
+$28
+mprj_analog_io\[19\]
+mprj_io_in\[26\]
+mprj_io_slow_sel\[26\]
+mprj_io_dm\[79\]
+mprj_io_analog_en\[26\]
+mprj_io_dm\[78\]
+mprj_io_analog_pol\[26\]
+mprj_io_inp_dis\[26\]
+mprj_io_analog_sel\[26\]
+mprj_io_dm\[80\]
+mprj_io_holdover\[26\]
+mprj_io_out\[26\]
+mprj_io_vtrip_sel\[26\]
+mprj_io_ib_mode_sel\[26\]
+mprj_io_oeb\[26\]
+mprj_io_one\[26\]
+$28
+mprj_analog_io\[20\]
+mprj_io_in\[27\]
+mprj_io_slow_sel\[27\]
+mprj_io_dm\[82\]
+mprj_io_analog_en\[27\]
+mprj_io_dm\[81\]
+mprj_io_analog_pol\[27\]
+mprj_io_inp_dis\[27\]
+mprj_io_analog_sel\[27\]
+mprj_io_dm\[83\]
+mprj_io_holdover\[27\]
+mprj_io_out\[27\]
+mprj_io_vtrip_sel\[27\]
+mprj_io_ib_mode_sel\[27\]
+mprj_io_oeb\[27\]
+mprj_io_one\[27\]
+$28
+mprj_analog_io\[21\]
+mprj_io_in\[28\]
+mprj_io_slow_sel\[28\]
+mprj_io_dm\[85\]
+mprj_io_analog_en\[28\]
+mprj_io_dm\[84\]
+mprj_io_analog_pol\[28\]
+mprj_io_inp_dis\[28\]
+mprj_io_analog_sel\[28\]
+mprj_io_dm\[86\]
+mprj_io_holdover\[28\]
+mprj_io_out\[28\]
+mprj_io_vtrip_sel\[28\]
+mprj_io_ib_mode_sel\[28\]
+mprj_io_oeb\[28\]
+mprj_io_one\[28\]
+$28
+mprj_analog_io\[22\]
+mprj_io_in\[29\]
+mprj_io_slow_sel\[29\]
+mprj_io_dm\[88\]
+mprj_io_analog_en\[29\]
+mprj_io_dm\[87\]
+mprj_io_analog_pol\[29\]
+mprj_io_inp_dis\[29\]
+mprj_io_analog_sel\[29\]
+mprj_io_dm\[89\]
+mprj_io_holdover\[29\]
+mprj_io_out\[29\]
+mprj_io_vtrip_sel\[29\]
+mprj_io_ib_mode_sel\[29\]
+mprj_io_oeb\[29\]
+mprj_io_one\[29\]
+$28
+mprj_analog_io\[23\]
+mprj_io_in\[30\]
+mprj_io_slow_sel\[30\]
+mprj_io_dm\[91\]
+mprj_io_analog_en\[30\]
+mprj_io_dm\[90\]
+mprj_io_analog_pol\[30\]
+mprj_io_inp_dis\[30\]
+mprj_io_analog_sel\[30\]
+mprj_io_dm\[92\]
+mprj_io_holdover\[30\]
+mprj_io_out\[30\]
+mprj_io_vtrip_sel\[30\]
+mprj_io_ib_mode_sel\[30\]
+mprj_io_oeb\[30\]
+mprj_io_one\[30\]
+$28
+mprj_analog_io\[24\]
+mprj_io_in\[31\]
+mprj_io_slow_sel\[31\]
+mprj_io_dm\[94\]
+mprj_io_analog_en\[31\]
+mprj_io_dm\[93\]
+mprj_io_analog_pol\[31\]
+mprj_io_inp_dis\[31\]
+mprj_io_analog_sel\[31\]
+mprj_io_dm\[95\]
+mprj_io_holdover\[31\]
+mprj_io_out\[31\]
+mprj_io_vtrip_sel\[31\]
+mprj_io_ib_mode_sel\[31\]
+mprj_io_oeb\[31\]
+mprj_io_one\[31\]
+$122
+mprj_analog_io\[25\]
+mprj_io_in\[32\]
+mprj_io_slow_sel\[32\]
+mprj_io_dm\[97\]
+mprj_io_analog_en\[32\]
+mprj_io_dm\[96\]
+mprj_io_analog_pol\[32\]
+mprj_io_inp_dis\[32\]
+mprj_io_analog_sel\[32\]
+mprj_io_dm\[98\]
+mprj_io_holdover\[32\]
+mprj_io_out\[32\]
+mprj_io_vtrip_sel\[32\]
+mprj_io_ib_mode_sel\[32\]
+mprj_io_oeb\[32\]
+mprj_io_one\[32\]
+$28
+mprj_analog_io\[26\]
+mprj_io_in\[33\]
+mprj_io_slow_sel\[33\]
+mprj_io_dm\[100\]
+mprj_io_analog_en\[33\]
+mprj_io_dm\[99\]
+mprj_io_analog_pol\[33\]
+mprj_io_inp_dis\[33\]
+mprj_io_analog_sel\[33\]
+mprj_io_dm\[101\]
+mprj_io_holdover\[33\]
+mprj_io_out\[33\]
+mprj_io_vtrip_sel\[33\]
+mprj_io_ib_mode_sel\[33\]
+mprj_io_oeb\[33\]
+mprj_io_one\[33\]
+$28
+mprj_analog_io\[27\]
+mprj_io_in\[34\]
+mprj_io_slow_sel\[34\]
+mprj_io_dm\[103\]
+mprj_io_analog_en\[34\]
+mprj_io_dm\[102\]
+mprj_io_analog_pol\[34\]
+mprj_io_inp_dis\[34\]
+mprj_io_analog_sel\[34\]
+mprj_io_dm\[104\]
+mprj_io_holdover\[34\]
+mprj_io_out\[34\]
+mprj_io_vtrip_sel\[34\]
+mprj_io_ib_mode_sel\[34\]
+mprj_io_oeb\[34\]
+mprj_io_one\[34\]
+$28
+mprj_analog_io\[28\]
+mprj_io_in\[35\]
+mprj_io_slow_sel\[35\]
+mprj_io_dm\[106\]
+mprj_io_analog_en\[35\]
+mprj_io_dm\[105\]
+mprj_io_analog_pol\[35\]
+mprj_io_inp_dis\[35\]
+mprj_io_analog_sel\[35\]
+mprj_io_dm\[107\]
+mprj_io_holdover\[35\]
+mprj_io_out\[35\]
+mprj_io_vtrip_sel\[35\]
+mprj_io_ib_mode_sel\[35\]
+mprj_io_oeb\[35\]
+mprj_io_one\[35\]
+$28
+mprj_io_in\[36\]
+mprj_io_slow_sel\[36\]
+mprj_io_dm\[109\]
+mprj_io_analog_en\[36\]
+mprj_io_dm\[108\]
+mprj_io_analog_pol\[36\]
+mprj_io_inp_dis\[36\]
+mprj_io_analog_sel\[36\]
+mprj_io_dm\[110\]
+mprj_io_holdover\[36\]
+mprj_io_out\[36\]
+mprj_io_vtrip_sel\[36\]
+mprj_io_ib_mode_sel\[36\]
+mprj_io_oeb\[36\]
+mprj_io_one\[36\]
+$28
+mprj_io_in\[37\]
+mprj_io_slow_sel\[37\]
+mprj_io_dm\[112\]
+mprj_io_analog_en\[37\]
+mprj_io_dm\[111\]
+mprj_io_analog_pol\[37\]
+mprj_io_inp_dis\[37\]
+mprj_io_analog_sel\[37\]
+mprj_io_dm\[113\]
+mprj_io_holdover\[37\]
+mprj_io_out\[37\]
+mprj_io_vtrip_sel\[37\]
+mprj_io_ib_mode_sel\[37\]
+mprj_io_oeb\[37\]
+mprj_io_one\[37\]
+$117

openlane/caravan_core/interactive.tcl

@@ -0,0 +1,165 @@
+package require openlane
+variable SCRIPT_DIR [file dirname [file normalize [info script]]]
+# prep -ignore_mismatches -design $SCRIPT_DIR -tag techlef_for_antenna -overwrite -verbose 0
+prep -ignore_mismatches -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 0
+
+set save_path $::env(CARAVEL_ROOT)
+
+################   Synthesis   ################
+run_synthesis
+# set_netlist $::env(DESIGN_DIR)/synth_configuration/caravel_core.v
+# set ::env(CURRENT_SDC) $::env(DESIGN_DIR)/sdc_files/base.sdc
+
+################   Floorplan   ################
+init_floorplan
+apply_def_template
+
+# Placing the macros in the core area and marking them fixed
+file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+manual_macro_placement -f
+
+# Tap/Decap insertion
+tap_decap_or
+
+# 
+set ::env(GRT_OBS) "\
+    pwell 0 4195 3165 4767, \
+    nwell 0 4195 3165 4767, \
+    li1 0 4195 3165 4767, \
+    met1 0 4195 3165 4767, \
+    met2 0 4195 3165 4767, \
+    met3 0 4195 3165 4767, \
+    met4 0 4195 3165 4767, \
+    met5 0 4195 3165 4767, \
+    met5 59.52 1183.09 3103.58 4703.09, \
+    met5 1943 1153 1944 1155, \
+    met5 1815 1130 1816 1132 \
+"
+add_route_obs
+
+run_power_grid_generation
+
+# run_magic
+# save_final_views
+# save_views -save_path .. -tag $::env(OPENLANE_RUN_TAG)
+################   placement   ################
+set ::env(PL_TARGET_DENSITY) 0.20
+run_placement
+
+################   CTS   ################
+run_cts
+run_resizer_timing
+
+################ Global Routing Optmization  ################
+run_resizer_design_routing
+run_resizer_timing_routing
+
+##   Placement again  ##
+set ::env(PL_TARGET_DENSITY) 0.25
+run_placement
+run_cts
+
+run_resizer_timing
+
+##  Routing Optmization  ##
+run_resizer_design_routing
+run_resizer_timing_routing
+
+################ Place and route on the optmized netlist ################
+set ::env(PL_TARGET_DENSITY) 0.27
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(GLB_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
+run_placement
+run_cts 
+
+# Adding met4/5 routing obstructions over the the RAMs and housekeeping to prevent routing DRCs
+set ::env(GRT_OBS) "\
+    met5 90 175.0 496.18 612.92, \
+    met5 582.00 175.00 988.18 612.92, \
+    met5 1800 125.00 2206.18 562.92, \
+    met5 2650 190 3060.23 740.95, \
+    met4 90 175.0 496.18 612.92, \
+    met4 582.00 175.00 988.18 612.92, \
+    met4 1800 125.00 2206.18 562.92, \
+    met4 2650 190 3060.23 740.95 \
+"
+# adding hk_serial_clock and hk_serial_load as clocks after CTS by changing
+# the sdc file to another one which they are defined as clocks in it. 
+set ::env(CURRENT_SDC) $::env(DESIGN_DIR)/sdc_files/base_2.sdc
+
+# set ::env(GRT_ALLOW_CONGESTION) 0
+run_routing
+################   RCX sta    ################
+run_parasitics_sta
+
+################   IR drop    ################
+# run_irdrop_report
+
+################   Antenna check    ################
+run_antenna_check
+
+################   magic    ################
+run_magic
+
+################   LVS    ################
+# run_magic_spice_export;
+# run_lvs;
+
+###############   DRC    ################
+# run_magic_drc
+
+################   Saving views and reports    ################
+save_final_views
+save_views -save_path .. -tag $::env(OPENLANE_RUN_TAG)
+## 
+    calc_total_runtime
+    save_state
+    generate_final_summary_report
+    check_timing_violations
+    if { [info exists arg_values(-save_path)]\
+        && $arg_values(-save_path) != "" } {
+        set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+    } else {
+        set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+    }
+    if {[info exists flags_map(-run_hooks)]} {
+        run_post_run_hooks
+    }
+    puts_success "Flow complete."
+    show_warnings "Note that the following warnings have been generated:"
+
+################   Copying reports    ################
+set run_dir $::env(DESIGN_DIR)/runs/$::env(RUN_TAG)
+## copying signoff reports
+set sourceDir $run_dir/reports/signoff
+set targetDir $::env(CARAVEL_ROOT)/signoff/$::env(DESIGN_NAME)/openlane-signoff/
+foreach f [glob -directory $sourceDir -nocomplain *] {
+    file copy -force $f $targetDir
+}
+## copying spefs
+set sourceDir $run_dir/results/routing/mca/spef/
+set targetDir $::env(CARAVEL_ROOT)/signoff/$::env(DESIGN_NAME)/openlane-signoff/spef/
+foreach f [glob -directory $sourceDir -nocomplain *] {
+    file copy -force $f $targetDir
+}
+## copying sdf
+set sourceDir $run_dir/results/routing/mca/sdf/nom/
+set targetDir $::env(CARAVEL_ROOT)/signoff/$::env(DESIGN_NAME)/openlane-signoff/sdf/nom/
+foreach f [glob -directory $sourceDir -nocomplain *] {
+    file copy -force $f $targetDir
+}
+set sourceDir $run_dir/results/routing/mca/sdf/min/
+set targetDir $::env(CARAVEL_ROOT)/signoff/$::env(DESIGN_NAME)/openlane-signoff/sdf/min/
+foreach f [glob -directory $sourceDir -nocomplain *] {
+    file copy -force $f $targetDir
+}
+set sourceDir $run_dir/results/routing/mca/sdf/max/
+set targetDir $::env(CARAVEL_ROOT)/signoff/$::env(DESIGN_NAME)/openlane-signoff/sdf/max/
+foreach f [glob -directory $sourceDir -nocomplain *] {
+    file copy -force $f $targetDir
+}
+## coping other files
+set flist [list $run_dir/config.tcl $run_dir/openlane.log $run_dir/runtime.yaml $run_dir/warnings.log]
+file copy -force {*}$flist $::env(CARAVEL_ROOT)/signoff/$::env(DESIGN_NAME)/

openlane/caravan_core/pdn_configuration/pdn.tcl

@@ -0,0 +1,227 @@
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl
+set_global_connections
+
+set secondary []
+foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
+    if { $vdd != $::env(VDD_NET)} {
+        lappend secondary $vdd
+
+        set db_net [[ord::get_db_block] findNet $vdd]
+        if {$db_net == "NULL"} {
+            set net [odb::dbNet_create [ord::get_db_block] $vdd]
+            $net setSpecial
+            $net setSigType "POWER"
+        }
+    }
+
+    if { $gnd != $::env(GND_NET)} {
+        lappend secondary $gnd
+
+        set db_net [[ord::get_db_block] findNet $gnd]
+        if {$db_net == "NULL"} {
+            set net [odb::dbNet_create [ord::get_db_block] $gnd]
+            $net setSpecial
+            $net setSigType "GROUND"
+        }
+    }
+}
+
+set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
+    -secondary_power $secondary
+
+    define_pdn_grid \
+        -name stdcell_grid \
+        -starts_with POWER \
+        -voltage_domain CORE \
+        -pins "met4 met5"
+
+####  core ring   ####
+add_pdn_stripe \
+    -grid stdcell_grid \
+    -layer met4 \
+    -width 5 \
+    -pitch 120 \
+    -offset 3.3 \
+    -spacing 1 \
+    -number_of_straps 1 \
+    -nets "vssd vccd vccd1 vssd1 vssd2 vccd2 vccd vssd" \
+    -starts_with POWER
+add_pdn_stripe \
+    -grid stdcell_grid \
+    -layer met4 \
+    -width 5 \
+    -pitch 120 \
+    -offset 3097.56 \
+    -spacing 1 \
+    -number_of_straps 1 \
+    -nets "vccd vssd vccd2 vssd2 vssd1 vccd1 vccd vssd" \
+    -starts_with POWER
+add_pdn_stripe \
+    -grid stdcell_grid \
+    -layer met5 \
+    -width 16 \
+    -pitch 120 \
+    -offset 5 \
+    -spacing 1.6 \
+    -number_of_straps 1 \
+    -nets "vccd vssd vccd1 vssd1 vssd2 vccd2" \
+    -starts_with POWER
+add_pdn_stripe \
+    -grid stdcell_grid \
+    -layer met5 \
+    -width 10 \
+    -pitch 146 \
+    -offset 1045.5 \
+    -spacing 1.6 \
+    -number_of_straps 1 \
+    -nets "vccd vccd2 vccd1 vssd vssd1 vssd2 vdda1 vssa1 vdda2 vssa2" \
+    -starts_with POWER
+
+####  std cells stripes  ####    
+    #Metal4
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer met4 \
+        -width 6.4 \
+        -pitch 100 \
+        -offset 117 \
+        -spacing 1.2 \
+        -nets "vccd vssd" \
+        -starts_with POWER
+
+    #Metal5
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer met5 \
+        -width 6.4 \
+        -pitch 120 \
+        -offset 181 \
+        -spacing 2.4 \
+        -nets "vccd vssd" \
+        -starts_with POWER
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer met5 \
+        -width 14.4 \
+        -pitch 120 \
+        -offset 239 \
+        -spacing 2.4 \
+        -number_of_straps 7 \
+        -nets "vccd vssd" \
+        -starts_with POWER
+
+####  mgmt_protect macros stripes  ####
+    #Metal4
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer met4 \
+        -width 4.8 \
+        -pitch 50 \
+        -offset 843 \
+        -spacing 3.2 \
+        -number_of_straps 2 \
+        -nets "vccd2 vssd2" \
+        -starts_with POWER
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer met4 \
+        -width 4.8 \
+        -pitch 100 \
+        -offset 1268 \
+        -spacing 3.2 \
+        -number_of_straps 3 \
+        -nets "vccd1 vssd1" \
+        -starts_with POWER
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer met4 \
+        -width 4.8 \
+        -pitch 40 \
+        -offset 1836 \
+        -spacing 3.2 \
+        -number_of_straps 2 \
+        -nets "vdda1 vssa1 vdda2 vssa2" \
+        -starts_with POWER
+
+#### user_id_programming
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer met4 \
+        -width 1.6 \
+        -pitch 120 \
+        -offset 2958.855 \
+        -spacing 21.18 \
+        -number_of_straps 1 \
+        -nets "vccd vssd" \
+        -starts_with POWER
+
+####  vssio and vddio stripes  ####
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer met5 \
+        -width 5 \
+        -pitch 14 \
+        -offset 137 \
+        -spacing 2 \
+        -number_of_straps 2 \
+        -nets "vddio vssio" \
+        -starts_with POWER
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer met4 \
+        -width 4.8 \
+        -pitch 386 \
+        -offset 647 \
+        -spacing 2 \
+        -number_of_straps 2 \
+        -nets "vddio vssio" \
+        -starts_with POWER
+
+
+add_pdn_connect \
+    -grid stdcell_grid \
+    -layers "met4 met5"
+
+# Adds the standard cell rails if enabled.
+if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer $::env(FP_PDN_RAIL_LAYER) \
+        -width $::env(FP_PDN_RAIL_WIDTH) \
+        -followpins \
+        -starts_with POWER
+
+    add_pdn_connect \
+        -grid stdcell_grid \
+        -layers "$::env(FP_PDN_RAIL_LAYER) met4"
+}
+
+define_pdn_grid \
+    -macro \
+    -default \
+    -name macro \
+    -starts_with POWER \
+    -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect \
+    -grid macro \
+    -layers "met3 met4"
+
+add_pdn_connect \
+    -grid macro \
+    -layers "met4 met5"
+

openlane/caravan_core/scripts/antenna_3.tcl

@@ -0,0 +1,4 @@
+repair_antennas "$::env(DIODE_CELL)" -iterations $::env(GRT_ANT_ITERS) -ratio_margin 25
+check_placement
+
+write

openlane/caravan_core/scripts/pin_order.py

@@ -0,0 +1,18 @@
+for i in range(0,38):
+    if i in range(7,36):
+      print(f"mprj_analog_io\[" + str(i-7) + "\]")                                                                                                                                                                                
+    print(f"mprj_io_in\[" + str(i) + "\]")
+    print(f"mprj_io_slow_sel\[" + str(i) + "\]")                                                                                                                                                                       
+    print(f"mprj_io_dm\[" + str(i*3+1) + "\]") 
+    print(f"mprj_io_analog_en\[" + str(i) + "\]") 
+    print(f"mprj_io_dm\[" + str(i*3+0) + "\]")
+    print(f"mprj_io_analog_pol\[" + str(i) + "\]") 
+    print(f"mprj_io_inp_dis\[" + str(i) + "\]") 
+    print(f"mprj_io_analog_sel\[" + str(i) + "\]") 
+    print(f"mprj_io_dm\[" + str(i*3+2) + "\]")
+    print(f"mprj_io_holdover\[" + str(i) + "\]") 
+    print(f"mprj_io_out\[" + str(i) + "\]") 
+    print(f"mprj_io_vtrip_sel\[" + str(i) + "\]")                                                                                                                                                                   
+    print(f"mprj_io_ib_mode_sel\[" + str(i) + "\]")                                                                                                                                                                    
+    print(f"mprj_io_oeb\[" + str(i) + "\]")                                                                                                                                                                       
+    print(f"mprj_io_one\[" + str(i) + "\]") 

openlane/caravan_core/sdc_files/base.sdc

@@ -6,7 +6,7 @@
 create_clock -name clk -period 18 [get_pins {clock_ctrl/core_clk}] 
 # create_clock -name clk -period 25 [get_ports {clock_core}] 
 
-set_clock_uncertainty 0.5 [get_clocks {clk}] 
+set_clock_uncertainty 0.55 [get_clocks {clk}] 
 
 set_propagated_clock [get_clocks {clk}]
 

openlane/caravan_core/synth_configuration/drc_exclude.cells

@@ -0,0 +1,211 @@
+sky130_fd_sc_hd__a2111oi_0
+sky130_fd_sc_hd__a21boi_0
+sky130_fd_sc_hd__and2_0
+sky130_fd_sc_hd__buf_16
+sky130_fd_sc_hd__clkdlybuf4s15_1
+sky130_fd_sc_hd__clkdlybuf4s18_1
+sky130_fd_sc_hd__fa_4
+sky130_fd_sc_hd__lpflow_bleeder_1
+sky130_fd_sc_hd__lpflow_clkbufkapwr_1
+sky130_fd_sc_hd__lpflow_clkbufkapwr_16
+sky130_fd_sc_hd__lpflow_clkbufkapwr_2
+sky130_fd_sc_hd__lpflow_clkbufkapwr_4
+sky130_fd_sc_hd__lpflow_clkbufkapwr_8
+sky130_fd_sc_hd__lpflow_clkinvkapwr_1
+sky130_fd_sc_hd__lpflow_clkinvkapwr_16
+sky130_fd_sc_hd__lpflow_clkinvkapwr_2
+sky130_fd_sc_hd__lpflow_clkinvkapwr_4
+sky130_fd_sc_hd__lpflow_clkinvkapwr_8
+sky130_fd_sc_hd__lpflow_decapkapwr_12
+sky130_fd_sc_hd__lpflow_decapkapwr_3
+sky130_fd_sc_hd__lpflow_decapkapwr_4
+sky130_fd_sc_hd__lpflow_decapkapwr_6
+sky130_fd_sc_hd__lpflow_decapkapwr_8
+sky130_fd_sc_hd__lpflow_inputiso0n_1
+sky130_fd_sc_hd__lpflow_inputiso0p_1
+sky130_fd_sc_hd__lpflow_inputiso1n_1
+sky130_fd_sc_hd__lpflow_inputiso1p_1
+sky130_fd_sc_hd__lpflow_inputisolatch_1
+sky130_fd_sc_hd__lpflow_isobufsrc_1
+sky130_fd_sc_hd__lpflow_isobufsrc_16
+sky130_fd_sc_hd__lpflow_isobufsrc_2
+sky130_fd_sc_hd__lpflow_isobufsrc_4
+sky130_fd_sc_hd__lpflow_isobufsrc_8
+sky130_fd_sc_hd__lpflow_isobufsrckapwr_16
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4
+sky130_fd_sc_hd__mux4_4
+sky130_fd_sc_hd__o21ai_0
+sky130_fd_sc_hd__o311ai_0
+sky130_fd_sc_hd__or2_0
+sky130_fd_sc_hd__probe_p_8
+sky130_fd_sc_hd__probec_p_8
+sky130_fd_sc_hd__xor3_1
+sky130_fd_sc_hd__xor3_2
+sky130_fd_sc_hd__xor3_4
+sky130_fd_sc_hd__xnor3_1
+sky130_fd_sc_hd__xnor3_2
+sky130_fd_sc_hd__xnor3_4
+sky130_fd_sc_hd__a2111oi_1
+sky130_fd_sc_hd__a211o_1
+sky130_fd_sc_hd__a211oi_1
+sky130_fd_sc_hd__a2111o_1
+sky130_fd_sc_hd__a21bo_1
+sky130_fd_sc_hd__a21boi_1
+sky130_fd_sc_hd__a21o_1
+sky130_fd_sc_hd__a21oi_1
+sky130_fd_sc_hd__a221o_1
+sky130_fd_sc_hd__a221oi_1
+sky130_fd_sc_hd__a222oi_1
+sky130_fd_sc_hd__a22o_1
+sky130_fd_sc_hd__a22oi_1
+sky130_fd_sc_hd__a2bb2o_1
+sky130_fd_sc_hd__a2bb2oi_1
+sky130_fd_sc_hd__a311o_1
+sky130_fd_sc_hd__a311oi_1
+sky130_fd_sc_hd__a2111o_1
+sky130_fd_sc_hd__a21bo_1
+sky130_fd_sc_hd__a21boi_1
+sky130_fd_sc_hd__a21o_1
+sky130_fd_sc_hd__a21oi_1
+sky130_fd_sc_hd__a221o_1
+sky130_fd_sc_hd__a221oi_1
+sky130_fd_sc_hd__a222oi_1
+sky130_fd_sc_hd__a22o_1
+sky130_fd_sc_hd__a22oi_1
+sky130_fd_sc_hd__a2bb2o_1
+sky130_fd_sc_hd__a2bb2oi_1
+sky130_fd_sc_hd__a311o_1
+sky130_fd_sc_hd__a311oi_1
+sky130_fd_sc_hd__a31o_1
+sky130_fd_sc_hd__a31oi_1
+sky130_fd_sc_hd__a32o_1
+sky130_fd_sc_hd__a32oi_1
+sky130_fd_sc_hd__a41o_1
+sky130_fd_sc_hd__a41oi_1
+sky130_fd_sc_hd__and2_1
+sky130_fd_sc_hd__and2b_1
+sky130_fd_sc_hd__and3_1
+sky130_fd_sc_hd__and3b_1
+sky130_fd_sc_hd__and4_1
+sky130_fd_sc_hd__and4b_1
+sky130_fd_sc_hd__and4bb_1
+sky130_fd_sc_hd__dfbbn_1
+sky130_fd_sc_hd__dfbbp_1
+sky130_fd_sc_hd__dfrbp_1
+sky130_fd_sc_hd__dfrtn_1
+sky130_fd_sc_hd__dfrtp_1
+sky130_fd_sc_hd__dfsbp_1
+sky130_fd_sc_hd__dfstp_1
+sky130_fd_sc_hd__dfxbp_1
+sky130_fd_sc_hd__dfxtp_1
+sky130_fd_sc_hd__ebufn_1
+sky130_fd_sc_hd__inv_1
+sky130_fd_sc_hd__nand2_1
+sky130_fd_sc_hd__nand2b_1
+sky130_fd_sc_hd__nand3_1
+sky130_fd_sc_hd__nand3b_1
+sky130_fd_sc_hd__nand4_1
+sky130_fd_sc_hd__nand4b_1
+sky130_fd_sc_hd__nand4bb_1
+sky130_fd_sc_hd__nor2_1
+sky130_fd_sc_hd__nor2b_1
+sky130_fd_sc_hd__nor3_1
+sky130_fd_sc_hd__nor3b_1
+sky130_fd_sc_hd__nor4_1
+sky130_fd_sc_hd__nor4b_1
+sky130_fd_sc_hd__nor4bb_1
+sky130_fd_sc_hd__o2111a_1
+sky130_fd_sc_hd__o2111ai_1
+sky130_fd_sc_hd__o211a_1
+sky130_fd_sc_hd__o211ai_1
+sky130_fd_sc_hd__o21a_1
+sky130_fd_sc_hd__o21ai_1
+sky130_fd_sc_hd__o21ba_1
+sky130_fd_sc_hd__o21bai_1
+sky130_fd_sc_hd__o221a_1
+sky130_fd_sc_hd__o221ai_1
+sky130_fd_sc_hd__o22a_1
+sky130_fd_sc_hd__o22ai_1
+sky130_fd_sc_hd__o2bb2a_1
+sky130_fd_sc_hd__o2bb2ai_1
+sky130_fd_sc_hd__o311a_1
+sky130_fd_sc_hd__o311ai_1
+sky130_fd_sc_hd__o31a_1
+sky130_fd_sc_hd__o31ai_1
+sky130_fd_sc_hd__o32a_1
+sky130_fd_sc_hd__o32ai_1
+sky130_fd_sc_hd__o41a_1
+sky130_fd_sc_hd__o41ai_1
+sky130_fd_sc_hd__or2_1
+sky130_fd_sc_hd__or2b_1
+sky130_fd_sc_hd__or3_1
+sky130_fd_sc_hd__or3b_1
+sky130_fd_sc_hd__or4_1
+sky130_fd_sc_hd__or4b_1
+sky130_fd_sc_hd__or4bb_1
+sky130_fd_sc_hd__xnor2_1
+sky130_fd_sc_hd__xor2_1
+sky130_fd_sc_hd__or2
+sky130_fd_sc_hd__or2_0
+sky130_fd_sc_hd__or2_1
+sky130_fd_sc_hd__or2_2
+sky130_fd_sc_hd__or2_4
+sky130_fd_sc_hd__or2b
+sky130_fd_sc_hd__or2b_1
+sky130_fd_sc_hd__or2b_2
+sky130_fd_sc_hd__or2b_4
+sky130_fd_sc_hd__or3
+sky130_fd_sc_hd__or3_1
+sky130_fd_sc_hd__or3_2
+sky130_fd_sc_hd__or3_4
+sky130_fd_sc_hd__or3b
+sky130_fd_sc_hd__or3b_1
+sky130_fd_sc_hd__or3b_2
+sky130_fd_sc_hd__or3b_4
+sky130_fd_sc_hd__or4
+sky130_fd_sc_hd__or4_1
+sky130_fd_sc_hd__or4_2
+sky130_fd_sc_hd__or4_4
+sky130_fd_sc_hd__or4b
+sky130_fd_sc_hd__or4b_1
+sky130_fd_sc_hd__or4b_2
+sky130_fd_sc_hd__or4b_4
+sky130_fd_sc_hd__or4bb
+sky130_fd_sc_hd__or4bb_1
+sky130_fd_sc_hd__or4bb_2
+sky130_fd_sc_hd__or4bb_4
+sky130_fd_sc_hd__inv_2
+sky130_fd_sc_hd__a21boi_0
+sky130_fd_sc_hd__buf_1
+sky130_fd_sc_hd__buf_2
+sky130_fd_sc_hd__bufbuf_1
+sky130_fd_sc_hd__bufinv_1
+sky130_fd_sc_hd__clkbuf_1
+sky130_fd_sc_hd__clkbuf_2
+sky130_fd_sc_hd__clkdlybuf4s15_1
+sky130_fd_sc_hd__clkdlybuf4s18_1
+sky130_fd_sc_hd__clkdlybuf4s25_1
+sky130_fd_sc_hd__clkdlybuf4s25_2
+sky130_fd_sc_hd__clkdlybuf4s50_1
+sky130_fd_sc_hd__clkdlybuf4s50_2
+sky130_fd_sc_hd__clkinv_1
+sky130_fd_sc_hd__dlygate4sd1_1
+sky130_fd_sc_hd__dlygate4sd2_1
+sky130_fd_sc_hd__dlygate4sd2_2
+sky130_fd_sc_hd__dlygate4sd3_1
+sky130_fd_sc_hd__dlygate4sd3_2
+sky130_fd_sc_hd__dlymetal6s2s_1
+sky130_fd_sc_hd__dlymetal6s4s_1
+sky130_fd_sc_hd__dlymetal6s4s_2
+sky130_fd_sc_hd__dlymetal6s6s_1
+sky130_fd_sc_hd__dlymetal6s6s_2
+sky130_fd_sc_hd__a22oi_4
+sky130_fd_sc_hd__a22oi_2
+sky130_fd_sc_hd__a22oi_1
+sky130_fd_sc_hd__and2_2

openlane/caravan_core/synth_configuration/no_synth.cells

@@ -0,0 +1,232 @@
+sky130_fd_sc_hd__clkbuf_1
+sky130_fd_sc_hd__buf_1
+sky130_fd_sc_hd__clkbuf_16
+sky130_fd_sc_hd__clkbuf_2
+sky130_fd_sc_hd__clkbuf_4
+sky130_fd_sc_hd__clkbuf_8
+sky130_fd_sc_hd__clkdlybuf4s15_1
+sky130_fd_sc_hd__clkdlybuf4s15_2
+sky130_fd_sc_hd__clkdlybuf4s18_1
+sky130_fd_sc_hd__clkdlybuf4s18_2
+sky130_fd_sc_hd__clkdlybuf4s25_1
+sky130_fd_sc_hd__clkdlybuf4s25_2
+sky130_fd_sc_hd__clkdlybuf4s50_1
+sky130_fd_sc_hd__clkdlybuf4s50_2
+sky130_fd_sc_hd__clkinv_1
+sky130_fd_sc_hd__clkinv_16
+sky130_fd_sc_hd__clkinv_2
+sky130_fd_sc_hd__clkinv_4
+sky130_fd_sc_hd__clkinv_8
+sky130_fd_sc_hd__clkinvlp_2
+sky130_fd_sc_hd__clkinvlp_4
+sky130_fd_sc_hd__decap_12
+sky130_fd_sc_hd__decap_3
+sky130_fd_sc_hd__decap_4
+sky130_fd_sc_hd__decap_6
+sky130_fd_sc_hd__decap_8
+sky130_fd_sc_hd__diode_2
+sky130_fd_sc_hd__dlclkp_1
+sky130_fd_sc_hd__dlclkp_2
+sky130_fd_sc_hd__dlclkp_4
+sky130_fd_sc_hd__dlrbn_1
+sky130_fd_sc_hd__dlrbn_2
+sky130_fd_sc_hd__dlrbp_1
+sky130_fd_sc_hd__dlrbp_2
+sky130_fd_sc_hd__dlrtn_1
+sky130_fd_sc_hd__dlrtn_2
+sky130_fd_sc_hd__dlrtn_4
+sky130_fd_sc_hd__dlrtp_1
+sky130_fd_sc_hd__dlrtp_2
+sky130_fd_sc_hd__dlrtp_4
+sky130_fd_sc_hd__dlxbn_1
+sky130_fd_sc_hd__dlxbn_2
+sky130_fd_sc_hd__dlxbp_1
+sky130_fd_sc_hd__dlygate4sd1_1
+sky130_fd_sc_hd__dlygate4sd2_1
+sky130_fd_sc_hd__dlygate4sd3_1
+sky130_fd_sc_hd__dlymetal6s2s_1
+sky130_fd_sc_hd__dlymetal6s4s_1
+sky130_fd_sc_hd__dlymetal6s6s_1
+sky130_fd_sc_hd__edfxbp_1
+sky130_fd_sc_hd__edfxtp_1
+sky130_fd_sc_hd__einvn_0
+sky130_fd_sc_hd__einvn_1
+sky130_fd_sc_hd__einvn_2
+sky130_fd_sc_hd__einvn_4
+sky130_fd_sc_hd__einvn_8
+sky130_fd_sc_hd__einvp_1
+sky130_fd_sc_hd__einvp_2
+sky130_fd_sc_hd__einvp_4
+sky130_fd_sc_hd__einvp_8
+sky130_fd_sc_hd__fah_1
+sky130_fd_sc_hd__fahcin_1
+sky130_fd_sc_hd__fahcon_1
+sky130_fd_sc_hd__ha_1
+sky130_fd_sc_hd__ha_2
+sky130_fd_sc_hd__ha_4
+sky130_fd_sc_hd__macro_sparecell
+sky130_fd_sc_hd__maj3_1
+sky130_fd_sc_hd__maj3_2
+sky130_fd_sc_hd__maj3_4
+sky130_fd_sc_hd__mux2i_1
+sky130_fd_sc_hd__mux2i_2
+sky130_fd_sc_hd__mux2i_4
+sky130_fd_sc_hd__sdfbbn_1
+sky130_fd_sc_hd__sdfbbn_2
+sky130_fd_sc_hd__sdfbbp_1
+sky130_fd_sc_hd__sdfrbp_1
+sky130_fd_sc_hd__sdfrbp_2
+sky130_fd_sc_hd__sdfrtn_1
+sky130_fd_sc_hd__sdfrtp_1
+sky130_fd_sc_hd__sdfrtp_2
+sky130_fd_sc_hd__sdfrtp_4
+sky130_fd_sc_hd__sdfsbp_1
+sky130_fd_sc_hd__sdfsbp_2
+sky130_fd_sc_hd__sdfstp_1
+sky130_fd_sc_hd__sdfstp_2
+sky130_fd_sc_hd__sdfstp_4
+sky130_fd_sc_hd__sdfxbp_1
+sky130_fd_sc_hd__sdfxbp_2
+sky130_fd_sc_hd__sdfxtp_1
+sky130_fd_sc_hd__sdfxtp_2
+sky130_fd_sc_hd__sdfxtp_4
+sky130_fd_sc_hd__sdlclkp_1
+sky130_fd_sc_hd__sdlclkp_2
+sky130_fd_sc_hd__sdlclkp_4
+sky130_fd_sc_hd__sedfxbp_1
+sky130_fd_sc_hd__sedfxbp_2
+sky130_fd_sc_hd__sedfxtp_1
+sky130_fd_sc_hd__sedfxtp_2
+sky130_fd_sc_hd__sedfxtp_4
+sky130_fd_sc_hd__a2111oi_1
+sky130_fd_sc_hd__a211o_1
+sky130_fd_sc_hd__a211oi_1
+sky130_fd_sc_hd__a2111o_1
+sky130_fd_sc_hd__a21bo_1
+sky130_fd_sc_hd__a21boi_1
+sky130_fd_sc_hd__a21o_1
+sky130_fd_sc_hd__a21oi_1
+sky130_fd_sc_hd__a221o_1
+sky130_fd_sc_hd__a221oi_1
+sky130_fd_sc_hd__a222oi_1
+sky130_fd_sc_hd__a22o_1
+sky130_fd_sc_hd__a22oi_1
+sky130_fd_sc_hd__a2bb2o_1
+sky130_fd_sc_hd__a2bb2oi_1
+sky130_fd_sc_hd__a311o_1
+sky130_fd_sc_hd__a311oi_1
+sky130_fd_sc_hd__a2111o_1
+sky130_fd_sc_hd__a21bo_1
+sky130_fd_sc_hd__a21boi_1
+sky130_fd_sc_hd__a21o_1
+sky130_fd_sc_hd__a21oi_1
+sky130_fd_sc_hd__a221o_1
+sky130_fd_sc_hd__a221oi_1
+sky130_fd_sc_hd__a222oi_1
+sky130_fd_sc_hd__a22o_1
+sky130_fd_sc_hd__a22oi_1
+sky130_fd_sc_hd__a2bb2o_1
+sky130_fd_sc_hd__a2bb2oi_1
+sky130_fd_sc_hd__a311o_1
+sky130_fd_sc_hd__a311oi_1
+sky130_fd_sc_hd__a31o_1
+sky130_fd_sc_hd__a31oi_1
+sky130_fd_sc_hd__a32o_1
+sky130_fd_sc_hd__a32oi_1
+sky130_fd_sc_hd__a41o_1
+sky130_fd_sc_hd__a41oi_1
+sky130_fd_sc_hd__and2_1
+sky130_fd_sc_hd__and2b_1
+sky130_fd_sc_hd__and3_1
+sky130_fd_sc_hd__and3b_1
+sky130_fd_sc_hd__and4_1
+sky130_fd_sc_hd__and4b_1
+sky130_fd_sc_hd__and4bb_1
+sky130_fd_sc_hd__dfbbn_1
+sky130_fd_sc_hd__dfbbp_1
+sky130_fd_sc_hd__dfrbp_1
+sky130_fd_sc_hd__dfrtn_1
+sky130_fd_sc_hd__dfrtp_1
+sky130_fd_sc_hd__dfsbp_1
+sky130_fd_sc_hd__dfstp_1
+sky130_fd_sc_hd__dfxbp_1
+sky130_fd_sc_hd__dfxtp_1
+sky130_fd_sc_hd__ebufn_1
+sky130_fd_sc_hd__inv_1
+sky130_fd_sc_hd__nand2_1
+sky130_fd_sc_hd__nand2b_1
+sky130_fd_sc_hd__nand3_1
+sky130_fd_sc_hd__nand3b_1
+sky130_fd_sc_hd__nand4_1
+sky130_fd_sc_hd__nand4b_1
+sky130_fd_sc_hd__nand4bb_1
+sky130_fd_sc_hd__nor2_1
+sky130_fd_sc_hd__nor2b_1
+sky130_fd_sc_hd__nor3_1
+sky130_fd_sc_hd__nor3b_1
+sky130_fd_sc_hd__nor4_1
+sky130_fd_sc_hd__nor4b_1
+sky130_fd_sc_hd__nor4bb_1
+sky130_fd_sc_hd__o2111a_1
+sky130_fd_sc_hd__o2111ai_1
+sky130_fd_sc_hd__o211a_1
+sky130_fd_sc_hd__o211ai_1
+sky130_fd_sc_hd__o21a_1
+sky130_fd_sc_hd__o21ai_1
+sky130_fd_sc_hd__o21ba_1
+sky130_fd_sc_hd__o21bai_1
+sky130_fd_sc_hd__o221a_1
+sky130_fd_sc_hd__o221ai_1
+sky130_fd_sc_hd__o22a_1
+sky130_fd_sc_hd__o22ai_1
+sky130_fd_sc_hd__o2bb2a_1
+sky130_fd_sc_hd__o2bb2ai_1
+sky130_fd_sc_hd__o311a_1
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+sky130_fd_sc_hd__o32a_1
+sky130_fd_sc_hd__o32ai_1
+sky130_fd_sc_hd__o41a_1
+sky130_fd_sc_hd__o41ai_1
+sky130_fd_sc_hd__or2_1
+sky130_fd_sc_hd__or2b_1
+sky130_fd_sc_hd__or3_1
+sky130_fd_sc_hd__or3b_1
+sky130_fd_sc_hd__or4_1
+sky130_fd_sc_hd__or4b_1
+sky130_fd_sc_hd__or4bb_1
+sky130_fd_sc_hd__xnor2_1
+sky130_fd_sc_hd__xor2_1
+sky130_fd_sc_hd__or2
+sky130_fd_sc_hd__or2_0
+sky130_fd_sc_hd__or2_1
+sky130_fd_sc_hd__or2_2
+sky130_fd_sc_hd__or2_4
+sky130_fd_sc_hd__or2b
+sky130_fd_sc_hd__or2b_1
+sky130_fd_sc_hd__or2b_2
+sky130_fd_sc_hd__or2b_4
+sky130_fd_sc_hd__or3
+sky130_fd_sc_hd__or3_1
+sky130_fd_sc_hd__or3_2
+sky130_fd_sc_hd__or3_4
+sky130_fd_sc_hd__or3b
+sky130_fd_sc_hd__or3b_1
+sky130_fd_sc_hd__or3b_2
+sky130_fd_sc_hd__or3b_4
+sky130_fd_sc_hd__or4
+sky130_fd_sc_hd__or4_1
+sky130_fd_sc_hd__or4_2
+sky130_fd_sc_hd__or4_4
+sky130_fd_sc_hd__or4b
+sky130_fd_sc_hd__or4b_1
+sky130_fd_sc_hd__or4b_2
+sky130_fd_sc_hd__or4b_4
+sky130_fd_sc_hd__or4bb
+sky130_fd_sc_hd__or4bb_1
+sky130_fd_sc_hd__or4bb_2
+sky130_fd_sc_hd__or4bb_4
+sky130_fd_sc_hd__inv_2
+sky130_fd_sc_hd__a21boi_0
+sky130_fd_sc_hd__and2_2

openlane/caravan_core/synth_configuration/yosys_mapping.v

@@ -0,0 +1,33 @@
+module \$_ALDFF_PN_ (D, C, L, AD, Q);
+input D, C, L, AD;
+output reg Q;
+
+wire RN, SN;
+wire L_N;
+
+\$_OR_ R_NAND ( .Y(RN), .A(L), .B(AD) );
+\$_NOT_ NAND_NOT ( .A(L), .Y(L_N));
+\$_NAND_ S_NAND ( .Y(SN), .A(L_N), .B(AD) );
+
+\$_DFFSR_PNN_ SRFF (.C(C), 
+    .S(SN), 
+    .R(RN), 
+    .D(D), 
+    .Q(Q)
+);
+
+endmodule
+
+module \$_MUX_ (
+    output Y,
+    input A,
+    input B,
+    input S
+    );
+  sky130_fd_sc_hd__mux2_2 _TECHMAP_MUX (
+      .X(Y),
+      .A0(A),
+      .A1(B),
+      .S(S)
+  );
+endmodule