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Move decleration of some signal in caravel.v to fix error in iverilog

This commit is contained in:
M0stafaRady 2022-10-20 06:26:55 -07:00
parent 891afe841b
commit 98d089ed08
1 changed files with 6 additions and 4 deletions
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10
verilog/rtl/caravel.v
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@ -244,6 +244,12 @@ module caravel (
wire por_l_buf;
wire porb_h_buf;
// SoC core
wire caravel_clk;
wire caravel_clk2;
wire caravel_rstn;
// top-level buffers
buff_flash_clkrst flash_clkrst_buffers (
`ifdef USE_POWER_PINS
@ -399,10 +405,6 @@ module caravel (
.mprj_analog_io(user_analog_io)
);
// SoC core
wire caravel_clk;
wire caravel_clk2;
wire caravel_rstn;
// Logic analyzer signals
wire [127:0] la_data_in_user; // From CPU to MPRJ