[DATA] Update digital_pll

This commit is contained in:
manarabdelaty 2021-12-07 13:19:02 +02:00
parent c178372fea
commit 966b1f22bb
10 changed files with 12842 additions and 13006 deletions

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@ -339,7 +339,7 @@ MACRO digital_pll
LAYER li1 ; LAYER li1 ;
RECT 5.520 5.355 69.460 68.085 ; RECT 5.520 5.355 69.460 68.085 ;
LAYER met1 ; LAYER met1 ;
RECT 2.830 5.200 72.150 68.640 ; RECT 2.830 5.200 72.150 68.980 ;
LAYER met2 ; LAYER met2 ;
RECT 3.410 70.720 8.090 72.605 ; RECT 3.410 70.720 8.090 72.605 ;
RECT 8.930 70.720 14.070 72.605 ; RECT 8.930 70.720 14.070 72.605 ;
@ -397,8 +397,6 @@ MACRO digital_pll
RECT 4.400 5.760 70.600 7.160 ; RECT 4.400 5.760 70.600 7.160 ;
RECT 4.000 3.080 71.000 5.760 ; RECT 4.000 3.080 71.000 5.760 ;
RECT 4.400 2.215 71.000 3.080 ; RECT 4.400 2.215 71.000 3.080 ;
LAYER met4 ;
RECT 49.055 24.655 49.385 39.945 ;
END END
END digital_pll END digital_pll
END LIBRARY END LIBRARY

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@ -1,11 +1,11 @@
magic magic
tech sky130A tech sky130A
magscale 1 2 magscale 1 2
timestamp 1638470894 timestamp 1638875309
<< obsli1 >> << obsli1 >>
rect 1104 1071 13892 13617 rect 1104 1071 13892 13617
<< obsm1 >> << obsm1 >>
rect 566 1040 14430 13728 rect 566 1040 14430 13796
<< metal2 >> << metal2 >>
rect 570 14200 626 15000 rect 570 14200 626 15000
rect 1674 14200 1730 15000 rect 1674 14200 1730 15000
@ -106,8 +106,6 @@ rect 880 443 14200 616
rect 4208 1040 4528 13648 rect 4208 1040 4528 13648
rect 8208 1040 8528 13648 rect 8208 1040 8528 13648
rect 12208 1040 12528 13648 rect 12208 1040 12528 13648
<< obsm4 >>
rect 9811 4931 9877 7989
<< metal5 >> << metal5 >>
rect 1104 12210 13892 12530 rect 1104 12210 13892 12530
rect 1104 8210 13892 8530 rect 1104 8210 13892 8530
@ -204,7 +202,7 @@ string LEFclass BLOCK
string FIXED_BBOX 0 0 15000 15000 string FIXED_BBOX 0 0 15000 15000
string LEFview TRUE string LEFview TRUE
string GDS_FILE ../gds/digital_pll.gds string GDS_FILE ../gds/digital_pll.gds
string GDS_END 1095830 string GDS_END 1091926
string GDS_START 342938 string GDS_START 342938
<< end >> << end >>

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@ -1,6 +1,6 @@
############################################################################### ###############################################################################
# Created by write_sdc # Created by write_sdc
# Thu Dec 2 18:46:39 2021 # Tue Dec 7 11:07:45 2021
############################################################################### ###############################################################################
current_design digital_pll current_design digital_pll
############################################################################### ###############################################################################

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@ -1 +1 @@
openlane 2021.11.23_01.42.34-9-gc3ec957 openlane 2021.11.23_01.42.34-11-g0c24fcf

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@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
0,/home/ma/ef/caravel_openframe/openlane/digital_pll,digital_pll,digital_pll,flow completed,0h2m10s0ms,0h1m42s0ms,110933.33333333334,0.005625,55466.66666666667,81.42,550.99,312,0,0,0,0,0,0,0,0,0,0,-1,5644,2222,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,3849516.0,0.0,32.42,24.29,0.0,0.0,0.0,613,808,120,303,0,0,0,646,0,0,0,0,0,0,0,4,31,72,20,46,50,0,96,90.9090909090909,11.0,10.0,AREA 0,6,50,1,40,40,0.82,0,sky130_fd_sc_hd,0,4 0,/home/ma/ef/caravel_openframe/openlane/digital_pll,digital_pll,digital_pll,flow completed,0h0m56s0ms,0h0m47s0ms,110933.33333333334,0.005625,55466.66666666667,81.42,551.6,312,0,0,0,0,0,0,0,0,0,0,-1,5632,2218,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,3849516.0,0.0,32.42,24.29,0.0,0.0,0.0,613,808,120,303,0,0,0,646,4,3,17,11,331,19,12,27,31,72,20,46,50,0,96,90.9090909090909,11.0,10.0,AREA 0,6,50,1,40,40,0.82,0,sky130_fd_sc_hd,0,4

1 design design_name config flow_status total_runtime routed_runtime (Cell/mm^2)/Core_Util DIEAREA_mm^2 CellPer_mm^2 OpenDP_Util Peak_Memory_Usage_MB cell_count tritonRoute_violations Short_violations MetSpc_violations OffGrid_violations MinHole_violations Other_violations Magic_violations antenna_violations lvs_total_errors cvc_total_errors klayout_violations wire_length vias wns pl_wns optimized_wns fastroute_wns spef_wns tns pl_tns optimized_tns fastroute_tns spef_tns HPWL routing_layer1_pct routing_layer2_pct routing_layer3_pct routing_layer4_pct routing_layer5_pct routing_layer6_pct wires_count wire_bits public_wires_count public_wire_bits memories_count memory_bits processes_count cells_pre_abc AND DFF NAND NOR OR XOR XNOR MUX inputs outputs level EndCaps TapCells Diodes Total_Physical_Cells suggested_clock_frequency suggested_clock_period CLOCK_PERIOD SYNTH_STRATEGY SYNTH_MAX_FANOUT FP_CORE_UTIL FP_ASPECT_RATIO FP_PDN_VPITCH FP_PDN_HPITCH PL_TARGET_DENSITY GLB_RT_ADJUSTMENT STD_CELL_LIBRARY CELL_PAD DIODE_INSERTION_STRATEGY
2 0 /home/ma/ef/caravel_openframe/openlane/digital_pll digital_pll digital_pll flow completed 0h2m10s0ms 0h0m56s0ms 0h1m42s0ms 0h0m47s0ms 110933.33333333334 0.005625 55466.66666666667 81.42 550.99 551.6 312 0 0 0 0 0 0 0 0 0 0 -1 5644 5632 2222 2218 0.0 0.0 -1 0.0 -1 0.0 0.0 -1 0.0 -1 3849516.0 0.0 32.42 24.29 0.0 0.0 0.0 613 808 120 303 0 0 0 646 0 4 0 3 0 17 0 11 0 331 0 19 0 12 4 27 31 72 20 46 50 0 96 90.9090909090909 11.0 10.0 AREA 0 6 50 1 40 40 0.82 0 sky130_fd_sc_hd 0 4

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