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reharden!: gpio_control_block 

- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition

- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
	- to add obstruction before pdn
	- to manually insert buffers on some ports
	- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn

- misc changes:
* fix openlane makefile to properly detect interactive script

!important still need to run dynamic simulations
!important depends on some updates to openlane
This commit is contained in:
kareem 2022-09-27 07:09:26 -07:00
parent c1e0d5ba06
commit 85f7f86c4e
17 changed files with 20061 additions and 15246 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5228
def/gpio_control_block.def
View File

File diff suppressed because it is too large Load Diff

300
lef/gpio_control_block.lef
View File

@ -348,23 +348,27 @@ MACRO gpio_control_block
USE POWER ; USE POWER ;
PORT PORT
LAYER met4 ; LAYER met4 ;
RECT 12.800 5.200 14.400 57.360 ; RECT 12.800 2.480 14.400 60.080 ;
END END
PORT PORT
LAYER met4 ; LAYER met4 ;
RECT 37.800 5.200 39.400 57.360 ; RECT 37.800 2.480 39.400 60.080 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 5.900 49.460 7.500 ; RECT 4.360 5.900 51.760 7.500 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 22.800 49.460 24.400 ; RECT 4.360 22.800 51.760 24.400 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 39.700 49.460 41.300 ; RECT 4.360 39.700 51.760 41.300 ;
END
PORT
LAYER met5 ;
RECT 4.360 56.600 51.760 58.200 ;
END END
END vccd END vccd
PIN vccd1 PIN vccd1
@ -372,23 +376,23 @@ MACRO gpio_control_block
USE POWER ; USE POWER ;
PORT PORT
LAYER met4 ; LAYER met4 ;
RECT 17.800 5.200 19.400 57.360 ; RECT 17.800 2.480 19.400 60.080 ;
END END
PORT PORT
LAYER met4 ; LAYER met4 ;
RECT 42.800 5.200 44.400 57.360 ; RECT 42.800 2.480 44.400 60.080 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 11.140 49.460 12.740 ; RECT 4.360 11.140 51.760 12.740 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 28.040 49.460 29.640 ; RECT 4.360 28.040 51.760 29.640 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 44.940 49.460 46.540 ; RECT 4.360 44.940 51.760 46.540 ;
END END
END vccd1 END vccd1
PIN vssd PIN vssd
@ -396,19 +400,19 @@ MACRO gpio_control_block
USE GROUND ; USE GROUND ;
PORT PORT
LAYER met4 ; LAYER met4 ;
RECT 25.300 5.200 26.900 57.360 ; RECT 25.300 2.480 26.900 60.080 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 14.350 49.460 15.950 ; RECT 4.360 14.350 51.760 15.950 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 31.250 49.460 32.850 ; RECT 4.360 31.250 51.760 32.850 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 48.150 49.460 49.750 ; RECT 4.360 48.150 51.760 49.750 ;
END END
END vssd END vssd
PIN vssd1 PIN vssd1
@ -416,19 +420,19 @@ MACRO gpio_control_block
USE GROUND ; USE GROUND ;
PORT PORT
LAYER met4 ; LAYER met4 ;
RECT 30.300 5.200 31.900 57.360 ; RECT 30.300 2.480 31.900 60.080 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 19.590 49.460 21.190 ; RECT 4.360 19.590 51.760 21.190 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 36.490 49.460 38.090 ; RECT 4.360 36.490 51.760 38.090 ;
END END
PORT PORT
LAYER met5 ; LAYER met5 ;
RECT 4.360 53.390 49.460 54.990 ; RECT 4.360 53.390 51.760 54.990 ;
END END
END vssd1 END vssd1
PIN zero PIN zero
@ -449,7 +453,20 @@ MACRO gpio_control_block
LAYER li1 ; LAYER li1 ;
RECT 49.815 64.845 169.810 64.930 ; RECT 49.815 64.845 169.810 64.930 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 57.405 169.810 64.845 ; RECT 0.000 59.925 169.810 64.845 ;
RECT 0.000 59.755 4.745 59.925 ;
LAYER li1 ;
RECT 4.745 59.755 169.810 59.925 ;
LAYER li1 ;
RECT 0.000 59.585 169.810 59.755 ;
RECT 0.000 57.645 6.100 59.585 ;
LAYER li1 ;
RECT 6.100 57.645 169.810 59.585 ;
LAYER li1 ;
RECT 0.000 57.405 8.925 57.645 ;
LAYER li1 ;
RECT 8.925 57.405 169.810 57.645 ;
LAYER li1 ;
RECT 0.000 30.025 4.265 57.405 ; RECT 0.000 30.025 4.265 57.405 ;
LAYER li1 ; LAYER li1 ;
RECT 4.265 30.025 169.810 57.405 ; RECT 4.265 30.025 169.810 57.405 ;
@ -466,9 +483,9 @@ MACRO gpio_control_block
LAYER li1 ; LAYER li1 ;
RECT 16.795 29.665 169.810 29.835 ; RECT 16.795 29.665 169.810 29.835 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 27.455 6.985 29.665 ; RECT 0.000 27.455 6.065 29.665 ;
LAYER li1 ; LAYER li1 ;
RECT 6.985 27.455 169.810 29.665 ; RECT 6.065 27.455 169.810 29.665 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 27.285 16.795 27.455 ; RECT 0.000 27.285 16.795 27.455 ;
LAYER li1 ; LAYER li1 ;
@ -478,37 +495,37 @@ MACRO gpio_control_block
LAYER li1 ; LAYER li1 ;
RECT 4.745 27.115 169.810 27.285 ; RECT 4.745 27.115 169.810 27.285 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 26.855 16.795 27.115 ; RECT 0.000 26.945 16.795 27.115 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 26.855 169.810 27.115 ; RECT 16.795 26.945 169.810 27.115 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 26.565 16.905 26.855 ; RECT 0.000 26.185 16.905 26.945 ;
LAYER li1 ; LAYER li1 ;
RECT 16.905 26.565 169.810 26.855 ; RECT 16.905 26.185 169.810 26.945 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 26.395 17.400 26.565 ; RECT 0.000 26.015 17.450 26.185 ;
LAYER li1 ; LAYER li1 ;
RECT 17.400 26.395 169.810 26.565 ; RECT 17.450 26.015 169.810 26.185 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 26.225 16.795 26.395 ; RECT 0.000 25.835 16.795 26.015 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 26.225 169.810 26.395 ; RECT 16.795 25.835 169.810 26.015 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 25.575 16.650 26.225 ; RECT 0.000 25.465 16.645 25.835 ;
LAYER li1 ; LAYER li1 ;
RECT 16.650 25.575 169.810 26.225 ; RECT 16.645 25.465 169.810 25.835 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 25.405 16.795 25.575 ; RECT 0.000 25.285 16.795 25.465 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 25.405 169.810 25.575 ; RECT 16.795 25.285 169.810 25.465 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 25.235 17.400 25.405 ; RECT 0.000 25.115 17.450 25.285 ;
LAYER li1 ; LAYER li1 ;
RECT 17.400 25.235 169.810 25.405 ; RECT 17.450 25.115 169.810 25.285 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 24.735 16.905 25.235 ; RECT 0.000 24.735 16.905 25.115 ;
LAYER li1 ; LAYER li1 ;
RECT 16.905 24.735 169.810 25.235 ; RECT 16.905 24.735 169.810 25.115 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 24.565 16.795 24.735 ; RECT 0.000 24.565 16.795 24.735 ;
LAYER li1 ; LAYER li1 ;
@ -522,183 +539,171 @@ MACRO gpio_control_block
LAYER li1 ; LAYER li1 ;
RECT 16.795 24.225 169.810 24.395 ; RECT 16.795 24.225 169.810 24.395 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 23.725 16.905 24.225 ; RECT 0.000 22.015 16.645 24.225 ;
LAYER li1 ; LAYER li1 ;
RECT 16.905 23.725 169.810 24.225 ; RECT 16.645 22.015 169.810 24.225 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 23.555 17.400 23.725 ; RECT 0.000 21.845 16.795 22.015 ;
LAYER li1 ; LAYER li1 ;
RECT 17.400 23.555 169.810 23.725 ; RECT 16.795 21.845 169.810 22.015 ;
LAYER li1 ;
RECT 0.000 23.385 16.795 23.555 ;
LAYER li1 ;
RECT 16.795 23.385 169.810 23.555 ;
LAYER li1 ;
RECT 0.000 22.735 16.650 23.385 ;
LAYER li1 ;
RECT 16.650 22.735 169.810 23.385 ;
LAYER li1 ;
RECT 0.000 22.565 16.795 22.735 ;
LAYER li1 ;
RECT 16.795 22.565 169.810 22.735 ;
LAYER li1 ;
RECT 0.000 22.395 17.400 22.565 ;
LAYER li1 ;
RECT 17.400 22.395 169.810 22.565 ;
LAYER li1 ;
RECT 0.000 22.105 16.905 22.395 ;
LAYER li1 ;
RECT 16.905 22.105 169.810 22.395 ;
LAYER li1 ;
RECT 0.000 21.845 16.795 22.105 ;
LAYER li1 ;
RECT 16.795 21.845 169.810 22.105 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 21.675 15.325 21.845 ; RECT 0.000 21.675 15.325 21.845 ;
LAYER li1 ; LAYER li1 ;
RECT 15.325 21.675 169.810 21.845 ; RECT 15.325 21.675 169.810 21.845 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 21.505 16.795 21.675 ; RECT 0.000 20.865 16.950 21.675 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 21.505 169.810 21.675 ; RECT 16.950 20.865 169.810 21.675 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 19.295 16.645 21.505 ; RECT 0.000 20.365 16.795 20.865 ;
LAYER li1 ; LAYER li1 ;
RECT 16.645 19.295 169.810 21.505 ; RECT 16.795 20.365 169.810 20.865 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 19.125 16.795 19.295 ; RECT 0.000 19.805 16.645 20.365 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 19.125 169.810 19.295 ; RECT 16.645 19.805 169.810 20.365 ;
LAYER li1 ;
RECT 0.000 19.635 16.795 19.805 ;
LAYER li1 ;
RECT 16.795 19.635 169.810 19.805 ;
LAYER li1 ;
RECT 0.000 19.125 16.950 19.635 ;
LAYER li1 ;
RECT 16.950 19.125 169.810 19.635 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 18.955 15.325 19.125 ; RECT 0.000 18.955 15.325 19.125 ;
LAYER li1 ; LAYER li1 ;
RECT 15.325 18.955 169.810 19.125 ; RECT 15.325 18.955 169.810 19.125 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 18.210 17.005 18.955 ; RECT 0.000 18.785 16.795 18.955 ;
LAYER li1 ; LAYER li1 ;
RECT 17.005 18.210 169.810 18.955 ; RECT 16.795 18.785 169.810 18.955 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 18.040 16.795 18.210 ; RECT 0.000 16.575 16.645 18.785 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 18.040 169.810 18.210 ; RECT 16.645 16.575 169.810 18.785 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 17.055 16.735 18.040 ; RECT 0.000 16.405 16.795 16.575 ;
LAYER li1 ; LAYER li1 ;
RECT 16.735 17.055 169.810 18.040 ; RECT 16.795 16.405 169.810 16.575 ;
LAYER li1 ;
RECT 0.000 16.885 16.795 17.055 ;
LAYER li1 ;
RECT 16.795 16.885 169.810 17.055 ;
LAYER li1 ;
RECT 0.000 16.405 17.035 16.885 ;
LAYER li1 ;
RECT 17.035 16.405 169.810 16.885 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 16.235 15.325 16.405 ; RECT 0.000 16.235 15.325 16.405 ;
LAYER li1 ; LAYER li1 ;
RECT 15.325 16.235 169.810 16.405 ; RECT 15.325 16.235 169.810 16.405 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 16.065 16.795 16.235 ; RECT 0.000 15.425 16.950 16.235 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 16.065 169.810 16.235 ; RECT 16.950 15.425 169.810 16.235 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 13.855 16.645 16.065 ; RECT 0.000 14.925 16.795 15.425 ;
LAYER li1 ; LAYER li1 ;
RECT 16.645 13.855 169.810 16.065 ; RECT 16.795 14.925 169.810 15.425 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 13.685 16.795 13.855 ; RECT 0.000 14.365 16.645 14.925 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 13.685 169.810 13.855 ; RECT 16.645 14.365 169.810 14.925 ;
LAYER li1 ;
RECT 0.000 14.195 16.795 14.365 ;
LAYER li1 ;
RECT 16.795 14.195 169.810 14.365 ;
LAYER li1 ;
RECT 0.000 13.685 16.950 14.195 ;
LAYER li1 ;
RECT 16.950 13.685 169.810 14.195 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 13.515 15.325 13.685 ; RECT 0.000 13.515 15.325 13.685 ;
LAYER li1 ; LAYER li1 ;
RECT 15.325 13.515 169.810 13.685 ; RECT 15.325 13.515 169.810 13.685 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 13.345 16.795 13.515 ; RECT 0.000 13.005 16.950 13.515 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 13.345 169.810 13.515 ; RECT 16.950 13.005 169.810 13.515 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 11.135 16.645 13.345 ; RECT 0.000 12.835 16.795 13.005 ;
LAYER li1 ; LAYER li1 ;
RECT 16.645 11.135 169.810 13.345 ; RECT 16.795 12.835 169.810 13.005 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 10.965 16.795 11.135 ; RECT 0.000 12.275 16.645 12.835 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 10.965 169.810 11.135 ; RECT 16.645 12.275 169.810 12.835 ;
LAYER li1 ;
RECT 0.000 11.775 16.795 12.275 ;
LAYER li1 ;
RECT 16.795 11.775 169.810 12.275 ;
LAYER li1 ;
RECT 0.000 10.965 16.950 11.775 ;
LAYER li1 ;
RECT 16.950 10.965 169.810 11.775 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 10.795 15.325 10.965 ; RECT 0.000 10.795 15.325 10.965 ;
LAYER li1 ; LAYER li1 ;
RECT 15.325 10.795 169.810 10.965 ; RECT 15.325 10.795 169.810 10.965 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 10.535 16.795 10.795 ; RECT 0.000 10.020 16.795 10.795 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 10.535 169.810 10.795 ; RECT 16.795 10.020 169.810 10.795 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 10.245 16.905 10.535 ; RECT 0.000 9.825 16.970 10.020 ;
LAYER li1 ; LAYER li1 ;
RECT 16.905 10.245 169.810 10.535 ; RECT 16.970 9.825 169.810 10.020 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 10.075 17.400 10.245 ; RECT 0.000 9.655 17.920 9.825 ;
LAYER li1 ; LAYER li1 ;
RECT 17.400 10.075 169.810 10.245 ; RECT 17.920 9.655 169.810 9.825 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 9.905 16.795 10.075 ; RECT 0.000 9.000 16.840 9.655 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 9.905 169.810 10.075 ; RECT 16.840 9.000 169.810 9.655 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 9.255 16.645 9.905 ; RECT 0.000 8.670 16.905 9.000 ;
LAYER li1 ; LAYER li1 ;
RECT 16.645 9.255 169.810 9.905 ; RECT 16.905 8.670 169.810 9.000 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 9.085 16.795 9.255 ; RECT 0.000 8.245 16.795 8.670 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 9.085 169.810 9.255 ; RECT 16.795 8.245 169.810 8.670 ;
LAYER li1 ;
RECT 0.000 8.915 17.400 9.085 ;
LAYER li1 ;
RECT 17.400 8.915 169.810 9.085 ;
LAYER li1 ;
RECT 0.000 8.415 16.905 8.915 ;
LAYER li1 ;
RECT 16.905 8.415 169.810 8.915 ;
LAYER li1 ;
RECT 0.000 8.245 16.795 8.415 ;
LAYER li1 ;
RECT 16.795 8.245 169.810 8.415 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 8.075 15.325 8.245 ; RECT 0.000 8.075 15.325 8.245 ;
LAYER li1 ; LAYER li1 ;
RECT 15.325 8.075 169.810 8.245 ; RECT 15.325 8.075 169.810 8.245 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 7.330 17.005 8.075 ; RECT 0.000 7.905 16.795 8.075 ;
LAYER li1 ; LAYER li1 ;
RECT 17.005 7.330 169.810 8.075 ; RECT 16.795 7.905 169.810 8.075 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 7.160 16.795 7.330 ; RECT 0.000 5.695 16.645 7.905 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 7.160 169.810 7.330 ; RECT 16.645 5.695 169.810 7.905 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 6.175 16.735 7.160 ; RECT 0.000 5.525 16.795 5.695 ;
LAYER li1 ; LAYER li1 ;
RECT 16.735 6.175 169.810 7.160 ; RECT 16.795 5.525 169.810 5.695 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 6.005 16.795 6.175 ; RECT 0.000 5.355 4.745 5.525 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 6.005 169.810 6.175 ; RECT 4.745 5.355 169.810 5.525 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 5.525 17.035 6.005 ; RECT 0.000 5.185 16.795 5.355 ;
LAYER li1 ; LAYER li1 ;
RECT 17.035 5.525 169.810 6.005 ; RECT 16.795 5.185 169.810 5.355 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 5.355 15.325 5.525 ; RECT 0.000 2.975 6.525 5.185 ;
LAYER li1 ; LAYER li1 ;
RECT 15.325 5.355 169.810 5.525 ; RECT 6.525 2.975 169.810 5.185 ;
LAYER li1 ; LAYER li1 ;
RECT 0.000 0.000 16.795 5.355 ; RECT 0.000 2.805 16.795 2.975 ;
LAYER li1 ; LAYER li1 ;
RECT 16.795 0.000 169.810 5.355 ; RECT 16.795 2.805 169.810 2.975 ;
LAYER li1 ;
RECT 0.000 2.635 4.745 2.805 ;
LAYER li1 ;
RECT 4.745 2.635 169.810 2.805 ;
LAYER li1 ;
RECT 0.000 0.000 16.795 2.635 ;
LAYER li1 ;
RECT 16.795 0.000 169.810 2.635 ;
LAYER met1 ; LAYER met1 ;
RECT 4.600 0.000 170.000 65.000 ; RECT 4.300 0.000 170.000 65.000 ;
LAYER met2 ; LAYER met2 ;
RECT 5.250 60.720 6.710 65.000 ; RECT 5.250 60.720 6.710 65.000 ;
RECT 7.550 60.720 9.010 65.000 ; RECT 7.550 60.720 9.010 65.000 ;
@ -713,7 +718,7 @@ MACRO gpio_control_block
RECT 28.250 60.720 29.710 65.000 ; RECT 28.250 60.720 29.710 65.000 ;
RECT 30.550 60.720 32.010 65.000 ; RECT 30.550 60.720 32.010 65.000 ;
RECT 32.850 60.720 170.000 65.000 ; RECT 32.850 60.720 170.000 65.000 ;
RECT 4.970 0.000 170.000 60.720 ; RECT 4.700 0.000 170.000 60.720 ;
LAYER met3 ; LAYER met3 ;
RECT 6.280 60.840 69.600 61.705 ; RECT 6.280 60.840 69.600 61.705 ;
RECT 6.280 60.200 70.000 60.840 ; RECT 6.280 60.200 70.000 60.840 ;
@ -773,17 +778,18 @@ MACRO gpio_control_block
RECT 6.280 5.120 70.000 5.760 ; RECT 6.280 5.120 70.000 5.760 ;
RECT 6.280 3.720 69.600 5.120 ; RECT 6.280 3.720 69.600 5.120 ;
RECT 6.280 3.080 70.000 3.720 ; RECT 6.280 3.080 70.000 3.720 ;
RECT 6.280 2.215 69.600 3.080 ; RECT 6.280 1.680 69.600 3.080 ;
RECT 6.280 0.175 70.000 1.680 ;
LAYER met4 ; LAYER met4 ;
RECT 6.280 57.760 170.000 65.000 ; RECT 6.280 60.480 170.000 65.000 ;
RECT 6.280 4.800 12.400 57.760 ; RECT 6.280 2.080 12.400 60.480 ;
RECT 14.800 4.800 17.400 57.760 ; RECT 14.800 2.080 17.400 60.480 ;
RECT 19.800 4.800 24.900 57.760 ; RECT 19.800 2.080 24.900 60.480 ;
RECT 27.300 4.800 29.900 57.760 ; RECT 27.300 2.080 29.900 60.480 ;
RECT 32.300 4.800 37.400 57.760 ; RECT 32.300 2.080 37.400 60.480 ;
RECT 39.800 4.800 42.400 57.760 ; RECT 39.800 2.080 42.400 60.480 ;
RECT 44.800 4.800 170.000 57.760 ; RECT 44.800 2.080 170.000 60.480 ;
RECT 6.280 0.000 170.000 4.800 ; RECT 6.280 0.000 170.000 2.080 ;
LAYER met5 ; LAYER met5 ;
RECT 67.000 0.000 170.000 65.000 ; RECT 67.000 0.000 170.000 65.000 ;
END END

18121
mag/gpio_control_block.mag
View File

File diff suppressed because it is too large Load Diff

108
maglef/gpio_control_block.mag
View File

@ -1,12 +1,12 @@
magic magic
tech sky130A tech sky130A
magscale 1 2 magscale 1 2
timestamp 1663176680 timestamp 1664286915
<< obsli1 >> << obsli1 >>
rect 0 13000 853 13014 rect 0 13000 853 13014
rect 0 0 33962 13000 rect 0 0 33962 13000
<< obsm1 >> << obsm1 >>
rect 920 0 34000 13000 rect 860 0 34000 13000
<< metal2 >> << metal2 >>
rect 938 12200 994 13000 rect 938 12200 994 13000
rect 1398 12200 1454 13000 rect 1398 12200 1454 13000
@ -35,7 +35,7 @@ rect 5190 12144 5482 13000
rect 5650 12144 5942 13000 rect 5650 12144 5942 13000
rect 6110 12144 6402 13000 rect 6110 12144 6402 13000
rect 6570 12144 34000 13000 rect 6570 12144 34000 13000
rect 994 0 34000 12144 rect 940 0 34000 12144
<< metal3 >> << metal3 >>
rect 14000 12248 34000 12368 rect 14000 12248 34000 12368
rect 14000 11840 34000 11960 rect 14000 11840 34000 11960
@ -126,37 +126,39 @@ rect 1256 1152 13920 1432
rect 1256 1024 14000 1152 rect 1256 1024 14000 1152
rect 1256 744 13920 1024 rect 1256 744 13920 1024
rect 1256 616 14000 744 rect 1256 616 14000 744
rect 1256 443 13920 616 rect 1256 336 13920 616
rect 1256 35 14000 336
<< metal4 >> << metal4 >>
rect 2560 1040 2880 11472 rect 2560 496 2880 12016
rect 3560 1040 3880 11472 rect 3560 496 3880 12016
rect 5060 1040 5380 11472 rect 5060 496 5380 12016
rect 6060 1040 6380 11472 rect 6060 496 6380 12016
rect 7560 1040 7880 11472 rect 7560 496 7880 12016
rect 8560 1040 8880 11472 rect 8560 496 8880 12016
<< obsm4 >> << obsm4 >>
rect 1256 11552 34000 13000 rect 1256 12096 34000 13000
rect 1256 960 2480 11552 rect 1256 416 2480 12096
rect 2960 960 3480 11552 rect 2960 416 3480 12096
rect 3960 960 4980 11552 rect 3960 416 4980 12096
rect 5460 960 5980 11552 rect 5460 416 5980 12096
rect 6460 960 7480 11552 rect 6460 416 7480 12096
rect 7960 960 8480 11552 rect 7960 416 8480 12096
rect 8960 960 34000 11552 rect 8960 416 34000 12096
rect 1256 0 34000 960 rect 1256 0 34000 416
<< metal5 >> << metal5 >>
rect 872 10678 9892 10998 rect 872 11320 10352 11640
rect 872 9630 9892 9950 rect 872 10678 10352 10998
rect 872 8988 9892 9308 rect 872 9630 10352 9950
rect 872 7940 9892 8260 rect 872 8988 10352 9308
rect 872 7298 9892 7618 rect 872 7940 10352 8260
rect 872 6250 9892 6570 rect 872 7298 10352 7618
rect 872 5608 9892 5928 rect 872 6250 10352 6570
rect 872 4560 9892 4880 rect 872 5608 10352 5928
rect 872 3918 9892 4238 rect 872 4560 10352 4880
rect 872 2870 9892 3190 rect 872 3918 10352 4238
rect 872 2228 9892 2548 rect 872 2870 10352 3190
rect 872 1180 9892 1500 rect 872 2228 10352 2548
rect 872 1180 10352 1500
<< obsm5 >> << obsm5 >>
rect 13400 0 34000 13000 rect 13400 0 34000 13000
<< labels >> << labels >>
@ -244,41 +246,43 @@ rlabel metal3 s 14000 11840 34000 11960 6 user_gpio_oeb
port 41 nsew signal input port 41 nsew signal input
rlabel metal3 s 14000 12248 34000 12368 6 user_gpio_out rlabel metal3 s 14000 12248 34000 12368 6 user_gpio_out
port 42 nsew signal input port 42 nsew signal input
rlabel metal4 s 2560 1040 2880 11472 6 vccd rlabel metal4 s 2560 496 2880 12016 6 vccd
port 43 nsew power bidirectional port 43 nsew power bidirectional
rlabel metal4 s 7560 1040 7880 11472 6 vccd rlabel metal4 s 7560 496 7880 12016 6 vccd
port 43 nsew power bidirectional port 43 nsew power bidirectional
rlabel metal5 s 872 1180 9892 1500 6 vccd rlabel metal5 s 872 1180 10352 1500 6 vccd
port 43 nsew power bidirectional port 43 nsew power bidirectional
rlabel metal5 s 872 4560 9892 4880 6 vccd rlabel metal5 s 872 4560 10352 4880 6 vccd
port 43 nsew power bidirectional port 43 nsew power bidirectional
rlabel metal5 s 872 7940 9892 8260 6 vccd rlabel metal5 s 872 7940 10352 8260 6 vccd
port 43 nsew power bidirectional port 43 nsew power bidirectional
rlabel metal4 s 3560 1040 3880 11472 6 vccd1 rlabel metal5 s 872 11320 10352 11640 6 vccd
port 43 nsew power bidirectional
rlabel metal4 s 3560 496 3880 12016 6 vccd1
port 44 nsew power bidirectional port 44 nsew power bidirectional
rlabel metal4 s 8560 1040 8880 11472 6 vccd1 rlabel metal4 s 8560 496 8880 12016 6 vccd1
port 44 nsew power bidirectional port 44 nsew power bidirectional
rlabel metal5 s 872 2228 9892 2548 6 vccd1 rlabel metal5 s 872 2228 10352 2548 6 vccd1
port 44 nsew power bidirectional port 44 nsew power bidirectional
rlabel metal5 s 872 5608 9892 5928 6 vccd1 rlabel metal5 s 872 5608 10352 5928 6 vccd1
port 44 nsew power bidirectional port 44 nsew power bidirectional
rlabel metal5 s 872 8988 9892 9308 6 vccd1 rlabel metal5 s 872 8988 10352 9308 6 vccd1
port 44 nsew power bidirectional port 44 nsew power bidirectional
rlabel metal4 s 5060 1040 5380 11472 6 vssd rlabel metal4 s 5060 496 5380 12016 6 vssd
port 45 nsew ground bidirectional port 45 nsew ground bidirectional
rlabel metal5 s 872 2870 9892 3190 6 vssd rlabel metal5 s 872 2870 10352 3190 6 vssd
port 45 nsew ground bidirectional port 45 nsew ground bidirectional
rlabel metal5 s 872 6250 9892 6570 6 vssd rlabel metal5 s 872 6250 10352 6570 6 vssd
port 45 nsew ground bidirectional port 45 nsew ground bidirectional
rlabel metal5 s 872 9630 9892 9950 6 vssd rlabel metal5 s 872 9630 10352 9950 6 vssd
port 45 nsew ground bidirectional port 45 nsew ground bidirectional
rlabel metal4 s 6060 1040 6380 11472 6 vssd1 rlabel metal4 s 6060 496 6380 12016 6 vssd1
port 46 nsew ground bidirectional port 46 nsew ground bidirectional
rlabel metal5 s 872 3918 9892 4238 6 vssd1 rlabel metal5 s 872 3918 10352 4238 6 vssd1
port 46 nsew ground bidirectional port 46 nsew ground bidirectional
rlabel metal5 s 872 7298 9892 7618 6 vssd1 rlabel metal5 s 872 7298 10352 7618 6 vssd1
port 46 nsew ground bidirectional port 46 nsew ground bidirectional
rlabel metal5 s 872 10678 9892 10998 6 vssd1 rlabel metal5 s 872 10678 10352 10998 6 vssd1
port 46 nsew ground bidirectional port 46 nsew ground bidirectional
rlabel metal3 s 14000 416 34000 536 6 zero rlabel metal3 s 14000 416 34000 536 6 zero
port 47 nsew signal output port 47 nsew signal output
@ -286,8 +290,8 @@ port 47 nsew signal output
string FIXED_BBOX 0 0 34000 13000 string FIXED_BBOX 0 0 34000 13000
string LEFclass BLOCK string LEFclass BLOCK
string LEFview TRUE string LEFview TRUE
string GDS_END 446664 string GDS_END 572784
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_09_14_10_30/results/signoff/gpio_control_block.magic.gds string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_09_27_06_53/results/signoff/gpio_control_block.magic.gds
string GDS_START 156052 string GDS_START 204218
<< end >> << end >>

18
openlane/Makefile
View File

@ -35,6 +35,7 @@ docker_mounts = \
-v $(PDK_ROOT):$(PDK_ROOT) \ -v $(PDK_ROOT):$(PDK_ROOT) \
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
-v $(PWD):$(PWD) \ -v $(PWD):$(PWD) \
-v $(HOME):$(HOME)
docker_env = \ docker_env = \
-e PDK_ROOT=$(PDK_ROOT) \ -e PDK_ROOT=$(PDK_ROOT) \
@ -60,23 +61,22 @@ list:
@echo $(designs) @echo $(designs)
.PHONY: $(designs) .PHONY: $(designs)
$(designs) : export current_design=$@
$(designs) : % : ./%/config.tcl $(designs) : % : ./%/config.tcl
ifeq (,$(wildcard ./$(current_design)/interactive.tcl)) ifneq (,$(wildcard ./$(MAKECMDGOALS)/interactive.tcl)))
# $(current_design) $(docker_run) \
$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_interactive)
else
# $(MAKECMDGOALS)
mkdir -p ./$*/runs/$(OPENLANE_RUN_TAG) mkdir -p ./$*/runs/$(OPENLANE_RUN_TAG)
rm -rf ./$*/runs/$* rm -rf ./$*/runs/$*
ln -s $$(realpath ./$*/runs/$(OPENLANE_RUN_TAG)) ./$*/runs/$* ln -s $$(realpath ./$*/runs/$(OPENLANE_RUN_TAG)) ./$*/runs/$*
$(docker_run) \ $(docker_run) \
$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd) $(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd)
else
$(docker_run) \
$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_interactive)
endif endif
@mkdir -p ../signoff/$*/ @mkdir -p ../signoff/$*/
@cp ./$*/runs/$*/OPENLANE_VERSION ../signoff/$*/ @cp ./$*/runs/$(OPENLANE_RUN_TAG)/OPENLANE_VERSION ../signoff/$*/
@cp ./$*/runs/$*/PDK_SOURCES ../signoff/$*/ @cp ./$*/runs/$(OPENLANE_RUN_TAG)/PDK_SOURCES ../signoff/$*/
@cp ./$*/runs/$*/reports/*.csv ../signoff/$*/ @cp ./$*/runs/$(OPENLANE_RUN_TAG)/reports/*.csv ../signoff/$*/
.PHONY: openlane .PHONY: openlane
openlane: check-openlane-env openlane: check-openlane-env

89
openlane/gpio_control_block/base.sdc
View File

@ -14,6 +14,22 @@ create_clock -name serial_load -period 50.0000 [get_ports {serial_load}]
set_clock_transition 0.1500 [get_clocks {serial_load}] set_clock_transition 0.1500 [get_clocks {serial_load}]
set_clock_uncertainty 0.4000 serial_load set_clock_uncertainty 0.4000 serial_load
set_propagated_clock [get_clocks {serial_load}] set_propagated_clock [get_clocks {serial_load}]
set_max_transition 1.25 [current_design]
set clk_input [get_port serial_clock)]
set clk_indx [lsearch [all_inputs] $clk_input]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx ""]
set_input_transition 5.0 $all_inputs_wo_clk
#set_driving_cell -lib_cell sky130_fd_sc_hd__buf_1 -pin {X} -input_transition_rise 1.0000 -input_transition_fall 1.0000 [all_inputs]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
set_max_fanout 7.0000 [current_design]
#
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [all_outputs]
set_load -pin_load 0.25 [all_outputs]
#
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[0]}] set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[0]}]
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[10]}] set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[10]}]
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[11]}] set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[11]}]
@ -35,76 +51,3 @@ set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports
#set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load}] #set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load}]
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_oeb}] set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_oeb}]
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_out}] set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_out}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_in}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {one}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_en}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_pol}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_sel}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[0]}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[1]}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[2]}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_holdover}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ib_mode_sel}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_inenb}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_out}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_outenb}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_slow_sel}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_vtrip_sel}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn_out}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_clock_out}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_out}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load_out}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_in}]
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {zero}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_in}]
set_load -pin_load 0.0334 [get_ports {one}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_en}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_pol}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_sel}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_holdover}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_ib_mode_sel}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_inenb}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_out}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_outenb}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_slow_sel}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_vtrip_sel}]
set_load -pin_load 0.0334 [get_ports {resetn_out}]
set_load -pin_load 0.0334 [get_ports {serial_clock_out}]
set_load -pin_load 0.0334 [get_ports {serial_data_out}]
set_load -pin_load 0.0334 [get_ports {serial_load_out}]
set_load -pin_load 0.0334 [get_ports {user_gpio_in}]
set_load -pin_load 0.0334 [get_ports {zero}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[2]}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[1]}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_oeb}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_out}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pad_gpio_in}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetn}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_clock}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_data_in}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_load}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_oeb}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_out}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]

53
openlane/gpio_control_block/buffer.tcl Normal file
View File

@ -0,0 +1,53 @@
# Copyright 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
foreach lib $::env(LIB_RESIZER_OPT) {
read_liberty $lib
}
if { [info exists ::env(EXTRA_LIBS) ] } {
foreach lib $::env(EXTRA_LIBS) {
read_liberty $lib
}
}
if {[catch {read_lef $::env(MERGED_LEF)} errmsg]} {
puts stderr $errmsg
exit 1
}
if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
puts stderr $errmsg
exit 1
}
source $::env(SCRIPTS_DIR)/openroad/insert_buffer.tcl
puts "inserting buffer on serial_clock_out"
set serial_clock_out_instance [get_property [get_cells -of_objects serial_clock_out] name]
insert_buffer ${serial_clock_out_instance}/X ITerm sky130_fd_sc_hd__clkbuf_16 serial_clock_out_buffered serial_clock_out_buffer
puts "inserting buffer on serial_load_out"
set serial_load_out_instance [get_property [get_cells -of_objects serial_load_out] name]
insert_buffer ${serial_load_out_instance}/X ITerm sky130_fd_sc_hd__clkbuf_16 serial_load_out_buffered serial_load_out_buffer
# .HI(one),
# .LO(zero));
puts "inserting buffer on one"
set const_instance [get_property [get_cells -of_objects one] name]
insert_buffer ${const_instance}/HI ITerm sky130_fd_sc_hd__buf_16 one_buffered one_buffer
puts "inserting buffer on zero"
set const_instance [get_property [get_cells -of_objects zero] name]
insert_buffer ${const_instance}/LO ITerm sky130_fd_sc_hd__buf_16 zero_buffered zero_buffer
write_def $::env(SAVE_DEF)

27
openlane/gpio_control_block/config.tcl
View File

@ -21,6 +21,7 @@ set ::env(VERILOG_FILES) "\
$::env(DESIGN_DIR)/../../verilog/rtl/gpio_control_block.v" $::env(DESIGN_DIR)/../../verilog/rtl/gpio_control_block.v"
set ::env(PL_TARGET_DENSITY) 0.8
set ::env(CLOCK_PORT) "serial_clock" set ::env(CLOCK_PORT) "serial_clock"
set ::env(FP_DEF_TEMPLATE) "$::env(DESIGN_DIR)/template/gpio_control_block.def" set ::env(FP_DEF_TEMPLATE) "$::env(DESIGN_DIR)/template/gpio_control_block.def"
@ -42,12 +43,13 @@ set ::env(SYNTH_STRATEGY) "AREA 0"
set ::env(FP_SIZING) absolute set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 170 65" set ::env(DIE_AREA) "0 0 170 65"
set ::env(RIGHT_MARGIN_MULT) 262 set ::env(RIGHT_MARGIN_MULT) 257
set ::env(LEFT_MARGIN_MULT) 10 set ::env(LEFT_MARGIN_MULT) 10
set ::env(TOP_MARGIN_MULT) 2 set ::env(TOP_MARGIN_MULT) 1
set ::env(BOTTOM_MARGIN_MULT) 2 set ::env(BOTTOM_MARGIN_MULT) 1
set ::env(DPL_CELL_PADDING) 0 set ::env(DPL_CELL_PADDING) 0
set ::env(GPL_CELL_PADDING) 0
## PDN ## PDN
set ::env(FP_PDN_MACRO_HOOKS) "\ set ::env(FP_PDN_MACRO_HOOKS) "\
@ -76,7 +78,7 @@ set ::env(FP_PDN_VSPACING) 3.4
set ::env(FP_PDN_HSPACING) 3.4 set ::env(FP_PDN_HSPACING) 3.4
## Placement ## Placement
set ::env(PL_TARGET_DENSITY) 0.7 set ::env(PL_TARGET_DENSITY) 0.9
# for some reason resizer is leaving a floating net after running repair_tie_fanout command # for some reason resizer is leaving a floating net after running repair_tie_fanout command
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 0 set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 0
@ -96,7 +98,7 @@ set ::env(GRT_OBS) "\
li1 16.83000 0 49.41000 5.24000, li1 16.83000 0 49.41000 5.24000,
li1 49.000 0 169.81000 64.84500, li1 49.000 0 169.81000 64.84500,
met5 67 0 170 65, met5 67 0 170 65,
met4 67 0 170 65, met4 49 0 170 65,
met2 120 0 170 65, met2 120 0 170 65,
met1 120 0 170 65" met1 120 0 170 65"
@ -120,18 +122,24 @@ set ::env(EXTRA_GDS_FILES) "\
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 #Placement
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
#Post cts
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0 set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 1
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 1
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 1
set ::env(PL_RESIZER_MAX_CAP_MARGIN) 1
set ::env(CLOCK_TREE_SYNTH) 1 set ::env(CLOCK_TREE_SYNTH) 1
set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/gpio_control_block.def set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/gpio_control_block.def
set ::env(SYNTH_BUFFERING) 0 set ::env(SYNTH_BUFFERING) 0
set ::env(SYNTH_SIZING) 0 set ::env(SYNTH_SIZING) 0
# 0.07 ns 70 ps # 0.07 ns 70 ps
# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.07 # set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.07
# set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1 # set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
# set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 2 # set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 2
@ -142,3 +150,6 @@ set ::env(QUIT_ON_LVS_ERROR) 1
set ::env(SYNTH_EXTRA_MAPPING_FILE) $::env(DESIGN_DIR)/yosys_mapping.v set ::env(SYNTH_EXTRA_MAPPING_FILE) $::env(DESIGN_DIR)/yosys_mapping.v
set ::env(DECAP_CELL) {sky130_fd_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3} set ::env(DECAP_CELL) {sky130_fd_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3}
set ::env(DRC_EXCLUDE_CELL_LIST) $::env(DESIGN_DIR)/drc_exclude_list.txt
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) $::env(DESIGN_DIR)/drc_exclude_list.txt
set ::env(RSZ_DONT_TOUCH) "user_gpio_out user_gpio_oeb serial_clock_out serial_load_out gpio_defaults*"

37
openlane/gpio_control_block/drc_exclude_list.txt Normal file
View File

@ -0,0 +1,37 @@
sky130_fd_sc_hd__clkdlybuf4s15_1
sky130_fd_sc_hd__clkdlybuf4s18_1
sky130_fd_sc_hd__lpflow_bleeder_1
sky130_fd_sc_hd__lpflow_clkbufkapwr_1
sky130_fd_sc_hd__lpflow_clkbufkapwr_16
sky130_fd_sc_hd__lpflow_clkbufkapwr_2
sky130_fd_sc_hd__lpflow_clkbufkapwr_4
sky130_fd_sc_hd__lpflow_clkbufkapwr_8
sky130_fd_sc_hd__lpflow_clkinvkapwr_1
sky130_fd_sc_hd__lpflow_clkinvkapwr_16
sky130_fd_sc_hd__lpflow_clkinvkapwr_2
sky130_fd_sc_hd__lpflow_clkinvkapwr_4
sky130_fd_sc_hd__lpflow_clkinvkapwr_8
sky130_fd_sc_hd__lpflow_decapkapwr_12
sky130_fd_sc_hd__lpflow_decapkapwr_3
sky130_fd_sc_hd__lpflow_decapkapwr_4
sky130_fd_sc_hd__lpflow_decapkapwr_6
sky130_fd_sc_hd__lpflow_decapkapwr_8
sky130_fd_sc_hd__lpflow_inputiso0n_1
sky130_fd_sc_hd__lpflow_inputiso0p_1
sky130_fd_sc_hd__lpflow_inputiso1n_1
sky130_fd_sc_hd__lpflow_inputiso1p_1
sky130_fd_sc_hd__lpflow_inputisolatch_1
sky130_fd_sc_hd__lpflow_isobufsrc_1
sky130_fd_sc_hd__lpflow_isobufsrc_16
sky130_fd_sc_hd__lpflow_isobufsrc_2
sky130_fd_sc_hd__lpflow_isobufsrc_4
sky130_fd_sc_hd__lpflow_isobufsrc_8
sky130_fd_sc_hd__lpflow_isobufsrckapwr_16
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4

114
openlane/gpio_control_block/interactive.tcl Normal file
View File

@ -0,0 +1,114 @@
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
package require openlane
proc custom_run_placement {args} {
global SCRIPT_DIR
global_placement_or
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
set log [index_file $::env(placement_logs)/resizer-1.log]
set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/resizer-1.def]
set ::env(SAVE_SDC) [index_file $::env(placement_tmpfiles)/resizer-1.sdc]
run_openroad_script $::env(SCRIPTS_DIR)/openroad/resizer.tcl -indexed_log $log
set_def $::env(SAVE_DEF)
set ::env(CURRENT_SDC) $::env(SAVE_SDC)
set dont_use_buffers "sky130_fd_sc_hd__probe* sky130_fd_sc_hd__bufbuf* sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_8 sky130_fd_sc_hd__buf_12 sky130_fd_sc_hd__clkbuf* "
set dont_use_old ""
if { [info exists ::env(DONT_USE_CELLS)] } {
set ::env(DONT_USE_CELLS) "$::env(DONT_USE_CELLS) $dont_use_buffers"
} else {
set ::env(DONT_USE_CELLS) "$dont_use_buffers"
set dont_use_old ::env(DONT_USE_CELLS)
}
set dont_touch_old "$::env(RSZ_DONT_TOUCH)"
set ::env(RSZ_DONT_TOUCH) "$::env(RSZ_DONT_TOUCH) mgmt_gpio_out mgmt_gpio_oeb pad_gpio_in user_gpio_oeb user_gpio_out"
set log [index_file $::env(placement_logs)/resizer-2.log]
set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/resizer-2.def]
set ::env(SAVE_SDC) [index_file $::env(placement_tmpfiles)/resizer-2.sdc]
run_openroad_script $SCRIPT_DIR/buffer.tcl -indexed_log $log
set_def $::env(SAVE_DEF)
set ::env(CURRENT_SDC) $::env(SAVE_SDC)
write_verilog $::env(placement_results)/$::env(DESIGN_NAME).resized.v -log $::env(placement_logs)/write_verilog.log
set ::env(RSZ_DONT_TOUCH) "$dont_touch_old"
set ::env(DONT_USE_CELLS) $dont_use_old
exit 1
detailed_placement_or -def $::env(placement_results)/$::env(DESIGN_NAME).def -log $::env(placement_logs)/detailed.log
}
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
prep -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 0
exec rm -rf $SCRIPT_DIR/runs/gpio_control_block_interactive
exec ln -sf $SCRIPT_DIR/runs/$::env(OPENLANE_RUN_TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
run_synthesis
init_floorplan
place_io
apply_def_template
file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
manual_macro_placement -f
tap_decap_or
add_route_obs
run_power_grid_generation
set dont_use_old ::env(DONT_USE_CELLS)
global_placement_or
set ::env(DONT_USE_CELLS) "$::env(DONT_USE_CELLS) sky130_fd_sc_hd__buf_1"
run_resizer_design
set ::env(DONT_USE_CELLS) "$dont_use_old"
set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/buffer_insert.def]
run_openroad_script $SCRIPT_DIR/buffer.tcl -indexed_log [index_file $::env(placement_logs)/buffer_insert.log]
set_def $::env(SAVE_DEF)
write_verilog [index_file $::env(placement_tmpfiles)/buffer_insert.v] -log $::env(placement_logs)/write_verilog_buffer.log
set ::env(UNBUFFER_NETS) "serial_clock_out_buffered|serial_load_out_buffered"
write_verilog [index_file $::env(placement_tmpfiles)/buffer_remove.v] -log $::env(placement_logs)/write_verilog_buffer_remove.log
detailed_placement_or -def $::env(CURRENT_DEF) -log $::env(placement_logs)/detailed.log
run_cts
remove_buffers_from_nets
run_resizer_timing_routing
ins_diode_cells_4
ins_fill_cells
global_routing
set global_routed_netlist [index_file $::env(routing_tmpfiles)/global.v]
write_verilog $global_routed_netlist -log $::env(routing_logs)/write_verilog_global.log
# detailed routing
detailed_routing
set detailed_routed_netlist [index_file $::env(routing_tmpfiles)/detailed.v]
write_verilog $detailed_routed_netlist -log $::env(routing_logs)/write_verilog_detailed.log
# for lvs
set_netlist $detailed_routed_netlist
run_parasitics_sta
run_irdrop_report
run_magic
run_magic_spice_export;
run_lvs; # requires run_magic_spice_export
run_magic_drc
run_antenna_check
run_lef_cvc
calc_total_runtime
save_final_views
save_final_views -save_path .. -tag $::env(RUN_TAG)
save_state
generate_final_summary_report
check_timing_violations

4
openlane/gpio_control_block/pdn.tcl
View File

@ -111,7 +111,7 @@ add_pdn_stripe \
-layer $::env(FP_PDN_UPPER_LAYER) \ -layer $::env(FP_PDN_UPPER_LAYER) \
-width $::env(FP_PDN_HWIDTH) \ -width $::env(FP_PDN_HWIDTH) \
-pitch 16.9 \ -pitch 16.9 \
-offset 6.5 \ -offset 9.22 \
-spacing 6.85 \ -spacing 6.85 \
-nets "vccd1 vssd1"\ -nets "vccd1 vssd1"\
-starts_with POWER -extend_to_core_ring -starts_with POWER -extend_to_core_ring
@ -121,7 +121,7 @@ add_pdn_stripe \
-layer $::env(FP_PDN_UPPER_LAYER) \ -layer $::env(FP_PDN_UPPER_LAYER) \
-width $::env(FP_PDN_HWIDTH) \ -width $::env(FP_PDN_HWIDTH) \
-pitch 16.9 \ -pitch 16.9 \
-offset 1.26 \ -offset 3.98 \
-spacing 6.85 \ -spacing 6.85 \
-nets "vccd vssd"\ -nets "vccd vssd"\
-starts_with POWER -extend_to_core_ring -starts_with POWER -extend_to_core_ring

31
openlane/gpio_logic_high/config.tcl
View File

@ -13,14 +13,13 @@
# limitations under the License. # limitations under the License.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) gpio_logic_high set ::env(DESIGN_NAME) gpio_logic_high
set ::env(DESIGN_IS_CORE) 0 set ::env(DESIGN_IS_CORE) 0
set ::env(VERILOG_FILES) "\ set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/defines.v\ $::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
$script_dir/../../verilog/rtl/gpio_logic_high.v" $::env(DESIGN_DIR)/../../verilog/rtl/gpio_logic_high.v"
set ::env(CLOCK_PORT) "" set ::env(CLOCK_PORT) ""
set ::env(CLOCK_TREE_SYNTH) 0 set ::env(CLOCK_TREE_SYNTH) 0
@ -30,20 +29,23 @@ set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
## Floorplan ## Floorplan
set ::env(DIE_AREA) "0 0 7 16" set ::env(DIE_AREA) "0 0 7 10"
set ::env(FP_SIZING) absolute set ::env(FP_SIZING) absolute
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_HORIZONTAL_HALO) 0 set ::env(FP_PDN_HORIZONTAL_HALO) 0
set ::env(FP_VERTICAL_HALO) 0 set ::env(FP_PDN_VERTICAL_HALO) 0
set ::env(FP_TOP_HORIZONTAL_HALO) 0
set ::env(FP_TOP_VERTICAL_HALO) 0
set ::env(FP_TAPCELL_DIST) 4 set ::env(FP_TAPCELL_DIST) 4
set ::env(TOP_MARGIN_MULT) 0 set ::env(TOP_MARGIN_MULT) 1
set ::env(BOTTOM_MARGIN_MULT) 0 set ::env(BOTTOM_MARGIN_MULT) 1
set ::env(LEFT_MARGIN_MULT) 0 set ::env(LEFT_MARGIN_MULT) 1
set ::env(RIGHT_MARGIN_MULT) 0 set ::env(RIGHT_MARGIN_MULT) 1
set ::env(CELL_PAD) 0 set ::env(CELL_PAD) 0
@ -53,13 +55,14 @@ set ::env(GND_NETS) "vssd1"
## PDN Configuration ## PDN Configuration
set ::env(FP_PDN_AUTO_ADJUST) 0 set ::env(FP_PDN_AUTO_ADJUST) 0
set ::env(FP_PDN_VWIDTH) 1.4 set ::env(FP_PDN_VWIDTH) 1.0
set ::env(FP_PDN_VOFFSET) 1 set ::env(FP_PDN_VOFFSET) 1
set ::env(FP_PDN_VPITCH) 7.4 set ::env(FP_PDN_VPITCH) 6
## Placement ## Placement
set ::env(PL_TARGET_DENSITY) 0.8 set ::env(PL_TARGET_DENSITY) 0.8
set ::env(PL_RANDOM_INITIAL_PLACEMENT) 1 set ::env(PL_RANDOM_INITIAL_PLACEMENT) 0
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0

91
sdc/gpio_control_block.sdc
View File

@ -1,6 +1,6 @@
############################################################################### ###############################################################################
# Created by write_sdc # Created by write_sdc
# Wed Sep 14 17:30:57 2022 # Tue Sep 27 13:54:44 2022
############################################################################### ###############################################################################
current_design gpio_control_block current_design gpio_control_block
############################################################################### ###############################################################################
@ -57,52 +57,53 @@ set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_port
############################################################################### ###############################################################################
# Environment # Environment
############################################################################### ###############################################################################
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_in}] set_load -pin_load 0.2500 [get_ports {mgmt_gpio_in}]
set_load -pin_load 0.0334 [get_ports {one}] set_load -pin_load 0.2500 [get_ports {one}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_en}] set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_en}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_pol}] set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_pol}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_sel}] set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_sel}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_holdover}] set_load -pin_load 0.2500 [get_ports {pad_gpio_holdover}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_ib_mode_sel}] set_load -pin_load 0.2500 [get_ports {pad_gpio_ib_mode_sel}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_inenb}] set_load -pin_load 0.2500 [get_ports {pad_gpio_inenb}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_out}] set_load -pin_load 0.2500 [get_ports {pad_gpio_out}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_outenb}] set_load -pin_load 0.2500 [get_ports {pad_gpio_outenb}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_slow_sel}] set_load -pin_load 0.2500 [get_ports {pad_gpio_slow_sel}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_vtrip_sel}] set_load -pin_load 0.2500 [get_ports {pad_gpio_vtrip_sel}]
set_load -pin_load 0.0334 [get_ports {resetn_out}] set_load -pin_load 0.2500 [get_ports {resetn_out}]
set_load -pin_load 0.0334 [get_ports {serial_clock_out}] set_load -pin_load 0.2500 [get_ports {serial_clock_out}]
set_load -pin_load 0.0334 [get_ports {serial_data_out}] set_load -pin_load 0.2500 [get_ports {serial_data_out}]
set_load -pin_load 0.0334 [get_ports {serial_load_out}] set_load -pin_load 0.2500 [get_ports {serial_load_out}]
set_load -pin_load 0.0334 [get_ports {user_gpio_in}] set_load -pin_load 0.2500 [get_ports {user_gpio_in}]
set_load -pin_load 0.0334 [get_ports {zero}] set_load -pin_load 0.2500 [get_ports {zero}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[2]}] set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[2]}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[1]}] set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[1]}]
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[0]}] set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_oeb}] set_input_transition 5.0000 [get_ports {mgmt_gpio_oeb}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_out}] set_input_transition 5.0000 [get_ports {mgmt_gpio_out}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pad_gpio_in}] set_input_transition 5.0000 [get_ports {pad_gpio_in}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetn}] set_input_transition 5.0000 [get_ports {resetn}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_clock}] set_input_transition 5.0000 [get_ports {serial_clock}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_data_in}] set_input_transition 5.0000 [get_ports {serial_data_in}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_load}] set_input_transition 5.0000 [get_ports {serial_load}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_oeb}] set_input_transition 5.0000 [get_ports {user_gpio_oeb}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_out}] set_input_transition 5.0000 [get_ports {user_gpio_out}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[12]}] set_input_transition 5.0000 [get_ports {gpio_defaults[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[11]}] set_input_transition 5.0000 [get_ports {gpio_defaults[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[10]}] set_input_transition 5.0000 [get_ports {gpio_defaults[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[9]}] set_input_transition 5.0000 [get_ports {gpio_defaults[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[8]}] set_input_transition 5.0000 [get_ports {gpio_defaults[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[7]}] set_input_transition 5.0000 [get_ports {gpio_defaults[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[6]}] set_input_transition 5.0000 [get_ports {gpio_defaults[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[5]}] set_input_transition 5.0000 [get_ports {gpio_defaults[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[4]}] set_input_transition 5.0000 [get_ports {gpio_defaults[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[3]}] set_input_transition 5.0000 [get_ports {gpio_defaults[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[2]}] set_input_transition 5.0000 [get_ports {gpio_defaults[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[1]}] set_input_transition 5.0000 [get_ports {gpio_defaults[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[0]}] set_input_transition 5.0000 [get_ports {gpio_defaults[0]}]
set_timing_derate -early 0.9500 set_timing_derate -early 0.9500
set_timing_derate -late 1.0500 set_timing_derate -late 1.0500
############################################################################### ###############################################################################
# Design Rules # Design Rules
############################################################################### ###############################################################################
set_max_fanout 5.0000 [current_design] set_max_transition 1.2500 [current_design]
set_max_fanout 7.0000 [current_design]

1916
sdf/gpio_control_block.sdf
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File diff suppressed because it is too large Load Diff

7471
spef/gpio_control_block.spef
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File diff suppressed because it is too large Load Diff

529
spi/lvs/gpio_control_block.spice
View File

@ -1,31 +1,19 @@
* NGSPICE file created from gpio_control_block.ext - technology: sky130A * NGSPICE file created from gpio_control_block.ext - technology: sky130A
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_2 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_4 abstract view
.subckt sky130_fd_sc_hd__dfrtp_2 CLK D RESET_B VGND VNB VPB VPWR Q .subckt sky130_fd_sc_hd__dfrtp_4 CLK D RESET_B VGND VNB VPB VPWR Q
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__and2b_2 abstract view
.subckt sky130_fd_sc_hd__and2b_2 A_N B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_2 abstract view
.subckt sky130_fd_sc_hd__dfbbn_2 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR .subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__nand2b_2 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_2 abstract view
.subckt sky130_fd_sc_hd__nand2b_2 A_N B VGND VNB VPB VPWR Y .subckt sky130_fd_sc_hd__dfbbn_2 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_16 abstract view
.subckt sky130_fd_sc_hd__buf_16 A VGND VNB VPB VPWR X
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_16 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_16 abstract view
@ -36,32 +24,32 @@
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y .subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR .subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__dlygate4sd3_1 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__dlygate4sd3_1 abstract view
.subckt sky130_fd_sc_hd__dlygate4sd3_1 A VGND VNB VPB VPWR X .subckt sky130_fd_sc_hd__dlygate4sd3_1 A VGND VNB VPB VPWR X
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_12 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR .subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_6 abstract view
.subckt sky130_fd_sc_hd__decap_6 VGND VNB VPB VPWR
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO .subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_2 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__nand2b_2 abstract view
.subckt sky130_fd_sc_hd__or2_2 A B VGND VNB VPB VPWR X .subckt sky130_fd_sc_hd__nand2b_2 A_N B VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_0 abstract view
.subckt sky130_fd_sc_hd__or2_0 A B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_2 abstract view
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__einvp_8 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__einvp_8 abstract view
@ -72,32 +60,44 @@
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR .subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__o21ai_4 abstract view
.subckt sky130_fd_sc_hd__o21ai_4 A1 A2 B1 VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_6 abstract view
.subckt sky130_fd_sc_hd__decap_6 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for gpio_logic_high abstract view * Black-box entry subcircuit for gpio_logic_high abstract view
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1 .subckt gpio_logic_high gpio_logic1 vccd1 vssd1
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__ebufn_8 abstract view
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR .subckt sky130_fd_sc_hd__ebufn_8 A TE_B VGND VNB VPB VPWR Z
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__mux2_1 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__o21ai_2 abstract view
.subckt sky130_fd_sc_hd__mux2_1 A0 A1 S VGND VNB VPB VPWR X .subckt sky130_fd_sc_hd__o21ai_2 A1 A2 B1 VGND VNB VPB VPWR Y
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__ebufn_2 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__and2b_2 abstract view
.subckt sky130_fd_sc_hd__ebufn_2 A TE_B VGND VNB VPB VPWR Z .subckt sky130_fd_sc_hd__and2b_2 A_N B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_2 abstract view
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__and3b_2 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__and3b_2 abstract view
.subckt sky130_fd_sc_hd__and3b_2 A_N B C VGND VNB VPB VPWR X .subckt sky130_fd_sc_hd__and3b_2 A_N B C VGND VNB VPB VPWR X
.ends .ends
* Black-box entry subcircuit for sky130_fd_sc_hd__a31o_2 abstract view * Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_2 abstract view
.subckt sky130_fd_sc_hd__a31o_2 A1 A2 A3 B1 VGND VNB VPB VPWR X .subckt sky130_fd_sc_hd__dfrtp_2 CLK D RESET_B VGND VNB VPB VPWR Q
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__mux2_4 abstract view
.subckt sky130_fd_sc_hd__mux2_4 A0 A1 S VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_0 abstract view
.subckt sky130_fd_sc_hd__and2_0 A B VGND VNB VPB VPWR X
.ends .ends
.subckt gpio_control_block gpio_defaults[0] gpio_defaults[10] gpio_defaults[11] gpio_defaults[12] .subckt gpio_control_block gpio_defaults[0] gpio_defaults[10] gpio_defaults[11] gpio_defaults[12]
@ -108,318 +108,277 @@
+ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel + pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
+ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load + resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
+ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero + serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
X_131_ _131_/CLK hold1/A resetn vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__dfrtp_2 X_131_ _134_/CLK _131_/D _085_/A vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_4
X_062_ _105_/Q user_gpio_oeb vssd vssd vccd vccd _062_/X sky130_fd_sc_hd__and2b_2 XFILLER_0_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__132__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XFILLER_20_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_114_ _101__10/Y hold1/X _085_/X _086_/Y vssd vssd vccd vccd pad_gpio_dm[2] _114_/Q_N X_114_ _101__6/Y _127_/D _081_/X _082_/Y vssd vssd vccd vccd _114_/Q _114_/Q_N sky130_fd_sc_hd__dfbbn_2
+ sky130_fd_sc_hd__dfbbn_2 Xoutput20 _135_/Q vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_16
XFILLER_13_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 Xoutput7 _121_/Q vssd vssd vccd vccd pad_gpio_ana_pol sky130_fd_sc_hd__buf_16
XFILLER_15_65 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 X_130_ _130_/CLK hold8/X _095_/A vssd vssd vccd vccd _130_/Q sky130_fd_sc_hd__dfrtp_4
X_130_ _133_/A _130_/D resetn vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_2 X_113_ _100__5/Y hold6/X _079_/X _080_/Y vssd vssd vccd vccd _113_/Q _113_/Q_N sky130_fd_sc_hd__dfbbn_2
X_061_ pad_gpio_inenb _111_/Q vssd vssd vccd vccd _061_/Y sky130_fd_sc_hd__nand2b_2 Xclkbuf_1_0__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _103__8/A sky130_fd_sc_hd__clkbuf_16
X_113_ _100__9/Y _130_/D _083_/X _084_/Y vssd vssd vccd vccd pad_gpio_dm[1] _113_/Q_N X_097__2 _104__9/A vssd vssd vccd vccd _097__2/Y sky130_fd_sc_hd__inv_2
+ sky130_fd_sc_hd__dfbbn_2 Xoutput8 _120_/Q vssd vssd vccd vccd pad_gpio_ana_sel sky130_fd_sc_hd__buf_16
Xclkbuf_1_0__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _100__9/A sky130_fd_sc_hd__clkbuf_16 Xoutput10 _117_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_16
XANTENNA__135__A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_060_ _139_/A vssd vssd vccd vccd _060_/Y sky130_fd_sc_hd__inv_2
X_104__13 _100__9/A vssd vssd vccd vccd _104__13/Y sky130_fd_sc_hd__inv_2 X_112_ _099__4/Y hold1/X _077_/X _078_/Y vssd vssd vccd vccd _112_/Q _112_/Q_N sky130_fd_sc_hd__dfbbn_2
X_094__3 _134_/A vssd vssd vccd vccd _094__3/Y sky130_fd_sc_hd__inv_2 XANTENNA__065__A0 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_18_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 Xhold10 _132_/Q vssd vssd vccd vccd _133_/D sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_18_44 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2 Xoutput9 _116_/Q vssd vssd vccd vccd pad_gpio_dm[0] sky130_fd_sc_hd__buf_16
Xhold10 _124_/Q vssd vssd vccd vccd _125_/D sky130_fd_sc_hd__dlygate4sd3_1 Xoutput11 _118_/Q vssd vssd vccd vccd pad_gpio_dm[2] sky130_fd_sc_hd__buf_16
XANTENNA__122__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__084__A_N _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_112_ _099__8/Y hold8/X _081_/X _082_/Y vssd vssd vccd vccd pad_gpio_dm[0] _065_/A1 XFILLER_3_48 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
+ sky130_fd_sc_hd__dfbbn_2 X_111_ _098__3/Y _131_/D _075_/X _076_/Y vssd vssd vccd vccd _111_/Q _111_/Q_N sky130_fd_sc_hd__dfbbn_2
XANTENNA__065__A0 mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 Xhold11 _127_/Q vssd vssd vccd vccd _128_/D sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__061__A_N pad_gpio_inenb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_107__12 _103__8/A vssd vssd vccd vccd _107__12/Y sky130_fd_sc_hd__inv_2
XANTENNA__084__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 Xoutput12 _110_/Q vssd vssd vccd vccd pad_gpio_holdover sky130_fd_sc_hd__buf_16
X_111_ _098__7/Y hold5/X _079_/X _080_/Y vssd vssd vccd vccd _111_/Q _111_/Q_N sky130_fd_sc_hd__dfbbn_2 X_110_ _097__2/Y hold4/X _073_/X _074_/Y vssd vssd vccd vccd _110_/Q _110_/Q_N sky130_fd_sc_hd__dfbbn_2
XANTENNA__067__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 Xhold12 _130_/Q vssd vssd vccd vccd _131_/D sky130_fd_sc_hd__dlygate4sd3_1
Xhold11 _125_/Q vssd vssd vccd vccd _126_/D sky130_fd_sc_hd__dlygate4sd3_1 XANTENNA__072__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_11_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12 XANTENNA__074__A_N _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__075__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 Xoutput13 _114_/Q vssd vssd vccd vccd pad_gpio_ib_mode_sel sky130_fd_sc_hd__buf_16
XFILLER_18_79 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 XANTENNA__083__A _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__131__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__080__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_18_24 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2 XANTENNA__075__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__072__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 Xhold13 _126_/Q vssd vssd vccd vccd _127_/D sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__074__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__083__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_110_ _097__6/Y hold9/X _077_/X _078_/Y vssd vssd vccd vccd pad_gpio_ib_mode_sel
+ _110_/Q_N sky130_fd_sc_hd__dfbbn_2
Xhold12 _123_/Q vssd vssd vccd vccd _124_/D sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_1_71 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
XFILLER_1_82 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__067__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__083__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__080__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_12_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
XFILLER_3_39 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__064__C mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__075__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__091__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold13 _129_/Q vssd vssd vccd vccd _130_/D sky130_fd_sc_hd__dlygate4sd3_1
X_097__6 _100__9/A vssd vssd vccd vccd _097__6/Y sky130_fd_sc_hd__inv_2
XANTENNA__083__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__078__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_7_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__064__A_N pad_gpio_dm[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__078__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__089__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 Xoutput14 _113_/Q vssd vssd vccd vccd pad_gpio_inenb sky130_fd_sc_hd__buf_16
XANTENNA__125__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__125__RESET_B _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__091__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__091__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__086__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__086__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_18_48 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4 Xoutput15 _070_/Y vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__buf_16
XFILLER_18_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__089__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__094__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xconst_source vssd vssd vccd vccd one zero sky130_fd_sc_hd__conb_1 XANTENNA__089__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__119__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_100__5 _104__9/A vssd vssd vccd vccd _100__5/Y sky130_fd_sc_hd__inv_2
Xconst_source vssd vssd vccd vccd one_buffer/A zero_buffer/A sky130_fd_sc_hd__conb_1
XFILLER_19_70 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xoutput16 _065_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__buf_16
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_1_75 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 Xoutput17 _111_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_16
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_079_ resetn gpio_defaults[1] vssd vssd vccd vccd _079_/X sky130_fd_sc_hd__or2_2 XFILLER_10_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__128__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_096_ _095_/A gpio_defaults[7] vssd vssd vccd vccd _096_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_1_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_1_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_079_ _083_/A gpio_defaults[3] vssd vssd vccd vccd _079_/X sky130_fd_sc_hd__or2_0
Xoutput18 _112_/Q vssd vssd vccd vccd pad_gpio_vtrip_sel sky130_fd_sc_hd__buf_16
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__090__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_095_ _095_/A gpio_defaults[7] vssd vssd vccd vccd _095_/X sky130_fd_sc_hd__or2_0
XFILLER_18_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12 XANTENNA_input4_A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_078_ resetn gpio_defaults[4] vssd vssd vccd vccd _078_/Y sky130_fd_sc_hd__nand2b_2 X_078_ _085_/A gpio_defaults[9] vssd vssd vccd vccd _078_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_7_76 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 Xoutput19 _136_/X vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_16
XFILLER_7_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_103__8 _103__8/A vssd vssd vccd vccd _103__8/Y sky130_fd_sc_hd__inv_2
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__080__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 Xfanout21 _095_/A vssd vssd vccd vccd _091_/A sky130_fd_sc_hd__buf_2
XFILLER_10_76 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 XANTENNA__080__A_N _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_1_56 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12 X_094_ _091_/A gpio_defaults[6] vssd vssd vccd vccd _094_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_1_78 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 X_077_ _089_/A gpio_defaults[9] vssd vssd vccd vccd _077_/X sky130_fd_sc_hd__or2_0
X_100__9 _100__9/A vssd vssd vccd vccd _100__9/Y sky130_fd_sc_hd__inv_2 X_129_ _130_/CLK hold9/X _095_/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_4
X_077_ resetn gpio_defaults[4] vssd vssd vccd vccd _077_/X sky130_fd_sc_hd__or2_2
X_129_ _133_/A hold8/X resetn vssd vssd vccd vccd _129_/Q sky130_fd_sc_hd__dfrtp_2
X_103__12 _100__9/A vssd vssd vccd vccd _103__12/Y sky130_fd_sc_hd__inv_2
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_8_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2 Xfanout22 fanout28/X vssd vssd vccd vccd _095_/A sky130_fd_sc_hd__buf_2
X_076_ resetn gpio_defaults[3] vssd vssd vccd vccd _076_/Y sky130_fd_sc_hd__nand2b_2 X_093_ _095_/A gpio_defaults[6] vssd vssd vccd vccd _093_/X sky130_fd_sc_hd__or2_0
XFILLER_10_44 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 X_076_ _085_/A gpio_defaults[8] vssd vssd vccd vccd _076_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_1_68 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 Xinput1 mgmt_gpio_oeb vssd vssd vccd vccd _067_/C sky130_fd_sc_hd__buf_2
XANTENNA__070__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_128_ _130_/CLK _128_/D _095_/A vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_4
X_128_ _133_/A hold2/X resetn vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_2
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__121__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 Xfanout23 _072_/A_N vssd vssd vccd vccd _083_/A sky130_fd_sc_hd__buf_2
X_092_ resetn gpio_defaults[7] vssd vssd vccd vccd _092_/Y sky130_fd_sc_hd__nand2b_2 X_092_ _091_/A gpio_defaults[5] vssd vssd vccd vccd _092_/Y sky130_fd_sc_hd__nand2b_2
Xgpio_in_buf _058_/Y gpio_in_buf/TE vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__einvp_8 Xgpio_in_buf _060_/Y gpio_in_buf/TE vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__einvp_8
XFILLER_16_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4 XANTENNA_input2_A mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_075_ resetn gpio_defaults[3] vssd vssd vccd vccd _075_/X sky130_fd_sc_hd__or2_2 Xinput2 mgmt_gpio_out vssd vssd vccd vccd input2/X sky130_fd_sc_hd__buf_2
X_058_ pad_gpio_in vssd vssd vccd vccd _058_/Y sky130_fd_sc_hd__inv_2 X_075_ _085_/A gpio_defaults[8] vssd vssd vccd vccd _075_/X sky130_fd_sc_hd__or2_0
X_127_ _130_/CLK _127_/D _091_/A vssd vssd vccd vccd _127_/Q sky130_fd_sc_hd__dfrtp_4
XANTENNA_clkbuf_0_serial_load_A serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA_clkbuf_0_serial_load_A serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_127_ _133_/A hold7/X resetn vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_2
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_074_ resetn gpio_defaults[9] vssd vssd vccd vccd _074_/Y sky130_fd_sc_hd__nand2b_2 X_106__11 _103__8/A vssd vssd vccd vccd _106__11/Y sky130_fd_sc_hd__inv_2
X_091_ resetn gpio_defaults[7] vssd vssd vccd vccd _091_/X sky130_fd_sc_hd__or2_2 Xfanout24 fanout28/X vssd vssd vccd vccd _072_/A_N sky130_fd_sc_hd__buf_2
X_126_ _126_/CLK _126_/D resetn vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_2 XFILLER_19_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_70 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
Xinput3 pad_gpio_in vssd vssd vccd vccd _139_/A sky130_fd_sc_hd__buf_2
X_091_ _091_/A gpio_defaults[5] vssd vssd vccd vccd _091_/X sky130_fd_sc_hd__or2_0
X_074_ _083_/A gpio_defaults[2] vssd vssd vccd vccd _074_/Y sky130_fd_sc_hd__nand2b_2
X_126_ _130_/CLK hold6/X _091_/A vssd vssd vccd vccd _126_/Q sky130_fd_sc_hd__dfrtp_4
X_098__3 _103__8/A vssd vssd vccd vccd _098__3/Y sky130_fd_sc_hd__inv_2
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_095__4 _134_/A vssd vssd vccd vccd _095__4/Y sky130_fd_sc_hd__inv_2 X_109_ _061__1/Y hold3/X _071_/X _072_/Y vssd vssd vccd vccd _109_/Q _109_/Q_N sky130_fd_sc_hd__dfbbn_2
XFILLER_13_35 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 Xfanout25 fanout28/X vssd vssd vccd vccd _089_/A sky130_fd_sc_hd__buf_2
X_109_ _096__5/Y hold4/X _075_/X _076_/Y vssd vssd vccd vccd pad_gpio_inenb _109_/Q_N XTAP_71 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA__130__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_60 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_60 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_090_ resetn gpio_defaults[6] vssd vssd vccd vccd _090_/Y sky130_fd_sc_hd__nand2b_2 Xinput4 resetn vssd vssd vccd vccd input4/X sky130_fd_sc_hd__buf_2
XANTENNA__073__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_090_ _136_/A gpio_defaults[12] vssd vssd vccd vccd _090_/Y sky130_fd_sc_hd__nand2b_2
XANTENNA__062__B user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_073_ _083_/A gpio_defaults[2] vssd vssd vccd vccd _073_/X sky130_fd_sc_hd__or2_0
X_073_ resetn gpio_defaults[9] vssd vssd vccd vccd _073_/X sky130_fd_sc_hd__or2_2 X_125_ _130_/CLK hold4/X _083_/A vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_4
XFILLER_2_70 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 XANTENNA__073__A _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_125_ _126_/CLK _125_/D resetn vssd vssd vccd vccd _125_/Q sky130_fd_sc_hd__dfrtp_2 Xfanout26 fanout28/X vssd vssd vccd vccd _136_/A sky130_fd_sc_hd__buf_2
XANTENNA__070__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XTAP_72 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_108_ _095__4/Y hold2/X _073_/X _074_/Y vssd vssd vccd vccd pad_gpio_vtrip_sel _108_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA__081__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_61 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_61 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_072_ resetn gpio_defaults[8] vssd vssd vccd vccd _072_/Y sky130_fd_sc_hd__nand2b_2 X_072_ _072_/A_N gpio_defaults[0] vssd vssd vccd vccd _072_/Y sky130_fd_sc_hd__nand2b_2
XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__086__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 Xinput5 serial_data_in vssd vssd vccd vccd _122_/D sky130_fd_sc_hd__buf_2
XANTENNA__068__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_124_ _130_/CLK hold5/X _072_/A_N vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_4
XANTENNA__073__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__073__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_124_ _126_/CLK _124_/D resetn vssd vssd vccd vccd _124_/Q sky130_fd_sc_hd__dfrtp_2 Xfanout27 fanout28/X vssd vssd vccd vccd _085_/A sky130_fd_sc_hd__buf_2
XANTENNA__079__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__079__A _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_14_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12 XANTENNA__076__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_107_ _094__3/Y hold7/X _071_/X _072_/Y vssd vssd vccd vccd pad_gpio_slow_sel _107_/Q_N XANTENNA__081__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
+ sky130_fd_sc_hd__dfbbn_2 XTAP_73 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__124__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_071_ _089_/A gpio_defaults[0] vssd vssd vccd vccd _071_/X sky130_fd_sc_hd__or2_0
X_060__14 _133_/A vssd vssd vccd vccd _131_/CLK sky130_fd_sc_hd__inv_2
XANTENNA__076__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__081__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_62 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_62 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_071_ resetn gpio_defaults[8] vssd vssd vccd vccd _071_/X sky130_fd_sc_hd__or2_2
XFILLER_10_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__087__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_123_ _130_/CLK hold3/X _072_/A_N vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_4
XTAP_40 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XANTENNA__084__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_2_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 Xfanout28 input4/X vssd vssd vccd vccd fanout28/X sky130_fd_sc_hd__buf_2
X_106_ _093__2/Y hold3/X _069_/X _070_/Y vssd vssd vccd vccd pad_gpio_holdover _106_/Q_N XANTENNA__079__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
+ sky130_fd_sc_hd__dfbbn_2
X_123_ _126_/CLK hold9/X resetn vssd vssd vccd vccd _123_/Q sky130_fd_sc_hd__dfrtp_2
XANTENNA__084__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__079__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__076__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_070_ resetn gpio_defaults[2] vssd vssd vccd vccd _070_/Y sky130_fd_sc_hd__nand2b_2
XTAP_63 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_63 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__118__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_070_ _068_/X _069_/Y _066_/Y vssd vssd vccd vccd _070_/Y sky130_fd_sc_hd__o21ai_4
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__092__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__092__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__087__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__087__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_41 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 X_122_ _134_/CLK _122_/D _072_/A_N vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_4
X_098__7 _134_/A vssd vssd vccd vccd _098__7/Y sky130_fd_sc_hd__inv_2 XANTENNA__095__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_122_ _126_/CLK hold4/X resetn vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_2 Xserial_clock_out_buffer _134_/CLK vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_16
XFILLER_2_40 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_105_ _059__1/Y hold6/X _067_/X _068_/Y vssd vssd vccd vccd _105_/Q _105_/Q_N sky130_fd_sc_hd__dfbbn_2
XTAP_64 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_64 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_53 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_53 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_42 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_42 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_121_ _126_/CLK hold3/X resetn vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_2 XFILLER_2_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_12_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12 X_121_ _108__13/Y hold8/X _095_/X _096_/Y vssd vssd vccd vccd _121_/Q _121_/Q_N sky130_fd_sc_hd__dfbbn_2
XTAP_65 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_65 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_14_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_54 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_54 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_101__6 _103__8/A vssd vssd vccd vccd _101__6/Y sky130_fd_sc_hd__inv_2
XTAP_43 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_43 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_120_ _126_/CLK hold5/X resetn vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_2 X_120_ _107__12/Y hold9/X _093_/X _094_/Y vssd vssd vccd vccd _120_/Q _120_/Q_N sky130_fd_sc_hd__dfbbn_2
XANTENNA__127__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XFILLER_2_42 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
XFILLER_17_72 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 XFILLER_8_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold1 hold1/A vssd vssd vccd vccd hold1/X sky130_fd_sc_hd__dlygate4sd3_1 Xhold1 hold1/A vssd vssd vccd vccd hold1/X sky130_fd_sc_hd__dlygate4sd3_1
XTAP_66 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_55 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_55 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_44 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_44 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_102__11 _100__9/A vssd vssd vccd vccd _102__11/Y sky130_fd_sc_hd__inv_2
Xhold2 hold2/A vssd vssd vccd vccd hold2/X sky130_fd_sc_hd__dlygate4sd3_1 Xhold2 hold2/A vssd vssd vccd vccd hold2/X sky130_fd_sc_hd__dlygate4sd3_1
Xclkbuf_0_serial_load serial_load vssd vssd vccd vccd clkbuf_0_serial_load/X sky130_fd_sc_hd__clkbuf_16 Xclkbuf_0_serial_load serial_load vssd vssd vccd vccd clkbuf_0_serial_load/X sky130_fd_sc_hd__clkbuf_16
Xclkbuf_1_0__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _126_/CLK Xclkbuf_1_0__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _130_/CLK
+ sky130_fd_sc_hd__clkbuf_16 + sky130_fd_sc_hd__clkbuf_16
XFILLER_14_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 XTAP_67 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_56 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_56 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
Xgpio_logic_high gpio_in_buf/TE vccd1 vssd1 gpio_logic_high Xgpio_logic_high gpio_in_buf/TE vccd1 vssd1 gpio_logic_high
XFILLER_2_44 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_5_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_40 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
Xone_buffer one_buffer/A vssd vssd vccd vccd one sky130_fd_sc_hd__buf_16
XFILLER_8_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold3 hold3/A vssd vssd vccd vccd hold3/X sky130_fd_sc_hd__dlygate4sd3_1 Xhold3 hold3/A vssd vssd vccd vccd hold3/X sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_10_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_68 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XPHY_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_46 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_46 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__120__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_105__10 _104__9/A vssd vssd vccd vccd _105__10/Y sky130_fd_sc_hd__inv_2
Xhold4 hold4/A vssd vssd vccd vccd hold4/X sky130_fd_sc_hd__dlygate4sd3_1 Xhold4 hold4/A vssd vssd vccd vccd hold4/X sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__092__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_104__9 _104__9/A vssd vssd vccd vccd _104__9/Y sky130_fd_sc_hd__inv_2
XTAP_69 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_14_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_58 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_58 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_5_56 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_47 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_47 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_093__2 _134_/A vssd vssd vccd vccd _093__2/Y sky130_fd_sc_hd__inv_2
XPHY_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_0_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_17_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold5 hold5/A vssd vssd vccd vccd hold5/X sky130_fd_sc_hd__dlygate4sd3_1 Xhold5 hold5/A vssd vssd vccd vccd hold5/X sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__082__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_59 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_59 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XPHY_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_48 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XPHY_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_17_11 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 XTAP_48 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_089_ _089_/A gpio_defaults[12] vssd vssd vccd vccd _089_/X sky130_fd_sc_hd__or2_0
Xhold6 hold6/A vssd vssd vccd vccd hold6/X sky130_fd_sc_hd__dlygate4sd3_1 Xhold6 hold6/A vssd vssd vccd vccd hold6/X sky130_fd_sc_hd__dlygate4sd3_1
X_089_ resetn gpio_defaults[6] vssd vssd vccd vccd _089_/X sky130_fd_sc_hd__or2_2 Xzero_buffer zero_buffer/A vssd vssd vccd vccd zero sky130_fd_sc_hd__buf_16
XTAP_49 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XTAP_49 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_38 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1 XFILLER_0_91 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_0_80 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
XPHY_33 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_33 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__072__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16 Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__063__A2 mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA_input5_A serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_2_48 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__118__D serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XFILLER_3_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_088_ resetn gpio_defaults[5] vssd vssd vccd vccd _088_/Y sky130_fd_sc_hd__nand2b_2 X_088_ _089_/A gpio_defaults[11] vssd vssd vccd vccd _088_/Y sky130_fd_sc_hd__nand2b_2
XANTENNA__058__A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold7 hold7/A vssd vssd vccd vccd hold7/X sky130_fd_sc_hd__dlygate4sd3_1 Xhold7 hold7/A vssd vssd vccd vccd hold7/X sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__071__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_39 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__066__A0 user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__123__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_087_ _089_/A gpio_defaults[11] vssd vssd vccd vccd _087_/X sky130_fd_sc_hd__or2_0
Xclkbuf_1_1__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _134_/A sky130_fd_sc_hd__clkbuf_16 X_099__4 _104__9/A vssd vssd vccd vccd _099__4/Y sky130_fd_sc_hd__inv_2
XANTENNA__069__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_087_ resetn gpio_defaults[5] vssd vssd vccd vccd _087_/X sky130_fd_sc_hd__or2_2
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__dlygate4sd3_1 Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__dlygate4sd3_1
X_096__5 _134_/A vssd vssd vccd vccd _096__5/Y sky130_fd_sc_hd__inv_2 Xclkbuf_1_1__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _104__9/A sky130_fd_sc_hd__clkbuf_16
XANTENNA__071__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__071__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_139_ _139_/A _063_/Y vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_8
XANTENNA__066__B user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8 X_086_ _085_/A gpio_defaults[10] vssd vssd vccd vccd _086_/Y sky130_fd_sc_hd__nand2b_2
XANTENNA__077__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 Xclkbuf_1_1__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _134_/CLK
X_086_ resetn gpio_defaults[12] vssd vssd vccd vccd _086_/Y sky130_fd_sc_hd__nand2b_2 + sky130_fd_sc_hd__clkbuf_16
XANTENNA__074__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__074__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xclkbuf_1_1__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__clkbuf_16
XFILLER_11_48 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_11_15 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_3_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__085__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_069_ resetn gpio_defaults[2] vssd vssd vccd vccd _069_/X sky130_fd_sc_hd__or2_2
XANTENNA__069__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold9 hold9/A vssd vssd vccd vccd hold9/X sky130_fd_sc_hd__dlygate4sd3_1 Xhold9 hold9/A vssd vssd vccd vccd hold9/X sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_0_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 X_069_ input2/X _068_/B _109_/Q vssd vssd vccd vccd _069_/Y sky130_fd_sc_hd__o21ai_2
XFILLER_6_60 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 X_108__13 _103__8/A vssd vssd vccd vccd _108__13/Y sky130_fd_sc_hd__inv_2
XANTENNA__082__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__082__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__077__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__077__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__085__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA_input3_A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_085_ resetn gpio_defaults[12] vssd vssd vccd vccd _085_/X sky130_fd_sc_hd__or2_2 XANTENNA__090__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__090__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA__085__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_068_ resetn gpio_defaults[0] vssd vssd vccd vccd _068_/Y sky130_fd_sc_hd__nand2b_2 X_085_ _085_/A gpio_defaults[10] vssd vssd vccd vccd _085_/X sky130_fd_sc_hd__or2_0
XFILLER_17_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8 X_068_ _116_/Q_N _068_/B vssd vssd vccd vccd _068_/X sky130_fd_sc_hd__and2b_2
XPHY_37 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_37 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_14_38 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 XANTENNA__093__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_6_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 XANTENNA__088__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__088__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_067_ _118_/Q _117_/Q _067_/C vssd vssd vccd vccd _068_/B sky130_fd_sc_hd__and3b_2
XANTENNA__088__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_136_ _136_/A vssd vssd vccd vccd _136_/X sky130_fd_sc_hd__buf_2
X_067_ resetn gpio_defaults[0] vssd vssd vccd vccd _067_/X sky130_fd_sc_hd__or2_2 X_084_ _083_/A gpio_defaults[1] vssd vssd vccd vccd _084_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_8_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 XANTENNA__096__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_0_52 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12 X_119_ _106__11/Y _128_/D _091_/X _092_/Y vssd vssd vccd vccd _119_/Q _119_/Q_N sky130_fd_sc_hd__dfbbn_2
X_084_ resetn gpio_defaults[11] vssd vssd vccd vccd _084_/Y sky130_fd_sc_hd__nand2b_2 X_062__14 _130_/CLK vssd vssd vccd vccd _135_/CLK sky130_fd_sc_hd__inv_2
X_119_ _126_/CLK hold6/X resetn vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_2 XPHY_38 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__126__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_101__10 _134_/A vssd vssd vccd vccd _101__10/Y sky130_fd_sc_hd__inv_2
XPHY_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__078__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_083_ _083_/A gpio_defaults[1] vssd vssd vccd vccd _083_/X sky130_fd_sc_hd__or2_0
X_083_ resetn gpio_defaults[11] vssd vssd vccd vccd _083_/X sky130_fd_sc_hd__or2_2 X_118_ _105__10/Y hold7/X _089_/X _090_/Y vssd vssd vccd vccd _118_/Q _118_/Q_N sky130_fd_sc_hd__dfbbn_2
X_099__8 _100__9/A vssd vssd vccd vccd _099__8/Y sky130_fd_sc_hd__inv_2 X_135_ _135_/CLK hold7/A _136_/A vssd vssd vccd vccd _135_/Q sky130_fd_sc_hd__dfrtp_2
XFILLER_18_71 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 X_061__1 _104__9/A vssd vssd vccd vccd _061__1/Y sky130_fd_sc_hd__inv_2
X_118_ _133_/A serial_data_in resetn vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_2 X_066_ _109_/Q user_gpio_out vssd vssd vccd vccd _066_/Y sky130_fd_sc_hd__nand2b_2
X_066_ user_gpio_out _065_/X _105_/Q vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__mux2_1 XFILLER_0_31 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_135_ pad_gpio_in _061_/Y vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_2 XPHY_39 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_0_64 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
XPHY_28 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_28 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_134_ _134_/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__buf_2 X_134_ _134_/CLK hold2/X _089_/A vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_4
X_059__1 _134_/A vssd vssd vccd vccd _059__1/Y sky130_fd_sc_hd__inv_2 X_065_ user_gpio_oeb _064_/X _109_/Q vssd vssd vccd vccd _065_/X sky130_fd_sc_hd__mux2_4
XFILLER_0_76 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 X_082_ _091_/A gpio_defaults[4] vssd vssd vccd vccd _082_/Y sky130_fd_sc_hd__nand2b_2
X_082_ resetn gpio_defaults[10] vssd vssd vccd vccd _082_/Y sky130_fd_sc_hd__nand2b_2 Xserial_load_out_buffer _104__9/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__clkbuf_16
X_065_ mgmt_gpio_out _065_/A1 _065_/S vssd vssd vccd vccd _065_/X sky130_fd_sc_hd__mux2_1 XANTENNA_input1_A mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__068__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_117_ _104__9/Y hold2/X _087_/X _088_/Y vssd vssd vccd vccd _117_/Q _117_/Q_N sky130_fd_sc_hd__dfbbn_2
XFILLER_18_61 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_15_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
X_117_ _104__13/Y _126_/D _091_/X _092_/Y vssd vssd vccd vccd pad_gpio_ana_pol _117_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XPHY_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_102__7 _104__9/A vssd vssd vccd vccd _102__7/Y sky130_fd_sc_hd__inv_2
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_081_ resetn gpio_defaults[10] vssd vssd vccd vccd _081_/X sky130_fd_sc_hd__or2_2 X_081_ _091_/A gpio_defaults[4] vssd vssd vccd vccd _081_/X sky130_fd_sc_hd__or2_0
X_133_ _133_/A vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__buf_2 X_133_ _134_/CLK _133_/D _089_/A vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_4
X_064_ pad_gpio_dm[2] pad_gpio_dm[1] mgmt_gpio_oeb vssd vssd vccd vccd _065_/S sky130_fd_sc_hd__and3b_2 X_064_ _115_/Q _067_/C vssd vssd vccd vccd _064_/X sky130_fd_sc_hd__and2_0
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3 XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_116_ _103__12/Y _125_/D _089_/X _090_/Y vssd vssd vccd vccd pad_gpio_ana_sel _116_/Q_N X_116_ _103__8/Y _133_/D _085_/X _086_/Y vssd vssd vccd vccd _116_/Q _116_/Q_N sky130_fd_sc_hd__dfbbn_2
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA_clkbuf_0_serial_clock_A serial_clock vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 XANTENNA_clkbuf_0_serial_clock_A serial_clock vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_080_ resetn gpio_defaults[1] vssd vssd vccd vccd _080_/Y sky130_fd_sc_hd__nand2b_2 X_063_ _113_/Q _115_/Q vssd vssd vccd vccd _063_/Y sky130_fd_sc_hd__nand2b_2
X_132_ resetn vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_2 X_132_ _134_/CLK hold1/X _085_/A vssd vssd vccd vccd _132_/Q sky130_fd_sc_hd__dfrtp_4
X_063_ _111_/Q mgmt_gpio_oeb _105_/Q _062_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__a31o_2 X_080_ _083_/A gpio_defaults[3] vssd vssd vccd vccd _080_/Y sky130_fd_sc_hd__nand2b_2
XANTENNA__129__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2 X_115_ _102__7/Y hold5/X _083_/X _084_/Y vssd vssd vccd vccd _115_/Q _115_/Q_N sky130_fd_sc_hd__dfbbn_2
XFILLER_18_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1 Xoutput6 _119_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_16
XFILLER_18_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_115_ _102__11/Y _124_/D _087_/X _088_/Y vssd vssd vccd vccd pad_gpio_ana_en _115_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
.ends .ends

1170
verilog/gl/gpio_control_block.v
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