Add test hk_disable

verilog/dv/cocotb/tests.json

@@ -227,5 +227,12 @@
             "GL":["r_gl","nightly","weekly","tape_out"],
             "GL_SDF":["r_sdf","weekly","tape_out"],
             "description":"check clock redirect is working as expected"}
+
+        ,"hk_disable" :{"level":0, 
+            "SW":true,
+            "RTL":["r_rtl","setup","nightly","weekly","tape_out"],
+            "GL":["r_gl","nightly","weekly","tape_out"],
+            "GL_SDF":["r_sdf","weekly","tape_out"],
+            "description":"check Housekeeping SPI disable register is working"}
     }
 }

verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c

@@ -15,4 +15,4 @@ void main(){
     while (reg_mprj_xfer == 1);
     reg_debug_1 =0xAA;
     return; 
-    }
+}

verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c

@@ -0,0 +1,14 @@
+#include <defs.h>
+#include <stub.c>
+// --------------------------------------------------------
+
+void main(){
+    reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
+    reg_debug_1  = 0x0;
+    reg_debug_2  = 0xBB;
+
+    while (reg_debug_1 != 0xAA);
+    reg_hkspi_disable = 0;
+    // reg_hkspi_pll_ena =0;
+    reg_debug_1 =0xBB;
+}

verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py

@@ -1,3 +1,4 @@
+from faulthandler import disable
 import random
 import cocotb
 from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
@@ -18,7 +19,7 @@ core_clock = 0
 @cocotb.test()
 @repot_test
 async def clock_redirect(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=13060)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -86,3 +87,61 @@ async def calculate_clk_period(clk,name):
         core_clock = val         
     return val
 
+
+@cocotb.test()
+@repot_test
+async def hk_disable(dut):
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=11243)
+    cpu = RiskV(dut)
+    cpu.cpu_force_reset()
+    cpu.cpu_release_reset()
+
+    # check spi working by writing to PLL enables
+    old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
+    cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
+    await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
+    pll_enable = dut.uut.housekeeping.pll_ena.value.integer
+    cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
+    if pll_enable == 1-old_pll_enable: 
+        cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}") 
+    else: 
+        cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}")
+    old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
+    cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
+    await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
+    pll_enable = dut.uut.housekeeping.pll_ena.value.integer
+    cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
+    if pll_enable == 1-old_pll_enable: 
+        cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}") 
+    else: 
+        cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}")
+            
+    # disable Housekeeping SPIca 
+    await write_reg_spi(caravelEnv,0x6f,0x1)
+
+    # try to change pll_en 
+    old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
+    cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
+    await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
+    pll_enable = dut.uut.housekeeping.pll_ena.value.integer
+    cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
+    if pll_enable == 1-old_pll_enable: 
+        cocotb.log.error(f"[TEST] Error: SPI swap pll_enable value from {old_pll_enable} to {pll_enable} while housekeeping spi is disabled") 
+    else: 
+        cocotb.log.info(f"[TEST] pass: SPI isn't working when SPI housekeeping is disabled")
+            
+    # enable SPI housekeeping through firmware 
+    await wait_reg2(cpu,caravelEnv,0xBB)  # start waiting on reg1 AA
+    cpu.write_debug_reg1_backdoor(0xAA) 
+    await wait_reg1(cpu,caravelEnv,0xBB) # enabled the housekeeping
+
+    old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
+    cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
+    await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
+    pll_enable = dut.uut.housekeeping.pll_ena.value.integer
+    cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
+    if pll_enable == 1-old_pll_enable: 
+        cocotb.log.info(f"[TEST] Pass: Housekeeping SPI has been enabled correctly through firmware") 
+    else: 
+        cocotb.log.error(f"[TEST] Error: Housekeeping SPI failed to be enabled through firmware")
+