mirror of https://github.com/efabless/caravel.git
chore: add self-review for 3 blocks:
* gpio_control_block * digital_pll * caravel_clocking
This commit is contained in:
kareem
parent
e5683a8967
commit
7e3a33f9d7
File diff suppressed because one or more lines are too long
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@ -0,0 +1,31 @@
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Max transition on internal signals: 1.25ns
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Hold WNS (F2F): 0.00
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Setup WNS (F2F): -0.52 (ss-max)
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lvs clean: Y
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drc clean: Y
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cvc clean: Y
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Antenna Violations: 0
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Antenna Violations (400-500): 0
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Antenna Violations (500-800): 0
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Antenna Violations (800-1000): 0
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non-physical cells: 1530 - 1216 = 314
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decap cell count: 460
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% decap: 460 / 1530 * 100 = 30.1%
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max ir drop: 8.10e-10 V
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Verilog "assign" in the netlist: N
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Does the netlist show cells from different libraries: N
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Does the macro have mixed power domains powered cells: N
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Any internal macros with floating input ports: N
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Output ports not connected to any logic inside the macro: N
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Input ports not connected to any logic inside the macro: N
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Tri-state cells are connected directly to output ports: N
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Analog Signals are not digitally buffered: N
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Output ports are properly buffred (>=buf_4): Y
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buffer cells count: 49
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logic cells that are not buffers count: 265
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buf_1 & buf_2 cells count: 12
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0.5mm or longer wire count: 0
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@ -0,0 +1,326 @@
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_050_ 1.45
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_072_ 1.45
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_168_ 1.72
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_093_ 1.79
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_190_ 1.84
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net36 1.84
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_098_ 2.035
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_165_ 2.06
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_089_ 2.13
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_146_ 2.18
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_148_ 2.18
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_154_ 2.18
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_198_ 2.18
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_172_ 2.3
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_091_ 2.375
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_135_ 2.375
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_140_ 2.375
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_194_ 2.375
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_196_ 2.375
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_078_ 2.47
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_157_ 2.47
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_017_ 2.52
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_163_ 2.52
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net3 2.52
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_066_ 2.615
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_076_ 2.615
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_170_ 2.64
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_052_ 2.715
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net32 2.715
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_164_ 2.79
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_006_ 2.835
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_021_ 2.835
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_038_ 2.835
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net31 2.835
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net33 2.835
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net35 2.835
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divider2.syncNp\[1\] 2.85
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_160_ 2.865
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_166_ 2.865
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_090_ 2.955
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_155_ 2.98
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_158_ 3.105
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_008_ 3.175
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_065_ 3.175
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_094_ 3.295
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_178_ 3.295
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_022_ 3.32
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_134_ 3.32
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reset_delay\[1\] 3.405
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net34 3.54
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_162_ 3.56
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_156_ 3.68
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_192_ 3.68
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_088_ 3.755
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_096_ 3.755
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_200_ 3.855
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_100_ 3.875
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_067_ 3.975
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_174_ 3.995
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_033_ 4.095
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_117_ 4.095
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net37 4.095
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reset_delay\[2\] 4.25
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_159_ 4.36
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_161_ 4.36
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_004_ 4.415
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_131_ 4.435
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_069_ 4.51
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_043_ 4.555
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_045_ 4.6
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_126_ 4.6
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_106_ 4.795
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_012_ 4.915
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_119_ 4.92
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divider2.odd_0.old_N\[0\] 5.015
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_068_ 5.06
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_123_ 5.095
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_101_ 5.135
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_115_ 5.135
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_102_ 5.255
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_189_ 5.28
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ext_clk_syncd 5.335
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reset_delay\[0\] 5.365
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_070_ 5.375
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_073_ 5.375
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_020_ 5.435
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_049_ 5.435
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net39 5.435
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divider.odd_0.old_N\[1\] 5.505
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_029_ 5.555
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_057_ 5.555
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_141_ 5.555
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_109_ 5.595
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_110_ 5.595
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_185_ 5.595
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_188_ 5.78
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_056_ 5.795
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divider2.odd_0.old_N\[2\] 5.84
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_075_ 5.895
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_095_ 5.935
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_107_ 5.935
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_181_ 5.935
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_199_ 5.935
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_099_ 6.015
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_180_ 6.055
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_114_ 6.175
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_015_ 6.18
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_019_ 6.2
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divider.syncNp\[1\] 6.245
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_016_ 6.355
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_132_ 6.355
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_103_ 6.42
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_047_ 6.5
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_097_ 6.595
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net10 6.595
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_007_ 6.6
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_133_ 6.69
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_187_ 6.695
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_013_ 6.735
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_186_ 6.735
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_112_ 6.76
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_169_ 6.78
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net38 6.815
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_018_ 6.855
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_048_ 6.855
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_183_ 6.87
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_014_ 6.9
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_040_ 6.975
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_124_ 7.275
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_025_ 7.3
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divider2.syncNp\[0\] 7.3
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_143_ 7.36
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sel2[0] 7.365
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_062_ 7.435
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_179_ 7.52
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_120_ 7.64
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clknet_1_0__leaf_ext_clk 7.675
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_111_ 7.68
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_193_ 7.68
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_113_ 7.755
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sel2[1] 7.83
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_149_ 7.86
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_171_ 7.9
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_054_ 7.935
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_116_ 7.98
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user_clk_buffered 7.98
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sel2[2] 8.005
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divider.odd_0.old_N\[2\] 8.12
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_092_ 8.275
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_153_ 8.315
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net30 8.32
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_173_ 8.455
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_077_ 8.595
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divider2.odd_0.rst_pulse 8.625
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sel[2] 8.73
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_055_ 8.835
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_104_ 8.9
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_176_ 8.915
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sel[0] 8.92
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_058_ 8.975
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ext_reset 9.065
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_144_ 9.08
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ext_clk_sel 9.405
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ext_clk_syncd_pre 9.435
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_184_ 9.455
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_122_ 9.575
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_182_ 9.655
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divider.syncNp\[0\] 9.74
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sel[1] 9.745
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_041_ 10.12
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resetb 10.26
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_036_ 10.29
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_027_ 10.32
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_037_ 10.775
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_009_ 10.78
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clknet_1_1__leaf_ext_clk 10.9
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divider2.syncNp\[2\] 10.9
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_175_ 10.915
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_060_ 10.92
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_061_ 11.12
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_121_ 11.535
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_074_ 11.575
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_152_ 11.675
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_125_ 11.72
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_118_ 11.915
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_059_ 12.075
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divider.odd_0.old_N\[0\] 12.12
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_024_ 12.155
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divider.odd_0.out_counter2 12.38
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_177_ 12.495
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_044_ 12.66
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_064_ 12.73
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divider.syncNp\[2\] 13.14
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_053_ 13.235
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_005_ 13.24
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_042_ 13.36
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_063_ 13.44
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divider.odd_0.rst_pulse 13.455
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_108_ 13.635
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_151_ 13.715
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_026_ 13.795
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_150_ 13.96
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_105_ 14.255
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_197_ 14.555
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divider2.odd_0.initial_begin\[2\] 14.595
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_191_ 14.69
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divider2.odd_0.old_N\[1\] 15.15
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_011_ 15.335
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_145_ 15.52
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_046_ 15.535
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_000_ 15.775
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clknet_0_net10 15.86
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divider.even_0.counter\[2\] 15.96
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_147_ 15.995
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_010_ 16.46
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_023_ 16.555
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_195_ 16.855
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core_clk 16.9
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ext_clk 17.44
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divider.out 17.555
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_002_ 17.93
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_039_ 18.175
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_035_ 18.41
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clknet_1_0__leaf__037_ 18.52
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divider2.even_0.counter\[2\] 19.035
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clknet_0_ext_clk 20.095
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_028_ 20.25
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divider.odd_0.out_counter 20.38
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_051_ 20.675
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net11 20.7
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_071_ 20.795
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divider2.out 21.46
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divider.even_0.counter\[1\] 21.945
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user_clk 22.04
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_031_ 22.535
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divider2.odd_0.counter2\[2\] 22.58
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divider2.odd_0.initial_begin\[1\] 22.64
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divider2.even_0.counter\[1\] 23.425
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_032_ 24.195
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divider2.odd_0.out_counter2 24.295
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clknet_0_pll_clk 25.185
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net2 26.44
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_139_ 26.685
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divider.odd_0.initial_begin\[2\] 27.1
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_003_ 27.45
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clknet_0_pll_clk90 27.75
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resetb_sync 28.755
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divider2.odd_0.initial_begin\[0\] 29.085
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clknet_0_divider2.out 29.11
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divider2.even_0.N\[2\] 29.52
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_136_ 29.935
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divider2.even_0.N\[0\] 30.06
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clknet_1_0__leaf_divider.out 30.195
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divider.even_0.out_counter 30.46
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clknet_1_1__leaf_divider.out 30.49
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clknet_1_1__leaf_net10 30.56
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_142_ 30.6
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clknet_1_1__leaf_divider2.out 30.985
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_130_ 31.2
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use_pll_second 31.495
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divider.odd_0.initial_begin\[0\] 31.54
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divider.odd_0.initial_begin\[1\] 34.305
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divider2.odd_0.counter2\[1\] 34.33
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clknet_0_divider.out 34.775
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_167_ 35.08
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divider.odd_0.counter2\[2\] 35.43
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divider.even_0.counter\[0\] 35.44
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net5 35.915
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clknet_1_1__leaf__037_ 36.555
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divider.even_0.N\[0\] 37.4
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divider2.even_0.out_counter 37.805
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net6 39.32
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divider.odd_0.counter2\[1\] 39.465
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_001_ 39.47
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clknet_1_0__leaf_divider2.out 39.5
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net1 41.16
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use_pll_first 41.655
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divider2.odd_0.counter\[0\] 44.09
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divider2.even_0.counter\[0\] 44.595
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divider.odd_0.counter2\[0\] 45.395
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divider2.odd_0.out_counter 45.525
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_138_ 46.275
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clknet_0__037_ 47.695
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net4 48.26
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_137_ 49.085
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divider.even_0.N\[2\] 49.23
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divider2.odd_0.counter2\[0\] 51.04
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_034_ 52.715
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_129_ 52.83
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divider.odd_0.counter\[2\] 54.365
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net9 55.195
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divider2.odd_0.counter\[2\] 56.065
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pll_clk90 56.695
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divider.odd_0.counter\[0\] 58.335
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net16 59.205
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divider.even_0.N\[1\] 59.265
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pll_clk_sel 60.08
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_030_ 63.345
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divider2.odd_0.counter\[1\] 64.815
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_127_ 68.685
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divider2.even_0.N\[1\] 74.42
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divider.odd_0.counter\[1\] 76.265
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net20 80.23
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clknet_1_1__leaf_pll_clk90 81.725
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net8 83.1
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pll_clk 83.92
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net21 90.58
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net23 93.17
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clknet_1_0__leaf_pll_clk90 105.3
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net7 109.635
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net25 114.165
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net22 118.28
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net15 121.335
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_128_ 122.47
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net24 124.99
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net29 129.47
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clknet_1_0__leaf_pll_clk 133.48
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net17 135.105
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net14 136.48
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net27 136.565
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clknet_1_1__leaf_pll_clk 140.0
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net26 140.915
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net13 176.145
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net28 185.145
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net18 186.43
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net19 205.98
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@ -0,0 +1,326 @@
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core_clk 16.9
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ext_clk 17.44
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ext_clk_sel 9.405
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ext_reset 9.065
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pll_clk 83.92
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pll_clk90 56.695
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resetb 10.26
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resetb_sync 28.755
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sel2[0] 7.365
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sel2[1] 7.83
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sel2[2] 8.005
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sel[0] 8.92
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sel[1] 9.745
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sel[2] 8.73
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user_clk 22.04
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_000_ 15.775
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_001_ 39.47
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_002_ 17.93
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_003_ 27.45
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_004_ 4.415
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_005_ 13.24
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_006_ 2.835
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_007_ 6.6
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_008_ 3.175
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_009_ 10.78
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_010_ 16.46
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_011_ 15.335
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_012_ 4.915
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_013_ 6.735
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_014_ 6.9
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_015_ 6.18
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_016_ 6.355
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_017_ 2.52
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_018_ 6.855
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_019_ 6.2
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_020_ 5.435
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_021_ 2.835
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_022_ 3.32
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_023_ 16.555
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_024_ 12.155
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_025_ 7.3
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_026_ 13.795
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_027_ 10.32
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_028_ 20.25
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_029_ 5.555
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_030_ 63.345
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_031_ 22.535
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_032_ 24.195
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_033_ 4.095
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_034_ 52.715
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_035_ 18.41
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_036_ 10.29
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_037_ 10.775
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_038_ 2.835
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_039_ 18.175
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_040_ 6.975
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_041_ 10.12
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_042_ 13.36
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_043_ 4.555
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_044_ 12.66
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_045_ 4.6
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_046_ 15.535
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_047_ 6.5
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_048_ 6.855
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_049_ 5.435
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_050_ 1.45
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_051_ 20.675
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_052_ 2.715
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_053_ 13.235
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_054_ 7.935
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_055_ 8.835
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_056_ 5.795
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_057_ 5.555
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_058_ 8.975
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_059_ 12.075
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_060_ 10.92
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_061_ 11.12
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_062_ 7.435
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_063_ 13.44
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_064_ 12.73
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_065_ 3.175
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_066_ 2.615
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_067_ 3.975
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_068_ 5.06
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_069_ 4.51
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_070_ 5.375
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_071_ 20.795
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_072_ 1.45
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_073_ 5.375
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_074_ 11.575
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_075_ 5.895
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_076_ 2.615
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_077_ 8.595
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_078_ 2.47
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_088_ 3.755
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_089_ 2.13
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_090_ 2.955
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_091_ 2.375
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_092_ 8.275
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_093_ 1.79
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_094_ 3.295
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_095_ 5.935
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_096_ 3.755
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_097_ 6.595
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_098_ 2.035
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_099_ 6.015
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_100_ 3.875
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_101_ 5.135
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_102_ 5.255
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_103_ 6.42
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_104_ 8.9
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_105_ 14.255
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_106_ 4.795
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_107_ 5.935
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_108_ 13.635
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_109_ 5.595
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_110_ 5.595
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_111_ 7.68
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_112_ 6.76
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_113_ 7.755
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_114_ 6.175
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_115_ 5.135
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_116_ 7.98
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_117_ 4.095
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_118_ 11.915
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_119_ 4.92
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_120_ 7.64
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_121_ 11.535
|
||||
_122_ 9.575
|
||||
_123_ 5.095
|
||||
_124_ 7.275
|
||||
_125_ 11.72
|
||||
_126_ 4.6
|
||||
_127_ 68.685
|
||||
_128_ 122.47
|
||||
_129_ 52.83
|
||||
_130_ 31.2
|
||||
_131_ 4.435
|
||||
_132_ 6.355
|
||||
_133_ 6.69
|
||||
_134_ 3.32
|
||||
_135_ 2.375
|
||||
_136_ 29.935
|
||||
_137_ 49.085
|
||||
_138_ 46.275
|
||||
_139_ 26.685
|
||||
_140_ 2.375
|
||||
_141_ 5.555
|
||||
_142_ 30.6
|
||||
_143_ 7.36
|
||||
_144_ 9.08
|
||||
_145_ 15.52
|
||||
_146_ 2.18
|
||||
_147_ 15.995
|
||||
_148_ 2.18
|
||||
_149_ 7.86
|
||||
_150_ 13.96
|
||||
_151_ 13.715
|
||||
_152_ 11.675
|
||||
_153_ 8.315
|
||||
_154_ 2.18
|
||||
_155_ 2.98
|
||||
_156_ 3.68
|
||||
_157_ 2.47
|
||||
_158_ 3.105
|
||||
_159_ 4.36
|
||||
_160_ 2.865
|
||||
_161_ 4.36
|
||||
_162_ 3.56
|
||||
_163_ 2.52
|
||||
_164_ 2.79
|
||||
_165_ 2.06
|
||||
_166_ 2.865
|
||||
_167_ 35.08
|
||||
_168_ 1.72
|
||||
_169_ 6.78
|
||||
_170_ 2.64
|
||||
_171_ 7.9
|
||||
_172_ 2.3
|
||||
_173_ 8.455
|
||||
_174_ 3.995
|
||||
_175_ 10.915
|
||||
_176_ 8.915
|
||||
_177_ 12.495
|
||||
_178_ 3.295
|
||||
_179_ 7.52
|
||||
_180_ 6.055
|
||||
_181_ 5.935
|
||||
_182_ 9.655
|
||||
_183_ 6.87
|
||||
_184_ 9.455
|
||||
_185_ 5.595
|
||||
_186_ 6.735
|
||||
_187_ 6.695
|
||||
_188_ 5.78
|
||||
_189_ 5.28
|
||||
_190_ 1.84
|
||||
_191_ 14.69
|
||||
_192_ 3.68
|
||||
_193_ 7.68
|
||||
_194_ 2.375
|
||||
_195_ 16.855
|
||||
_196_ 2.375
|
||||
_197_ 14.555
|
||||
_198_ 2.18
|
||||
_199_ 5.935
|
||||
_200_ 3.855
|
||||
clknet_0__037_ 47.695
|
||||
clknet_0_divider.out 34.775
|
||||
clknet_0_divider2.out 29.11
|
||||
clknet_0_ext_clk 20.095
|
||||
clknet_0_net10 15.86
|
||||
clknet_0_pll_clk 25.185
|
||||
clknet_0_pll_clk90 27.75
|
||||
clknet_1_0__leaf__037_ 18.52
|
||||
clknet_1_0__leaf_divider.out 30.195
|
||||
clknet_1_0__leaf_divider2.out 39.5
|
||||
clknet_1_0__leaf_ext_clk 7.675
|
||||
clknet_1_0__leaf_pll_clk 133.48
|
||||
clknet_1_0__leaf_pll_clk90 105.3
|
||||
clknet_1_1__leaf__037_ 36.555
|
||||
clknet_1_1__leaf_divider.out 30.49
|
||||
clknet_1_1__leaf_divider2.out 30.985
|
||||
clknet_1_1__leaf_ext_clk 10.9
|
||||
clknet_1_1__leaf_net10 30.56
|
||||
clknet_1_1__leaf_pll_clk 140.0
|
||||
clknet_1_1__leaf_pll_clk90 81.725
|
||||
divider.even_0.N\[0\] 37.4
|
||||
divider.even_0.N\[1\] 59.265
|
||||
divider.even_0.N\[2\] 49.23
|
||||
divider.even_0.counter\[0\] 35.44
|
||||
divider.even_0.counter\[1\] 21.945
|
||||
divider.even_0.counter\[2\] 15.96
|
||||
divider.even_0.out_counter 30.46
|
||||
divider.odd_0.counter2\[0\] 45.395
|
||||
divider.odd_0.counter2\[1\] 39.465
|
||||
divider.odd_0.counter2\[2\] 35.43
|
||||
divider.odd_0.counter\[0\] 58.335
|
||||
divider.odd_0.counter\[1\] 76.265
|
||||
divider.odd_0.counter\[2\] 54.365
|
||||
divider.odd_0.initial_begin\[0\] 31.54
|
||||
divider.odd_0.initial_begin\[1\] 34.305
|
||||
divider.odd_0.initial_begin\[2\] 27.1
|
||||
divider.odd_0.old_N\[0\] 12.12
|
||||
divider.odd_0.old_N\[1\] 5.505
|
||||
divider.odd_0.old_N\[2\] 8.12
|
||||
divider.odd_0.out_counter 20.38
|
||||
divider.odd_0.out_counter2 12.38
|
||||
divider.odd_0.rst_pulse 13.455
|
||||
divider.out 17.555
|
||||
divider.syncNp\[0\] 9.74
|
||||
divider.syncNp\[1\] 6.245
|
||||
divider.syncNp\[2\] 13.14
|
||||
divider2.even_0.N\[0\] 30.06
|
||||
divider2.even_0.N\[1\] 74.42
|
||||
divider2.even_0.N\[2\] 29.52
|
||||
divider2.even_0.counter\[0\] 44.595
|
||||
divider2.even_0.counter\[1\] 23.425
|
||||
divider2.even_0.counter\[2\] 19.035
|
||||
divider2.even_0.out_counter 37.805
|
||||
divider2.odd_0.counter2\[0\] 51.04
|
||||
divider2.odd_0.counter2\[1\] 34.33
|
||||
divider2.odd_0.counter2\[2\] 22.58
|
||||
divider2.odd_0.counter\[0\] 44.09
|
||||
divider2.odd_0.counter\[1\] 64.815
|
||||
divider2.odd_0.counter\[2\] 56.065
|
||||
divider2.odd_0.initial_begin\[0\] 29.085
|
||||
divider2.odd_0.initial_begin\[1\] 22.64
|
||||
divider2.odd_0.initial_begin\[2\] 14.595
|
||||
divider2.odd_0.old_N\[0\] 5.015
|
||||
divider2.odd_0.old_N\[1\] 15.15
|
||||
divider2.odd_0.old_N\[2\] 5.84
|
||||
divider2.odd_0.out_counter 45.525
|
||||
divider2.odd_0.out_counter2 24.295
|
||||
divider2.odd_0.rst_pulse 8.625
|
||||
divider2.out 21.46
|
||||
divider2.syncNp\[0\] 7.3
|
||||
divider2.syncNp\[1\] 2.85
|
||||
divider2.syncNp\[2\] 10.9
|
||||
ext_clk_syncd 5.335
|
||||
ext_clk_syncd_pre 9.435
|
||||
net1 41.16
|
||||
net10 6.595
|
||||
net11 20.7
|
||||
net13 176.145
|
||||
net14 136.48
|
||||
net15 121.335
|
||||
net16 59.205
|
||||
net17 135.105
|
||||
net18 186.43
|
||||
net19 205.98
|
||||
net2 26.44
|
||||
net20 80.23
|
||||
net21 90.58
|
||||
net22 118.28
|
||||
net23 93.17
|
||||
net24 124.99
|
||||
net25 114.165
|
||||
net26 140.915
|
||||
net27 136.565
|
||||
net28 185.145
|
||||
net29 129.47
|
||||
net3 2.52
|
||||
net30 8.32
|
||||
net31 2.835
|
||||
net32 2.715
|
||||
net33 2.835
|
||||
net34 3.54
|
||||
net35 2.835
|
||||
net36 1.84
|
||||
net37 4.095
|
||||
net38 6.815
|
||||
net39 5.435
|
||||
net4 48.26
|
||||
net5 35.915
|
||||
net6 39.32
|
||||
net7 109.635
|
||||
net8 83.1
|
||||
net9 55.195
|
||||
pll_clk_sel 60.08
|
||||
reset_delay\[0\] 5.365
|
||||
reset_delay\[1\] 3.405
|
||||
reset_delay\[2\] 4.25
|
||||
use_pll_first 41.655
|
||||
use_pll_second 31.495
|
||||
user_clk_buffered 7.98
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,31 @@
|
|||
Max transition on internal signals: 1.25ns
|
||||
Hold WNS (F2F): -0.02 (ff-*)
|
||||
Setup WNS (F2F): -1.17 (ss-max)
|
||||
|
||||
lvs clean: Y
|
||||
drc clean: Y
|
||||
cvc clean: Y
|
||||
Antenna Violations: 0
|
||||
Antenna Violations (400-500): 0
|
||||
Antenna Violations (500-800): 0
|
||||
Antenna Violations (800-1000): 0
|
||||
|
||||
non-physical cells: 1093 - 730 = 363
|
||||
decap cell count: 206
|
||||
% decap: 206 / 1093 * 100 = 18.8%
|
||||
max ir drop: 1.69e-09 V
|
||||
|
||||
Verilog "assign" in the netlist: N
|
||||
Does the netlist show cells from different libraries: N
|
||||
Does the macro have mixed power domains powered cells: N
|
||||
Any internal macros with floating input ports: N
|
||||
Output ports not connected to any logic inside the macro: N
|
||||
Input ports not connected to any logic inside the macro: N
|
||||
Tri-state cells are connected directly to output ports: N
|
||||
Analog Signals are not digitally buffered: N
|
||||
Output ports are properly buffred (>=buf_4): Y
|
||||
buffer cells count: 59
|
||||
logic cells that are not buffers count: 363 - 59 = 304
|
||||
buf_1 & buf_2 cells count: 57
|
||||
0.5mm or longer wire count: 0
|
||||
|
||||
|
|
@ -0,0 +1,371 @@
|
|||
ringosc.dstage\[4\].id.d2 1.38
|
||||
ringosc.dstage\[8\].id.d2 1.38
|
||||
_003_ 1.575
|
||||
_010_ 1.575
|
||||
ringosc.dstage\[7\].id.d0 1.72
|
||||
_030_ 1.79
|
||||
_109_ 1.84
|
||||
ringosc.c\[0\] 1.84
|
||||
_087_ 2.035
|
||||
_138_ 2.035
|
||||
_076_ 2.13
|
||||
_189_ 2.13
|
||||
_203_ 2.155
|
||||
_007_ 2.28
|
||||
ringosc.iss.ctrl0 2.3
|
||||
_042_ 2.375
|
||||
_084_ 2.375
|
||||
_159_ 2.375
|
||||
ringosc.dstage\[1\].id.d2 2.375
|
||||
ringosc.iss.d2 2.375
|
||||
ringosc.c\[1\] 2.47
|
||||
_139_ 2.52
|
||||
_145_ 2.52
|
||||
_005_ 2.595
|
||||
_016_ 2.595
|
||||
_185_ 2.715
|
||||
_156_ 2.745
|
||||
_029_ 2.76
|
||||
_146_ 2.76
|
||||
_154_ 2.81
|
||||
ringosc.dstage\[8\].id.d0 2.835
|
||||
_006_ 2.935
|
||||
_012_ 2.935
|
||||
ringosc.dstage\[11\].id.d2 2.955
|
||||
_150_ 3.055
|
||||
_204_ 3.055
|
||||
_136_ 3.075
|
||||
_188_ 3.075
|
||||
_022_ 3.15
|
||||
_137_ 3.175
|
||||
_144_ 3.2
|
||||
_020_ 3.275
|
||||
_182_ 3.395
|
||||
_135_ 3.44
|
||||
_019_ 3.66
|
||||
_149_ 4.02
|
||||
ringosc.dstage\[6\].id.d2 4.14
|
||||
_036_ 4.335
|
||||
ringosc.dstage\[1\].id.trim\[0\] 4.435
|
||||
_049_ 4.51
|
||||
_039_ 4.755
|
||||
ringosc.iss.d0 4.755
|
||||
_026_ 4.895
|
||||
_093_ 4.94
|
||||
clockp[0] 4.945
|
||||
ringosc.dstage\[5\].id.d1 4.97
|
||||
_002_ 4.99
|
||||
_152_ 5.015
|
||||
ringosc.dstage\[7\].id.d2 5.095
|
||||
_070_ 5.19
|
||||
_134_ 5.19
|
||||
_032_ 5.215
|
||||
ringosc.dstage\[4\].id.trim\[0\] 5.23
|
||||
ringosc.dstage\[10\].id.d0 5.235
|
||||
ringosc.dstage\[8\].id.trim\[1\] 5.235
|
||||
_078_ 5.26
|
||||
_120_ 5.31
|
||||
_013_ 5.315
|
||||
_004_ 5.34
|
||||
_046_ 5.36
|
||||
_018_ 5.385
|
||||
ringosc.dstage\[8\].id.d1 5.43
|
||||
_126_ 5.47
|
||||
_041_ 5.475
|
||||
ringosc.clockp\[1\] 5.53
|
||||
ringosc.dstage\[10\].id.out 5.555
|
||||
ringosc.dstage\[1\].id.d1 5.57
|
||||
ringosc.dstage\[9\].id.d0 5.595
|
||||
_183_ 5.86
|
||||
_069_ 5.895
|
||||
ringosc.dstage\[0\].id.out 5.935
|
||||
ringosc.dstage\[3\].id.d0 5.96
|
||||
ringosc.dstage\[2\].id.trim\[1\] 6.015
|
||||
ringosc.dstage\[7\].id.trim\[1\] 6.015
|
||||
_133_ 6.055
|
||||
_190_ 6.115
|
||||
_031_ 6.135
|
||||
_071_ 6.155
|
||||
_143_ 6.165
|
||||
_092_ 6.235
|
||||
_113_ 6.235
|
||||
_207_ 6.235
|
||||
_011_ 6.25
|
||||
ringosc.dstage\[9\].id.d1 6.295
|
||||
_067_ 6.3
|
||||
ringosc.dstage\[2\].id.d0 6.32
|
||||
_140_ 6.335
|
||||
ringosc.dstage\[10\].id.trim\[1\] 6.355
|
||||
_028_ 6.38
|
||||
_008_ 6.4
|
||||
ringosc.dstage\[5\].id.d0 6.475
|
||||
_201_ 6.48
|
||||
_155_ 6.55
|
||||
_187_ 6.6
|
||||
_009_ 6.67
|
||||
_062_ 6.695
|
||||
ringosc.iss.one 6.695
|
||||
_082_ 6.935
|
||||
_085_ 6.955
|
||||
_132_ 6.955
|
||||
pll_control.oscbuf\[0\] 6.975
|
||||
_015_ 7.015
|
||||
_086_ 7.075
|
||||
ringosc.dstage\[11\].id.ts 7.15
|
||||
ringosc.dstage\[0\].id.d1 7.17
|
||||
ringosc.dstage\[5\].id.d2 7.23
|
||||
_127_ 7.275
|
||||
_202_ 7.315
|
||||
ringosc.dstage\[2\].id.d2 7.36
|
||||
ringosc.dstage\[3\].id.out 7.395
|
||||
_000_ 7.425
|
||||
ringosc.dstage\[1\].id.d0 7.435
|
||||
_118_ 7.485
|
||||
_080_ 7.52
|
||||
_164_ 7.71
|
||||
_091_ 7.715
|
||||
_035_ 7.76
|
||||
ringosc.dstage\[3\].id.d1 7.775
|
||||
_014_ 7.8
|
||||
_054_ 7.815
|
||||
_068_ 7.83
|
||||
ringosc.dstage\[11\].id.d0 7.855
|
||||
ringosc.dstage\[6\].id.trim\[0\] 7.855
|
||||
_077_ 7.86
|
||||
ringosc.dstage\[3\].id.trim\[0\] 8.195
|
||||
ringosc.dstage\[5\].id.trim\[0\] 8.195
|
||||
_111_ 8.275
|
||||
ringosc.dstage\[4\].id.d0 8.395
|
||||
_153_ 8.4
|
||||
_200_ 8.525
|
||||
_047_ 8.58
|
||||
ringosc.dstage\[7\].id.d1 8.595
|
||||
_040_ 8.615
|
||||
ringosc.dstage\[10\].id.in 8.71
|
||||
_090_ 8.895
|
||||
ringosc.dstage\[0\].id.d2 8.895
|
||||
_088_ 8.955
|
||||
_179_ 8.98
|
||||
_199_ 8.995
|
||||
_197_ 9.27
|
||||
_043_ 9.295
|
||||
_037_ 9.415
|
||||
_116_ 9.44
|
||||
ringosc.dstage\[0\].id.d0 9.535
|
||||
ringosc.dstage\[10\].id.d2 9.54
|
||||
_184_ 9.62
|
||||
ringosc.dstage\[11\].id.d1 9.695
|
||||
osc 9.88
|
||||
_021_ 10.03
|
||||
ringosc.dstage\[9\].id.d2 10.12
|
||||
ringosc.dstage\[10\].id.d1 10.15
|
||||
_064_ 10.175
|
||||
_024_ 10.195
|
||||
ext_trim[1] 10.205
|
||||
ringosc.dstage\[2\].id.out 10.365
|
||||
_103_ 10.47
|
||||
pll_control.count1\[1\] 10.47
|
||||
_048_ 10.535
|
||||
_063_ 10.535
|
||||
ringosc.dstage\[11\].id.trim\[1\] 10.595
|
||||
ringosc.dstage\[4\].id.d1 10.595
|
||||
_074_ 10.62
|
||||
_081_ 10.77
|
||||
ringosc.dstage\[7\].id.trim\[0\] 11.2
|
||||
_038_ 11.235
|
||||
_079_ 11.255
|
||||
_119_ 11.415
|
||||
_033_ 11.675
|
||||
pll_control.prep\[1\] 11.97
|
||||
_089_ 12.04
|
||||
_141_ 12.16
|
||||
_148_ 12.235
|
||||
_027_ 12.3
|
||||
_034_ 12.375
|
||||
ringosc.dstage\[8\].id.out 12.46
|
||||
ringosc.dstage\[9\].id.trim\[1\] 12.475
|
||||
_198_ 12.49
|
||||
_147_ 12.615
|
||||
ringosc.dstage\[6\].id.d1 12.79
|
||||
ringosc.iss.d1 13.09
|
||||
ringosc.dstage\[4\].id.out 13.175
|
||||
_169_ 13.21
|
||||
_058_ 13.23
|
||||
pll_control.prep\[2\] 13.275
|
||||
_075_ 13.34
|
||||
_195_ 13.58
|
||||
ringosc.dstage\[5\].id.ts 13.61
|
||||
_163_ 13.835
|
||||
pll_control.oscbuf\[2\] 14.0
|
||||
ringosc.dstage\[10\].id.ts 14.065
|
||||
ringosc.dstage\[6\].id.out 14.435
|
||||
pll_control.prep\[0\] 14.475
|
||||
ringosc.dstage\[9\].id.ts 14.855
|
||||
_121_ 14.98
|
||||
_051_ 15.0
|
||||
ringosc.dstage\[1\].id.out 15.085
|
||||
ringosc.dstage\[1\].id.ts 15.975
|
||||
_073_ 16.05
|
||||
ringosc.dstage\[8\].id.ts 16.15
|
||||
ringosc.dstage\[2\].id.trim\[0\] 16.19
|
||||
_001_ 16.345
|
||||
_205_ 16.695
|
||||
_165_ 16.85
|
||||
_102_ 16.855
|
||||
pll_control.count1\[4\] 16.905
|
||||
_023_ 16.94
|
||||
_065_ 17.045
|
||||
ext_trim[4] 17.2
|
||||
_066_ 17.615
|
||||
_083_ 17.615
|
||||
_191_ 17.635
|
||||
div[2] 17.77
|
||||
ringosc.dstage\[2\].id.d1 17.87
|
||||
_061_ 17.96
|
||||
pll_control.count1\[3\] 18.075
|
||||
_161_ 18.12
|
||||
_060_ 18.295
|
||||
ringosc.dstage\[0\].id.trim\[0\] 18.575
|
||||
ringosc.dstage\[3\].id.d2 18.595
|
||||
_017_ 19.03
|
||||
_131_ 19.16
|
||||
_094_ 19.22
|
||||
_104_ 19.35
|
||||
ringosc.dstage\[0\].id.ts 19.495
|
||||
ringosc.dstage\[3\].id.trim\[1\] 19.675
|
||||
_194_ 19.74
|
||||
_059_ 19.955
|
||||
pll_control.tval\[1\] 20.005
|
||||
ringosc.dstage\[5\].id.out 20.135
|
||||
_112_ 20.415
|
||||
_105_ 20.575
|
||||
ringosc.dstage\[6\].id.d0 20.96
|
||||
_129_ 21.235
|
||||
ringosc.dstage\[4\].id.ts 21.895
|
||||
ringosc.iss.trim\[1\] 21.9
|
||||
_072_ 22.545
|
||||
_115_ 22.765
|
||||
pll_control.count0\[0\] 22.92
|
||||
ext_trim[5] 22.99
|
||||
ext_trim[6] 23.025
|
||||
_025_ 23.56
|
||||
ext_trim[13] 24.175
|
||||
_055_ 24.58
|
||||
_192_ 25.075
|
||||
_196_ 25.075
|
||||
ringosc.dstage\[11\].id.out 25.11
|
||||
ext_trim[11] 25.14
|
||||
_162_ 25.17
|
||||
_056_ 25.19
|
||||
_175_ 25.455
|
||||
_098_ 26.095
|
||||
pll_control.tint\[1\] 26.1
|
||||
resetb 26.23
|
||||
_125_ 26.635
|
||||
pll_control.count1\[0\] 26.655
|
||||
pll_control.count1\[2\] 26.73
|
||||
_101_ 26.955
|
||||
_057_ 27.38
|
||||
_142_ 27.95
|
||||
_107_ 28.53
|
||||
_151_ 28.55
|
||||
pll_control.oscbuf\[1\] 28.765
|
||||
_206_ 28.935
|
||||
ringosc.dstage\[7\].id.ts 29.085
|
||||
_170_ 29.215
|
||||
_168_ 29.335
|
||||
ext_trim[14] 29.56
|
||||
ringosc.dstage\[6\].id.trim\[1\] 29.835
|
||||
ringosc.dstage\[8\].id.trim\[0\] 30.395
|
||||
_130_ 31.19
|
||||
enable 31.225
|
||||
ext_trim[12] 31.27
|
||||
div[4] 31.375
|
||||
ringosc.dstage\[6\].id.ts 31.395
|
||||
ext_trim[7] 31.88
|
||||
ext_trim[23] 32.005
|
||||
_174_ 32.32
|
||||
ext_trim[0] 32.46
|
||||
_106_ 32.685
|
||||
_128_ 34.255
|
||||
ext_trim[16] 34.355
|
||||
ringosc.dstage\[0\].id.trim\[1\] 34.435
|
||||
ringosc.dstage\[9\].id.trim\[0\] 35.2
|
||||
ext_trim[3] 35.385
|
||||
_193_ 35.92
|
||||
_171_ 36.215
|
||||
_208_ 36.525
|
||||
ringosc.dstage\[1\].id.trim\[1\] 37.75
|
||||
pll_control.count0\[1\] 37.935
|
||||
ext_trim[15] 38.66
|
||||
_097_ 39.165
|
||||
ext_trim[10] 39.28
|
||||
pll_control.tint\[3\] 40.64
|
||||
clockp[1] 40.645
|
||||
ringosc.dstage\[3\].id.ts 40.72
|
||||
pll_control.count0\[4\] 40.905
|
||||
div[3] 40.945
|
||||
_172_ 42.145
|
||||
ext_trim[24] 43.205
|
||||
pll_control.tval\[0\] 43.355
|
||||
ringosc.dstage\[7\].id.out 43.455
|
||||
_117_ 44.33
|
||||
ext_trim[22] 44.53
|
||||
_114_ 44.94
|
||||
div[1] 45.165
|
||||
_211_ 45.23
|
||||
_177_ 47.705
|
||||
ext_trim[17] 48.3
|
||||
ringosc.dstage\[4\].id.trim\[1\] 48.675
|
||||
_210_ 48.845
|
||||
_209_ 52.46
|
||||
pll_control.tint\[2\] 53.22
|
||||
_166_ 53.24
|
||||
_096_ 54.24
|
||||
_110_ 54.26
|
||||
_108_ 55.58
|
||||
_100_ 55.75
|
||||
ringosc.dstage\[10\].id.trim\[0\] 56.035
|
||||
pll_control.tint\[0\] 57.225
|
||||
_181_ 57.475
|
||||
pll_control.count0\[2\] 57.585
|
||||
div[0] 58.155
|
||||
_178_ 59.01
|
||||
ringosc.dstage\[5\].id.trim\[1\] 59.565
|
||||
ext_trim[25] 59.69
|
||||
ext_trim[19] 60.54
|
||||
_173_ 60.86
|
||||
_176_ 61.095
|
||||
_095_ 61.1
|
||||
_124_ 61.3
|
||||
_052_ 61.485
|
||||
ext_trim[20] 61.665
|
||||
pll_control.count0\[3\] 63.74
|
||||
_180_ 63.96
|
||||
_053_ 64.045
|
||||
ext_trim[21] 64.325
|
||||
_160_ 65.675
|
||||
ringosc.dstage\[11\].id.trim\[0\] 66.1
|
||||
ext_trim[18] 67.19
|
||||
_050_ 70.23
|
||||
ringosc.dstage\[2\].id.ts 70.935
|
||||
ringosc.iss.trim\[0\] 72.24
|
||||
_167_ 75.37
|
||||
_123_ 75.84
|
||||
pll_control.tint\[4\] 78.825
|
||||
ringosc.iss.reset 79.64
|
||||
ext_trim[9] 81.41
|
||||
ext_trim[2] 83.52
|
||||
_157_ 85.145
|
||||
_212_ 88.185
|
||||
_045_ 88.87
|
||||
_099_ 90.52
|
||||
_122_ 91.085
|
||||
ext_trim[8] 92.66
|
||||
_158_ 94.085
|
||||
_213_ 110.955
|
||||
ringosc.dstage\[0\].id.in 116.96
|
||||
_044_ 118.205
|
||||
dco 122.445
|
||||
_186_ 159.71
|
||||
pll_control.clock 191.96
|
||||
|
|
@ -0,0 +1,371 @@
|
|||
clockp[0] 4.945
|
||||
clockp[1] 40.645
|
||||
dco 122.445
|
||||
div[0] 58.155
|
||||
div[1] 45.165
|
||||
div[2] 17.77
|
||||
div[3] 40.945
|
||||
div[4] 31.375
|
||||
enable 31.225
|
||||
ext_trim[0] 32.46
|
||||
ext_trim[10] 39.28
|
||||
ext_trim[11] 25.14
|
||||
ext_trim[12] 31.27
|
||||
ext_trim[13] 24.175
|
||||
ext_trim[14] 29.56
|
||||
ext_trim[15] 38.66
|
||||
ext_trim[16] 34.355
|
||||
ext_trim[17] 48.3
|
||||
ext_trim[18] 67.19
|
||||
ext_trim[19] 60.54
|
||||
ext_trim[1] 10.205
|
||||
ext_trim[20] 61.665
|
||||
ext_trim[21] 64.325
|
||||
ext_trim[22] 44.53
|
||||
ext_trim[23] 32.005
|
||||
ext_trim[24] 43.205
|
||||
ext_trim[25] 59.69
|
||||
ext_trim[2] 83.52
|
||||
ext_trim[3] 35.385
|
||||
ext_trim[4] 17.2
|
||||
ext_trim[5] 22.99
|
||||
ext_trim[6] 23.025
|
||||
ext_trim[7] 31.88
|
||||
ext_trim[8] 92.66
|
||||
ext_trim[9] 81.41
|
||||
osc 9.88
|
||||
resetb 26.23
|
||||
_000_ 7.425
|
||||
_001_ 16.345
|
||||
_002_ 4.99
|
||||
_003_ 1.575
|
||||
_004_ 5.34
|
||||
_005_ 2.595
|
||||
_006_ 2.935
|
||||
_007_ 2.28
|
||||
_008_ 6.4
|
||||
_009_ 6.67
|
||||
_010_ 1.575
|
||||
_011_ 6.25
|
||||
_012_ 2.935
|
||||
_013_ 5.315
|
||||
_014_ 7.8
|
||||
_015_ 7.015
|
||||
_016_ 2.595
|
||||
_017_ 19.03
|
||||
_018_ 5.385
|
||||
_019_ 3.66
|
||||
_020_ 3.275
|
||||
_021_ 10.03
|
||||
_022_ 3.15
|
||||
_023_ 16.94
|
||||
_024_ 10.195
|
||||
_025_ 23.56
|
||||
_026_ 4.895
|
||||
_027_ 12.3
|
||||
_028_ 6.38
|
||||
_029_ 2.76
|
||||
_030_ 1.79
|
||||
_031_ 6.135
|
||||
_032_ 5.215
|
||||
_033_ 11.675
|
||||
_034_ 12.375
|
||||
_035_ 7.76
|
||||
_036_ 4.335
|
||||
_037_ 9.415
|
||||
_038_ 11.235
|
||||
_039_ 4.755
|
||||
_040_ 8.615
|
||||
_041_ 5.475
|
||||
_042_ 2.375
|
||||
_043_ 9.295
|
||||
_044_ 118.205
|
||||
_045_ 88.87
|
||||
_046_ 5.36
|
||||
_047_ 8.58
|
||||
_048_ 10.535
|
||||
_049_ 4.51
|
||||
_050_ 70.23
|
||||
_051_ 15.0
|
||||
_052_ 61.485
|
||||
_053_ 64.045
|
||||
_054_ 7.815
|
||||
_055_ 24.58
|
||||
_056_ 25.19
|
||||
_057_ 27.38
|
||||
_058_ 13.23
|
||||
_059_ 19.955
|
||||
_060_ 18.295
|
||||
_061_ 17.96
|
||||
_062_ 6.695
|
||||
_063_ 10.535
|
||||
_064_ 10.175
|
||||
_065_ 17.045
|
||||
_066_ 17.615
|
||||
_067_ 6.3
|
||||
_068_ 7.83
|
||||
_069_ 5.895
|
||||
_070_ 5.19
|
||||
_071_ 6.155
|
||||
_072_ 22.545
|
||||
_073_ 16.05
|
||||
_074_ 10.62
|
||||
_075_ 13.34
|
||||
_076_ 2.13
|
||||
_077_ 7.86
|
||||
_078_ 5.26
|
||||
_079_ 11.255
|
||||
_080_ 7.52
|
||||
_081_ 10.77
|
||||
_082_ 6.935
|
||||
_083_ 17.615
|
||||
_084_ 2.375
|
||||
_085_ 6.955
|
||||
_086_ 7.075
|
||||
_087_ 2.035
|
||||
_088_ 8.955
|
||||
_089_ 12.04
|
||||
_090_ 8.895
|
||||
_091_ 7.715
|
||||
_092_ 6.235
|
||||
_093_ 4.94
|
||||
_094_ 19.22
|
||||
_095_ 61.1
|
||||
_096_ 54.24
|
||||
_097_ 39.165
|
||||
_098_ 26.095
|
||||
_099_ 90.52
|
||||
_100_ 55.75
|
||||
_101_ 26.955
|
||||
_102_ 16.855
|
||||
_103_ 10.47
|
||||
_104_ 19.35
|
||||
_105_ 20.575
|
||||
_106_ 32.685
|
||||
_107_ 28.53
|
||||
_108_ 55.58
|
||||
_109_ 1.84
|
||||
_110_ 54.26
|
||||
_111_ 8.275
|
||||
_112_ 20.415
|
||||
_113_ 6.235
|
||||
_114_ 44.94
|
||||
_115_ 22.765
|
||||
_116_ 9.44
|
||||
_117_ 44.33
|
||||
_118_ 7.485
|
||||
_119_ 11.415
|
||||
_120_ 5.31
|
||||
_121_ 14.98
|
||||
_122_ 91.085
|
||||
_123_ 75.84
|
||||
_124_ 61.3
|
||||
_125_ 26.635
|
||||
_126_ 5.47
|
||||
_127_ 7.275
|
||||
_128_ 34.255
|
||||
_129_ 21.235
|
||||
_130_ 31.19
|
||||
_131_ 19.16
|
||||
_132_ 6.955
|
||||
_133_ 6.055
|
||||
_134_ 5.19
|
||||
_135_ 3.44
|
||||
_136_ 3.075
|
||||
_137_ 3.175
|
||||
_138_ 2.035
|
||||
_139_ 2.52
|
||||
_140_ 6.335
|
||||
_141_ 12.16
|
||||
_142_ 27.95
|
||||
_143_ 6.165
|
||||
_144_ 3.2
|
||||
_145_ 2.52
|
||||
_146_ 2.76
|
||||
_147_ 12.615
|
||||
_148_ 12.235
|
||||
_149_ 4.02
|
||||
_150_ 3.055
|
||||
_151_ 28.55
|
||||
_152_ 5.015
|
||||
_153_ 8.4
|
||||
_154_ 2.81
|
||||
_155_ 6.55
|
||||
_156_ 2.745
|
||||
_157_ 85.145
|
||||
_158_ 94.085
|
||||
_159_ 2.375
|
||||
_160_ 65.675
|
||||
_161_ 18.12
|
||||
_162_ 25.17
|
||||
_163_ 13.835
|
||||
_164_ 7.71
|
||||
_165_ 16.85
|
||||
_166_ 53.24
|
||||
_167_ 75.37
|
||||
_168_ 29.335
|
||||
_169_ 13.21
|
||||
_170_ 29.215
|
||||
_171_ 36.215
|
||||
_172_ 42.145
|
||||
_173_ 60.86
|
||||
_174_ 32.32
|
||||
_175_ 25.455
|
||||
_176_ 61.095
|
||||
_177_ 47.705
|
||||
_178_ 59.01
|
||||
_179_ 8.98
|
||||
_180_ 63.96
|
||||
_181_ 57.475
|
||||
_182_ 3.395
|
||||
_183_ 5.86
|
||||
_184_ 9.62
|
||||
_185_ 2.715
|
||||
_186_ 159.71
|
||||
_187_ 6.6
|
||||
_188_ 3.075
|
||||
_189_ 2.13
|
||||
_190_ 6.115
|
||||
_191_ 17.635
|
||||
_192_ 25.075
|
||||
_193_ 35.92
|
||||
_194_ 19.74
|
||||
_195_ 13.58
|
||||
_196_ 25.075
|
||||
_197_ 9.27
|
||||
_198_ 12.49
|
||||
_199_ 8.995
|
||||
_200_ 8.525
|
||||
_201_ 6.48
|
||||
_202_ 7.315
|
||||
_203_ 2.155
|
||||
_204_ 3.055
|
||||
_205_ 16.695
|
||||
_206_ 28.935
|
||||
_207_ 6.235
|
||||
_208_ 36.525
|
||||
_209_ 52.46
|
||||
_210_ 48.845
|
||||
_211_ 45.23
|
||||
_212_ 88.185
|
||||
_213_ 110.955
|
||||
pll_control.clock 191.96
|
||||
pll_control.count0\[0\] 22.92
|
||||
pll_control.count0\[1\] 37.935
|
||||
pll_control.count0\[2\] 57.585
|
||||
pll_control.count0\[3\] 63.74
|
||||
pll_control.count0\[4\] 40.905
|
||||
pll_control.count1\[0\] 26.655
|
||||
pll_control.count1\[1\] 10.47
|
||||
pll_control.count1\[2\] 26.73
|
||||
pll_control.count1\[3\] 18.075
|
||||
pll_control.count1\[4\] 16.905
|
||||
pll_control.oscbuf\[0\] 6.975
|
||||
pll_control.oscbuf\[1\] 28.765
|
||||
pll_control.oscbuf\[2\] 14.0
|
||||
pll_control.prep\[0\] 14.475
|
||||
pll_control.prep\[1\] 11.97
|
||||
pll_control.prep\[2\] 13.275
|
||||
pll_control.tint\[0\] 57.225
|
||||
pll_control.tint\[1\] 26.1
|
||||
pll_control.tint\[2\] 53.22
|
||||
pll_control.tint\[3\] 40.64
|
||||
pll_control.tint\[4\] 78.825
|
||||
pll_control.tval\[0\] 43.355
|
||||
pll_control.tval\[1\] 20.005
|
||||
ringosc.c\[0\] 1.84
|
||||
ringosc.c\[1\] 2.47
|
||||
ringosc.clockp\[1\] 5.53
|
||||
ringosc.dstage\[0\].id.d0 9.535
|
||||
ringosc.dstage\[0\].id.d1 7.17
|
||||
ringosc.dstage\[0\].id.d2 8.895
|
||||
ringosc.dstage\[0\].id.in 116.96
|
||||
ringosc.dstage\[0\].id.out 5.935
|
||||
ringosc.dstage\[0\].id.trim\[0\] 18.575
|
||||
ringosc.dstage\[0\].id.trim\[1\] 34.435
|
||||
ringosc.dstage\[0\].id.ts 19.495
|
||||
ringosc.dstage\[10\].id.d0 5.235
|
||||
ringosc.dstage\[10\].id.d1 10.15
|
||||
ringosc.dstage\[10\].id.d2 9.54
|
||||
ringosc.dstage\[10\].id.in 8.71
|
||||
ringosc.dstage\[10\].id.out 5.555
|
||||
ringosc.dstage\[10\].id.trim\[0\] 56.035
|
||||
ringosc.dstage\[10\].id.trim\[1\] 6.355
|
||||
ringosc.dstage\[10\].id.ts 14.065
|
||||
ringosc.dstage\[11\].id.d0 7.855
|
||||
ringosc.dstage\[11\].id.d1 9.695
|
||||
ringosc.dstage\[11\].id.d2 2.955
|
||||
ringosc.dstage\[11\].id.out 25.11
|
||||
ringosc.dstage\[11\].id.trim\[0\] 66.1
|
||||
ringosc.dstage\[11\].id.trim\[1\] 10.595
|
||||
ringosc.dstage\[11\].id.ts 7.15
|
||||
ringosc.dstage\[1\].id.d0 7.435
|
||||
ringosc.dstage\[1\].id.d1 5.57
|
||||
ringosc.dstage\[1\].id.d2 2.375
|
||||
ringosc.dstage\[1\].id.out 15.085
|
||||
ringosc.dstage\[1\].id.trim\[0\] 4.435
|
||||
ringosc.dstage\[1\].id.trim\[1\] 37.75
|
||||
ringosc.dstage\[1\].id.ts 15.975
|
||||
ringosc.dstage\[2\].id.d0 6.32
|
||||
ringosc.dstage\[2\].id.d1 17.87
|
||||
ringosc.dstage\[2\].id.d2 7.36
|
||||
ringosc.dstage\[2\].id.out 10.365
|
||||
ringosc.dstage\[2\].id.trim\[0\] 16.19
|
||||
ringosc.dstage\[2\].id.trim\[1\] 6.015
|
||||
ringosc.dstage\[2\].id.ts 70.935
|
||||
ringosc.dstage\[3\].id.d0 5.96
|
||||
ringosc.dstage\[3\].id.d1 7.775
|
||||
ringosc.dstage\[3\].id.d2 18.595
|
||||
ringosc.dstage\[3\].id.out 7.395
|
||||
ringosc.dstage\[3\].id.trim\[0\] 8.195
|
||||
ringosc.dstage\[3\].id.trim\[1\] 19.675
|
||||
ringosc.dstage\[3\].id.ts 40.72
|
||||
ringosc.dstage\[4\].id.d0 8.395
|
||||
ringosc.dstage\[4\].id.d1 10.595
|
||||
ringosc.dstage\[4\].id.d2 1.38
|
||||
ringosc.dstage\[4\].id.out 13.175
|
||||
ringosc.dstage\[4\].id.trim\[0\] 5.23
|
||||
ringosc.dstage\[4\].id.trim\[1\] 48.675
|
||||
ringosc.dstage\[4\].id.ts 21.895
|
||||
ringosc.dstage\[5\].id.d0 6.475
|
||||
ringosc.dstage\[5\].id.d1 4.97
|
||||
ringosc.dstage\[5\].id.d2 7.23
|
||||
ringosc.dstage\[5\].id.out 20.135
|
||||
ringosc.dstage\[5\].id.trim\[0\] 8.195
|
||||
ringosc.dstage\[5\].id.trim\[1\] 59.565
|
||||
ringosc.dstage\[5\].id.ts 13.61
|
||||
ringosc.dstage\[6\].id.d0 20.96
|
||||
ringosc.dstage\[6\].id.d1 12.79
|
||||
ringosc.dstage\[6\].id.d2 4.14
|
||||
ringosc.dstage\[6\].id.out 14.435
|
||||
ringosc.dstage\[6\].id.trim\[0\] 7.855
|
||||
ringosc.dstage\[6\].id.trim\[1\] 29.835
|
||||
ringosc.dstage\[6\].id.ts 31.395
|
||||
ringosc.dstage\[7\].id.d0 1.72
|
||||
ringosc.dstage\[7\].id.d1 8.595
|
||||
ringosc.dstage\[7\].id.d2 5.095
|
||||
ringosc.dstage\[7\].id.out 43.455
|
||||
ringosc.dstage\[7\].id.trim\[0\] 11.2
|
||||
ringosc.dstage\[7\].id.trim\[1\] 6.015
|
||||
ringosc.dstage\[7\].id.ts 29.085
|
||||
ringosc.dstage\[8\].id.d0 2.835
|
||||
ringosc.dstage\[8\].id.d1 5.43
|
||||
ringosc.dstage\[8\].id.d2 1.38
|
||||
ringosc.dstage\[8\].id.out 12.46
|
||||
ringosc.dstage\[8\].id.trim\[0\] 30.395
|
||||
ringosc.dstage\[8\].id.trim\[1\] 5.235
|
||||
ringosc.dstage\[8\].id.ts 16.15
|
||||
ringosc.dstage\[9\].id.d0 5.595
|
||||
ringosc.dstage\[9\].id.d1 6.295
|
||||
ringosc.dstage\[9\].id.d2 10.12
|
||||
ringosc.dstage\[9\].id.trim\[0\] 35.2
|
||||
ringosc.dstage\[9\].id.trim\[1\] 12.475
|
||||
ringosc.dstage\[9\].id.ts 14.855
|
||||
ringosc.iss.ctrl0 2.3
|
||||
ringosc.iss.d0 4.755
|
||||
ringosc.iss.d1 13.09
|
||||
ringosc.iss.d2 2.375
|
||||
ringosc.iss.one 6.695
|
||||
ringosc.iss.reset 79.64
|
||||
ringosc.iss.trim\[0\] 72.24
|
||||
ringosc.iss.trim\[1\] 21.9
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,31 @@
|
|||
Max transition on internal signals: 1.25ns
|
||||
Hold WNS (F2F): 0.00
|
||||
Setup WNS (F2F): 0.00
|
||||
|
||||
lvs clean: Y
|
||||
drc clean: Y
|
||||
cvc clean: N/A - cvc doesn't work with designs that have macros(gpio_logic_high)
|
||||
Antenna Violations: 0
|
||||
Antenna Violations (400-500): 0
|
||||
Antenna Violations (500-800): 0
|
||||
Antenna Violations (800-1000): 0
|
||||
|
||||
non-physical cells: 264 - 131 = 133
|
||||
decap cell count: 42
|
||||
% decap: 42 / 264 * 100 = 15.9%
|
||||
max ir drop: 1.01e-09 V
|
||||
|
||||
Verilog "assign" in the netlist: N
|
||||
Does the netlist show cells from different libraries: N
|
||||
Does the macro have mixed power domains powered cells: Y - gpio_logic_high uses another power domain
|
||||
Any internal macros with floating input ports: N
|
||||
Output ports not connected to any logic inside the macro: N
|
||||
Input ports not connected to any logic inside the macro: N
|
||||
Tri-state cells are connected directly to output ports: N
|
||||
Analog Signals are not digitally buffered: N
|
||||
Output ports are properly buffred (>=buf_4): Y
|
||||
buffer cells count: 56
|
||||
logic cells that are not buffers count: 133 - 56 = 77
|
||||
buf_1 & buf_2 cells count: 29
|
||||
0.5mm or longer wire count: 0
|
||||
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
_016_ 3.3
|
||||
shift_register\[0\] 3.515
|
||||
_041_ 3.755
|
||||
shift_register\[6\] 5.26
|
||||
net16 5.53
|
||||
_025_ 5.935
|
||||
net48 6.18
|
||||
_015_ 6.235
|
||||
shift_register\[11\] 6.355
|
||||
shift_register\[9\] 7.155
|
||||
_026_ 8.035
|
||||
shift_register\[4\] 8.075
|
||||
_008_ 8.105
|
||||
shift_register\[5\] 8.495
|
||||
shift_register\[7\] 8.655
|
||||
shift_register\[10\] 8.995
|
||||
_044_ 9.44
|
||||
shift_register\[8\] 9.875
|
||||
_000_ 9.95
|
||||
net17 9.995
|
||||
net3 10.35
|
||||
net49 10.455
|
||||
_006_ 10.54
|
||||
_004_ 10.97
|
||||
_024_ 11.57
|
||||
_001_ 12.16
|
||||
net35 13.335
|
||||
net21 13.66
|
||||
net55 13.84
|
||||
net56 14.18
|
||||
net53 14.215
|
||||
_023_ 14.46
|
||||
net9 14.555
|
||||
net57 15.095
|
||||
net43 16.095
|
||||
_003_ 16.5
|
||||
net6 16.595
|
||||
net44 17.14
|
||||
one_buffered 18.28
|
||||
net18 18.94
|
||||
_014_ 19.71
|
||||
net14 19.895
|
||||
net39 21.395
|
||||
_042_ 21.85
|
||||
net4 21.86
|
||||
_007_ 22.095
|
||||
shift_register\[3\] 23.98
|
||||
net8 24.535
|
||||
zero_buffered 25.06
|
||||
net58 25.435
|
||||
clknet_0_serial_load 25.495
|
||||
_021_ 25.8
|
||||
net47 26.4
|
||||
_012_ 26.45
|
||||
_022_ 26.58
|
||||
_011_ 26.68
|
||||
net42 27.1
|
||||
_045_ 27.535
|
||||
_013_ 27.635
|
||||
net38 27.635
|
||||
net19 27.915
|
||||
mgmt_ena 28.005
|
||||
net34 28.28
|
||||
_010_ 28.58
|
||||
_018_ 29.26
|
||||
net52 29.325
|
||||
net46 29.955
|
||||
_002_ 30.04
|
||||
pad_gpio_out 30.05
|
||||
net1 30.09
|
||||
net20 30.3
|
||||
shift_register\[1\] 30.52
|
||||
pad_gpio_inenb 30.57
|
||||
net37 32.295
|
||||
gpio_outenb 32.38
|
||||
_017_ 32.975
|
||||
net7 33.075
|
||||
net51 33.515
|
||||
gpio_logic1 34.03
|
||||
net10 34.2
|
||||
shift_register\[12\] 34.47
|
||||
_009_ 35.78
|
||||
shift_register\[2\] 36.455
|
||||
net54 37.745
|
||||
clknet_0_serial_clock 37.995
|
||||
net13 39.74
|
||||
net15 40.68
|
||||
net41 41.16
|
||||
net36 41.375
|
||||
mgmt_gpio_oeb 41.465
|
||||
net32 42.215
|
||||
_043_ 42.6
|
||||
net50 43.035
|
||||
_005_ 43.18
|
||||
pad_gpio_ana_pol 43.85
|
||||
_019_ 44.315
|
||||
pad_gpio_dm[0] 44.725
|
||||
mgmt_gpio_in 45.285
|
||||
pad_gpio_dm[1] 45.305
|
||||
one 46.445
|
||||
net12 46.83
|
||||
net11 47.435
|
||||
_020_ 47.67
|
||||
pad_gpio_slow_sel 47.685
|
||||
net33 48.195
|
||||
pad_gpio_ana_en 49.69
|
||||
pad_gpio_ib_mode_sel 49.83
|
||||
net45 49.875
|
||||
serial_data_out 50.385
|
||||
pad_gpio_holdover 50.51
|
||||
pad_gpio_ana_sel 51.65
|
||||
pad_gpio_dm[2] 51.79
|
||||
net40 53.12
|
||||
zero 53.685
|
||||
net2 56.14
|
||||
pad_gpio_vtrip_sel 57.505
|
||||
net5 58.32
|
||||
resetn_out 58.65
|
||||
gpio_defaults[7] 58.875
|
||||
user_gpio_in 58.985
|
||||
gpio_defaults[10] 61.945
|
||||
gpio_defaults[6] 64.07
|
||||
pad_gpio_outenb 64.43
|
||||
resetn 65.985
|
||||
mgmt_gpio_out 70.07
|
||||
serial_data_in 70.53
|
||||
gpio_defaults[11] 71.83
|
||||
net22 73.29
|
||||
gpio_defaults[2] 74.865
|
||||
net24 75.05
|
||||
serial_clock_out 76.83
|
||||
pad_gpio_in 77.23
|
||||
serial_load 77.25
|
||||
gpio_defaults[5] 78.435
|
||||
serial_clock_out_buffered 79.475
|
||||
serial_clock 80.345
|
||||
gpio_defaults[3] 80.82
|
||||
net29 86.8
|
||||
net26 86.91
|
||||
net31 88.24
|
||||
net23 88.7
|
||||
net25 88.96
|
||||
gpio_defaults[12] 91.77
|
||||
gpio_defaults[8] 92.175
|
||||
net27 93.655
|
||||
user_gpio_out 94.245
|
||||
clknet_1_0__leaf_serial_load 95.575
|
||||
clknet_1_0__leaf_serial_clock 95.61
|
||||
serial_load_out 106.23
|
||||
gpio_defaults[0] 113.895
|
||||
user_gpio_oeb 116.19
|
||||
serial_load_out_buffered 119.705
|
||||
gpio_defaults[4] 120.325
|
||||
gpio_defaults[9] 125.28
|
||||
net28 128.6
|
||||
net30 129.82
|
||||
gpio_defaults[1] 137.94
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
gpio_defaults[0] 113.895
|
||||
gpio_defaults[10] 61.945
|
||||
gpio_defaults[11] 71.83
|
||||
gpio_defaults[12] 91.77
|
||||
gpio_defaults[1] 137.94
|
||||
gpio_defaults[2] 74.865
|
||||
gpio_defaults[3] 80.82
|
||||
gpio_defaults[4] 120.325
|
||||
gpio_defaults[5] 78.435
|
||||
gpio_defaults[6] 64.07
|
||||
gpio_defaults[7] 58.875
|
||||
gpio_defaults[8] 92.175
|
||||
gpio_defaults[9] 125.28
|
||||
mgmt_gpio_in 45.285
|
||||
mgmt_gpio_oeb 41.465
|
||||
mgmt_gpio_out 70.07
|
||||
one 46.445
|
||||
pad_gpio_ana_en 49.69
|
||||
pad_gpio_ana_pol 43.85
|
||||
pad_gpio_ana_sel 51.65
|
||||
pad_gpio_dm[0] 44.725
|
||||
pad_gpio_dm[1] 45.305
|
||||
pad_gpio_dm[2] 51.79
|
||||
pad_gpio_holdover 50.51
|
||||
pad_gpio_ib_mode_sel 49.83
|
||||
pad_gpio_in 77.23
|
||||
pad_gpio_inenb 30.57
|
||||
pad_gpio_out 30.05
|
||||
pad_gpio_outenb 64.43
|
||||
pad_gpio_slow_sel 47.685
|
||||
pad_gpio_vtrip_sel 57.505
|
||||
resetn 65.985
|
||||
resetn_out 58.65
|
||||
serial_clock 80.345
|
||||
serial_clock_out 76.83
|
||||
serial_data_in 70.53
|
||||
serial_data_out 50.385
|
||||
serial_load 77.25
|
||||
serial_load_out 106.23
|
||||
user_gpio_in 58.985
|
||||
user_gpio_oeb 116.19
|
||||
user_gpio_out 94.245
|
||||
zero 53.685
|
||||
_000_ 9.95
|
||||
_001_ 12.16
|
||||
_002_ 30.04
|
||||
_003_ 16.5
|
||||
_004_ 10.97
|
||||
_005_ 43.18
|
||||
_006_ 10.54
|
||||
_007_ 22.095
|
||||
_008_ 8.105
|
||||
_009_ 35.78
|
||||
_010_ 28.58
|
||||
_011_ 26.68
|
||||
_012_ 26.45
|
||||
_013_ 27.635
|
||||
_014_ 19.71
|
||||
_015_ 6.235
|
||||
_016_ 3.3
|
||||
_017_ 32.975
|
||||
_018_ 29.26
|
||||
_019_ 44.315
|
||||
_020_ 47.67
|
||||
_021_ 25.8
|
||||
_022_ 26.58
|
||||
_023_ 14.46
|
||||
_024_ 11.57
|
||||
_025_ 5.935
|
||||
_026_ 8.035
|
||||
_041_ 3.755
|
||||
_042_ 21.85
|
||||
_043_ 42.6
|
||||
_044_ 9.44
|
||||
_045_ 27.535
|
||||
clknet_0_serial_clock 37.995
|
||||
clknet_0_serial_load 25.495
|
||||
clknet_1_0__leaf_serial_clock 95.61
|
||||
clknet_1_0__leaf_serial_load 95.575
|
||||
gpio_logic1 34.03
|
||||
gpio_outenb 32.38
|
||||
mgmt_ena 28.005
|
||||
net1 30.09
|
||||
net10 34.2
|
||||
net11 47.435
|
||||
net12 46.83
|
||||
net13 39.74
|
||||
net14 19.895
|
||||
net15 40.68
|
||||
net16 5.53
|
||||
net17 9.995
|
||||
net18 18.94
|
||||
net19 27.915
|
||||
net2 56.14
|
||||
net20 30.3
|
||||
net21 13.66
|
||||
net22 73.29
|
||||
net23 88.7
|
||||
net24 75.05
|
||||
net25 88.96
|
||||
net26 86.91
|
||||
net27 93.655
|
||||
net28 128.6
|
||||
net29 86.8
|
||||
net3 10.35
|
||||
net30 129.82
|
||||
net31 88.24
|
||||
net32 42.215
|
||||
net33 48.195
|
||||
net34 28.28
|
||||
net35 13.335
|
||||
net36 41.375
|
||||
net37 32.295
|
||||
net38 27.635
|
||||
net39 21.395
|
||||
net4 21.86
|
||||
net40 53.12
|
||||
net41 41.16
|
||||
net42 27.1
|
||||
net43 16.095
|
||||
net44 17.14
|
||||
net45 49.875
|
||||
net46 29.955
|
||||
net47 26.4
|
||||
net48 6.18
|
||||
net49 10.455
|
||||
net5 58.32
|
||||
net50 43.035
|
||||
net51 33.515
|
||||
net52 29.325
|
||||
net53 14.215
|
||||
net54 37.745
|
||||
net55 13.84
|
||||
net56 14.18
|
||||
net57 15.095
|
||||
net58 25.435
|
||||
net6 16.595
|
||||
net7 33.075
|
||||
net8 24.535
|
||||
net9 14.555
|
||||
one_buffered 18.28
|
||||
serial_clock_out_buffered 79.475
|
||||
serial_load_out_buffered 119.705
|
||||
shift_register\[0\] 3.515
|
||||
shift_register\[10\] 8.995
|
||||
shift_register\[11\] 6.355
|
||||
shift_register\[12\] 34.47
|
||||
shift_register\[1\] 30.52
|
||||
shift_register\[2\] 36.455
|
||||
shift_register\[3\] 23.98
|
||||
shift_register\[4\] 8.075
|
||||
shift_register\[5\] 8.495
|
||||
shift_register\[6\] 5.26
|
||||
shift_register\[7\] 8.655
|
||||
shift_register\[8\] 9.875
|
||||
shift_register\[9\] 7.155
|
||||
zero_buffered 25.06
|
||||
Loading…
Reference in New Issue