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Merge pull request #358 from efabless/cocotb 

Cocotb - updates
This commit is contained in:
Jeff DiCorpo 2022-10-30 18:31:11 -07:00 committed by GitHub
parent 2c934064e9 0da9e78e57
commit e5683a8967
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GPG Key ID: 4AEE18F83AFDEB23
28 changed files with 254 additions and 129 deletions
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3
verilog/dv/cocotb/.gitignore vendored
View File

@ -8,4 +8,5 @@ __pycache__
*.yml
*.hex*
*.elf
AN.DB
AN.DB
includes.v

2
verilog/dv/cocotb/README.md
View File

@ -16,6 +16,8 @@ Prerequisites
- iverilog or vcs
- export CARAVEL_ROOT= \<caravel repo root\>
- export MCW_ROOT= \<caravel_mgmt_soc_litex repo root\>
- export PDK_ROOT= \<PDK repo root\>
- export PDK= \<PDK variant sky130A,sky130B,.... \>
run a test
=============================

2
verilog/dv/cocotb/caravel_tests.py
View File

@ -45,7 +45,7 @@ from tests.uart.uart import *
from tests.spi_master.spi_master import *
from tests.logicAnalyzer.la import *
from tests.debug.debug import *
from tests.cpu.cpu_reset import *
# archive tests
@cocotb.test()

6
verilog/dv/cocotb/caravel_top.sv
View File

@ -1,5 +1,9 @@
`timescale 1 ns / 1 ps
`ifdef VCS
`ifndef GL
`include "includes.v" // in case of RTL coverage is needed and it doesn't work correctly without include files by this way
`endif // ~ GL
`ifndef ENABLE_SDF
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
@ -14,7 +18,7 @@
`include "cvc-pdk/sky130_fd_sc_hd.v"
`include "cvc-pdk/primitives_hvl.v"
`include "cvc-pdk/sky130_fd_sc_hvl.v"
`endif // ENABLE_SDF
`endif // ~ ENABLE_SDF
`endif // VCS
module caravel_top ;

4
verilog/dv/cocotb/sdf_includes.v
View File

@ -1,3 +1,7 @@
initial begin
`ifndef CARAVAN
$sdf_annotate({`MAIN_PATH,"/../../../signoff/caravel/primetime-signoff/sdf/",`CORNER,"/caravel.", `SDF_POSTFIX,".sdf"}, uut,,{`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/caravel_sdf.log"},"MINIMUM");
`else
$sdf_annotate({`MAIN_PATH,"/../../../signoff/caravan/primetime-signoff/sdf/",`CORNER,"/caravan.", `SDF_POSTFIX,".sdf"}, uut,,{`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/caravan_sdf.log"},"MINIMUM");
`endif
end

126
verilog/dv/cocotb/tests.json
View File

@ -12,26 +12,26 @@
"SW":true,
"RTL":["r_caravan_rtl"],
"GL":["r_caravan_gl"],
"GL_SDF":[],
"GL_SDF":["r_caravan_sdf"],
"description":"configure all gpios as mgmt input using automatic approach firmware and check them for caravan"}
,"hk_disable" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"check Housekeeping SPI disable register is working"}
,"uart_rx" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"test uart reception"}
,"hk_regs_rst_spi" :{"level":0,
"SW":false,
"RTL":["r_rtl","r_caravan_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"check reset value of house keeping registers by reading them trough the spi housekeeping"}
,"gpio_all_i_user" :{"level":0,
@ -53,7 +53,7 @@
"SW":true,
"RTL":["r_caravan_rtl"],
"GL":["r_caravan_gl"],
"GL_SDF":[],
"GL_SDF":["r_caravan_sdf"],
"description":"configure all gpios as mgmt input pull up using automatic approach firmware and check them for caravan"}
,"gpio_all_i_pu_user" :{"level":0,
@ -73,7 +73,7 @@
"SW":true,
"RTL":["r_caravan_rtl"],
"GL":["r_caravan_gl"],
"GL_SDF":[],
"GL_SDF":["r_caravan_sdf"],
"description":"configure all gpios as mgmt input pull down using automatic approach firmware and check them for caravan"}
,"gpio_all_i_pd_user" :{"level":0,
@ -101,7 +101,7 @@
"SW":true,
"RTL":["r_caravan_rtl"],
"GL":["r_caravan_gl"],
"GL_SDF":[],
"GL_SDF":["r_caravan_sdf"],
"description":"configure all gpios as mgmt output using automatic approach firmware and check them for caravan"}
,"gpio_all_o_user" :{"level":0,
@ -114,7 +114,7 @@
"SW":false,
"RTL":["r_rtl","r_caravan_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"bit bash test for housekeeping registers"}
,"IRQ_timer" :{"level":2,
"SW":true,
@ -139,9 +139,9 @@
,"mgmt_gpio_out" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"tests blinking of mgmt gpio bit as an output"}
,"bitbang_spi_i" :{"level":0,
@ -154,75 +154,75 @@
"SW":false,
"RTL":["r_rtl","r_caravan_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"write then read(the written value) from random housekeeping registers through the SPI housekeeping"}
,"IRQ_external" :{"level":2,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"test external interrupt by mprj 7"}
,"IRQ_uart" :{"level":2,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"test timer0 interrupt"}
,"mgmt_gpio_in" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"tests blinking of mgmt gpio bit as an output"}
,"timer0_oneshot" :{"level":0,
"SW":true,
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"check timer0 oneshot mode"}
,"uart_loopback" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"test uart in loopback mode input and output is shorted"}
,"timer0_periodic" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"check timer0 periodic mode"}
,"uart_tx" :{"level":0,
"SW":true,
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"test uart transmit"}
,"debug" :{"level":0,
"SW":true,
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"use caravel in debug mode and check reading and writing from dff2 RAM"}
,"spi_master_rd" :{"level":0,
"SW":true,
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"using SPI master for reading from external memory"}
,"user_pass_thru_rd" :{"level":0,
"SW":true,
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"use the housekeeping spi in user pass thru mode to read from external mem"}
,"clock_redirect" :{"level":0,
@ -236,13 +236,13 @@
"SW":true,
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"send random number of blinks through mgmt_gpio and expect to recieve the same number back "}
,"la" :{"level":0,
"SW":true,
"RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"check logic analyzer input and output enable"}
@ -269,50 +269,50 @@
,"mem_dff" :{"level":2,
"SW":true,
"RTL":["r_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"Memory stress for all space of dff"}
,"bitbang_cpu_all_01" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"shift all the register with 01"}
,"mem_dff2" :{"level":2,
"SW":true,
"RTL":["r_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"Memory stress for all space of dff2"}
,"bitbang_cpu_all_10" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"shift all the register with 10"}
,"bitbang_cpu_all_1100" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"shift all the register with 1100"}
,"bitbang_cpu_all_0011" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"shift all the register with 0011"}
,"cpu_stress" :{"level":2,
"SW":true,
"RTL":["r_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"RTL":["r_rtl","r_caravan_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","r_caravan_sdf","weekly","tape_out"],
"description":"stress the cpu with heavy processing"}
,"bitbang_no_cpu_all_o" :{"level":0,
"SW":false,
@ -344,6 +344,12 @@
"GL":[],
"GL_SDF":[],
"description":"try housekeeping spi Write and Read in n-byte mode "}
,"cpu_reset" :{"level":3,
"SW":true,
"RTL":["r_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"test cpu reset register inside the housekeeping "}
}
}

4
verilog/dv/cocotb/tests/bitbang/bitbang_tests.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def bitbang_no_cpu_all_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=10206)
caravelEnv,clock = await test_configure(dut,timeout_cycles=9373)
cpu = RiskV(dut)
cpu.cpu_force_reset()
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
@ -129,7 +129,7 @@ async def bitbang_no_cpu_all_o(dut):
@cocotb.test()
@repot_test
async def bitbang_no_cpu_all_i(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=8005)
caravelEnv,clock = await test_configure(dut,timeout_cycles=7351)
cpu = RiskV(dut)
cpu.cpu_force_reset()
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)

43
verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py
View File

@ -15,7 +15,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def bitbang_cpu_all_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=2075459)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1842534)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -57,15 +57,20 @@ async def bitbang_cpu_all_o(dut):
@cocotb.test()
@repot_test
async def bitbang_cpu_all_10(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=1581680)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1452270)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xFF)
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
if Macros['CARAVAN']:
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]")
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
if Macros['CARAVAN']:
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
type = True # type of shifting 01 or 10
for gpio in gpios_l:
if not Macros['GL']:
@ -104,15 +109,20 @@ def shift(gpio,shift_type):
@cocotb.test()
@repot_test
async def bitbang_cpu_all_01(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=2863378)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1452269)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xFF)
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
if Macros['CARAVAN']:
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]")
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
if Macros['CARAVAN']:
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
type = False # type of shifting 01 or 10
for gpio in gpios_l:
if not Macros['GL']:
@ -131,15 +141,20 @@ async def bitbang_cpu_all_01(dut):
@cocotb.test()
@repot_test
async def bitbang_cpu_all_0011(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=5963970)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1402860)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xFF)
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
if Macros['CARAVAN']:
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]")
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
if Macros['CARAVAN']:
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
type = 2 # type of shifting 01 or 10
for gpio in gpios_l:
if not Macros['GL']:
@ -158,15 +173,19 @@ async def bitbang_cpu_all_0011(dut):
@cocotb.test()
@repot_test
async def bitbang_cpu_all_1100(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=5962067)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1402426)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xFF)
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
if Macros['CARAVAN']:
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]")
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
if Macros['CARAVAN']:
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
type = 0 # type of shifting 01 or 10
for gpio in gpios_l:
if not Macros['GL']:
@ -214,7 +233,7 @@ def shift_2(gpio,shift_type):
@cocotb.test()
@repot_test
async def bitbang_cpu_all_i(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=1691295)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1641382)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -264,7 +283,7 @@ async def bitbang_cpu_all_i(dut):
@cocotb.test()
@repot_test
async def bitbang_spi_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=2639757)
caravelEnv,clock = await test_configure(dut,timeout_cycles=294252)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -329,7 +348,7 @@ async def bitbang_spi_o(dut):
@cocotb.test()
@repot_test
async def bitbang_spi_i(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=11156703)
caravelEnv,clock = await test_configure(dut,timeout_cycles=55417)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

18
verilog/dv/cocotb/tests/cpu/cpu_reset.c Normal file
View File

@ -0,0 +1,18 @@
#include <defs.h>
#include <stub.c>
// Empty C code
void main()
{
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_1 = 0x1;
reg_debug_1 = 0x2;
reg_debug_1 = 0x3;
reg_debug_1 = 0x4;
reg_debug_1 = 0x5;
while(reg_debug_2 == 0x0);
reg_hkspi_reset = 1;
}

67
verilog/dv/cocotb/tests/cpu/cpu_reset.py Normal file
View File

@ -0,0 +1,67 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from tests.housekeeping.housekeeping_spi.spi_access_functions import *
reg = Regs()
@cocotb.test()
@repot_test
async def cpu_reset(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=34823)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start cpu_reset test")
# wait for CPU to write 5 at debug_reg1
while True:
if cpu.read_debug_reg1() == 5:
cocotb.log.info("[TEST] debug reg 1 = 5" )
break
await ClockCycles(caravelEnv.clk,1)
# put the cpu under reset using spi
cocotb.log.info("[TEST] asserting cpu reset register using SPI")
await write_reg_spi(caravelEnv,0xb,1)
await ClockCycles(caravelEnv.clk,1000)
if cpu.read_debug_reg1() == 0:
cocotb.log.info("[TEST] asserting cpu reset register using SPI successfully rest the cpu")
else:
cocotb.log.error("[TEST] asserting cpu reset register using SPI successfully doesn't rest the cpu")
cocotb.log.info("[TEST] deasserting cpu reset register using SPI")
await write_reg_spi(caravelEnv,0xb,0)
watchdog = 12000
while True:
if cpu.read_debug_reg1() == 5:
cocotb.log.info("[TEST] deasserting cpu reset register using SPI wakes the cpu up" )
break
watchdog -=1
if watchdog <0:
cocotb.log.error("[TEST] deasserting cpu reset register using SPI doesn't wake the cpu up" )
break
await ClockCycles(caravelEnv.clk,1)
cocotb.log.info("[TEST] asserting cpu reset register using firmware")
cpu.write_debug_reg2_backdoor(0xAA)
await ClockCycles(caravelEnv.clk,10000)
watchdog = 8000
while True:
if cpu.read_debug_reg1() == 0:
cocotb.log.info("[TEST] asserting cpu reset register using firmware successfully rest the cpu" )
break
watchdog -=1
if watchdog <0:
cocotb.log.error("[TEST] asserting cpu reset register using firmware successfully doesn't rest the cpu" )
break
await ClockCycles(caravelEnv.clk,100)

2
verilog/dv/cocotb/tests/cpu/cpu_stress.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def cpu_stress(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=1492541)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1377432)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/debug/debug.py
View File

@ -19,7 +19,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def debug(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=33840)
caravelEnv,clock = await test_configure(dut,timeout_cycles=31011)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

6
verilog/dv/cocotb/tests/gpio/gpio.py
View File

@ -15,7 +15,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def gpio_all_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=586652)
caravelEnv,clock = await test_configure(dut,timeout_cycles=538624)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -156,7 +156,7 @@ async def gpio_all_i(dut):
@cocotb.test()
@repot_test
async def gpio_all_i_pu(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
caravelEnv,clock = await test_configure(dut,timeout_cycles=54138,num_error=2000)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -258,7 +258,7 @@ async def gpio_all_i_pu(dut):
@cocotb.test()
@repot_test
async def gpio_all_i_pd(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
caravelEnv,clock = await test_configure(dut,timeout_cycles=54138,num_error=2000)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

8
verilog/dv/cocotb/tests/gpio/gpio_user.py
View File

@ -73,7 +73,7 @@ async def gpio_all_o_user(dut):
@cocotb.test()
@repot_test
async def gpio_all_i_user(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=56694)
caravelEnv,clock = await test_configure(dut,timeout_cycles=498255)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -155,7 +155,7 @@ async def gpio_all_i_user(dut):
@cocotb.test()
@repot_test
async def gpio_all_i_pu_user(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
caravelEnv,clock = await test_configure(dut,timeout_cycles=56875,num_error=2000)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -257,7 +257,7 @@ async def gpio_all_i_pu_user(dut):
@cocotb.test()
@repot_test
async def gpio_all_i_pd_user(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
caravelEnv,clock = await test_configure(dut,timeout_cycles=54138,num_error=2000)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -361,7 +361,7 @@ async def gpio_all_i_pd_user(dut):
@cocotb.test()
@repot_test
async def gpio_all_bidir_user(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=290455)
caravelEnv,clock = await test_configure(dut,timeout_cycles=266662)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/housekeeping/general/pll.py
View File

@ -16,7 +16,7 @@ user_clock = 0
@cocotb.test()
@repot_test
async def pll(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
caravelEnv,clock = await test_configure(dut,timeout_cycles=47279)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

4
verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py
View File

@ -19,7 +19,7 @@ core_clock = 0
@cocotb.test()
@repot_test
async def clock_redirect(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=13060)
caravelEnv,clock = await test_configure(dut,timeout_cycles=13052)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -92,7 +92,7 @@ async def calculate_clk_period(clk,name):
@cocotb.test()
@repot_test
async def hk_disable(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=12409)
caravelEnv,clock = await test_configure(dut,timeout_cycles=11393)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

10
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py
View File

@ -18,7 +18,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def hk_regs_wr_wb(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=700,num_error=INFINITY)
caravelEnv,clock = await test_configure(dut,timeout_cycles=611,num_error=INFINITY)
cpu = RiskV(dut)
cpu.cpu_force_reset()
with open('wb_models/housekeepingWB/HK_regs.json') as f:
@ -70,7 +70,7 @@ async def hk_regs_wr_wb(dut):
@cocotb.test()
@repot_test
async def hk_regs_wr_wb_cpu(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=198243,num_error=INFINITY)
caravelEnv,clock = await test_configure(dut,timeout_cycles=182983,num_error=INFINITY)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -98,7 +98,7 @@ async def hk_regs_wr_wb_cpu(dut):
@cocotb.test()
@repot_test
async def hk_regs_wr_spi(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1851,num_error=INFINITY)
with open('wb_models/housekeepingWB/HK_regs.json') as f:
regs = json.load(f)
@ -113,7 +113,7 @@ async def hk_regs_wr_spi(dut):
if address in [111,36,10]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled and 10 0xa cpu irq is self resetting
continue
# address = int(key,16)
if address in [0x69,0x6A,0x6B,0x6C,0x6D]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
if address in [0x69,0x6A,0x6B,0x6C,0x6D,0x13]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value and xfer
continue
data_in = random.getrandbits(bits_num)
cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
@ -157,7 +157,7 @@ async def hk_regs_wr_spi(dut):
@cocotb.test()
@repot_test
async def hk_regs_rst_spi(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
caravelEnv,clock = await test_configure(dut,timeout_cycles=2879,num_error=INFINITY)
with open('wb_models/housekeepingWB/HK_regs.json') as f:
regs = json.load(f)

2
verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py
View File

@ -17,7 +17,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def user_pass_thru_rd(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=14833)
caravelEnv,clock = await test_configure(dut,timeout_cycles=13771)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/irq/IRQ_external.py
View File

@ -17,7 +17,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def IRQ_external(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=164360)
caravelEnv,clock = await test_configure(dut,timeout_cycles=155225)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/irq/IRQ_timer.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def IRQ_timer(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=166519)
caravelEnv,clock = await test_configure(dut,timeout_cycles=152854)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/irq/IRQ_uart.py
View File

@ -21,7 +21,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def IRQ_uart(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=18613481)
caravelEnv,clock = await test_configure(dut,timeout_cycles=318039)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/logicAnalyzer/la.py
View File

@ -15,7 +15,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def la(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
caravelEnv,clock = await test_configure(dut,timeout_cycles=67415)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

4
verilog/dv/cocotb/tests/mem/mem_stress.py
View File

@ -13,7 +13,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def mem_dff2(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=1426536)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1309819)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -38,7 +38,7 @@ async def mem_dff2(dut):
@cocotb.test()
@repot_test
async def mem_dff(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=2378120)
caravelEnv,clock = await test_configure(dut,timeout_cycles=2096205)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

8
verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py
View File

@ -15,7 +15,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def mgmt_gpio_out(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=99562)
caravelEnv,clock = await test_configure(dut,timeout_cycles=91385)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -63,7 +63,7 @@ async def mgmt_gpio_out(dut):
@cocotb.test()
@repot_test
async def mgmt_gpio_in(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=326525)
caravelEnv,clock = await test_configure(dut,timeout_cycles=277033)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -112,11 +112,11 @@ async def mgmt_gpio_in(dut):
@cocotb.test()
@repot_test
async def mgmt_gpio_bidir(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=243058)
caravelEnv,clock = await test_configure(dut,timeout_cycles=194697)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start mgmt_gpio_in test")
cocotb.log.info(f"[TEST] Start mgmt_gpio_bidir test")
phases_fails = 3
phases_passes = 0
pass_list = (0x1B,0x2B,0xFF)

4
verilog/dv/cocotb/tests/spi_master/spi_master.py
View File

@ -22,7 +22,7 @@ async def spi_master_rd(dut):
the method of testing used can't work if 2 addresses Consecutive have the same address
"""
caravelEnv,clock = await test_configure(dut,timeout_cycles=214842)
caravelEnv,clock = await test_configure(dut,timeout_cycles=213888)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -62,7 +62,7 @@ async def spi_master_temp(dut):
the method of testing used can't work if 2 addresses Consecutive have the same address
"""
caravelEnv,clock = await test_configure(dut,timeout_cycles=214842)
caravelEnv,clock = await test_configure(dut,timeout_cycles=39554)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

4
verilog/dv/cocotb/tests/timer/timer.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def timer0_oneshot(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=1114136)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1023545)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -56,7 +56,7 @@ async def timer0_oneshot(dut):
@cocotb.test()
@repot_test
async def timer0_periodic(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58257)
caravelEnv,clock = await test_configure(dut,timeout_cycles=52016)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

6
verilog/dv/cocotb/tests/uart/uart.py
View File

@ -19,7 +19,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def uart_tx(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=375862)
caravelEnv,clock = await test_configure(dut,timeout_cycles=346140)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -62,7 +62,7 @@ async def start_of_tx(caravelEnv):
@cocotb.test()
@repot_test
async def uart_rx(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=104029)
caravelEnv,clock = await test_configure(dut,timeout_cycles=98315)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -132,7 +132,7 @@ async def uart_check_char_recieved(caravelEnv,cpu):
@cocotb.test()
@repot_test
async def uart_loopback(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=216756)
caravelEnv,clock = await test_configure(dut,timeout_cycles=199021)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

38
verilog/dv/cocotb/verify_cocotb.py
View File

@ -34,7 +34,7 @@ def search_str(file_path, word):
else:
return "failed"
def change_dff(str,new_str,file_path):
def change_str(str,new_str,file_path):
# Read in the file
with open(file_path, 'r') as file :
filedata = file.read()
@ -140,7 +140,9 @@ class RunTest:
VERILOG_PATH = os.getenv('VERILOG_PATH')
dirs = f'+incdir+\\\"{PDK_ROOT}/{PDK}\\\" '
if self.sim_type == "RTL":
dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/rtl_caravel_vcs.list\\\" '
shutil.copyfile(f'{VERILOG_PATH}/includes/rtl_caravel_vcs.v', f"{self.cocotb_path}/includes.v")
change_str(str="\"caravel_mgmt_soc_litex/verilog",new_str=f"\"{VERILOG_PATH}",file_path=f"{self.cocotb_path}/includes.v")
change_str(str="\"caravel/verilog",new_str=f"\"{CARAVEL_PATH}",file_path=f"{self.cocotb_path}/includes.v")
else:
dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/gl_caravel_vcs.list\\\" '
macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS '
@ -169,15 +171,17 @@ class RunTest:
os.environ["TESTCASE"] = f"{self.test_name}"
os.environ["MODULE"] = f"caravel_tests"
os.environ["SIM"] = self.sim_type
# user_project = f"-v {CARAVEL_PATH}/rtl/__user_project_wrapper.v"
# if caravan:
# print ("Use caravan")
# macros = f'+define+CARAVAN {macros} '
# user_project = f"-v {CARAVEL_PATH}/rtl/__user_analog_project_wrapper.v"
os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.full_test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
user_project = f"-v {CARAVEL_PATH}/rtl/__user_project_wrapper.v"
if caravan:
print ("Use caravan")
macros = f'+define+CARAVAN {macros} '
user_project = f"-v {CARAVEL_PATH}/rtl/__user_analog_project_wrapper.v"
os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {user_project} {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.full_test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
os.system(f"vcs +lint=TFIPC-L {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
self.passed = search_str(self.test_log.name,"Test passed with (0)criticals (0)errors")
Path(f'{self.sim_path}/{self.passed}').touch()
os.system("rm -rf AN.DB ucli.key core") # delete vcs additional files
#delete wave when passed
if self.passed == "passed" and zip_waves:
os.chdir(f'{self.cocotb_path}/{self.sim_path}')
@ -248,14 +252,14 @@ class RunTest:
new_LINKER_SCRIPT = f"{self.cocotb_path}/{self.sim_path}/sections.lds"
shutil.copyfile(LINKER_SCRIPT, new_LINKER_SCRIPT)
if ram == "dff2":
change_dff(str="> dff ",new_str="> dff2 ",file_path=new_LINKER_SCRIPT)
change_dff(str="> dff\n",new_str="> dff2\n",file_path=new_LINKER_SCRIPT)
change_dff(str="ORIGIN(dff)",new_str="ORIGIN(dff2)",file_path=new_LINKER_SCRIPT)
change_dff(str="LENGTH(dff)",new_str="LENGTH(dff2)",file_path=new_LINKER_SCRIPT)
change_str(str="> dff ",new_str="> dff2 ",file_path=new_LINKER_SCRIPT)
change_str(str="> dff\n",new_str="> dff2\n",file_path=new_LINKER_SCRIPT)
change_str(str="ORIGIN(dff)",new_str="ORIGIN(dff2)",file_path=new_LINKER_SCRIPT)
change_str(str="LENGTH(dff)",new_str="LENGTH(dff2)",file_path=new_LINKER_SCRIPT)
elif ram == "dff":
change_dff(str="> dff2 ",new_str="> dff ",file_path=new_LINKER_SCRIPT)
change_dff(str="ORIGIN(dff2)",new_str="ORIGIN(dff)",file_path=new_LINKER_SCRIPT)
change_dff(str="LENGTH(dff2)",new_str="LENGTH(dff)",file_path=new_LINKER_SCRIPT)
change_str(str="> dff2 ",new_str="> dff ",file_path=new_LINKER_SCRIPT)
change_str(str="ORIGIN(dff2)",new_str="ORIGIN(dff)",file_path=new_LINKER_SCRIPT)
change_str(str="LENGTH(dff2)",new_str="LENGTH(dff)",file_path=new_LINKER_SCRIPT)
else:
print(f"ERROR: wrong trype of ram {ram} need to be used for now the oldy rams that can be used for flashing and data are dff and dff2")
sys.exit()
@ -390,8 +394,8 @@ class RunRegression:
def generate_cov(self):
os.chdir(f"{self.cocotb_path}/sim/{os.getenv('RUNTAG')}")
os.system(f"urg -dir RTL*/*.vdb -format both -show tests -report coverageRTL/")
os.system(f"urg -dir GL*/*.vdb -format both -show tests -report coverageGL/")
os.system(f"urg -dir SDF*/*.vdb -format both -show tests -report coverageSDF/")
# os.system(f"urg -dir GL*/*.vdb -format both -show tests -report coverageGL/")
# os.system(f"urg -dir SDF*/*.vdb -format both -show tests -report coverageSDF/")
os.chdir(self.cocotb_path)
def update_reg_log(self):