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increase timeout for uart_rx and add uart_ev_pending_write

This commit is contained in:
M0stafaRady 2022-10-05 15:02:07 -07:00
parent 8e21a2f722
commit 78613c95cc
2 changed files with 4 additions and 4 deletions
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4
verilog/dv/cocotb/tests/uart/uart.py
View File

@ -61,7 +61,7 @@ async def start_of_tx(caravelEnv):
@cocotb.test()
@repot_test
async def uart_rx(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=95844)
caravelEnv,clock = await test_configure(dut,timeout_cycles=11195844)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -120,7 +120,7 @@ async def uart_check_char_recieved(caravelEnv,cpu):
cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}")
return
if reg1 == 0x1E:
cocotb.log.error(f"[TEST] Failed Pass cpu has recieved the wrong character {chr(int(reg_uart_data,2))}")
cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character {chr(int(reg_uart_data,2))}")
return
await ClockCycles(caravelEnv.clk,1)

4
verilog/dv/cocotb/tests/uart/uart_rx.c
View File

@ -17,14 +17,14 @@
#include <defs.h>
#include <stub.c>
#include <uart.h>
// --------------------------------------------------------
void wait_for_char(char *c){
while (uart_rxempty_read() == 1);
if (reg_uart_data == *c){
reg_debug_1 = 0x1B; // recieved the correct character
uart_ev_pending_write(UART_EV_RX);
}else{
reg_debug_1 = 0x1E; // timeout didn't recieve the character
}