From 78613c95cc44ce7bf3b886b6cba1015e90496a55 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 5 Oct 2022 15:02:07 -0700 Subject: [PATCH] increase timeout for uart_rx and add uart_ev_pending_write --- verilog/dv/cocotb/tests/uart/uart.py | 4 ++-- verilog/dv/cocotb/tests/uart/uart_rx.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 0cf6eb79..3d499938 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -61,7 +61,7 @@ async def start_of_tx(caravelEnv): @cocotb.test() @repot_test async def uart_rx(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=95844) + caravelEnv,clock = await test_configure(dut,timeout_cycles=11195844) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -120,7 +120,7 @@ async def uart_check_char_recieved(caravelEnv,cpu): cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}") return if reg1 == 0x1E: - cocotb.log.error(f"[TEST] Failed Pass cpu has recieved the wrong character {chr(int(reg_uart_data,2))}") + cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character {chr(int(reg_uart_data,2))}") return await ClockCycles(caravelEnv.clk,1) \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/uart/uart_rx.c b/verilog/dv/cocotb/tests/uart/uart_rx.c index 8a0ec37d..bb50c117 100644 --- a/verilog/dv/cocotb/tests/uart/uart_rx.c +++ b/verilog/dv/cocotb/tests/uart/uart_rx.c @@ -17,14 +17,14 @@ #include #include - +#include // -------------------------------------------------------- void wait_for_char(char *c){ - while (uart_rxempty_read() == 1); if (reg_uart_data == *c){ reg_debug_1 = 0x1B; // recieved the correct character + uart_ev_pending_write(UART_EV_RX); }else{ reg_debug_1 = 0x1E; // timeout didn't recieve the character }