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fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX);

This commit is contained in:
M0stafaRady 2022-10-06 02:14:59 -07:00
parent a6e7b46128
commit 6830c79ae8
2 changed files with 6 additions and 6 deletions
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10
verilog/dv/cocotb/tests/uart/uart.py
View File

@ -61,7 +61,7 @@ async def start_of_tx(caravelEnv):
@cocotb.test() @cocotb.test()
@repot_test @repot_test
async def uart_rx(dut): async def uart_rx(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=11195844) caravelEnv,clock = await test_configure(dut,timeout_cycles=104029)
cpu = RiskV(dut) cpu = RiskV(dut)
cpu.cpu_force_reset() cpu.cpu_force_reset()
cpu.cpu_release_reset() cpu.cpu_release_reset()
@ -95,7 +95,7 @@ async def uart_send_char(caravelEnv,char):
caravelEnv.drive_gpio_in((5,5),0) caravelEnv.drive_gpio_in((5,5),0)
await Timer(bit_time_ns, units='ns') await Timer(bit_time_ns, units='ns')
#send bits #send bits
for i in range(8): for i in reversed(range(8)):
caravelEnv.drive_gpio_in((5,5),char_bits[i]) caravelEnv.drive_gpio_in((5,5),char_bits[i])
await Timer(bit_time_ns, units='ns') await Timer(bit_time_ns, units='ns')
@ -113,14 +113,14 @@ async def uart_send_char(caravelEnv,char):
async def uart_check_char_recieved(caravelEnv,cpu): async def uart_check_char_recieved(caravelEnv,cpu):
# check cpu recieved the correct character # check cpu recieved the correct character
while True: while True:
# reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
reg1 = cpu.read_debug_reg1() reg1 = cpu.read_debug_reg1()
cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}") cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}")
if reg1 == 0x1B: if reg1 == 0x1B:
cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character ") cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}")
return return
if reg1 == 0x1E: if reg1 == 0x1E:
cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character ") cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character {chr(int(reg_uart_data,2))}")
return return
await ClockCycles(caravelEnv.clk,1) await ClockCycles(caravelEnv.clk,1)

2
verilog/dv/cocotb/tests/uart/uart_rx.c
View File

@ -24,10 +24,10 @@ void wait_for_char(char *c){
while (uart_rxempty_read() == 1); while (uart_rxempty_read() == 1);
if (reg_uart_data == *c){ if (reg_uart_data == *c){
reg_debug_1 = 0x1B; // recieved the correct character reg_debug_1 = 0x1B; // recieved the correct character
uart_ev_pending_write(UART_EV_RX);
}else{ }else{
reg_debug_1 = 0x1E; // timeout didn't recieve the character reg_debug_1 = 0x1E; // timeout didn't recieve the character
} }
uart_ev_pending_write(UART_EV_RX);
} }