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remove `./spef` and `./sdf` directories at the top-level 

add them to `./signoff/openlane-signoff/` as they are generated from openlane
This commit is contained in:
Passant 2022-10-19 14:59:36 -07:00
parent 35852895cf
commit 59cdcf471d
71 changed files with 28708 additions and 757708 deletions
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186
sdf/buff_flash_clkrst.sdf
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(DESIGN "buff_flash_clkrst")
(DATE "Thu Oct 13 17:29:08 2022")
(VENDOR "Parallax")
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(VERSION "2.3.1")
(DIVIDER .)
(VOLTAGE 1.800::1.800)
(PROCESS "1.000::1.000")
(TEMPERATURE 25.000::25.000)
(TIMESCALE 1ns)
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(INTERCONNECT in_n[1] BUF\[4\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
(INTERCONNECT in_n[2] BUF\[5\].A (0.022:0.022:0.022) (0.009:0.009:0.009))
(INTERCONNECT in_n[3] BUF\[6\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
(INTERCONNECT in_n[4] BUF\[7\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
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(INTERCONNECT BUF\[14\].X out_s[11] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[1\].X out_n[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[2\].X out_n[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[3\].X out_s[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
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sdf/caravel_clocking.sdf
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sdf/caravel_clocking/max/caravel_clocking.ff.sdf
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sdf/caravel_clocking/max/caravel_clocking.ss.sdf
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sdf/caravel_clocking/max/caravel_clocking.tt.sdf
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sdf/caravel_clocking/min/caravel_clocking.ff.sdf
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sdf/caravel_clocking/min/caravel_clocking.ss.sdf
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sdf/caravel_clocking/min/caravel_clocking.tt.sdf
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sdf/caravel_clocking/nom/caravel_clocking.ff.sdf
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sdf/caravel_clocking/nom/caravel_clocking.ss.sdf
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sdf/caravel_clocking/nom/caravel_clocking.tt.sdf
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sdf/digital_pll.sdf
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sdf/gpio_control_block.sdf
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sdf/housekeeping.sdf
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sdf/mgmt_protect.sdf
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186
sdf/multicorner/min/buff_flash_clkrst.ff.sdf
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(DIVIDER .)
(VOLTAGE 1.600::1.600)
(PROCESS "1.000::1.000")
(TEMPERATURE 100.000::100.000)
(TIMESCALE 1ns)
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(INSTANCE)
(DELAY
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(INTERCONNECT in_n[11] BUF\[14\].A (0.017:0.017:0.017) (0.006:0.006:0.006))
(INTERCONNECT in_n[1] BUF\[4\].A (0.014:0.014:0.014) (0.004:0.004:0.004))
(INTERCONNECT in_n[2] BUF\[5\].A (0.015:0.015:0.015) (0.005:0.005:0.005))
(INTERCONNECT in_n[3] BUF\[6\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
(INTERCONNECT in_n[4] BUF\[7\].A (0.014:0.014:0.014) (0.004:0.004:0.004))
(INTERCONNECT in_n[5] BUF\[8\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
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(INTERCONNECT BUF\[10\].X out_s[7] (0.000:0.000:0.000) (0.000:0.000:0.000))
(INTERCONNECT BUF\[11\].X out_s[8] (0.001:0.001:0.001) (0.001:0.001:0.001))
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186
sdf/multicorner/min/buff_flash_clkrst.ss.sdf
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@ -1,186 +0,0 @@
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sdf/multicorner/min/buff_flash_clkrst.tt.sdf
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@ -1,186 +0,0 @@
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186
sdf/multicorner/nom/buff_flash_clkrst.ff.sdf
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@ -1,186 +0,0 @@
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186
sdf/multicorner/nom/buff_flash_clkrst.ss.sdf
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@ -1,186 +0,0 @@
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)
)

186
sdf/multicorner/nom/buff_flash_clkrst.tt.sdf
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@ -1,186 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "buff_flash_clkrst")
(DATE "Thu Oct 13 17:29:07 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.1")
(DIVIDER .)
(VOLTAGE 1.600::1.600)
(PROCESS "1.000::1.000")
(TEMPERATURE 100.000::100.000)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "buff_flash_clkrst")
(INSTANCE)
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)
)
)
)

79
signoff/buff_flash_clkrst/openlane-signoff/buff_flash_clkrst.sdc Normal file
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@ -0,0 +1,79 @@
###############################################################################
# Created by write_sdc
# Thu Oct 13 17:28:51 2022
###############################################################################
current_design buff_flash_clkrst
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name __VIRTUAL_CLK__ -period 8.0000
set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[0]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[10]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[11]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[1]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[2]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[3]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[4]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[5]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[6]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[7]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[8]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[9]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_s[0]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_s[1]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_s[2]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_n[0]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_n[1]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_n[2]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[0]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[10]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[11]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[1]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[2]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[3]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[4]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[5]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[6]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[7]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[8]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[9]}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {out_n[2]}]
set_load -pin_load 0.0334 [get_ports {out_n[1]}]
set_load -pin_load 0.0334 [get_ports {out_n[0]}]
set_load -pin_load 0.0334 [get_ports {out_s[11]}]
set_load -pin_load 0.0334 [get_ports {out_s[10]}]
set_load -pin_load 0.0334 [get_ports {out_s[9]}]
set_load -pin_load 0.0334 [get_ports {out_s[8]}]
set_load -pin_load 0.0334 [get_ports {out_s[7]}]
set_load -pin_load 0.0334 [get_ports {out_s[6]}]
set_load -pin_load 0.0334 [get_ports {out_s[5]}]
set_load -pin_load 0.0334 [get_ports {out_s[4]}]
set_load -pin_load 0.0334 [get_ports {out_s[3]}]
set_load -pin_load 0.0334 [get_ports {out_s[2]}]
set_load -pin_load 0.0334 [get_ports {out_s[1]}]
set_load -pin_load 0.0334 [get_ports {out_s[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_s[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_s[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_s[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 10.0000 [current_design]

583
signoff/buff_flash_clkrst/openlane-signoff/lib/buff_flash_clkrst.lib Normal file
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@ -0,0 +1,583 @@
library (buff_flash_clkrst) {
comment : "";
delay_model : table_lookup;
simulation : false;
capacitive_load_unit (1,pF);
leakage_power_unit : 1pW;
current_unit : "1A";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1v";
library_features(report_delay_calculation);
input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_lower_threshold_pct_rise : 20;
slew_lower_threshold_pct_fall : 20;
slew_upper_threshold_pct_rise : 80;
slew_upper_threshold_pct_fall : 80;
slew_derate_from_library : 1.0;
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.80;
lu_table_template(template_1) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_10) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_11) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_12) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_13) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_14) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_15) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_16) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_17) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_18) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_19) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_2) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_20) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_21) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_22) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_23) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_24) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_25) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_26) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_27) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_28) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_29) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_3) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_30) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_4) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_5) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_6) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_7) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_8) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_9) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
type ("in_n") {
base_type : array;
data_type : bit;
bit_width : 12;
bit_from : 11;
bit_to : 0;
}
type ("in_s") {
base_type : array;
data_type : bit;
bit_width : 3;
bit_from : 2;
bit_to : 0;
}
type ("out_n") {
base_type : array;
data_type : bit;
bit_width : 3;
bit_from : 2;
bit_to : 0;
}
type ("out_s") {
base_type : array;
data_type : bit;
bit_width : 12;
bit_from : 11;
bit_to : 0;
}
cell ("buff_flash_clkrst") {
pin("VPWR") {
direction : input;
capacitance : 0.0002;
}
pin("VGND") {
direction : input;
capacitance : 0.0002;
}
bus("in_n") {
bus_type : in_n;
direction : input;
capacitance : 0.0000;
pin("in_n[11]") {
direction : input;
capacitance : 0.0071;
}
pin("in_n[10]") {
direction : input;
capacitance : 0.0047;
}
pin("in_n[9]") {
direction : input;
capacitance : 0.0061;
}
pin("in_n[8]") {
direction : input;
capacitance : 0.0050;
}
pin("in_n[7]") {
direction : input;
capacitance : 0.0060;
}
pin("in_n[6]") {
direction : input;
capacitance : 0.0059;
}
pin("in_n[5]") {
direction : input;
capacitance : 0.0052;
}
pin("in_n[4]") {
direction : input;
capacitance : 0.0055;
}
pin("in_n[3]") {
direction : input;
capacitance : 0.0049;
}
pin("in_n[2]") {
direction : input;
capacitance : 0.0062;
}
pin("in_n[1]") {
direction : input;
capacitance : 0.0055;
}
pin("in_n[0]") {
direction : input;
capacitance : 0.0049;
}
}
bus("in_s") {
bus_type : in_s;
direction : input;
capacitance : 0.0000;
pin("in_s[2]") {
direction : input;
capacitance : 0.0049;
}
pin("in_s[1]") {
direction : input;
capacitance : 0.0061;
}
pin("in_s[0]") {
direction : input;
capacitance : 0.0047;
}
}
bus("out_n") {
bus_type : out_n;
direction : output;
capacitance : 0.0000;
pin("out_n[2]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_s[2]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_29) {
values("0.12205,0.12483,0.13320,0.15618,0.22127,0.43583,1.18473");
}
rise_transition(template_29) {
values("0.02209,0.02435,0.03145,0.05499,0.13876,0.44350,1.51271");
}
cell_fall(template_30) {
values("0.12088,0.12342,0.13084,0.14981,0.19636,0.33046,0.78848");
}
fall_transition(template_30) {
values("0.02101,0.02246,0.02767,0.04268,0.08998,0.26118,0.88479");
}
}
}
pin("out_n[1]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_s[1]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_27) {
values("0.12720,0.12998,0.13836,0.16133,0.22643,0.44114,1.18891");
}
rise_transition(template_27) {
values("0.02209,0.02433,0.03145,0.05498,0.13875,0.44330,1.51127");
}
cell_fall(template_28) {
values("0.12337,0.12590,0.13332,0.15231,0.19882,0.33296,0.79091");
}
fall_transition(template_28) {
values("0.02104,0.02245,0.02769,0.04266,0.08998,0.26119,0.88461");
}
}
}
pin("out_n[0]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_s[0]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_25) {
values("0.12244,0.12522,0.13359,0.15658,0.22167,0.43621,1.18525");
}
rise_transition(template_25) {
values("0.02209,0.02435,0.03146,0.05499,0.13876,0.44352,1.51289");
}
cell_fall(template_26) {
values("0.12131,0.12386,0.13128,0.15024,0.19680,0.33089,0.78892");
}
fall_transition(template_26) {
values("0.02101,0.02246,0.02767,0.04268,0.08997,0.26118,0.88481");
}
}
}
}
bus("out_s") {
bus_type : out_s;
direction : output;
capacitance : 0.0000;
pin("out_s[11]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[11]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_5) {
values("0.13459,0.13737,0.14576,0.16871,0.23382,0.44864,1.19553");
}
rise_transition(template_5) {
values("0.02209,0.02432,0.03144,0.05497,0.13874,0.44315,1.51013");
}
cell_fall(template_6) {
values("0.12778,0.13030,0.13772,0.15673,0.20321,0.33738,0.79528");
}
fall_transition(template_6) {
values("0.02106,0.02244,0.02770,0.04264,0.08998,0.26119,0.88446");
}
}
}
pin("out_s[10]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[10]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_3) {
values("0.12170,0.12448,0.13285,0.15583,0.22093,0.43546,1.18452");
}
rise_transition(template_3) {
values("0.02209,0.02435,0.03146,0.05499,0.13876,0.44353,1.51292");
}
cell_fall(template_4) {
values("0.12079,0.12334,0.13076,0.14972,0.19628,0.33037,0.78841");
}
fall_transition(template_4) {
values("0.02101,0.02246,0.02767,0.04268,0.08997,0.26118,0.88481");
}
}
}
pin("out_s[9]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[9]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_23) {
values("0.12666,0.12945,0.13783,0.16079,0.22589,0.44060,1.18840");
}
rise_transition(template_23) {
values("0.02209,0.02433,0.03145,0.05498,0.13875,0.44331,1.51130");
}
cell_fall(template_24) {
values("0.12300,0.12553,0.13296,0.15194,0.19846,0.33259,0.79055");
}
fall_transition(template_24) {
values("0.02104,0.02245,0.02769,0.04266,0.08998,0.26119,0.88461");
}
}
}
pin("out_s[8]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[8]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_21) {
values("0.12260,0.12538,0.13375,0.15673,0.22183,0.43640,1.18519");
}
rise_transition(template_21) {
values("0.02209,0.02435,0.03145,0.05499,0.13876,0.44348,1.51258");
}
cell_fall(template_22) {
values("0.12116,0.12371,0.13113,0.15009,0.19664,0.33074,0.78876");
}
fall_transition(template_22) {
values("0.02102,0.02246,0.02767,0.04268,0.08998,0.26118,0.88477");
}
}
}
pin("out_s[7]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[7]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_19) {
values("0.12734,0.13012,0.13850,0.16147,0.22657,0.44127,1.18913");
}
rise_transition(template_19) {
values("0.02209,0.02434,0.03145,0.05498,0.13875,0.44332,1.51139");
}
cell_fall(template_20) {
values("0.12358,0.12611,0.13354,0.15252,0.19904,0.33317,0.79113");
}
fall_transition(template_20) {
values("0.02104,0.02245,0.02769,0.04266,0.08998,0.26118,0.88462");
}
}
}
pin("out_s[6]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[6]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_17) {
values("0.12738,0.13016,0.13854,0.16151,0.22661,0.44129,1.18928");
}
rise_transition(template_17) {
values("0.02209,0.02434,0.03145,0.05498,0.13875,0.44334,1.51155");
}
cell_fall(template_18) {
values("0.12376,0.12629,0.13371,0.15269,0.19922,0.33334,0.79131");
}
fall_transition(template_18) {
values("0.02104,0.02245,0.02768,0.04266,0.08998,0.26118,0.88464");
}
}
}
pin("out_s[5]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[5]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_15) {
values("0.12304,0.12582,0.13419,0.15717,0.22227,0.43687,1.18545");
}
rise_transition(template_15) {
values("0.02209,0.02434,0.03145,0.05499,0.13876,0.44344,1.51232");
}
cell_fall(template_16) {
values("0.12125,0.12379,0.13122,0.15018,0.19673,0.33084,0.78884");
}
fall_transition(template_16) {
values("0.02102,0.02245,0.02767,0.04267,0.08998,0.26118,0.88474");
}
}
}
pin("out_s[4]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[4]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_13) {
values("0.12397,0.12675,0.13513,0.15810,0.22320,0.43783,1.18618");
}
rise_transition(template_13) {
values("0.02209,0.02434,0.03145,0.05498,0.13875,0.44340,1.51201");
}
cell_fall(template_14) {
values("0.12166,0.12420,0.13163,0.15060,0.19714,0.33125,0.78924");
}
fall_transition(template_14) {
values("0.02103,0.02245,0.02768,0.04267,0.08998,0.26118,0.88470");
}
}
}
pin("out_s[3]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[3]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_11) {
values("0.12175,0.12453,0.13290,0.15588,0.22098,0.43553,1.18443");
}
rise_transition(template_11) {
values("0.02209,0.02435,0.03145,0.05499,0.13876,0.44350,1.51271");
}
cell_fall(template_12) {
values("0.12066,0.12320,0.13063,0.14959,0.19614,0.33024,0.78826");
}
fall_transition(template_12) {
values("0.02101,0.02246,0.02767,0.04268,0.08998,0.26118,0.88479");
}
}
}
pin("out_s[2]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[2]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_9) {
values("0.12766,0.13044,0.13883,0.16179,0.22689,0.44161,1.18933");
}
rise_transition(template_9) {
values("0.02209,0.02433,0.03145,0.05498,0.13875,0.44330,1.51120");
}
cell_fall(template_10) {
values("0.12366,0.12619,0.13361,0.15260,0.19911,0.33325,0.79120");
}
fall_transition(template_10) {
values("0.02104,0.02245,0.02769,0.04266,0.08998,0.26119,0.88460");
}
}
}
pin("out_s[1]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[1]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_7) {
values("0.12485,0.12763,0.13601,0.15898,0.22408,0.43872,1.18704");
}
rise_transition(template_7) {
values("0.02209,0.02434,0.03145,0.05498,0.13875,0.44340,1.51198");
}
cell_fall(template_8) {
values("0.12228,0.12482,0.13224,0.15122,0.19775,0.33187,0.78986");
}
fall_transition(template_8) {
values("0.02103,0.02245,0.02768,0.04267,0.08998,0.26118,0.88469");
}
}
}
pin("out_s[0]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[0]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_1) {
values("0.12197,0.12475,0.13312,0.15611,0.22120,0.43576,1.18463");
}
rise_transition(template_1) {
values("0.02209,0.02435,0.03145,0.05499,0.13876,0.44349,1.51268");
}
cell_fall(template_2) {
values("0.12080,0.12335,0.13077,0.14973,0.19629,0.33038,0.78841");
}
fall_transition(template_2) {
values("0.02102,0.02246,0.02767,0.04268,0.08998,0.26118,0.88478");
}
}
}
}
}
}

0
sdf/caravan.sdf → signoff/caravan/openlane-signoff/sdf/nom/caravan.tt.sdf
View File

0
spef/caravan/caravan.nom.spef → signoff/caravan/openlane-signoff/spef/caravan.nom.spef
View File

513
signoff/caravel_clocking/openlane-signoff/lib/caravel_clocking.lib Normal file
View File

@ -0,0 +1,513 @@
library (caravel_clocking) {
comment : "";
delay_model : table_lookup;
simulation : false;
capacitive_load_unit (1,pF);
leakage_power_unit : 1pW;
current_unit : "1A";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1v";
library_features(report_delay_calculation);
input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_lower_threshold_pct_rise : 20;
slew_lower_threshold_pct_fall : 20;
slew_upper_threshold_pct_rise : 80;
slew_upper_threshold_pct_fall : 80;
slew_derate_from_library : 1.0;
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.80;
lu_table_template(template_1) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00232, 0.01077, 0.05000, 0.23208, 1.07722, 5.00000");
}
lu_table_template(template_10) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_11) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00232, 0.01077, 0.05000, 0.23208, 1.07722, 5.00000");
}
lu_table_template(template_12) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00232, 0.01077, 0.05000, 0.23208, 1.07722, 5.00000");
}
lu_table_template(template_13) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_14) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_15) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_16) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_17) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_18) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_19) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_2) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00232, 0.01077, 0.05000, 0.23208, 1.07722, 5.00000");
}
lu_table_template(template_20) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_21) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_22) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_3) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_4) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_5) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_6) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_7) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_8) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_9) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
type ("sel") {
base_type : array;
data_type : bit;
bit_width : 3;
bit_from : 2;
bit_to : 0;
}
type ("sel2") {
base_type : array;
data_type : bit;
bit_width : 3;
bit_from : 2;
bit_to : 0;
}
cell ("caravel_clocking") {
pin("core_clk") {
direction : output;
capacitance : 0.2094;
timing() {
related_pin : "ext_clk";
timing_type : rising_edge;
cell_rise(template_3) {
values("1.66101,1.66289,1.66932,1.68895,1.74717,1.94899,2.70950");
}
rise_transition(template_3) {
values("0.02434,0.02582,0.03117,0.05049,0.12301,0.40936,1.50414");
}
cell_fall(template_4) {
values("-0.11201,-0.11030,-0.10445,-0.08790,-0.04459,0.08258,0.54403");
}
fall_transition(template_4) {
values("0.02325,0.02436,0.02827,0.04095,0.08430,0.25146,0.91403");
}
}
timing() {
related_pin : "ext_clk";
timing_type : falling_edge;
cell_rise(template_5) {
values("-0.15692,-0.15505,-0.14862,-0.12898,-0.07076,0.13106,0.89157");
}
rise_transition(template_5) {
values("0.02434,0.02582,0.03117,0.05049,0.12301,0.40936,1.50414");
}
cell_fall(template_6) {
values("2.99607,2.99779,3.00364,3.02018,3.06350,3.19066,3.65212");
}
fall_transition(template_6) {
values("0.02325,0.02436,0.02827,0.04095,0.08430,0.25146,0.91403");
}
}
timing() {
related_pin : "core_clk";
timing_type : rising_edge;
cell_rise(template_7) {
values("1.66101,1.66289,1.66932,1.68895,1.74717,1.94899,2.70950");
}
rise_transition(template_7) {
values("0.02434,0.02582,0.03117,0.05049,0.12301,0.40936,1.50414");
}
cell_fall(template_8) {
values("-0.11201,-0.11030,-0.10445,-0.08790,-0.04459,0.08258,0.54403");
}
fall_transition(template_8) {
values("0.02325,0.02436,0.02827,0.04095,0.08430,0.25146,0.91403");
}
}
timing() {
related_pin : "core_clk";
timing_type : falling_edge;
cell_rise(template_9) {
values("-0.15692,-0.15505,-0.14862,-0.12898,-0.07076,0.13106,0.89157");
}
rise_transition(template_9) {
values("0.02434,0.02582,0.03117,0.05049,0.12301,0.40936,1.50414");
}
cell_fall(template_10) {
values("15.49607,15.49779,15.50364,15.52018,15.56350,15.69066,16.15211");
}
fall_transition(template_10) {
values("0.02325,0.02436,0.02827,0.04095,0.08430,0.25146,0.91403");
}
}
}
pin("ext_clk") {
direction : input;
capacitance : 0.0113;
}
pin("ext_clk_sel") {
direction : input;
capacitance : 0.0038;
timing() {
related_pin : "pll_clk";
timing_type : hold_rising;
rise_constraint(scalar) {
values("0.27545");
}
fall_constraint(scalar) {
values("-0.59870");
}
}
timing() {
related_pin : "pll_clk";
timing_type : setup_rising;
rise_constraint(scalar) {
values("-0.06985");
}
fall_constraint(scalar) {
values("0.85359");
}
}
}
pin("ext_reset") {
direction : input;
capacitance : 0.0043;
timing() {
related_pin : "ext_clk";
timing_type : hold_rising;
rise_constraint(scalar) {
values("-5.52988");
}
fall_constraint(scalar) {
values("-6.42033");
}
}
timing() {
related_pin : "ext_clk";
timing_type : setup_rising;
rise_constraint(scalar) {
values("5.59236");
}
fall_constraint(scalar) {
values("6.56985");
}
}
}
pin("pll_clk") {
direction : input;
capacitance : 0.0217;
}
pin("pll_clk90") {
direction : input;
capacitance : 0.0155;
}
pin("resetb") {
direction : input;
capacitance : 0.0044;
timing() {
related_pin : "ext_clk";
timing_sense : negative_unate;
timing_type : hold_falling;
rise_constraint(scalar) {
values("2.67088");
}
}
timing() {
related_pin : "ext_clk";
timing_sense : negative_unate;
timing_type : setup_falling;
rise_constraint(scalar) {
values("-1.83114");
}
}
timing() {
related_pin : "pll_clk";
timing_type : hold_rising;
rise_constraint(scalar) {
values("0.56148");
}
fall_constraint(scalar) {
values("-0.63541");
}
}
timing() {
related_pin : "pll_clk";
timing_type : setup_rising;
rise_constraint(scalar) {
values("0.41085");
}
fall_constraint(scalar) {
values("1.06792");
}
}
timing() {
related_pin : "pll_clk";
timing_sense : negative_unate;
timing_type : hold_falling;
rise_constraint(scalar) {
values("1.58562");
}
}
timing() {
related_pin : "pll_clk";
timing_sense : negative_unate;
timing_type : setup_falling;
rise_constraint(scalar) {
values("-1.02788");
}
}
timing() {
related_pin : "pll_clk90";
timing_sense : positive_unate;
timing_type : hold_rising;
rise_constraint(scalar) {
values("0.53892");
}
}
timing() {
related_pin : "pll_clk90";
timing_sense : positive_unate;
timing_type : setup_rising;
rise_constraint(scalar) {
values("0.15517");
}
}
timing() {
related_pin : "pll_clk90";
timing_sense : negative_unate;
timing_type : hold_falling;
rise_constraint(scalar) {
values("1.56719");
}
}
timing() {
related_pin : "pll_clk90";
timing_sense : negative_unate;
timing_type : setup_falling;
rise_constraint(scalar) {
values("-0.70527");
}
}
}
pin("resetb_sync") {
direction : output;
capacitance : 0.2000;
timing() {
related_pin : "ext_reset";
timing_sense : negative_unate;
timing_type : combinational;
cell_rise(template_1) {
values("1.40631,1.40883,1.41875,1.45386,1.59465,2.23564,5.19283");
}
rise_transition(template_1) {
values("0.02247,0.02443,0.03316,0.07268,0.26583,1.18279,5.39656");
}
cell_fall(template_2) {
values("0.50304,0.50506,0.51263,0.53575,0.60447,0.87618,2.12327");
}
fall_transition(template_2) {
values("0.01885,0.02014,0.02505,0.04329,0.11876,0.48570,2.21348");
}
}
timing() {
related_pin : "ext_clk";
timing_type : falling_edge;
cell_rise(template_11) {
values("16.24807,16.25059,16.26051,16.29562,16.43641,17.07740,20.03459");
}
rise_transition(template_11) {
values("0.02247,0.02443,0.03316,0.07268,0.26583,1.18279,5.39656");
}
cell_fall(template_12) {
values("16.26107,16.26309,16.27067,16.29379,16.36251,16.63421,17.88131");
}
fall_transition(template_12) {
values("0.01885,0.02014,0.02505,0.04329,0.11876,0.48570,2.21348");
}
}
}
pin("user_clk") {
direction : output;
capacitance : 0.2000;
timing() {
related_pin : "ext_clk";
timing_type : rising_edge;
cell_rise(template_13) {
values("1.54263,1.54451,1.55093,1.57042,1.62858,1.83060,2.59730");
}
rise_transition(template_13) {
values("0.02439,0.02587,0.03120,0.05053,0.12314,0.40892,1.50596");
}
cell_fall(template_14) {
values("-0.10799,-0.10631,-0.10034,-0.08375,-0.04057,0.08664,0.54821");
}
fall_transition(template_14) {
values("0.02337,0.02442,0.02828,0.04105,0.08437,0.25148,0.91304");
}
}
timing() {
related_pin : "ext_clk";
timing_type : falling_edge;
cell_rise(template_15) {
values("-0.15037,-0.14850,-0.14207,-0.12258,-0.06442,0.13760,0.90429");
}
rise_transition(template_15) {
values("0.02439,0.02587,0.03120,0.05053,0.12314,0.40892,1.50596");
}
cell_fall(template_16) {
values("15.35966,15.36134,15.36731,15.38390,15.42708,15.55429,16.01586");
}
fall_transition(template_16) {
values("0.02337,0.02442,0.02828,0.04105,0.08437,0.25148,0.91304");
}
}
timing() {
related_pin : "pll_clk";
timing_type : rising_edge;
cell_rise(template_17) {
values("2.11329,2.11516,2.12159,2.14108,2.19924,2.40126,3.16795");
}
rise_transition(template_17) {
values("0.02439,0.02587,0.03120,0.05053,0.12314,0.40892,1.50596");
}
cell_fall(template_18) {
values("2.45140,2.45308,2.45905,2.47564,2.51882,2.64603,3.10759");
}
fall_transition(template_18) {
values("0.02337,0.02442,0.02828,0.04105,0.08437,0.25148,0.91304");
}
}
timing() {
related_pin : "pll_clk90";
timing_type : rising_edge;
cell_rise(template_19) {
values("2.51398,2.51585,2.52228,2.54177,2.59993,2.80195,3.56864");
}
rise_transition(template_19) {
values("0.02439,0.02587,0.03120,0.05053,0.12314,0.40892,1.50596");
}
cell_fall(template_20) {
values("2.51791,2.51959,2.52555,2.54215,2.58533,2.71254,3.17410");
}
fall_transition(template_20) {
values("0.02337,0.02442,0.02828,0.04105,0.08437,0.25148,0.91304");
}
}
timing() {
related_pin : "pll_clk90";
timing_type : falling_edge;
cell_rise(template_21) {
values("6.81800,6.81987,6.82630,6.84579,6.90395,7.10597,7.87266");
}
rise_transition(template_21) {
values("0.02439,0.02587,0.03120,0.05053,0.12314,0.40892,1.50596");
}
cell_fall(template_22) {
values("6.81403,6.81570,6.82167,6.83826,6.88145,7.00866,7.47022");
}
fall_transition(template_22) {
values("0.02337,0.02442,0.02828,0.04105,0.08437,0.25148,0.91304");
}
}
}
pin("VPWR") {
direction : input;
capacitance : 0.0002;
}
pin("VGND") {
direction : input;
capacitance : 0.0002;
}
bus("sel") {
bus_type : sel;
direction : input;
capacitance : 0.0000;
pin("sel[2]") {
direction : input;
capacitance : 0.0042;
}
pin("sel[1]") {
direction : input;
capacitance : 0.0043;
}
pin("sel[0]") {
direction : input;
capacitance : 0.0040;
}
}
bus("sel2") {
bus_type : sel2;
direction : input;
capacitance : 0.0000;
pin("sel2[2]") {
direction : input;
capacitance : 0.0041;
}
pin("sel2[1]") {
direction : input;
capacitance : 0.0041;
}
pin("sel2[0]") {
direction : input;
capacitance : 0.0041;
}
}
}
}

0
sdf/chip_io.sdf → signoff/chip_io/openlane-signoff/sdf/nom/chip_io.tt.sdf
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0
spef/chip_io/chip_io.nom.spef → signoff/chip_io/openlane-signoff/spef/chip_io.nom.spef
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23
signoff/constant_block/openlane-signoff/constant_block.sdc Normal file
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@ -0,0 +1,23 @@
###############################################################################
# Created by write_sdc
# Sat Oct 8 18:34:24 2022
###############################################################################
current_design constant_block
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name __VIRTUAL_CLK__ -period 10.0000
set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {one}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {zero}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {one}]
set_load -pin_load 0.0334 [get_ports {zero}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 10.0000 [current_design]

48
signoff/constant_block/openlane-signoff/lib/constant_block.lib Normal file
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@ -0,0 +1,48 @@
library (constant_block) {
comment : "";
delay_model : table_lookup;
simulation : false;
capacitive_load_unit (1,pF);
leakage_power_unit : 1pW;
current_unit : "1A";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1v";
library_features(report_delay_calculation);
input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_lower_threshold_pct_rise : 20;
slew_lower_threshold_pct_fall : 20;
slew_upper_threshold_pct_rise : 80;
slew_upper_threshold_pct_fall : 80;
slew_derate_from_library : 1.0;
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.80;
cell ("constant_block") {
pin("one") {
direction : output;
capacitance : 0.0334;
}
pin("zero") {
direction : output;
capacitance : 0.0334;
}
pin("vccd") {
direction : input;
capacitance : 0.0002;
}
pin("vssd") {
direction : input;
capacitance : 0.0002;
}
}
}

0
sdf/constant_block.sdf → signoff/constant_block/openlane-signoff/sdf/nom/constant_block.tt.sdf
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0
spef/constant_block/constant_block.nom.spef → signoff/constant_block/openlane-signoff/spef/constant_block.nom.spef
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0
sdf/gpio_defaults_block.sdf → signoff/gpio_defaults_block/openlane-signoff/sdf/nom/gpio_defaults_block.tt.sdf
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0
spef/gpio_defaults_block/gpio_defaults_block.nom.spef → signoff/gpio_defaults_block/openlane-signoff/spef/gpio_defaults_block.nom.spef
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0
spef/gpio_defaults_block_0403/gpio_defaults_block_0403.nom.spef → signoff/gpio_defaults_block_0403/openlane-signoff/spef/gpio_defaults_block_0403.nom.spef
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0
spef/gpio_defaults_block_1803/gpio_defaults_block_1803.nom.spef → signoff/gpio_defaults_block_1803/openlane-signoff/spef/gpio_defaults_block_1803.nom.spef
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0
sdf/gpio_logic_high.sdf → signoff/gpio_logic_high/openlane-signoff/sdf/nom/gpio_logic_high.tt.sdf
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0
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3028
signoff/housekeeping/openlane-signoff/lib/housekeeping.lib Normal file
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24434
signoff/mgmt_protect/openlane-signoff/lib/mgmt_protect.lib Normal file
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0
sdf/mgmt_protect_hv.sdf → signoff/mgmt_protect_hv/openlane-signoff/sdf/nom/mgmt_protect_hv.tt.sdf
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0
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0
sdf/mprj2_logic_high.sdf → signoff/mprj2_logic_high/openlane-signoff/sdf/nom/mprj2_logic_high.tt.sdf
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0
spef/mprj2_logic_high/mprj2_logic_high.nom.spef → signoff/mprj2_logic_high/openlane-signoff/spef/mprj2_logic_high.nom.spef
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0
sdf/mprj_logic_high.sdf → signoff/mprj_logic_high/openlane-signoff/sdf/nom/mprj_logic_high.tt.sdf
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0
spef/mprj_logic_high/mprj_logic_high.nom.spef → signoff/mprj_logic_high/openlane-signoff/spef/mprj_logic_high.nom.spef
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0
sdf/spare_logic_block.sdf → signoff/spare_logic_block/openlane-signoff/sdf/nom/spare_logic_block.tt.sdf
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0
spef/spare_logic_block/spare_logic_block.nom.spef → signoff/spare_logic_block/openlane-signoff/spef/spare_logic_block.nom.spef
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0
sdf/xres_buf.sdf → signoff/xres_buf/openlane-signoff/sdf/nom/xres_buf.tt.sdf
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0
spef/xres_buf/xres_buf.nom.spef → signoff/xres_buf/openlane-signoff/spef/xres_buf.nom.spef
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587
spef/buff_flash_clkrst.spef
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@ -1,587 +0,0 @@
*SPEF "ieee 1481-1999"
*DESIGN "buff_flash_clkrst"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*3 in_n[0]
*4 in_n[10]
*5 in_n[11]
*6 in_n[1]
*7 in_n[2]
*8 in_n[3]
*9 in_n[4]
*10 in_n[5]
*11 in_n[6]
*12 in_n[7]
*13 in_n[8]
*14 in_n[9]
*15 in_s[0]
*16 in_s[1]
*17 in_s[2]
*18 out_n[0]
*19 out_n[1]
*20 out_n[2]
*21 out_s[0]
*22 out_s[10]
*23 out_s[11]
*24 out_s[1]
*25 out_s[2]
*26 out_s[3]
*27 out_s[4]
*28 out_s[5]
*29 out_s[6]
*30 out_s[7]
*31 out_s[8]
*32 out_s[9]
*33 BUF\[0\]
*34 BUF\[10\]
*35 BUF\[11\]
*36 BUF\[12\]
*37 BUF\[13\]
*38 BUF\[14\]
*39 BUF\[1\]
*40 BUF\[2\]
*41 BUF\[3\]
*42 BUF\[4\]
*43 BUF\[5\]
*44 BUF\[6\]
*45 BUF\[7\]
*46 BUF\[8\]
*47 BUF\[9\]
*48 FILLER_0_19
*49 FILLER_0_27
*50 FILLER_0_29
*51 FILLER_0_3
*52 FILLER_0_41
*53 FILLER_0_54
*54 FILLER_0_57
*55 FILLER_0_7
*56 FILLER_0_70
*57 FILLER_0_74
*58 FILLER_1_17
*59 FILLER_1_3
*60 FILLER_1_32
*61 FILLER_1_47
*62 FILLER_1_55
*63 FILLER_1_57
*64 FILLER_1_70
*65 FILLER_1_74
*66 FILLER_2_26
*67 FILLER_2_29
*68 FILLER_2_3
*69 FILLER_2_52
*70 FILLER_2_67
*71 FILLER_3_15
*72 FILLER_3_27
*73 FILLER_3_3
*74 FILLER_3_42
*75 FILLER_3_54
*76 FILLER_3_57
*77 FILLER_3_70
*78 FILLER_3_74
*79 FILLER_4_19
*80 FILLER_4_27
*81 FILLER_4_29
*82 FILLER_4_3
*83 FILLER_4_41
*84 FILLER_4_53
*85 FILLER_4_57
*86 FILLER_4_7
*87 FILLER_4_70
*88 FILLER_4_74
*89 PHY_0
*90 PHY_1
*91 PHY_2
*92 PHY_3
*93 PHY_4
*94 PHY_5
*95 PHY_6
*96 PHY_7
*97 PHY_8
*98 PHY_9
*99 TAP_10
*100 TAP_11
*101 TAP_12
*102 TAP_13
*103 TAP_14
*104 TAP_15
*105 TAP_16
*PORTS
in_n[0] I
in_n[10] I
in_n[11] I
in_n[1] I
in_n[2] I
in_n[3] I
in_n[4] I
in_n[5] I
in_n[6] I
in_n[7] I
in_n[8] I
in_n[9] I
in_s[0] I
in_s[1] I
in_s[2] I
out_n[0] O
out_n[1] O
out_n[2] O
out_s[0] O
out_s[10] O
out_s[11] O
out_s[1] O
out_s[2] O
out_s[3] O
out_s[4] O
out_s[5] O
out_s[6] O
out_s[7] O
out_s[8] O
out_s[9] O
*D_NET *3 0.000746189
*CONN
*P in_n[0] I
*I *41:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[0] 0.000291118
2 *41:A 0.000291118
3 *41:A out_n[2] 0.000163953
4 *41:A *42:A 0
*RES
1 in_n[0] *41:A 20.5321
*END
*D_NET *4 0.000540091
*CONN
*P in_n[10] I
*I *37:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[10] 0.00024161
2 *37:A 0.00024161
3 *37:A out_s[10] 5.68722e-05
4 *37:A *36:A 0
5 *37:A *38:A 0
*RES
1 in_n[10] *37:A 18.55
*END
*D_NET *5 0.00290352
*CONN
*P in_n[11] I
*I *38:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[11] 0.00113707
2 *38:A 0.00113707
3 *38:A out_s[10] 0
4 *38:A out_s[11] 0.000304969
5 *38:A out_s[9] 0.000140933
6 *38:A *36:A 0.000183477
7 *37:A *38:A 0
*RES
1 in_n[11] *38:A 36.925
*END
*D_NET *6 0.00134243
*CONN
*P in_n[1] I
*I *42:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[1] 0.000293149
2 *42:A 0.000293149
3 *42:A out_s[0] 7.58571e-05
4 *42:A *43:A 0.000680277
5 *41:A *42:A 0
*RES
1 in_n[1] *42:A 22.7464
*END
*D_NET *7 0.00200548
*CONN
*P in_n[2] I
*I *43:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[2] 0.000625829
2 *43:A 0.000625829
3 *43:A out_s[0] 0
4 *43:A out_s[1] 6.74911e-05
5 *43:A out_s[2] 6.05161e-06
6 *43:A *44:A 0
7 *42:A *43:A 0.000680277
*RES
1 in_n[2] *43:A 27.5679
*END
*D_NET *8 0.000719992
*CONN
*P in_n[3] I
*I *44:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[3] 0.000359996
2 *44:A 0.000359996
3 *44:A *45:A 0
4 *43:A *44:A 0
*RES
1 in_n[3] *44:A 20.5321
*END
*D_NET *9 0.00131838
*CONN
*P in_n[4] I
*I *45:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[4] 0.000565243
2 *45:A 0.000565243
3 *45:A out_s[3] 0.000187893
4 *45:A *46:A 0
5 *44:A *45:A 0
*RES
1 in_n[4] *45:A 25.3893
*END
*D_NET *10 0.00105711
*CONN
*P in_n[5] I
*I *46:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[5] 0.000528554
2 *46:A 0.000528554
3 *45:A *46:A 0
*RES
1 in_n[5] *46:A 23.5679
*END
*D_NET *11 0.00171215
*CONN
*P in_n[6] I
*I *47:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[6] 0.000448575
2 *47:A 0.000448575
3 *47:A out_s[6] 0.000141554
4 *47:A *34:A 0.000673444
*RES
1 in_n[6] *47:A 25.3357
*END
*D_NET *12 0.00184731
*CONN
*P in_n[7] I
*I *34:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[7] 0.000505756
2 *34:A 0.000505756
3 *34:A out_s[6] 3.85148e-05
4 *34:A out_s[7] 0.000123836
5 *34:A out_s[8] 0
6 *34:A *35:A 0
7 *47:A *34:A 0.000673444
*RES
1 in_n[7] *34:A 26.2107
*END
*D_NET *13 0.00083737
*CONN
*P in_n[8] I
*I *35:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[8] 0.000415659
2 *35:A 0.000415659
3 *35:A out_s[8] 6.05161e-06
4 *35:A *36:A 0
5 *34:A *35:A 0
*RES
1 in_n[8] *35:A 21.1929
*END
*D_NET *14 0.00191759
*CONN
*P in_n[9] I
*I *36:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[9] 0.000817106
2 *36:A 0.000817106
3 *36:A out_s[10] 0
4 *36:A out_s[11] 9.98961e-05
5 *35:A *36:A 0
6 *37:A *36:A 0
7 *38:A *36:A 0.000183477
*RES
1 in_n[9] *36:A 29.3714
*END
*D_NET *15 0.000565776
*CONN
*P in_s[0] I
*I *33:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[0] 0.000232546
2 *33:A 0.000232546
3 *33:A out_n[0] 0.000100684
4 *33:A *39:A 0
*RES
1 in_s[0] *33:A 17.9071
*END
*D_NET *16 0.00194543
*CONN
*P in_s[1] I
*I *39:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[1] 0.000603696
2 *39:A 0.000603696
3 *39:A out_n[0] 0.000738039
4 *39:A out_n[2] 0
5 *39:A *40:A 0
6 *33:A *39:A 0
*RES
1 in_s[1] *39:A 27.4607
*END
*D_NET *17 0.000720944
*CONN
*P in_s[2] I
*I *40:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[2] 0.000360472
2 *40:A 0.000360472
3 *40:A out_s[0] 0
4 *39:A *40:A 0
*RES
1 in_s[2] *40:A 20.1214
*END
*D_NET *18 0.00251314
*CONN
*P out_n[0] O
*I *33:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[0] 0.00083721
2 *33:X 0.00083721
3 out_n[0] out_n[1] 0
4 out_n[0] out_n[2] 0
5 *33:A out_n[0] 0.000100684
6 *39:A out_n[0] 0.000738039
*RES
1 *33:X out_n[0] 32.2464
*END
*D_NET *19 0.0008921
*CONN
*P out_n[1] O
*I *39:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[1] 0.000313512
2 *39:X 0.000313512
3 out_n[1] out_n[2] 0.000265077
4 out_n[0] out_n[1] 0
*RES
1 *39:X out_n[1] 20.175
*END
*D_NET *20 0.00165991
*CONN
*P out_n[2] O
*I *40:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[2] 0.000615442
2 *40:X 0.000615442
3 out_n[2] out_s[0] 0
4 out_n[0] out_n[2] 0
5 out_n[1] out_n[2] 0.000265077
6 *39:A out_n[2] 0
7 *41:A out_n[2] 0.000163953
*RES
1 *40:X out_n[2] 26.7464
*END
*D_NET *21 0.00149166
*CONN
*P out_s[0] O
*I *41:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[0] 0.000551682
2 *41:X 0.000551682
3 out_s[0] out_s[1] 0.000312442
4 out_s[0] out_s[2] 0
5 out_n[2] out_s[0] 0
6 *40:A out_s[0] 0
7 *42:A out_s[0] 7.58571e-05
8 *43:A out_s[0] 0
*RES
1 *41:X out_s[0] 27.6214
*END
*D_NET *22 0.00205685
*CONN
*P out_s[10] O
*I *37:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[10] 0.000999988
2 *37:X 0.000999988
3 out_s[10] out_s[11] 0
4 out_s[10] out_s[9] 0
5 *36:A out_s[10] 0
6 *37:A out_s[10] 5.68722e-05
7 *38:A out_s[10] 0
*RES
1 *37:X out_s[10] 30.4607
*END
*D_NET *23 0.00269979
*CONN
*P out_s[11] O
*I *38:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[11] 0.001077
2 *38:X 0.001077
3 out_s[11] out_s[9] 0.000140933
4 out_s[10] out_s[11] 0
5 *36:A out_s[11] 9.98961e-05
6 *38:A out_s[11] 0.000304969
*RES
1 *38:X out_s[11] 28.3
*END
*D_NET *24 0.00141598
*CONN
*P out_s[1] O
*I *42:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[1] 0.000407902
2 *42:X 0.000407902
3 out_s[1] out_s[2] 0.000220246
4 out_s[1] out_s[3] 0
5 out_s[0] out_s[1] 0.000312442
6 *43:A out_s[1] 6.74911e-05
*RES
1 *42:X out_s[1] 23.9964
*END
*D_NET *25 0.000977116
*CONN
*P out_s[2] O
*I *43:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[2] 0.000375409
2 *43:X 0.000375409
3 out_s[2] out_s[3] 0
4 out_s[0] out_s[2] 0
5 out_s[1] out_s[2] 0.000220246
6 *43:A out_s[2] 6.05161e-06
*RES
1 *43:X out_s[2] 23.175
*END
*D_NET *26 0.00144163
*CONN
*P out_s[3] O
*I *44:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[3] 0.000626868
2 *44:X 0.000626868
3 out_s[3] out_s[4] 0
4 out_s[3] out_s[5] 0
5 out_s[1] out_s[3] 0
6 out_s[2] out_s[3] 0
7 *45:A out_s[3] 0.000187893
*RES
1 *44:X out_s[3] 25.9071
*END
*D_NET *27 0.000857812
*CONN
*P out_s[4] O
*I *45:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[4] 0.00037039
2 *45:X 0.00037039
3 out_s[4] out_s[5] 0.000117033
4 out_s[3] out_s[4] 0
*RES
1 *45:X out_s[4] 21.3
*END
*D_NET *28 0.0011436
*CONN
*P out_s[5] O
*I *46:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[5] 0.000513285
2 *46:X 0.000513285
3 out_s[5] out_s[6] 0
4 out_s[3] out_s[5] 0
5 out_s[4] out_s[5] 0.000117033
*RES
1 *46:X out_s[5] 23.175
*END
*D_NET *29 0.00186776
*CONN
*P out_s[6] O
*I *47:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[6] 0.000801981
2 *47:X 0.000801981
3 out_s[6] out_s[7] 8.37335e-05
4 out_s[5] out_s[6] 0
5 *34:A out_s[6] 3.85148e-05
6 *47:A out_s[6] 0.000141554
*RES
1 *47:X out_s[6] 27.5321
*END
*D_NET *30 0.00134038
*CONN
*P out_s[7] O
*I *34:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[7] 0.000566407
2 *34:X 0.000566407
3 out_s[7] out_s[8] 0
4 out_s[6] out_s[7] 8.37335e-05
5 *34:A out_s[7] 0.000123836
*RES
1 *34:X out_s[7] 24.3357
*END
*D_NET *31 0.00161835
*CONN
*P out_s[8] O
*I *35:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[8] 0.000784339
2 *35:X 0.000784339
3 out_s[8] out_s[9] 4.36202e-05
4 out_s[7] out_s[8] 0
5 *34:A out_s[8] 0
6 *35:A out_s[8] 6.05161e-06
*RES
1 *35:X out_s[8] 27.3893
*END
*D_NET *32 0.000618171
*CONN
*P out_s[9] O
*I *36:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[9] 0.000146343
2 *36:X 0.000146343
3 out_s[10] out_s[9] 0
4 out_s[11] out_s[9] 0.000140933
5 out_s[8] out_s[9] 4.36202e-05
6 *38:A out_s[9] 0.000140933
*RES
1 *36:X out_s[9] 17.4964
*END

71420
spef/caravan.spef
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80597
spef/caravel.spef
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11740
spef/caravel_clocking.spef
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9721
spef/chip_io.spef
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84
spef/constant_block.spef
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@ -1,84 +0,0 @@
*SPEF "ieee 1481-1999"
*DESIGN "constant_block"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*1 one
*4 zero
*5 one_unbuf
*6 zero_unbuf
*7 FILLER_0_0
*8 FILLER_0_24
*9 FILLER_0_27
*10 FILLER_1_0
*11 FILLER_1_16
*12 FILLER_1_24
*13 FILLER_1_4
*14 FILLER_1_8
*15 FILLER_2_0
*16 FILLER_2_24
*17 FILLER_2_27
*18 TAP_0
*19 TAP_1
*20 const_one_buf
*21 const_source
*22 const_zero_buf
*PORTS
one O
zero O
*D_NET *1 0.000496181
*CONN
*P one O
*I *20:X O *D sky130_fd_sc_hd__buf_16
*CAP
1 one 0.00024809
2 *20:X 0.00024809
*RES
1 *20:X one 19.8722
*END
*D_NET *4 0.000337027
*CONN
*P zero O
*I *22:X O *D sky130_fd_sc_hd__buf_16
*CAP
1 zero 0.000168514
2 *22:X 0.000168514
*RES
1 *22:X zero 19.5839
*END
*D_NET *5 0.000235339
*CONN
*I *20:A I *D sky130_fd_sc_hd__buf_16
*I *21:HI O *D sky130_fd_sc_hd__conb_1
*CAP
1 *20:A 0.000117669
2 *21:HI 0.000117669
*RES
1 *21:HI *20:A 30.1893
*END
*D_NET *6 0.000171306
*CONN
*I *22:A I *D sky130_fd_sc_hd__buf_16
*I *21:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 *22:A 8.56529e-05
2 *21:LO 8.56529e-05
*RES
1 *21:LO *22:A 29.5464
*END

14066
spef/digital_pll.spef
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5623
spef/gpio_control_block.spef
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6121
spef/gpio_control_block/gpio_control_block.max.spef
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5487
spef/gpio_control_block/gpio_control_block.min.spef
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5623
spef/gpio_control_block/gpio_control_block.nom.spef
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273
spef/gpio_defaults_block.spef
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@ -1,273 +0,0 @@
*SPEF "ieee 1481-1999"
*DESIGN "gpio_defaults_block"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*3 gpio_defaults_low\[0\]
*4 gpio_defaults_high\[10\]
*5 gpio_defaults_low\[11\]
*6 gpio_defaults_low\[12\]
*7 gpio_defaults_high\[1\]
*8 gpio_defaults_low\[2\]
*9 gpio_defaults_low\[3\]
*10 gpio_defaults_low\[4\]
*11 gpio_defaults_low\[5\]
*12 gpio_defaults_low\[6\]
*13 gpio_defaults_low\[7\]
*14 gpio_defaults_low\[8\]
*15 gpio_defaults_low\[9\]
*16 gpio_defaults_high\[0\]
*17 gpio_defaults_high\[11\]
*18 gpio_defaults_high\[12\]
*19 gpio_defaults_high\[2\]
*20 gpio_defaults_high\[3\]
*21 gpio_defaults_high\[4\]
*22 gpio_defaults_high\[5\]
*23 gpio_defaults_high\[6\]
*24 gpio_defaults_high\[7\]
*25 gpio_defaults_high\[8\]
*26 gpio_defaults_high\[9\]
*27 gpio_defaults_low\[10\]
*28 gpio_defaults_low\[1\]
*29 FILLER_0_29
*30 FILLER_0_3
*31 FILLER_0_33
*32 FILLER_0_38
*33 FILLER_0_43
*34 FILLER_0_48
*35 FILLER_0_55
*36 FILLER_0_60
*37 FILLER_0_9
*38 FILLER_1_15
*39 FILLER_1_27
*40 FILLER_1_3
*41 FILLER_1_39
*42 FILLER_1_51
*43 FILLER_1_55
*44 FILLER_1_57
*45 FILLER_1_61
*46 FILLER_2_15
*47 FILLER_2_27
*48 FILLER_2_29
*49 FILLER_2_3
*50 FILLER_2_41
*51 FILLER_2_53
*52 FILLER_2_57
*53 FILLER_2_61
*54 PHY_0
*55 PHY_1
*56 PHY_2
*57 PHY_3
*58 PHY_4
*59 PHY_5
*60 TAP_10
*61 TAP_6
*62 TAP_7
*63 TAP_8
*64 TAP_9
*65 gpio_default_value\[0\]
*66 gpio_default_value\[10\]
*67 gpio_default_value\[11\]
*68 gpio_default_value\[12\]
*69 gpio_default_value\[1\]
*70 gpio_default_value\[2\]
*71 gpio_default_value\[3\]
*72 gpio_default_value\[4\]
*73 gpio_default_value\[5\]
*74 gpio_default_value\[6\]
*75 gpio_default_value\[7\]
*76 gpio_default_value\[8\]
*77 gpio_default_value\[9\]
*PORTS
gpio_defaults[0] O
gpio_defaults[10] O
gpio_defaults[11] O
gpio_defaults[12] O
gpio_defaults[1] O
gpio_defaults[2] O
gpio_defaults[3] O
gpio_defaults[4] O
gpio_defaults[5] O
gpio_defaults[6] O
gpio_defaults[7] O
gpio_defaults[8] O
gpio_defaults[9] O
*D_NET *3 0.000662868
*CONN
*P gpio_defaults[0] O
*I *65:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[0] 0.000295589
2 *65:LO 0.000295589
3 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
*RES
1 *65:LO gpio_defaults[0] 21.1394
*END
*D_NET *4 0.000169932
*CONN
*P gpio_defaults[10] O
*I *66:HI O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[10] 8.49658e-05
2 *66:HI 8.49658e-05
3 gpio_defaults[10] gpio_defaults[11] 0
4 gpio_defaults[10] gpio_defaults[9] 0
*RES
1 *66:HI gpio_defaults[10] 15.7033
*END
*D_NET *5 0.000230895
*CONN
*P gpio_defaults[11] O
*I *67:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[11] 0.000115448
2 *67:LO 0.000115448
3 gpio_defaults[11] gpio_defaults[12] 0
4 gpio_defaults[10] gpio_defaults[11] 0
*RES
1 *67:LO gpio_defaults[11] 16.5338
*END
*D_NET *6 0.000822209
*CONN
*P gpio_defaults[12] O
*I *68:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[12] 0.000411104
2 *68:LO 0.000411104
3 gpio_defaults[11] gpio_defaults[12] 0
*RES
1 *68:LO gpio_defaults[12] 23.2185
*END
*D_NET *7 0.00071336
*CONN
*P gpio_defaults[1] O
*I *69:HI O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[1] 0.000307544
2 *69:HI 0.000307544
3 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
4 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
*RES
1 *69:HI gpio_defaults[1] 19.1997
*END
*D_NET *8 0.000464143
*CONN
*P gpio_defaults[2] O
*I *70:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[2] 0.00021878
2 *70:LO 0.00021878
3 gpio_defaults[2] gpio_defaults[3] 0
4 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
*RES
1 *70:LO gpio_defaults[2] 18.921
*END
*D_NET *9 0.000363376
*CONN
*P gpio_defaults[3] O
*I *71:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[3] 0.000181688
2 *71:LO 0.000181688
3 gpio_defaults[3] gpio_defaults[4] 0
4 gpio_defaults[2] gpio_defaults[3] 0
*RES
1 *71:LO gpio_defaults[3] 17.8118
*END
*D_NET *10 0.000236028
*CONN
*P gpio_defaults[4] O
*I *72:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[4] 0.000118014
2 *72:LO 0.000118014
3 gpio_defaults[4] gpio_defaults[5] 0
4 gpio_defaults[3] gpio_defaults[4] 0
*RES
1 *72:LO gpio_defaults[4] 16.5338
*END
*D_NET *11 0.000230895
*CONN
*P gpio_defaults[5] O
*I *73:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[5] 0.000115448
2 *73:LO 0.000115448
3 gpio_defaults[5] gpio_defaults[6] 0
4 gpio_defaults[4] gpio_defaults[5] 0
*RES
1 *73:LO gpio_defaults[5] 16.5338
*END
*D_NET *12 0.000230895
*CONN
*P gpio_defaults[6] O
*I *74:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[6] 0.000115448
2 *74:LO 0.000115448
3 gpio_defaults[6] gpio_defaults[7] 0
4 gpio_defaults[5] gpio_defaults[6] 0
*RES
1 *74:LO gpio_defaults[6] 16.5338
*END
*D_NET *13 0.00022764
*CONN
*P gpio_defaults[7] O
*I *75:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[7] 0.00011382
2 *75:LO 0.00011382
3 gpio_defaults[7] gpio_defaults[8] 0
4 gpio_defaults[6] gpio_defaults[7] 0
*RES
1 *75:LO gpio_defaults[7] 16.5338
*END
*D_NET *14 0.000224385
*CONN
*P gpio_defaults[8] O
*I *76:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[8] 0.000112192
2 *76:LO 0.000112192
3 gpio_defaults[8] gpio_defaults[9] 0
4 gpio_defaults[7] gpio_defaults[8] 0
*RES
1 *76:LO gpio_defaults[8] 16.5338
*END
*D_NET *15 0.00022764
*CONN
*P gpio_defaults[9] O
*I *77:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[9] 0.00011382
2 *77:LO 0.00011382
3 gpio_defaults[10] gpio_defaults[9] 0
4 gpio_defaults[8] gpio_defaults[9] 0
*RES
1 *77:LO gpio_defaults[9] 16.5338
*END

273
spef/gpio_defaults_block_0403.spef
View File

@ -1,273 +0,0 @@
*SPEF "ieee 1481-1999"
*DESIGN "gpio_defaults_block_0403"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*3 gpio_defaults_low\[0\]
*4 gpio_defaults_high\[10\]
*5 gpio_defaults_low\[11\]
*6 gpio_defaults_low\[12\]
*7 gpio_defaults_high\[1\]
*8 gpio_defaults_low\[2\]
*9 gpio_defaults_low\[3\]
*10 gpio_defaults_low\[4\]
*11 gpio_defaults_low\[5\]
*12 gpio_defaults_low\[6\]
*13 gpio_defaults_low\[7\]
*14 gpio_defaults_low\[8\]
*15 gpio_defaults_low\[9\]
*16 gpio_defaults_high\[0\]
*17 gpio_defaults_high\[11\]
*18 gpio_defaults_high\[12\]
*19 gpio_defaults_high\[2\]
*20 gpio_defaults_high\[3\]
*21 gpio_defaults_high\[4\]
*22 gpio_defaults_high\[5\]
*23 gpio_defaults_high\[6\]
*24 gpio_defaults_high\[7\]
*25 gpio_defaults_high\[8\]
*26 gpio_defaults_high\[9\]
*27 gpio_defaults_low\[10\]
*28 gpio_defaults_low\[1\]
*29 FILLER_0_29
*30 FILLER_0_3
*31 FILLER_0_33
*32 FILLER_0_38
*33 FILLER_0_43
*34 FILLER_0_48
*35 FILLER_0_55
*36 FILLER_0_60
*37 FILLER_0_9
*38 FILLER_1_15
*39 FILLER_1_27
*40 FILLER_1_3
*41 FILLER_1_39
*42 FILLER_1_51
*43 FILLER_1_55
*44 FILLER_1_57
*45 FILLER_1_61
*46 FILLER_2_15
*47 FILLER_2_27
*48 FILLER_2_29
*49 FILLER_2_3
*50 FILLER_2_41
*51 FILLER_2_53
*52 FILLER_2_57
*53 FILLER_2_61
*54 PHY_0
*55 PHY_1
*56 PHY_2
*57 PHY_3
*58 PHY_4
*59 PHY_5
*60 TAP_10
*61 TAP_6
*62 TAP_7
*63 TAP_8
*64 TAP_9
*65 gpio_default_value\[0\]
*66 gpio_default_value\[10\]
*67 gpio_default_value\[11\]
*68 gpio_default_value\[12\]
*69 gpio_default_value\[1\]
*70 gpio_default_value\[2\]
*71 gpio_default_value\[3\]
*72 gpio_default_value\[4\]
*73 gpio_default_value\[5\]
*74 gpio_default_value\[6\]
*75 gpio_default_value\[7\]
*76 gpio_default_value\[8\]
*77 gpio_default_value\[9\]
*PORTS
gpio_defaults[0] O
gpio_defaults[10] O
gpio_defaults[11] O
gpio_defaults[12] O
gpio_defaults[1] O
gpio_defaults[2] O
gpio_defaults[3] O
gpio_defaults[4] O
gpio_defaults[5] O
gpio_defaults[6] O
gpio_defaults[7] O
gpio_defaults[8] O
gpio_defaults[9] O
*D_NET *3 0.000662868
*CONN
*P gpio_defaults[0] O
*I *65:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[0] 0.000295589
2 *65:LO 0.000295589
3 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
*RES
1 *65:LO gpio_defaults[0] 21.1394
*END
*D_NET *4 0.000169932
*CONN
*P gpio_defaults[10] O
*I *66:HI O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[10] 8.49658e-05
2 *66:HI 8.49658e-05
3 gpio_defaults[10] gpio_defaults[11] 0
4 gpio_defaults[10] gpio_defaults[9] 0
*RES
1 *66:HI gpio_defaults[10] 15.7033
*END
*D_NET *5 0.000230895
*CONN
*P gpio_defaults[11] O
*I *67:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[11] 0.000115448
2 *67:LO 0.000115448
3 gpio_defaults[11] gpio_defaults[12] 0
4 gpio_defaults[10] gpio_defaults[11] 0
*RES
1 *67:LO gpio_defaults[11] 16.5338
*END
*D_NET *6 0.000822209
*CONN
*P gpio_defaults[12] O
*I *68:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[12] 0.000411104
2 *68:LO 0.000411104
3 gpio_defaults[11] gpio_defaults[12] 0
*RES
1 *68:LO gpio_defaults[12] 23.2185
*END
*D_NET *7 0.00071336
*CONN
*P gpio_defaults[1] O
*I *69:HI O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[1] 0.000307544
2 *69:HI 0.000307544
3 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
4 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
*RES
1 *69:HI gpio_defaults[1] 19.1997
*END
*D_NET *8 0.000464143
*CONN
*P gpio_defaults[2] O
*I *70:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[2] 0.00021878
2 *70:LO 0.00021878
3 gpio_defaults[2] gpio_defaults[3] 0
4 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
*RES
1 *70:LO gpio_defaults[2] 18.921
*END
*D_NET *9 0.000363376
*CONN
*P gpio_defaults[3] O
*I *71:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[3] 0.000181688
2 *71:LO 0.000181688
3 gpio_defaults[3] gpio_defaults[4] 0
4 gpio_defaults[2] gpio_defaults[3] 0
*RES
1 *71:LO gpio_defaults[3] 17.8118
*END
*D_NET *10 0.000236028
*CONN
*P gpio_defaults[4] O
*I *72:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[4] 0.000118014
2 *72:LO 0.000118014
3 gpio_defaults[4] gpio_defaults[5] 0
4 gpio_defaults[3] gpio_defaults[4] 0
*RES
1 *72:LO gpio_defaults[4] 16.5338
*END
*D_NET *11 0.000230895
*CONN
*P gpio_defaults[5] O
*I *73:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[5] 0.000115448
2 *73:LO 0.000115448
3 gpio_defaults[5] gpio_defaults[6] 0
4 gpio_defaults[4] gpio_defaults[5] 0
*RES
1 *73:LO gpio_defaults[5] 16.5338
*END
*D_NET *12 0.000230895
*CONN
*P gpio_defaults[6] O
*I *74:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[6] 0.000115448
2 *74:LO 0.000115448
3 gpio_defaults[6] gpio_defaults[7] 0
4 gpio_defaults[5] gpio_defaults[6] 0
*RES
1 *74:LO gpio_defaults[6] 16.5338
*END
*D_NET *13 0.00022764
*CONN
*P gpio_defaults[7] O
*I *75:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[7] 0.00011382
2 *75:LO 0.00011382
3 gpio_defaults[7] gpio_defaults[8] 0
4 gpio_defaults[6] gpio_defaults[7] 0
*RES
1 *75:LO gpio_defaults[7] 16.5338
*END
*D_NET *14 0.000224385
*CONN
*P gpio_defaults[8] O
*I *76:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[8] 0.000112192
2 *76:LO 0.000112192
3 gpio_defaults[8] gpio_defaults[9] 0
4 gpio_defaults[7] gpio_defaults[8] 0
*RES
1 *76:LO gpio_defaults[8] 16.5338
*END
*D_NET *15 0.00022764
*CONN
*P gpio_defaults[9] O
*I *77:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[9] 0.00011382
2 *77:LO 0.00011382
3 gpio_defaults[10] gpio_defaults[9] 0
4 gpio_defaults[8] gpio_defaults[9] 0
*RES
1 *77:LO gpio_defaults[9] 16.5338
*END

273
spef/gpio_defaults_block_1803.spef
View File

@ -1,273 +0,0 @@
*SPEF "ieee 1481-1999"
*DESIGN "gpio_defaults_block_1803"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*3 gpio_defaults_low\[0\]
*4 gpio_defaults_high\[10\]
*5 gpio_defaults_low\[11\]
*6 gpio_defaults_low\[12\]
*7 gpio_defaults_high\[1\]
*8 gpio_defaults_low\[2\]
*9 gpio_defaults_low\[3\]
*10 gpio_defaults_low\[4\]
*11 gpio_defaults_low\[5\]
*12 gpio_defaults_low\[6\]
*13 gpio_defaults_low\[7\]
*14 gpio_defaults_low\[8\]
*15 gpio_defaults_low\[9\]
*16 gpio_defaults_high\[0\]
*17 gpio_defaults_high\[11\]
*18 gpio_defaults_high\[12\]
*19 gpio_defaults_high\[2\]
*20 gpio_defaults_high\[3\]
*21 gpio_defaults_high\[4\]
*22 gpio_defaults_high\[5\]
*23 gpio_defaults_high\[6\]
*24 gpio_defaults_high\[7\]
*25 gpio_defaults_high\[8\]
*26 gpio_defaults_high\[9\]
*27 gpio_defaults_low\[10\]
*28 gpio_defaults_low\[1\]
*29 FILLER_0_29
*30 FILLER_0_3
*31 FILLER_0_33
*32 FILLER_0_38
*33 FILLER_0_43
*34 FILLER_0_48
*35 FILLER_0_55
*36 FILLER_0_60
*37 FILLER_0_9
*38 FILLER_1_15
*39 FILLER_1_27
*40 FILLER_1_3
*41 FILLER_1_39
*42 FILLER_1_51
*43 FILLER_1_55
*44 FILLER_1_57
*45 FILLER_1_61
*46 FILLER_2_15
*47 FILLER_2_27
*48 FILLER_2_29
*49 FILLER_2_3
*50 FILLER_2_41
*51 FILLER_2_53
*52 FILLER_2_57
*53 FILLER_2_61
*54 PHY_0
*55 PHY_1
*56 PHY_2
*57 PHY_3
*58 PHY_4
*59 PHY_5
*60 TAP_10
*61 TAP_6
*62 TAP_7
*63 TAP_8
*64 TAP_9
*65 gpio_default_value\[0\]
*66 gpio_default_value\[10\]
*67 gpio_default_value\[11\]
*68 gpio_default_value\[12\]
*69 gpio_default_value\[1\]
*70 gpio_default_value\[2\]
*71 gpio_default_value\[3\]
*72 gpio_default_value\[4\]
*73 gpio_default_value\[5\]
*74 gpio_default_value\[6\]
*75 gpio_default_value\[7\]
*76 gpio_default_value\[8\]
*77 gpio_default_value\[9\]
*PORTS
gpio_defaults[0] O
gpio_defaults[10] O
gpio_defaults[11] O
gpio_defaults[12] O
gpio_defaults[1] O
gpio_defaults[2] O
gpio_defaults[3] O
gpio_defaults[4] O
gpio_defaults[5] O
gpio_defaults[6] O
gpio_defaults[7] O
gpio_defaults[8] O
gpio_defaults[9] O
*D_NET *3 0.000662868
*CONN
*P gpio_defaults[0] O
*I *65:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[0] 0.000295589
2 *65:LO 0.000295589
3 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
*RES
1 *65:LO gpio_defaults[0] 21.1394
*END
*D_NET *4 0.000169932
*CONN
*P gpio_defaults[10] O
*I *66:HI O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[10] 8.49658e-05
2 *66:HI 8.49658e-05
3 gpio_defaults[10] gpio_defaults[11] 0
4 gpio_defaults[10] gpio_defaults[9] 0
*RES
1 *66:HI gpio_defaults[10] 15.7033
*END
*D_NET *5 0.000230895
*CONN
*P gpio_defaults[11] O
*I *67:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[11] 0.000115448
2 *67:LO 0.000115448
3 gpio_defaults[11] gpio_defaults[12] 0
4 gpio_defaults[10] gpio_defaults[11] 0
*RES
1 *67:LO gpio_defaults[11] 16.5338
*END
*D_NET *6 0.000822209
*CONN
*P gpio_defaults[12] O
*I *68:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[12] 0.000411104
2 *68:LO 0.000411104
3 gpio_defaults[11] gpio_defaults[12] 0
*RES
1 *68:LO gpio_defaults[12] 23.2185
*END
*D_NET *7 0.00071336
*CONN
*P gpio_defaults[1] O
*I *69:HI O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[1] 0.000307544
2 *69:HI 0.000307544
3 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
4 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
*RES
1 *69:HI gpio_defaults[1] 19.1997
*END
*D_NET *8 0.000464143
*CONN
*P gpio_defaults[2] O
*I *70:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[2] 0.00021878
2 *70:LO 0.00021878
3 gpio_defaults[2] gpio_defaults[3] 0
4 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
*RES
1 *70:LO gpio_defaults[2] 18.921
*END
*D_NET *9 0.000363376
*CONN
*P gpio_defaults[3] O
*I *71:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[3] 0.000181688
2 *71:LO 0.000181688
3 gpio_defaults[3] gpio_defaults[4] 0
4 gpio_defaults[2] gpio_defaults[3] 0
*RES
1 *71:LO gpio_defaults[3] 17.8118
*END
*D_NET *10 0.000236028
*CONN
*P gpio_defaults[4] O
*I *72:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[4] 0.000118014
2 *72:LO 0.000118014
3 gpio_defaults[4] gpio_defaults[5] 0
4 gpio_defaults[3] gpio_defaults[4] 0
*RES
1 *72:LO gpio_defaults[4] 16.5338
*END
*D_NET *11 0.000230895
*CONN
*P gpio_defaults[5] O
*I *73:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[5] 0.000115448
2 *73:LO 0.000115448
3 gpio_defaults[5] gpio_defaults[6] 0
4 gpio_defaults[4] gpio_defaults[5] 0
*RES
1 *73:LO gpio_defaults[5] 16.5338
*END
*D_NET *12 0.000230895
*CONN
*P gpio_defaults[6] O
*I *74:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[6] 0.000115448
2 *74:LO 0.000115448
3 gpio_defaults[6] gpio_defaults[7] 0
4 gpio_defaults[5] gpio_defaults[6] 0
*RES
1 *74:LO gpio_defaults[6] 16.5338
*END
*D_NET *13 0.00022764
*CONN
*P gpio_defaults[7] O
*I *75:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[7] 0.00011382
2 *75:LO 0.00011382
3 gpio_defaults[7] gpio_defaults[8] 0
4 gpio_defaults[6] gpio_defaults[7] 0
*RES
1 *75:LO gpio_defaults[7] 16.5338
*END
*D_NET *14 0.000224385
*CONN
*P gpio_defaults[8] O
*I *76:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[8] 0.000112192
2 *76:LO 0.000112192
3 gpio_defaults[8] gpio_defaults[9] 0
4 gpio_defaults[7] gpio_defaults[8] 0
*RES
1 *76:LO gpio_defaults[8] 16.5338
*END
*D_NET *15 0.00022764
*CONN
*P gpio_defaults[9] O
*I *77:LO O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_defaults[9] 0.00011382
2 *77:LO 0.00011382
3 gpio_defaults[10] gpio_defaults[9] 0
4 gpio_defaults[8] gpio_defaults[9] 0
*RES
1 *77:LO gpio_defaults[9] 16.5338
*END

57
spef/gpio_logic_high.spef
View File

@ -1,57 +0,0 @@
*SPEF "ieee 1481-1999"
*DESIGN "gpio_logic_high"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*1 gpio_logic1
*2 FILLER_0_3
*3 FILLER_0_7
*4 FILLER_0_9
*5 FILLER_1_11
*6 FILLER_1_3
*7 FILLER_2_3
*8 FILLER_2_7
*9 FILLER_2_9
*10 FILLER_3_3
*11 FILLER_4_3
*12 FILLER_4_7
*13 FILLER_4_9
*14 PHY_0
*15 PHY_1
*16 PHY_2
*17 PHY_3
*18 PHY_4
*19 PHY_5
*20 PHY_6
*21 PHY_7
*22 PHY_8
*23 PHY_9
*24 TAP_10
*25 TAP_11
*26 TAP_12
*27 gpio_logic_high
*PORTS
gpio_logic1 O
*D_NET *1 0.000513616
*CONN
*P gpio_logic1 O
*I *27:HI O *D sky130_fd_sc_hd__conb_1
*CAP
1 gpio_logic1 0.000256808
2 *27:HI 0.000256808
*RES
1 *27:HI gpio_logic1 21.9631
*END

372624
spef/housekeeping.spef
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File diff suppressed because it is too large Load Diff

204
spef/mgmt_protect_hv.spef
View File

@ -1,204 +0,0 @@
*SPEF "ieee 1481-1999"
*DESIGN "mgmt_protect_hv"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*1 mprj2_vdd_logic1
*2 mprj_vdd_logic1
*9 mprj2_vdd_logic1_h
*10 mprj_vdd_logic1_h
*11 mprj2_logic_high_hvl
*12 mprj2_logic_high_lv
*13 mprj_logic_high_hvl
*14 mprj_logic_high_lv
*15 FILLER_0_0
*16 FILLER_0_8
*17 FILLER_0_16
*18 FILLER_0_24
*19 FILLER_0_32
*20 FILLER_0_40
*21 FILLER_0_48
*22 FILLER_0_56
*23 FILLER_0_64
*24 FILLER_0_72
*25 FILLER_0_80
*26 FILLER_0_88
*27 FILLER_0_96
*28 FILLER_0_104
*29 FILLER_0_112
*30 FILLER_0_120
*31 FILLER_0_128
*32 FILLER_0_136
*33 FILLER_0_144
*34 FILLER_0_152
*35 FILLER_0_160
*36 FILLER_0_168
*37 FILLER_0_176
*38 FILLER_0_184
*39 FILLER_0_192
*40 FILLER_0_200
*41 FILLER_0_208
*42 FILLER_0_216
*43 FILLER_0_224
*44 FILLER_0_232
*45 FILLER_0_240
*46 FILLER_0_248
*47 FILLER_0_256
*48 FILLER_0_264
*49 FILLER_0_272
*50 FILLER_0_280
*51 FILLER_0_288
*52 FILLER_0_296
*53 FILLER_0_300
*54 FILLER_1_0
*55 FILLER_1_8
*56 FILLER_1_16
*57 FILLER_1_24
*58 FILLER_1_32
*59 FILLER_1_40
*60 FILLER_1_48
*61 FILLER_1_56
*62 FILLER_1_64
*63 FILLER_1_72
*64 FILLER_1_80
*65 FILLER_1_88
*66 FILLER_1_92
*67 FILLER_1_94
*68 FILLER_1_117
*69 FILLER_1_125
*70 FILLER_1_133
*71 FILLER_1_141
*72 FILLER_1_149
*73 FILLER_1_157
*74 FILLER_1_165
*75 FILLER_1_189
*76 FILLER_1_197
*77 FILLER_1_205
*78 FILLER_1_213
*79 FILLER_1_221
*80 FILLER_1_229
*81 FILLER_1_237
*82 FILLER_1_245
*83 FILLER_1_253
*84 FILLER_1_261
*85 FILLER_1_269
*86 FILLER_1_277
*87 FILLER_1_285
*88 FILLER_1_293
*89 FILLER_1_301
*90 FILLER_2_0
*91 FILLER_2_8
*92 FILLER_2_16
*93 FILLER_2_24
*94 FILLER_2_32
*95 FILLER_2_40
*96 FILLER_2_48
*97 FILLER_2_56
*98 FILLER_2_64
*99 FILLER_2_72
*100 FILLER_2_80
*101 FILLER_2_88
*102 FILLER_2_96
*103 FILLER_2_117
*104 FILLER_2_125
*105 FILLER_2_133
*106 FILLER_2_141
*107 FILLER_2_149
*108 FILLER_2_157
*109 FILLER_2_165
*110 FILLER_2_169
*111 FILLER_2_171
*112 FILLER_2_189
*113 FILLER_2_197
*114 FILLER_2_205
*115 FILLER_2_213
*116 FILLER_2_221
*117 FILLER_2_229
*118 FILLER_2_237
*119 FILLER_2_245
*120 FILLER_2_253
*121 FILLER_2_261
*122 FILLER_2_269
*123 FILLER_2_277
*124 FILLER_2_285
*125 FILLER_2_293
*126 FILLER_2_301
*PORTS
mprj2_vdd_logic1 O
mprj_vdd_logic1 O
*D_NET *1 0.00894054
*CONN
*P mprj2_vdd_logic1 O
*I *12:X O *D sky130_fd_sc_hvl__lsbufhv2lv_1
*CAP
1 mprj2_vdd_logic1 0.000164685
2 *12:X 0.000136495
3 *1:9 0.00433377
4 *1:8 0.00430558
5 *1:9 *2:5 0
*RES
1 *12:X *1:8 21.1315
2 *1:8 *1:9 104.917
3 *1:9 mprj2_vdd_logic1 10.6698
*END
*D_NET *2 0.005901
*CONN
*P mprj_vdd_logic1 O
*I *14:X O *D sky130_fd_sc_hvl__lsbufhv2lv_1
*CAP
1 mprj_vdd_logic1 0.000279428
2 *14:X 0
3 *2:5 0.00291451
4 *2:4 0.00263509
5 *2:5 *9:7 7.19686e-05
6 *1:9 *2:5 0
*RES
1 *14:X *2:4 9.24915
2 *2:4 *2:5 63.2489
3 *2:5 mprj_vdd_logic1 14.285
*END
*D_NET *9 0.00401189
*CONN
*I *12:A I *D sky130_fd_sc_hvl__lsbufhv2lv_1
*I *11:HI O *D sky130_fd_sc_hvl__conb_1
*CAP
1 *12:A 0.000185088
2 *11:HI 0
3 *9:7 0.00194467
4 *9:4 0.00175958
5 *12:A *10:8 5.05783e-05
6 *2:5 *9:7 7.19686e-05
*RES
1 *11:HI *9:4 9.24915
2 *9:4 *9:7 47.4938
3 *9:7 *12:A 17.9577
*END
*D_NET *10 0.00370034
*CONN
*I *14:A I *D sky130_fd_sc_hvl__lsbufhv2lv_1
*I *13:HI O *D sky130_fd_sc_hvl__conb_1
*CAP
1 *14:A 0.00172779
2 *13:HI 9.70922e-05
3 *10:8 0.00182488
4 *12:A *10:8 5.05783e-05
*RES
1 *13:HI *10:8 20.6796
2 *10:8 *14:A 48.192
*END

100
spef/mprj2_logic_high.spef
View File

@ -1,100 +0,0 @@
*SPEF "ieee 1481-1999"
*DESIGN "mprj2_logic_high"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*1 HI
*2 FILLER_0_109
*3 FILLER_0_113
*4 FILLER_0_125
*5 FILLER_0_137
*6 FILLER_0_141
*7 FILLER_0_15
*8 FILLER_0_153
*9 FILLER_0_165
*10 FILLER_0_169
*11 FILLER_0_181
*12 FILLER_0_193
*13 FILLER_0_197
*14 FILLER_0_209
*15 FILLER_0_213
*16 FILLER_0_27
*17 FILLER_0_29
*18 FILLER_0_3
*19 FILLER_0_41
*20 FILLER_0_53
*21 FILLER_0_57
*22 FILLER_0_69
*23 FILLER_0_81
*24 FILLER_0_85
*25 FILLER_0_97
*26 FILLER_1_107
*27 FILLER_1_111
*28 FILLER_1_113
*29 FILLER_1_125
*30 FILLER_1_137
*31 FILLER_1_141
*32 FILLER_1_15
*33 FILLER_1_153
*34 FILLER_1_165
*35 FILLER_1_169
*36 FILLER_1_181
*37 FILLER_1_193
*38 FILLER_1_197
*39 FILLER_1_209
*40 FILLER_1_213
*41 FILLER_1_27
*42 FILLER_1_29
*43 FILLER_1_3
*44 FILLER_1_41
*45 FILLER_1_53
*46 FILLER_1_57
*47 FILLER_1_69
*48 FILLER_1_81
*49 FILLER_1_85
*50 FILLER_1_91
*51 FILLER_1_95
*52 PHY_0
*53 PHY_1
*54 PHY_2
*55 PHY_3
*56 TAP_10
*57 TAP_11
*58 TAP_12
*59 TAP_13
*60 TAP_14
*61 TAP_15
*62 TAP_16
*63 TAP_17
*64 TAP_4
*65 TAP_5
*66 TAP_6
*67 TAP_7
*68 TAP_8
*69 TAP_9
*70 inst
*PORTS
HI O
*D_NET *1 0.00667596
*CONN
*P HI O
*I *70:HI O *D sky130_fd_sc_hd__conb_1
*CAP
1 HI 0.00333798
2 *70:HI 0.00333798
*RES
1 *70:HI HI 24.0614
*END

8669
spef/mprj_logic_high.spef
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File diff suppressed because it is too large Load Diff

1192
spef/spare_logic_block.spef
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File diff suppressed because it is too large Load Diff

65
spef/xres_buf.spef
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@ -1,65 +0,0 @@
*SPEF "ieee 1481-1999"
*DESIGN "xres_buf"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*1 A
*2 X
*3 lvlshiftdown
*4 ANTENNA_lvlshiftdown_A
*5 FILLER_0_0
*6 FILLER_0_8
*7 FILLER_0_16
*8 FILLER_0_24
*9 FILLER_0_28
*10 FILLER_0_30
*11 FILLER_1_0
*12 FILLER_1_8
*13 FILLER_1_12
*14 FILLER_1_30
*15 FILLER_2_0
*16 FILLER_2_8
*17 FILLER_2_10
*18 FILLER_2_30
*PORTS
A I
X O
*D_NET *1 0.000990495
*CONN
*P A I
*I *3:A I *D sky130_fd_sc_hvl__lsbufhv2lv_1
*I *4:DIODE I *D sky130_fd_sc_hvl__diode_2
*CAP
1 A 0.000411399
2 *3:A 0
3 *4:DIODE 8.38483e-05
4 *1:12 0.000495247
*RES
1 A *1:12 14.3355
2 *1:12 *4:DIODE 11.1541
3 *1:12 *3:A 9.24915
*END
*D_NET *2 0.00147572
*CONN
*P X O
*I *3:X O *D sky130_fd_sc_hvl__lsbufhv2lv_1
*CAP
1 X 0.00073786
2 *3:X 0.00073786
*RES
1 *3:X X 32.9072
*END