mirror of https://github.com/efabless/caravel.git
Merge branch 'caravel_redesign' of github.com:efabless/caravel into caravel_redesign
This commit is contained in:
Marwan Abbas
commit
458aaefc73
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@ -1,115 +0,0 @@
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### Caravel Signoff SDC
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||||
### Rev 1
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### Date: 5/10/2022
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||||
## MASTER CLOCKS
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create_clock -name clk -period 25 [get_ports {clock}]
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||||
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||||
create_clock -name hkspi_clk -period 100 [get_pins {housekeeping/mgmt_gpio_in[4]} ]
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create_clock -name hk_serial_clk -period 1000 [get_pins {housekeeping/serial_clock}]
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||||
create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
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set_clock_groups \
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-name clock_group \
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-logically_exclusive \
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-group [get_clocks {clk}]\
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-group [get_clocks {hk_serial_clk}]\
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-group [get_clocks {hk_serial_load}]\
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-group [get_clocks {hkspi_clk}]
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# clock <-> hk_serial_clk/load no paths
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# future note: CDC stuff
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# clock <-> hkspi_clk no paths with careful methods (clock is off)
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set_propagated_clock [get_clocks {clk}]
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set_propagated_clock [get_clocks {hk_serial_clk}]
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set_propagated_clock [get_clocks {hk_serial_load}]
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set_propagated_clock [get_clocks {hkspi_clk}]
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## INPUT/OUTPUT DELAYS
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set input_delay_value 4
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set output_delay_value 4
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puts "\[INFO\]: Setting output delay to: $output_delay_value"
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puts "\[INFO\]: Setting input delay to: $input_delay_value"
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {gpio}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[0]}]
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#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[1]}]
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set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[2]}]
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set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[3]}]
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#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[4]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[5]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[6]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[7]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[8]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[9]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[10]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[11]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[12]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[13]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[14]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[15]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[16]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[17]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[18]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[19]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[20]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[21]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[22]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[23]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[24]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[25]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[26]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[27]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[28]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[29]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[30]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[31]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[32]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[33]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[34]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[35]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[36]}]
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set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[37]}]
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set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_csb}]
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set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_clk}]
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set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0}]
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set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1}]
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# set_output_delay $output_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[1]}]
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set_max_fanout 12 [current_design]
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# synthesis max fanout should be less than 12 (7 maybe)
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## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
|
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set_case_analysis 0 [get_pins housekeeping/_5201_/S]
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set_case_analysis 0 [get_pins housekeeping/_5203_/S]
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# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0
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||||
|
||||
set_case_analysis 1 [get_pins padframe/*_pad/DM[2]]
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set_case_analysis 1 [get_pins padframe/*_pad/DM[1]]
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||||
set_case_analysis 0 [get_pins padframe/*_pad/DM[0]]
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set_case_analysis 0 [get_pins padframe/clock_pad/DM[2]]
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set_case_analysis 0 [get_pins padframe/clock_pad/DM[1]]
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set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]]
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## FALSE PATHS (ASYNCHRONOUS INPUTS)
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||||
set_false_path -from [get_ports {resetb}]
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||||
set_false_path -from [get_ports mprj_io[*]]
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set_false_path -from [get_ports gpio]
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#set_false_path -through [get_nets mprj_io_inp_dis[*]]
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||||
# set_timing_derate -early 1
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# set_timing_derate -late 1
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# TODO set this as parameter
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set cap_load 10
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puts "\[INFO\]: Setting load to: $cap_load"
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set_load $cap_load [all_outputs]
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|
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@ -1,111 +0,0 @@
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### GPIO Control Block Signoff SDC
|
||||
### Rev 1
|
||||
### Date: 5/10/2022
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||||
|
||||
###############################################################################
|
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# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name serial_clock -period 50.0000 [get_ports {serial_clock}]
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||||
set_clock_transition 0.1500 [get_clocks {serial_clock}]
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set_clock_uncertainty 0.1000 serial_clock
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||||
set_propagated_clock [get_clocks {serial_clock}]
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create_clock -name serial_load -period 50.0000 [get_ports {serial_load}]
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set_clock_transition 0.1500 [get_clocks {serial_load}]
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set_clock_uncertainty 0.1000 serial_load
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set_propagated_clock [get_clocks {serial_load}]
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|
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set input_delay 5
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set output_delay 5
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|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[0]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[10]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[11]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[12]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[1]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[2]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[3]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[4]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[5]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[6]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[7]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[8]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[9]}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_oeb}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_out}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_in}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_in}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_oeb}]
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set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_out}]
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||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_in}]
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set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {one}]
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||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_en}]
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||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_pol}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_sel}]
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||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[0]}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[1]}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[2]}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_holdover}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_inenb}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_outenb}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_slow_sel}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_clock_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_in}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {zero}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_in}]
|
||||
set_load -pin_load 0.2100 [get_ports {one}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_ana_en}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_ana_pol}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_ana_sel}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_holdover}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_inenb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_out}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_outenb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_slow_sel}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_load -pin_load 0.2100 [get_ports {resetn_out}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_clock_out}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_data_out}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_load_out}]
|
||||
set_load -pin_load 0.2100 [get_ports {user_gpio_in}]
|
||||
set_load -pin_load 0.2100 [get_ports {zero}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_dm[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_dm[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_dm[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pad_gpio_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetn}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_clock}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_data_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_load}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[0]}]
|
||||
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_transition 1 [current_design]
|
||||
set_max_fanout 7.0000 [current_design]
|
||||
167
sdc/caravel.sdc
167
sdc/caravel.sdc
|
|
@ -1,87 +1,120 @@
|
|||
set ::env(IO_PCT) "0.2"
|
||||
set ::env(SYNTH_MAX_FANOUT) "5"
|
||||
set ::env(SYNTH_CAP_LOAD) "33"
|
||||
set ::env(SYNTH_TIMING_DERATE) 0.05
|
||||
set ::env(SYNTH_CLOCK_UNCERTAINITY) 0.25
|
||||
set ::env(SYNTH_CLOCK_TRANSITION) 0.15
|
||||
### Caravel Signoff SDC
|
||||
### Rev 1
|
||||
### Date: 5/10/2022
|
||||
|
||||
## MASTER CLOCKS
|
||||
create_clock [get_ports {"clock"} ] -name "clock" -period 25
|
||||
set_propagated_clock [get_clocks {"clock"}]
|
||||
create_clock -name clk -period 25 [get_ports {clock}]
|
||||
|
||||
create_clock -name hkspi_clk -period 100 [get_pins {housekeeping/mgmt_gpio_in[4]} ]
|
||||
create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock}]
|
||||
create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
|
||||
# hk_serial_clk period is x2 core clock
|
||||
|
||||
set_clock_groups \
|
||||
-name clock_group \
|
||||
-logically_exclusive \
|
||||
-group [get_clocks {clk}]\
|
||||
-group [get_clocks {hk_serial_clk}]\
|
||||
-group [get_clocks {hk_serial_load}]\
|
||||
-group [get_clocks {hkspi_clk}]
|
||||
|
||||
# clock <-> hk_serial_clk/load no paths
|
||||
# future note: CDC stuff
|
||||
# clock <-> hkspi_clk no paths with careful methods (clock is off)
|
||||
|
||||
set_propagated_clock [get_clocks {clk}]
|
||||
set_propagated_clock [get_clocks {hk_serial_clk}]
|
||||
set_propagated_clock [get_clocks {hk_serial_load}]
|
||||
set_propagated_clock [get_clocks {hkspi_clk}]
|
||||
|
||||
## INPUT/OUTPUT DELAYS
|
||||
set input_delay_value 1
|
||||
set output_delay_value [expr 25 * $::env(IO_PCT)]
|
||||
set input_delay_value 4
|
||||
set output_delay_value 4
|
||||
puts "\[INFO\]: Setting output delay to: $output_delay_value"
|
||||
puts "\[INFO\]: Setting input delay to: $input_delay_value"
|
||||
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {gpio}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[0]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[1]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[2]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[3]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[4]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[5]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[6]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[7]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[8]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[9]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[10]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[11]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[12]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[13]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[14]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[15]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[16]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[17]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[18]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[19]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[20]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[21]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[22]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[23]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[25]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[26]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[27]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[28]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[33]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[34]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[35]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[36]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[37]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {gpio}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[0]}]
|
||||
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_csb}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_clk}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}]
|
||||
#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[1]}]
|
||||
|
||||
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[2]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[3]}]
|
||||
|
||||
#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[4]}]
|
||||
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[5]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[6]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[7]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[8]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[9]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[10]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[11]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[12]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[13]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[14]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[15]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[16]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[17]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[18]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[19]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[20]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[21]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[22]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[23]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[24]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[25]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[26]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[27]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[28]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[29]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[30]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[31]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[32]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[33]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[34]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[35]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[36]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[37]}]
|
||||
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_csb}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_clk}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1}]
|
||||
|
||||
# set_output_delay $output_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[1]}]
|
||||
|
||||
set_max_fanout 12 [current_design]
|
||||
# synthesis max fanout should be less than 12 (7 maybe)
|
||||
|
||||
## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
|
||||
set_case_analysis 0 [get_pins housekeeping/_4449_/S]
|
||||
set_case_analysis 0 [get_pins housekeeping/_4450_/S]
|
||||
set_case_analysis 0 [get_pins housekeeping/_3948_/S]
|
||||
set_case_analysis 0 [get_pins housekeeping/_3949_/S]
|
||||
|
||||
# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0
|
||||
|
||||
set_case_analysis 1 [get_pins padframe/*_pad/DM[2]]
|
||||
set_case_analysis 1 [get_pins padframe/*_pad/DM[1]]
|
||||
set_case_analysis 0 [get_pins padframe/*_pad/DM[0]]
|
||||
set_case_analysis 0 [get_pins padframe/*_pad/SLOW]
|
||||
set_case_analysis 0 [get_pins padframe/*_pad/ANALOG_EN]
|
||||
|
||||
set_case_analysis 0 [get_pins padframe/clock_pad/DM[2]]
|
||||
set_case_analysis 0 [get_pins padframe/clock_pad/DM[1]]
|
||||
set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]]
|
||||
|
||||
## FALSE PATHS (ASYNCHRONOUS INPUTS)
|
||||
set_false_path -from [get_ports {resetb}]
|
||||
set_false_path -from [get_ports mprj_io[*]]
|
||||
set_false_path -from [get_ports gpio]
|
||||
#set_false_path -through [get_nets mprj_io_inp_dis[*]]
|
||||
# set_timing_derate -early 1
|
||||
# set_timing_derate -late 1
|
||||
|
||||
# TODO set this as parameter
|
||||
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
|
||||
set cap_load 10
|
||||
puts "\[INFO\]: Setting load to: $cap_load"
|
||||
set_load $cap_load [all_outputs]
|
||||
set_load $cap_load [all_outputs]
|
||||
|
||||
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
|
||||
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
|
||||
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
|
||||
|
||||
puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
|
||||
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {clock}]
|
||||
|
||||
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
|
||||
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clock}]
|
||||
#add input transition for the inputs pins
|
||||
set_input_transition 2 [all_inputs]
|
||||
|
|
|
|||
|
|
@ -1,109 +1,111 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Sun Oct 9 23:50:57 2022
|
||||
###############################################################################
|
||||
current_design gpio_control_block
|
||||
### GPIO Control Block Signoff SDC
|
||||
### Rev 1
|
||||
### Date: 5/10/2022
|
||||
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name serial_clock -period 50.0000 [get_ports {serial_clock}]
|
||||
set_clock_transition 0.1500 [get_clocks {serial_clock}]
|
||||
set_clock_uncertainty 0.4000 serial_clock
|
||||
set_clock_uncertainty 0.1000 serial_clock
|
||||
set_propagated_clock [get_clocks {serial_clock}]
|
||||
create_clock -name serial_load -period 50.0000 [get_ports {serial_load}]
|
||||
set_clock_transition 0.1500 [get_clocks {serial_load}]
|
||||
set_clock_uncertainty 0.4000 serial_load
|
||||
set_clock_uncertainty 0.1000 serial_load
|
||||
set_propagated_clock [get_clocks {serial_load}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_out}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_in}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_in}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {one}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_en}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_pol}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_holdover}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_inenb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_outenb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_slow_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_clock_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {zero}]
|
||||
|
||||
set input_delay 5
|
||||
set output_delay 5
|
||||
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[0]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[10]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[11]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[12]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[1]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[2]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[3]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[4]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[5]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[6]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[7]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[8]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[9]}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_oeb}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_out}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_in}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_in}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_oeb}]
|
||||
set_input_delay $input_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_in}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {one}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_en}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_pol}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_sel}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[0]}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[1]}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[2]}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_holdover}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_inenb}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_outenb}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_slow_sel}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_clock_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load_out}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_in}]
|
||||
set_output_delay $output_delay -clock [get_clocks {serial_clock}] -add_delay [get_ports {zero}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.2500 [get_ports {mgmt_gpio_in}]
|
||||
set_load -pin_load 0.2500 [get_ports {one}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_en}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_pol}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_holdover}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_inenb}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_outenb}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_slow_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {resetn_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {serial_clock_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {serial_data_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {serial_load_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {user_gpio_in}]
|
||||
set_load -pin_load 0.2500 [get_ports {zero}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[2]}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[1]}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[0]}]
|
||||
set_input_transition 5.0000 [get_ports {mgmt_gpio_oeb}]
|
||||
set_input_transition 5.0000 [get_ports {mgmt_gpio_out}]
|
||||
set_input_transition 5.0000 [get_ports {pad_gpio_in}]
|
||||
set_input_transition 5.0000 [get_ports {resetn}]
|
||||
set_input_transition 5.0000 [get_ports {serial_clock}]
|
||||
set_input_transition 5.0000 [get_ports {serial_data_in}]
|
||||
set_input_transition 5.0000 [get_ports {serial_load}]
|
||||
set_input_transition 5.0000 [get_ports {user_gpio_oeb}]
|
||||
set_input_transition 5.0000 [get_ports {user_gpio_out}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[12]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[11]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[10]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[9]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[8]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[7]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[6]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[5]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[4]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[3]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[2]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[1]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_in}]
|
||||
set_load -pin_load 0.2100 [get_ports {one}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_ana_en}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_ana_pol}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_ana_sel}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_holdover}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_inenb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_out}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_outenb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_slow_sel}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_load -pin_load 0.2100 [get_ports {resetn_out}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_clock_out}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_data_out}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_load_out}]
|
||||
set_load -pin_load 0.2100 [get_ports {user_gpio_in}]
|
||||
set_load -pin_load 0.2100 [get_ports {zero}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_dm[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_dm[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_gpio_dm[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pad_gpio_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetn}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_clock}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_data_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_load}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[0]}]
|
||||
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_transition 1.2500 [current_design]
|
||||
set_max_transition 0.75 [current_design]
|
||||
set_max_fanout 7.0000 [current_design]
|
||||
|
|
|
|||
|
|
@ -1,381 +1,382 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Tue Oct 11 23:00:28 2022
|
||||
###############################################################################
|
||||
current_design housekeeping
|
||||
### Housekeeping Signoff SDC
|
||||
### Rev 1
|
||||
### Date: 5/10/2022
|
||||
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name wb_clk_i -period 25.0000 [get_ports {wb_clk_i}]
|
||||
set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
|
||||
set_clock_uncertainty 0.3000 wb_clk_i
|
||||
set_clock_transition 0.0100 [get_clocks {wb_clk_i}]
|
||||
set_clock_uncertainty 0.1000 wb_clk_i
|
||||
set_propagated_clock [get_clocks {wb_clk_i}]
|
||||
create_clock -name user_clock -period 25.0000 [get_ports {user_clock}]
|
||||
set_clock_transition 0.1500 [get_clocks {user_clock}]
|
||||
set_clock_uncertainty 0.3000 user_clock
|
||||
set_clock_transition 0.0100 [get_clocks {user_clock}]
|
||||
set_clock_uncertainty 0.1000 user_clock
|
||||
set_propagated_clock [get_clocks {user_clock}]
|
||||
create_clock -name sck -period 100.0000 [get_ports {mgmt_gpio_in[4]}]
|
||||
set_clock_transition 0.1500 [get_clocks {sck}]
|
||||
set_clock_uncertainty 0.3000 sck
|
||||
set_clock_transition 0.0100 [get_clocks {sck}]
|
||||
set_clock_uncertainty 0.1000 sck
|
||||
set_propagated_clock [get_clocks {sck}]
|
||||
create_generated_clock -name wbbd_sck -source [get_ports {wb_clk_i}] -divide_by 2 [get_pins {_7205_/Q}]
|
||||
set_propagated_clock [get_clocks {wbbd_sck}]
|
||||
set_clock_groups -name group1 -logically_exclusive \
|
||||
-group [get_clocks {sck}]\
|
||||
-group [get_clocks {wb_clk_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_mode}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_out}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[13]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[14]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[15]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[16]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[17]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[18]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[19]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[20]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[21]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[22]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[23]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[24]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[25]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[26]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[27]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[28]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[29]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[30]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[31]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[13]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[14]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[15]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[16]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[17]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[18]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[19]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[20]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[21]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[22]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[23]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[24]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[25]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[26]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[27]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[28]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[29]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[30]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[31]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[32]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[33]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[34]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[35]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[36]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[37]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[3]}]
|
||||
set_input_delay 0.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_di}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_di}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {porb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {qspi_enabled}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_tx}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_csb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_enabled}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sck}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdo}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdoenb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_clk}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_csb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {trap}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {uart_enabled}]
|
||||
set_input_delay 0.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_clock}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vcc_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vdd_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vcc_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vdd_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[13]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[14]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[15]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[16]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[17]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[18]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[19]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[20]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[21]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[22]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[23]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[24]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[25]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[26]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[27]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[28]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[29]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[30]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[31]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[13]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[14]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[15]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[16]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[17]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[18]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[19]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[20]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[21]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[22]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[23]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[24]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[25]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[26]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[27]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[28]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[29]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[30]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[31]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rstn_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[26]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[27]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[28]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[29]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[30]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[31]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[32]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[33]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[34]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[35]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[36]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[37]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[9]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[26]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[27]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[28]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[29]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[30]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[31]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[32]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[33]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[34]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[35]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[36]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[37]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[9]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_do}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_ieb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_do}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_ieb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_bypass}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_dco_ena}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_ena}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[9]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {reset}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_rx}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_1}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_2}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_load}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_resetn}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdi}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[26]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[27]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[28]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[29]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[30]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[31]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[9]}]
|
||||
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_mode}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_oeb}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_out}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[0]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[10]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[11]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[12]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[13]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[14]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[15]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[16]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[17]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[18]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[19]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[1]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[20]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[21]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[22]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[23]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[24]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[25]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[26]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[27]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[28]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[29]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[2]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[30]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[31]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[3]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[4]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[5]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[6]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[7]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[8]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[9]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[0]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[10]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[11]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[12]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[13]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[14]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[15]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[16]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[17]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[18]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[19]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[1]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[20]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[21]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[22]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[23]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[24]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[25]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[26]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[27]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[28]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[29]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[2]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[30]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[31]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[32]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[33]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[34]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[35]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[36]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[37]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[3]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[5]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[6]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[7]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[8]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[9]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_di}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_di}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {porb}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {qspi_enabled}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_tx}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_csb}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_enabled}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sck}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdo}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdoenb}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_clk}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_csb}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_do}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_oeb}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_do}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_oeb}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_do}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_oeb}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_do}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_oeb}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {trap}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {uart_enabled}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vcc_pwrgood}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vdd_pwrgood}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vcc_pwrgood}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vdd_pwrgood}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[0]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[10]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[11]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[12]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[13]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[14]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[15]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[16]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[17]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[18]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[19]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[1]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[20]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[21]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[22]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[23]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[24]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[25]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[26]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[27]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[28]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[29]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[2]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[30]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[31]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[3]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[4]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[5]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[6]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[7]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[8]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[9]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[0]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[10]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[11]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[12]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[13]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[14]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[15]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[16]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[17]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[18]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[19]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[1]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[20]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[21]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[22]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[23]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[24]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[25]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[26]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[27]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[28]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[29]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[2]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[30]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[31]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[3]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[4]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[5]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[6]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[7]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[8]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[9]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rstn_i}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[0]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[1]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[2]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[3]}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
|
||||
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_in}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[0]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[10]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[11]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[12]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[13]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[14]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[15]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[16]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[17]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[18]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[19]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[1]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[20]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[21]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[22]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[23]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[24]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[25]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[26]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[27]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[28]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[29]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[2]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[30]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[31]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[32]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[33]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[34]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[35]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[36]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[37]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[3]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[4]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[5]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[6]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[7]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[8]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[9]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[0]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[10]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[11]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[12]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[13]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[14]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[15]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[16]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[17]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[18]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[19]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[1]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[20]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[21]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[22]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[23]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[24]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[25]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[26]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[27]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[28]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[29]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[2]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[30]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[31]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[32]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[33]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[34]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[35]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[36]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[37]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[3]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[4]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[5]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[6]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[7]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[8]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[9]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk_oeb}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb_oeb}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_do}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_ieb}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_oeb}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_do}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_ieb}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_oeb}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[0]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[1]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[2]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_bypass}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_dco_ena}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[0]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[1]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[2]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[3]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[4]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_ena}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[0]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[1]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[2]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[0]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[10]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[11]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[12]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[13]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[14]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[15]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[16]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[17]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[18]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[19]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[1]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[20]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[21]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[22]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[23]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[24]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[25]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[2]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[3]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[4]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[5]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[6]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[7]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[8]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[9]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[0]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[1]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[2]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[3]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {reset}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_rx}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_1}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_2}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_load}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_resetn}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdi}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_di}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_di}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_di}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_di}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[0]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[10]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[11]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[12]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[13]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[14]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[15]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[16]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[17]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[18]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[19]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[1]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[20]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[21]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[22]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[23]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[24]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[25]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[26]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[27]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[28]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[29]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[2]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[30]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[31]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[3]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[4]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[5]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[6]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[7]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[8]}]
|
||||
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[9]}]
|
||||
|
||||
set_false_path\
|
||||
-from [list [get_ports {porb}]\
|
||||
[get_ports {wb_rstn_i}]]
|
||||
|
||||
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
|
|
@ -558,10 +559,9 @@ set_load -pin_load 0.2100 [get_ports {wb_dat_o[3]}]
|
|||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_transition 0.7500 [current_design]
|
||||
set_max_fanout 20.0000 [current_design]
|
||||
set_max_transition 0.75 [current_design]
|
||||
set_max_fanout 7.0000 [current_design]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,11 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Sun Oct 9 23:58:50 2022
|
||||
###############################################################################
|
||||
current_design mgmt_protect
|
||||
### Management Protect Signoff SDC
|
||||
### Rev 1
|
||||
### Date: 9/10/2022
|
||||
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name v_clk -period 4.0000
|
||||
create_clock -name v_clk -period 10
|
||||
set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {caravel_clk}]
|
||||
set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {caravel_clk2}]
|
||||
set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {caravel_rstn}]
|
||||
|
|
@ -1635,4 +1634,4 @@ set_load -pin_load 0.2000 [get_ports {user_irq[0]}]
|
|||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_transition 0.7500 [current_design]
|
||||
set_max_transition 0.75 [current_design]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,87 @@
|
|||
set ::env(IO_PCT) "0.2"
|
||||
set ::env(SYNTH_MAX_FANOUT) "5"
|
||||
set ::env(SYNTH_CAP_LOAD) "33"
|
||||
set ::env(SYNTH_TIMING_DERATE) 0.05
|
||||
set ::env(SYNTH_CLOCK_UNCERTAINITY) 0.25
|
||||
set ::env(SYNTH_CLOCK_TRANSITION) 0.15
|
||||
|
||||
## MASTER CLOCKS
|
||||
create_clock [get_ports {"clock"} ] -name "clock" -period 25
|
||||
set_propagated_clock [get_clocks {"clock"}]
|
||||
|
||||
## INPUT/OUTPUT DELAYS
|
||||
set input_delay_value 1
|
||||
set output_delay_value [expr 25 * $::env(IO_PCT)]
|
||||
puts "\[INFO\]: Setting output delay to: $output_delay_value"
|
||||
puts "\[INFO\]: Setting input delay to: $input_delay_value"
|
||||
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {gpio}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[0]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[1]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[2]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[3]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[4]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[5]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[6]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[7]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[8]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[9]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[10]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[11]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[12]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[13]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[14]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[15]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[16]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[17]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[18]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[19]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[20]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[21]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[22]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[23]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[25]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[26]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[27]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[28]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[33]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[34]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[35]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[36]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[37]}]
|
||||
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_csb}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_clk}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}]
|
||||
|
||||
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
|
||||
|
||||
## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
|
||||
set_case_analysis 0 [get_pins housekeeping/_4449_/S]
|
||||
set_case_analysis 0 [get_pins housekeeping/_4450_/S]
|
||||
|
||||
## FALSE PATHS (ASYNCHRONOUS INPUTS)
|
||||
set_false_path -from [get_ports {resetb}]
|
||||
set_false_path -from [get_ports mprj_io[*]]
|
||||
set_false_path -from [get_ports gpio]
|
||||
|
||||
# TODO set this as parameter
|
||||
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
|
||||
puts "\[INFO\]: Setting load to: $cap_load"
|
||||
set_load $cap_load [all_outputs]
|
||||
|
||||
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
|
||||
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
|
||||
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
|
||||
|
||||
puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
|
||||
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {clock}]
|
||||
|
||||
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
|
||||
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clock}]
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Sun Oct 9 23:50:57 2022
|
||||
###############################################################################
|
||||
current_design gpio_control_block
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name serial_clock -period 50.0000 [get_ports {serial_clock}]
|
||||
set_clock_transition 0.1500 [get_clocks {serial_clock}]
|
||||
set_clock_uncertainty 0.4000 serial_clock
|
||||
set_propagated_clock [get_clocks {serial_clock}]
|
||||
create_clock -name serial_load -period 50.0000 [get_ports {serial_load}]
|
||||
set_clock_transition 0.1500 [get_clocks {serial_load}]
|
||||
set_clock_uncertainty 0.4000 serial_load
|
||||
set_propagated_clock [get_clocks {serial_load}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_out}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_in}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_in}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {one}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_en}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_pol}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_holdover}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_inenb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_outenb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_slow_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_clock_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {zero}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.2500 [get_ports {mgmt_gpio_in}]
|
||||
set_load -pin_load 0.2500 [get_ports {one}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_en}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_pol}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_holdover}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_inenb}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_outenb}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_slow_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {resetn_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {serial_clock_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {serial_data_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {serial_load_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {user_gpio_in}]
|
||||
set_load -pin_load 0.2500 [get_ports {zero}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[2]}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[1]}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[0]}]
|
||||
set_input_transition 5.0000 [get_ports {mgmt_gpio_oeb}]
|
||||
set_input_transition 5.0000 [get_ports {mgmt_gpio_out}]
|
||||
set_input_transition 5.0000 [get_ports {pad_gpio_in}]
|
||||
set_input_transition 5.0000 [get_ports {resetn}]
|
||||
set_input_transition 5.0000 [get_ports {serial_clock}]
|
||||
set_input_transition 5.0000 [get_ports {serial_data_in}]
|
||||
set_input_transition 5.0000 [get_ports {serial_load}]
|
||||
set_input_transition 5.0000 [get_ports {user_gpio_oeb}]
|
||||
set_input_transition 5.0000 [get_ports {user_gpio_out}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[12]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[11]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[10]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[9]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[8]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[7]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[6]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[5]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[4]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[3]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[2]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[1]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_transition 1.2500 [current_design]
|
||||
set_max_fanout 7.0000 [current_design]
|
||||
|
|
@ -0,0 +1 @@
|
|||
openlane 2021.09.09_03.00.48-53-g97579eb
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
-ne openlane
|
||||
e6ba5d36a9b32a9f87626d49bf3c80cf3964ebeb
|
||||
-ne skywater-pdk
|
||||
c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
|
||||
-ne open_pdks
|
||||
f90a86bdd133bd629251d59eebb1aee8452c0f5c
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/project/openlane/gpio_defaults_block,gpio_defaults_block,gpio_defaults_block,flow_completed,0h0m57s,-1,78787.87878787878,0.00033,39393.93939393939,22.67,443.21,13,0,-1,-1,-1,-1,0,0,-1,0,0,-1,41,26,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,55260.0,0.0,2.33,0.0,0.0,0.0,-1,5,41,5,41,0,0,0,13,0,0,0,0,0,0,0,4,-1,-1,-1,6,5,0,11,90.9090909090909,11.0,10.0,AREA 0,5,50,1,7,7,0.92,0.0,sky130_fd_sc_hd,0,3
|
||||
|
|
|
@ -0,0 +1 @@
|
|||
openlane 2021.09.09_03.00.48-53-g97579eb
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
-ne openlane
|
||||
e6ba5d36a9b32a9f87626d49bf3c80cf3964ebeb
|
||||
-ne skywater-pdk
|
||||
c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
|
||||
-ne open_pdks
|
||||
f90a86bdd133bd629251d59eebb1aee8452c0f5c
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/project/openlane/gpio_defaults_block,gpio_defaults_block,gpio_defaults_block,flow_completed,0h0m57s,-1,78787.87878787878,0.00033,39393.93939393939,22.67,443.21,13,0,-1,-1,-1,-1,0,0,-1,0,0,-1,41,26,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,55260.0,0.0,2.33,0.0,0.0,0.0,-1,5,41,5,41,0,0,0,13,0,0,0,0,0,0,0,4,-1,-1,-1,6,5,0,11,90.9090909090909,11.0,10.0,AREA 0,5,50,1,7,7,0.92,0.0,sky130_fd_sc_hd,0,3
|
||||
|
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,567 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Tue Oct 11 23:00:28 2022
|
||||
###############################################################################
|
||||
current_design housekeeping
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name wb_clk_i -period 25.0000 [get_ports {wb_clk_i}]
|
||||
set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
|
||||
set_clock_uncertainty 0.3000 wb_clk_i
|
||||
set_propagated_clock [get_clocks {wb_clk_i}]
|
||||
create_clock -name user_clock -period 25.0000 [get_ports {user_clock}]
|
||||
set_clock_transition 0.1500 [get_clocks {user_clock}]
|
||||
set_clock_uncertainty 0.3000 user_clock
|
||||
set_propagated_clock [get_clocks {user_clock}]
|
||||
create_clock -name sck -period 100.0000 [get_ports {mgmt_gpio_in[4]}]
|
||||
set_clock_transition 0.1500 [get_clocks {sck}]
|
||||
set_clock_uncertainty 0.3000 sck
|
||||
set_propagated_clock [get_clocks {sck}]
|
||||
create_generated_clock -name wbbd_sck -source [get_ports {wb_clk_i}] -divide_by 2 [get_pins {_7205_/Q}]
|
||||
set_propagated_clock [get_clocks {wbbd_sck}]
|
||||
set_clock_groups -name group1 -logically_exclusive \
|
||||
-group [get_clocks {sck}]\
|
||||
-group [get_clocks {wb_clk_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_mode}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_out}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[13]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[14]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[15]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[16]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[17]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[18]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[19]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[20]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[21]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[22]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[23]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[24]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[25]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[26]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[27]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[28]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[29]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[30]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[31]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[13]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[14]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[15]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[16]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[17]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[18]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[19]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[20]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[21]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[22]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[23]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[24]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[25]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[26]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[27]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[28]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[29]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[30]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[31]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[32]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[33]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[34]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[35]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[36]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[37]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[3]}]
|
||||
set_input_delay 0.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_di}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_di}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {porb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {qspi_enabled}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_tx}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_csb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_enabled}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sck}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdo}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdoenb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_clk}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_csb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {trap}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {uart_enabled}]
|
||||
set_input_delay 0.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_clock}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vcc_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vdd_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vcc_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vdd_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[13]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[14]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[15]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[16]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[17]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[18]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[19]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[20]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[21]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[22]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[23]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[24]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[25]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[26]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[27]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[28]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[29]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[30]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[31]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[13]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[14]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[15]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[16]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[17]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[18]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[19]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[20]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[21]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[22]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[23]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[24]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[25]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[26]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[27]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[28]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[29]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[30]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[31]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rstn_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[26]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[27]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[28]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[29]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[30]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[31]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[32]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[33]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[34]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[35]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[36]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[37]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[9]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[26]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[27]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[28]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[29]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[30]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[31]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[32]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[33]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[34]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[35]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[36]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[37]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[9]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_do}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_ieb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_do}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_ieb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_bypass}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_dco_ena}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_ena}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[9]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {reset}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_rx}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_1}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_2}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_load}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_resetn}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdi}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[26]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[27]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[28]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[29]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[30]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[31]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[9]}]
|
||||
set_false_path\
|
||||
-from [list [get_ports {porb}]\
|
||||
[get_ports {wb_rstn_i}]]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.2100 [get_ports {debug_in}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_flash_clk}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_flash_clk_oeb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_flash_csb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_flash_csb_oeb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_flash_io0_do}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_flash_io0_ieb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_flash_io0_oeb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_flash_io1_do}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_flash_io1_ieb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pad_flash_io1_oeb}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_bypass}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_dco_ena}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_ena}]
|
||||
set_load -pin_load 0.2100 [get_ports {reset}]
|
||||
set_load -pin_load 0.2100 [get_ports {ser_rx}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_clock}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_data_1}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_data_2}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_load}]
|
||||
set_load -pin_load 0.2100 [get_ports {serial_resetn}]
|
||||
set_load -pin_load 0.2100 [get_ports {spi_sdi}]
|
||||
set_load -pin_load 0.2100 [get_ports {spimemio_flash_io0_di}]
|
||||
set_load -pin_load 0.2100 [get_ports {spimemio_flash_io1_di}]
|
||||
set_load -pin_load 0.2100 [get_ports {spimemio_flash_io2_di}]
|
||||
set_load -pin_load 0.2100 [get_ports {spimemio_flash_io3_di}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_ack_o}]
|
||||
set_load -pin_load 0.2100 [get_ports {irq[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {irq[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {irq[0]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[37]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[36]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[35]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[34]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[33]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[32]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[31]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[30]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[29]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[28]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[27]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[26]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[25]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[24]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[23]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[22]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[21]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[20]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[19]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[18]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[17]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[16]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[15]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[14]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[13]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[12]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[11]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[10]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[9]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[8]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[7]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[6]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[5]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[4]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[3]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_oeb[0]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[37]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[36]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[35]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[34]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[33]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[32]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[31]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[30]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[29]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[28]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[27]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[26]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[25]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[24]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[23]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[22]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[21]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[20]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[19]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[18]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[17]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[16]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[15]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[14]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[13]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[12]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[11]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[10]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[9]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[8]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[7]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[6]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[5]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[4]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[3]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {mgmt_gpio_out[0]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll90_sel[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll90_sel[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll90_sel[0]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_div[4]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_div[3]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_div[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_div[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_div[0]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_sel[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_sel[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_sel[0]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[25]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[24]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[23]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[22]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[21]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[20]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[19]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[18]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[17]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[16]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[15]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[14]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[13]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[12]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[11]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[10]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[9]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[8]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[7]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[6]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[5]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[4]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[3]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pll_trim[0]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pwr_ctrl_out[3]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pwr_ctrl_out[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pwr_ctrl_out[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {pwr_ctrl_out[0]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[31]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[30]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[29]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[28]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[27]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[26]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[25]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[24]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[23]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[22]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[21]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[20]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[19]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[18]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[17]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[16]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[15]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[14]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[13]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[12]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[11]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[10]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[9]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[8]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[7]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[6]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[5]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[4]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[3]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[2]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[1]}]
|
||||
set_load -pin_load 0.2100 [get_ports {wb_dat_o[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_transition 0.7500 [current_design]
|
||||
set_max_fanout 20.0000 [current_design]
|
||||
|
|
@ -1,11 +1,12 @@
|
|||
### Management Protect Signoff SDC
|
||||
### Rev 1
|
||||
### Date: 9/10/2022
|
||||
|
||||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Sun Oct 9 23:58:50 2022
|
||||
###############################################################################
|
||||
current_design mgmt_protect
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name v_clk -period 25.00
|
||||
create_clock -name v_clk -period 4.0000
|
||||
set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {caravel_clk}]
|
||||
set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {caravel_clk2}]
|
||||
set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {caravel_rstn}]
|
||||
|
|
@ -1634,4 +1635,4 @@ set_load -pin_load 0.2000 [get_ports {user_irq[0]}]
|
|||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_transition 1 [current_design]
|
||||
set_max_transition 0.7500 [current_design]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,84 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "constant_block"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*1 one
|
||||
*4 zero
|
||||
*5 one_unbuf
|
||||
*6 zero_unbuf
|
||||
*7 FILLER_0_0
|
||||
*8 FILLER_0_24
|
||||
*9 FILLER_0_27
|
||||
*10 FILLER_1_0
|
||||
*11 FILLER_1_16
|
||||
*12 FILLER_1_24
|
||||
*13 FILLER_1_4
|
||||
*14 FILLER_1_8
|
||||
*15 FILLER_2_0
|
||||
*16 FILLER_2_24
|
||||
*17 FILLER_2_27
|
||||
*18 TAP_0
|
||||
*19 TAP_1
|
||||
*20 const_one_buf
|
||||
*21 const_source
|
||||
*22 const_zero_buf
|
||||
|
||||
*PORTS
|
||||
one O
|
||||
zero O
|
||||
|
||||
*D_NET *1 0.000496181
|
||||
*CONN
|
||||
*P one O
|
||||
*I *20:X O *D sky130_fd_sc_hd__buf_16
|
||||
*CAP
|
||||
1 one 0.00024809
|
||||
2 *20:X 0.00024809
|
||||
*RES
|
||||
1 *20:X one 19.8722
|
||||
*END
|
||||
|
||||
*D_NET *4 0.000337027
|
||||
*CONN
|
||||
*P zero O
|
||||
*I *22:X O *D sky130_fd_sc_hd__buf_16
|
||||
*CAP
|
||||
1 zero 0.000168514
|
||||
2 *22:X 0.000168514
|
||||
*RES
|
||||
1 *22:X zero 19.5839
|
||||
*END
|
||||
|
||||
*D_NET *5 0.000235339
|
||||
*CONN
|
||||
*I *20:A I *D sky130_fd_sc_hd__buf_16
|
||||
*I *21:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 *20:A 0.000117669
|
||||
2 *21:HI 0.000117669
|
||||
*RES
|
||||
1 *21:HI *20:A 30.1893
|
||||
*END
|
||||
|
||||
*D_NET *6 0.000171306
|
||||
*CONN
|
||||
*I *22:A I *D sky130_fd_sc_hd__buf_16
|
||||
*I *21:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 *22:A 8.56529e-05
|
||||
2 *21:LO 8.56529e-05
|
||||
*RES
|
||||
1 *21:LO *22:A 29.5464
|
||||
*END
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,273 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "gpio_defaults_block"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*3 gpio_defaults_low\[0\]
|
||||
*4 gpio_defaults_high\[10\]
|
||||
*5 gpio_defaults_low\[11\]
|
||||
*6 gpio_defaults_low\[12\]
|
||||
*7 gpio_defaults_high\[1\]
|
||||
*8 gpio_defaults_low\[2\]
|
||||
*9 gpio_defaults_low\[3\]
|
||||
*10 gpio_defaults_low\[4\]
|
||||
*11 gpio_defaults_low\[5\]
|
||||
*12 gpio_defaults_low\[6\]
|
||||
*13 gpio_defaults_low\[7\]
|
||||
*14 gpio_defaults_low\[8\]
|
||||
*15 gpio_defaults_low\[9\]
|
||||
*16 gpio_defaults_high\[0\]
|
||||
*17 gpio_defaults_high\[11\]
|
||||
*18 gpio_defaults_high\[12\]
|
||||
*19 gpio_defaults_high\[2\]
|
||||
*20 gpio_defaults_high\[3\]
|
||||
*21 gpio_defaults_high\[4\]
|
||||
*22 gpio_defaults_high\[5\]
|
||||
*23 gpio_defaults_high\[6\]
|
||||
*24 gpio_defaults_high\[7\]
|
||||
*25 gpio_defaults_high\[8\]
|
||||
*26 gpio_defaults_high\[9\]
|
||||
*27 gpio_defaults_low\[10\]
|
||||
*28 gpio_defaults_low\[1\]
|
||||
*29 FILLER_0_29
|
||||
*30 FILLER_0_3
|
||||
*31 FILLER_0_33
|
||||
*32 FILLER_0_38
|
||||
*33 FILLER_0_43
|
||||
*34 FILLER_0_48
|
||||
*35 FILLER_0_55
|
||||
*36 FILLER_0_60
|
||||
*37 FILLER_0_9
|
||||
*38 FILLER_1_15
|
||||
*39 FILLER_1_27
|
||||
*40 FILLER_1_3
|
||||
*41 FILLER_1_39
|
||||
*42 FILLER_1_51
|
||||
*43 FILLER_1_55
|
||||
*44 FILLER_1_57
|
||||
*45 FILLER_1_61
|
||||
*46 FILLER_2_15
|
||||
*47 FILLER_2_27
|
||||
*48 FILLER_2_29
|
||||
*49 FILLER_2_3
|
||||
*50 FILLER_2_41
|
||||
*51 FILLER_2_53
|
||||
*52 FILLER_2_57
|
||||
*53 FILLER_2_61
|
||||
*54 PHY_0
|
||||
*55 PHY_1
|
||||
*56 PHY_2
|
||||
*57 PHY_3
|
||||
*58 PHY_4
|
||||
*59 PHY_5
|
||||
*60 TAP_10
|
||||
*61 TAP_6
|
||||
*62 TAP_7
|
||||
*63 TAP_8
|
||||
*64 TAP_9
|
||||
*65 gpio_default_value\[0\]
|
||||
*66 gpio_default_value\[10\]
|
||||
*67 gpio_default_value\[11\]
|
||||
*68 gpio_default_value\[12\]
|
||||
*69 gpio_default_value\[1\]
|
||||
*70 gpio_default_value\[2\]
|
||||
*71 gpio_default_value\[3\]
|
||||
*72 gpio_default_value\[4\]
|
||||
*73 gpio_default_value\[5\]
|
||||
*74 gpio_default_value\[6\]
|
||||
*75 gpio_default_value\[7\]
|
||||
*76 gpio_default_value\[8\]
|
||||
*77 gpio_default_value\[9\]
|
||||
|
||||
*PORTS
|
||||
gpio_defaults[0] O
|
||||
gpio_defaults[10] O
|
||||
gpio_defaults[11] O
|
||||
gpio_defaults[12] O
|
||||
gpio_defaults[1] O
|
||||
gpio_defaults[2] O
|
||||
gpio_defaults[3] O
|
||||
gpio_defaults[4] O
|
||||
gpio_defaults[5] O
|
||||
gpio_defaults[6] O
|
||||
gpio_defaults[7] O
|
||||
gpio_defaults[8] O
|
||||
gpio_defaults[9] O
|
||||
|
||||
*D_NET *3 0.000662868
|
||||
*CONN
|
||||
*P gpio_defaults[0] O
|
||||
*I *65:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[0] 0.000295589
|
||||
2 *65:LO 0.000295589
|
||||
3 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
|
||||
*RES
|
||||
1 *65:LO gpio_defaults[0] 21.1394
|
||||
*END
|
||||
|
||||
*D_NET *4 0.000169932
|
||||
*CONN
|
||||
*P gpio_defaults[10] O
|
||||
*I *66:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[10] 8.49658e-05
|
||||
2 *66:HI 8.49658e-05
|
||||
3 gpio_defaults[10] gpio_defaults[11] 0
|
||||
4 gpio_defaults[10] gpio_defaults[9] 0
|
||||
*RES
|
||||
1 *66:HI gpio_defaults[10] 15.7033
|
||||
*END
|
||||
|
||||
*D_NET *5 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[11] O
|
||||
*I *67:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[11] 0.000115448
|
||||
2 *67:LO 0.000115448
|
||||
3 gpio_defaults[11] gpio_defaults[12] 0
|
||||
4 gpio_defaults[10] gpio_defaults[11] 0
|
||||
*RES
|
||||
1 *67:LO gpio_defaults[11] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *6 0.000822209
|
||||
*CONN
|
||||
*P gpio_defaults[12] O
|
||||
*I *68:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[12] 0.000411104
|
||||
2 *68:LO 0.000411104
|
||||
3 gpio_defaults[11] gpio_defaults[12] 0
|
||||
*RES
|
||||
1 *68:LO gpio_defaults[12] 23.2185
|
||||
*END
|
||||
|
||||
*D_NET *7 0.00071336
|
||||
*CONN
|
||||
*P gpio_defaults[1] O
|
||||
*I *69:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[1] 0.000307544
|
||||
2 *69:HI 0.000307544
|
||||
3 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
|
||||
4 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
|
||||
*RES
|
||||
1 *69:HI gpio_defaults[1] 19.1997
|
||||
*END
|
||||
|
||||
*D_NET *8 0.000464143
|
||||
*CONN
|
||||
*P gpio_defaults[2] O
|
||||
*I *70:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[2] 0.00021878
|
||||
2 *70:LO 0.00021878
|
||||
3 gpio_defaults[2] gpio_defaults[3] 0
|
||||
4 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
|
||||
*RES
|
||||
1 *70:LO gpio_defaults[2] 18.921
|
||||
*END
|
||||
|
||||
*D_NET *9 0.000363376
|
||||
*CONN
|
||||
*P gpio_defaults[3] O
|
||||
*I *71:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[3] 0.000181688
|
||||
2 *71:LO 0.000181688
|
||||
3 gpio_defaults[3] gpio_defaults[4] 0
|
||||
4 gpio_defaults[2] gpio_defaults[3] 0
|
||||
*RES
|
||||
1 *71:LO gpio_defaults[3] 17.8118
|
||||
*END
|
||||
|
||||
*D_NET *10 0.000236028
|
||||
*CONN
|
||||
*P gpio_defaults[4] O
|
||||
*I *72:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[4] 0.000118014
|
||||
2 *72:LO 0.000118014
|
||||
3 gpio_defaults[4] gpio_defaults[5] 0
|
||||
4 gpio_defaults[3] gpio_defaults[4] 0
|
||||
*RES
|
||||
1 *72:LO gpio_defaults[4] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *11 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[5] O
|
||||
*I *73:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[5] 0.000115448
|
||||
2 *73:LO 0.000115448
|
||||
3 gpio_defaults[5] gpio_defaults[6] 0
|
||||
4 gpio_defaults[4] gpio_defaults[5] 0
|
||||
*RES
|
||||
1 *73:LO gpio_defaults[5] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *12 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[6] O
|
||||
*I *74:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[6] 0.000115448
|
||||
2 *74:LO 0.000115448
|
||||
3 gpio_defaults[6] gpio_defaults[7] 0
|
||||
4 gpio_defaults[5] gpio_defaults[6] 0
|
||||
*RES
|
||||
1 *74:LO gpio_defaults[6] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *13 0.00022764
|
||||
*CONN
|
||||
*P gpio_defaults[7] O
|
||||
*I *75:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[7] 0.00011382
|
||||
2 *75:LO 0.00011382
|
||||
3 gpio_defaults[7] gpio_defaults[8] 0
|
||||
4 gpio_defaults[6] gpio_defaults[7] 0
|
||||
*RES
|
||||
1 *75:LO gpio_defaults[7] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *14 0.000224385
|
||||
*CONN
|
||||
*P gpio_defaults[8] O
|
||||
*I *76:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[8] 0.000112192
|
||||
2 *76:LO 0.000112192
|
||||
3 gpio_defaults[8] gpio_defaults[9] 0
|
||||
4 gpio_defaults[7] gpio_defaults[8] 0
|
||||
*RES
|
||||
1 *76:LO gpio_defaults[8] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *15 0.00022764
|
||||
*CONN
|
||||
*P gpio_defaults[9] O
|
||||
*I *77:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[9] 0.00011382
|
||||
2 *77:LO 0.00011382
|
||||
3 gpio_defaults[10] gpio_defaults[9] 0
|
||||
4 gpio_defaults[8] gpio_defaults[9] 0
|
||||
*RES
|
||||
1 *77:LO gpio_defaults[9] 16.5338
|
||||
*END
|
||||
|
|
@ -0,0 +1,273 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "gpio_defaults_block_0403"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*3 gpio_defaults_low\[0\]
|
||||
*4 gpio_defaults_high\[10\]
|
||||
*5 gpio_defaults_low\[11\]
|
||||
*6 gpio_defaults_low\[12\]
|
||||
*7 gpio_defaults_high\[1\]
|
||||
*8 gpio_defaults_low\[2\]
|
||||
*9 gpio_defaults_low\[3\]
|
||||
*10 gpio_defaults_low\[4\]
|
||||
*11 gpio_defaults_low\[5\]
|
||||
*12 gpio_defaults_low\[6\]
|
||||
*13 gpio_defaults_low\[7\]
|
||||
*14 gpio_defaults_low\[8\]
|
||||
*15 gpio_defaults_low\[9\]
|
||||
*16 gpio_defaults_high\[0\]
|
||||
*17 gpio_defaults_high\[11\]
|
||||
*18 gpio_defaults_high\[12\]
|
||||
*19 gpio_defaults_high\[2\]
|
||||
*20 gpio_defaults_high\[3\]
|
||||
*21 gpio_defaults_high\[4\]
|
||||
*22 gpio_defaults_high\[5\]
|
||||
*23 gpio_defaults_high\[6\]
|
||||
*24 gpio_defaults_high\[7\]
|
||||
*25 gpio_defaults_high\[8\]
|
||||
*26 gpio_defaults_high\[9\]
|
||||
*27 gpio_defaults_low\[10\]
|
||||
*28 gpio_defaults_low\[1\]
|
||||
*29 FILLER_0_29
|
||||
*30 FILLER_0_3
|
||||
*31 FILLER_0_33
|
||||
*32 FILLER_0_38
|
||||
*33 FILLER_0_43
|
||||
*34 FILLER_0_48
|
||||
*35 FILLER_0_55
|
||||
*36 FILLER_0_60
|
||||
*37 FILLER_0_9
|
||||
*38 FILLER_1_15
|
||||
*39 FILLER_1_27
|
||||
*40 FILLER_1_3
|
||||
*41 FILLER_1_39
|
||||
*42 FILLER_1_51
|
||||
*43 FILLER_1_55
|
||||
*44 FILLER_1_57
|
||||
*45 FILLER_1_61
|
||||
*46 FILLER_2_15
|
||||
*47 FILLER_2_27
|
||||
*48 FILLER_2_29
|
||||
*49 FILLER_2_3
|
||||
*50 FILLER_2_41
|
||||
*51 FILLER_2_53
|
||||
*52 FILLER_2_57
|
||||
*53 FILLER_2_61
|
||||
*54 PHY_0
|
||||
*55 PHY_1
|
||||
*56 PHY_2
|
||||
*57 PHY_3
|
||||
*58 PHY_4
|
||||
*59 PHY_5
|
||||
*60 TAP_10
|
||||
*61 TAP_6
|
||||
*62 TAP_7
|
||||
*63 TAP_8
|
||||
*64 TAP_9
|
||||
*65 gpio_default_value\[0\]
|
||||
*66 gpio_default_value\[10\]
|
||||
*67 gpio_default_value\[11\]
|
||||
*68 gpio_default_value\[12\]
|
||||
*69 gpio_default_value\[1\]
|
||||
*70 gpio_default_value\[2\]
|
||||
*71 gpio_default_value\[3\]
|
||||
*72 gpio_default_value\[4\]
|
||||
*73 gpio_default_value\[5\]
|
||||
*74 gpio_default_value\[6\]
|
||||
*75 gpio_default_value\[7\]
|
||||
*76 gpio_default_value\[8\]
|
||||
*77 gpio_default_value\[9\]
|
||||
|
||||
*PORTS
|
||||
gpio_defaults[0] O
|
||||
gpio_defaults[10] O
|
||||
gpio_defaults[11] O
|
||||
gpio_defaults[12] O
|
||||
gpio_defaults[1] O
|
||||
gpio_defaults[2] O
|
||||
gpio_defaults[3] O
|
||||
gpio_defaults[4] O
|
||||
gpio_defaults[5] O
|
||||
gpio_defaults[6] O
|
||||
gpio_defaults[7] O
|
||||
gpio_defaults[8] O
|
||||
gpio_defaults[9] O
|
||||
|
||||
*D_NET *3 0.000662868
|
||||
*CONN
|
||||
*P gpio_defaults[0] O
|
||||
*I *65:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[0] 0.000295589
|
||||
2 *65:LO 0.000295589
|
||||
3 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
|
||||
*RES
|
||||
1 *65:LO gpio_defaults[0] 21.1394
|
||||
*END
|
||||
|
||||
*D_NET *4 0.000169932
|
||||
*CONN
|
||||
*P gpio_defaults[10] O
|
||||
*I *66:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[10] 8.49658e-05
|
||||
2 *66:HI 8.49658e-05
|
||||
3 gpio_defaults[10] gpio_defaults[11] 0
|
||||
4 gpio_defaults[10] gpio_defaults[9] 0
|
||||
*RES
|
||||
1 *66:HI gpio_defaults[10] 15.7033
|
||||
*END
|
||||
|
||||
*D_NET *5 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[11] O
|
||||
*I *67:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[11] 0.000115448
|
||||
2 *67:LO 0.000115448
|
||||
3 gpio_defaults[11] gpio_defaults[12] 0
|
||||
4 gpio_defaults[10] gpio_defaults[11] 0
|
||||
*RES
|
||||
1 *67:LO gpio_defaults[11] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *6 0.000822209
|
||||
*CONN
|
||||
*P gpio_defaults[12] O
|
||||
*I *68:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[12] 0.000411104
|
||||
2 *68:LO 0.000411104
|
||||
3 gpio_defaults[11] gpio_defaults[12] 0
|
||||
*RES
|
||||
1 *68:LO gpio_defaults[12] 23.2185
|
||||
*END
|
||||
|
||||
*D_NET *7 0.00071336
|
||||
*CONN
|
||||
*P gpio_defaults[1] O
|
||||
*I *69:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[1] 0.000307544
|
||||
2 *69:HI 0.000307544
|
||||
3 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
|
||||
4 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
|
||||
*RES
|
||||
1 *69:HI gpio_defaults[1] 19.1997
|
||||
*END
|
||||
|
||||
*D_NET *8 0.000464143
|
||||
*CONN
|
||||
*P gpio_defaults[2] O
|
||||
*I *70:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[2] 0.00021878
|
||||
2 *70:LO 0.00021878
|
||||
3 gpio_defaults[2] gpio_defaults[3] 0
|
||||
4 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
|
||||
*RES
|
||||
1 *70:LO gpio_defaults[2] 18.921
|
||||
*END
|
||||
|
||||
*D_NET *9 0.000363376
|
||||
*CONN
|
||||
*P gpio_defaults[3] O
|
||||
*I *71:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[3] 0.000181688
|
||||
2 *71:LO 0.000181688
|
||||
3 gpio_defaults[3] gpio_defaults[4] 0
|
||||
4 gpio_defaults[2] gpio_defaults[3] 0
|
||||
*RES
|
||||
1 *71:LO gpio_defaults[3] 17.8118
|
||||
*END
|
||||
|
||||
*D_NET *10 0.000236028
|
||||
*CONN
|
||||
*P gpio_defaults[4] O
|
||||
*I *72:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[4] 0.000118014
|
||||
2 *72:LO 0.000118014
|
||||
3 gpio_defaults[4] gpio_defaults[5] 0
|
||||
4 gpio_defaults[3] gpio_defaults[4] 0
|
||||
*RES
|
||||
1 *72:LO gpio_defaults[4] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *11 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[5] O
|
||||
*I *73:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[5] 0.000115448
|
||||
2 *73:LO 0.000115448
|
||||
3 gpio_defaults[5] gpio_defaults[6] 0
|
||||
4 gpio_defaults[4] gpio_defaults[5] 0
|
||||
*RES
|
||||
1 *73:LO gpio_defaults[5] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *12 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[6] O
|
||||
*I *74:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[6] 0.000115448
|
||||
2 *74:LO 0.000115448
|
||||
3 gpio_defaults[6] gpio_defaults[7] 0
|
||||
4 gpio_defaults[5] gpio_defaults[6] 0
|
||||
*RES
|
||||
1 *74:LO gpio_defaults[6] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *13 0.00022764
|
||||
*CONN
|
||||
*P gpio_defaults[7] O
|
||||
*I *75:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[7] 0.00011382
|
||||
2 *75:LO 0.00011382
|
||||
3 gpio_defaults[7] gpio_defaults[8] 0
|
||||
4 gpio_defaults[6] gpio_defaults[7] 0
|
||||
*RES
|
||||
1 *75:LO gpio_defaults[7] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *14 0.000224385
|
||||
*CONN
|
||||
*P gpio_defaults[8] O
|
||||
*I *76:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[8] 0.000112192
|
||||
2 *76:LO 0.000112192
|
||||
3 gpio_defaults[8] gpio_defaults[9] 0
|
||||
4 gpio_defaults[7] gpio_defaults[8] 0
|
||||
*RES
|
||||
1 *76:LO gpio_defaults[8] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *15 0.00022764
|
||||
*CONN
|
||||
*P gpio_defaults[9] O
|
||||
*I *77:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[9] 0.00011382
|
||||
2 *77:LO 0.00011382
|
||||
3 gpio_defaults[10] gpio_defaults[9] 0
|
||||
4 gpio_defaults[8] gpio_defaults[9] 0
|
||||
*RES
|
||||
1 *77:LO gpio_defaults[9] 16.5338
|
||||
*END
|
||||
|
|
@ -0,0 +1,273 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "gpio_defaults_block_1803"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*3 gpio_defaults_low\[0\]
|
||||
*4 gpio_defaults_high\[10\]
|
||||
*5 gpio_defaults_low\[11\]
|
||||
*6 gpio_defaults_low\[12\]
|
||||
*7 gpio_defaults_high\[1\]
|
||||
*8 gpio_defaults_low\[2\]
|
||||
*9 gpio_defaults_low\[3\]
|
||||
*10 gpio_defaults_low\[4\]
|
||||
*11 gpio_defaults_low\[5\]
|
||||
*12 gpio_defaults_low\[6\]
|
||||
*13 gpio_defaults_low\[7\]
|
||||
*14 gpio_defaults_low\[8\]
|
||||
*15 gpio_defaults_low\[9\]
|
||||
*16 gpio_defaults_high\[0\]
|
||||
*17 gpio_defaults_high\[11\]
|
||||
*18 gpio_defaults_high\[12\]
|
||||
*19 gpio_defaults_high\[2\]
|
||||
*20 gpio_defaults_high\[3\]
|
||||
*21 gpio_defaults_high\[4\]
|
||||
*22 gpio_defaults_high\[5\]
|
||||
*23 gpio_defaults_high\[6\]
|
||||
*24 gpio_defaults_high\[7\]
|
||||
*25 gpio_defaults_high\[8\]
|
||||
*26 gpio_defaults_high\[9\]
|
||||
*27 gpio_defaults_low\[10\]
|
||||
*28 gpio_defaults_low\[1\]
|
||||
*29 FILLER_0_29
|
||||
*30 FILLER_0_3
|
||||
*31 FILLER_0_33
|
||||
*32 FILLER_0_38
|
||||
*33 FILLER_0_43
|
||||
*34 FILLER_0_48
|
||||
*35 FILLER_0_55
|
||||
*36 FILLER_0_60
|
||||
*37 FILLER_0_9
|
||||
*38 FILLER_1_15
|
||||
*39 FILLER_1_27
|
||||
*40 FILLER_1_3
|
||||
*41 FILLER_1_39
|
||||
*42 FILLER_1_51
|
||||
*43 FILLER_1_55
|
||||
*44 FILLER_1_57
|
||||
*45 FILLER_1_61
|
||||
*46 FILLER_2_15
|
||||
*47 FILLER_2_27
|
||||
*48 FILLER_2_29
|
||||
*49 FILLER_2_3
|
||||
*50 FILLER_2_41
|
||||
*51 FILLER_2_53
|
||||
*52 FILLER_2_57
|
||||
*53 FILLER_2_61
|
||||
*54 PHY_0
|
||||
*55 PHY_1
|
||||
*56 PHY_2
|
||||
*57 PHY_3
|
||||
*58 PHY_4
|
||||
*59 PHY_5
|
||||
*60 TAP_10
|
||||
*61 TAP_6
|
||||
*62 TAP_7
|
||||
*63 TAP_8
|
||||
*64 TAP_9
|
||||
*65 gpio_default_value\[0\]
|
||||
*66 gpio_default_value\[10\]
|
||||
*67 gpio_default_value\[11\]
|
||||
*68 gpio_default_value\[12\]
|
||||
*69 gpio_default_value\[1\]
|
||||
*70 gpio_default_value\[2\]
|
||||
*71 gpio_default_value\[3\]
|
||||
*72 gpio_default_value\[4\]
|
||||
*73 gpio_default_value\[5\]
|
||||
*74 gpio_default_value\[6\]
|
||||
*75 gpio_default_value\[7\]
|
||||
*76 gpio_default_value\[8\]
|
||||
*77 gpio_default_value\[9\]
|
||||
|
||||
*PORTS
|
||||
gpio_defaults[0] O
|
||||
gpio_defaults[10] O
|
||||
gpio_defaults[11] O
|
||||
gpio_defaults[12] O
|
||||
gpio_defaults[1] O
|
||||
gpio_defaults[2] O
|
||||
gpio_defaults[3] O
|
||||
gpio_defaults[4] O
|
||||
gpio_defaults[5] O
|
||||
gpio_defaults[6] O
|
||||
gpio_defaults[7] O
|
||||
gpio_defaults[8] O
|
||||
gpio_defaults[9] O
|
||||
|
||||
*D_NET *3 0.000662868
|
||||
*CONN
|
||||
*P gpio_defaults[0] O
|
||||
*I *65:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[0] 0.000295589
|
||||
2 *65:LO 0.000295589
|
||||
3 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
|
||||
*RES
|
||||
1 *65:LO gpio_defaults[0] 21.1394
|
||||
*END
|
||||
|
||||
*D_NET *4 0.000169932
|
||||
*CONN
|
||||
*P gpio_defaults[10] O
|
||||
*I *66:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[10] 8.49658e-05
|
||||
2 *66:HI 8.49658e-05
|
||||
3 gpio_defaults[10] gpio_defaults[11] 0
|
||||
4 gpio_defaults[10] gpio_defaults[9] 0
|
||||
*RES
|
||||
1 *66:HI gpio_defaults[10] 15.7033
|
||||
*END
|
||||
|
||||
*D_NET *5 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[11] O
|
||||
*I *67:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[11] 0.000115448
|
||||
2 *67:LO 0.000115448
|
||||
3 gpio_defaults[11] gpio_defaults[12] 0
|
||||
4 gpio_defaults[10] gpio_defaults[11] 0
|
||||
*RES
|
||||
1 *67:LO gpio_defaults[11] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *6 0.000822209
|
||||
*CONN
|
||||
*P gpio_defaults[12] O
|
||||
*I *68:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[12] 0.000411104
|
||||
2 *68:LO 0.000411104
|
||||
3 gpio_defaults[11] gpio_defaults[12] 0
|
||||
*RES
|
||||
1 *68:LO gpio_defaults[12] 23.2185
|
||||
*END
|
||||
|
||||
*D_NET *7 0.00071336
|
||||
*CONN
|
||||
*P gpio_defaults[1] O
|
||||
*I *69:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[1] 0.000307544
|
||||
2 *69:HI 0.000307544
|
||||
3 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
|
||||
4 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
|
||||
*RES
|
||||
1 *69:HI gpio_defaults[1] 19.1997
|
||||
*END
|
||||
|
||||
*D_NET *8 0.000464143
|
||||
*CONN
|
||||
*P gpio_defaults[2] O
|
||||
*I *70:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[2] 0.00021878
|
||||
2 *70:LO 0.00021878
|
||||
3 gpio_defaults[2] gpio_defaults[3] 0
|
||||
4 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
|
||||
*RES
|
||||
1 *70:LO gpio_defaults[2] 18.921
|
||||
*END
|
||||
|
||||
*D_NET *9 0.000363376
|
||||
*CONN
|
||||
*P gpio_defaults[3] O
|
||||
*I *71:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[3] 0.000181688
|
||||
2 *71:LO 0.000181688
|
||||
3 gpio_defaults[3] gpio_defaults[4] 0
|
||||
4 gpio_defaults[2] gpio_defaults[3] 0
|
||||
*RES
|
||||
1 *71:LO gpio_defaults[3] 17.8118
|
||||
*END
|
||||
|
||||
*D_NET *10 0.000236028
|
||||
*CONN
|
||||
*P gpio_defaults[4] O
|
||||
*I *72:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[4] 0.000118014
|
||||
2 *72:LO 0.000118014
|
||||
3 gpio_defaults[4] gpio_defaults[5] 0
|
||||
4 gpio_defaults[3] gpio_defaults[4] 0
|
||||
*RES
|
||||
1 *72:LO gpio_defaults[4] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *11 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[5] O
|
||||
*I *73:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[5] 0.000115448
|
||||
2 *73:LO 0.000115448
|
||||
3 gpio_defaults[5] gpio_defaults[6] 0
|
||||
4 gpio_defaults[4] gpio_defaults[5] 0
|
||||
*RES
|
||||
1 *73:LO gpio_defaults[5] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *12 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[6] O
|
||||
*I *74:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[6] 0.000115448
|
||||
2 *74:LO 0.000115448
|
||||
3 gpio_defaults[6] gpio_defaults[7] 0
|
||||
4 gpio_defaults[5] gpio_defaults[6] 0
|
||||
*RES
|
||||
1 *74:LO gpio_defaults[6] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *13 0.00022764
|
||||
*CONN
|
||||
*P gpio_defaults[7] O
|
||||
*I *75:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[7] 0.00011382
|
||||
2 *75:LO 0.00011382
|
||||
3 gpio_defaults[7] gpio_defaults[8] 0
|
||||
4 gpio_defaults[6] gpio_defaults[7] 0
|
||||
*RES
|
||||
1 *75:LO gpio_defaults[7] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *14 0.000224385
|
||||
*CONN
|
||||
*P gpio_defaults[8] O
|
||||
*I *76:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[8] 0.000112192
|
||||
2 *76:LO 0.000112192
|
||||
3 gpio_defaults[8] gpio_defaults[9] 0
|
||||
4 gpio_defaults[7] gpio_defaults[8] 0
|
||||
*RES
|
||||
1 *76:LO gpio_defaults[8] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *15 0.00022764
|
||||
*CONN
|
||||
*P gpio_defaults[9] O
|
||||
*I *77:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[9] 0.00011382
|
||||
2 *77:LO 0.00011382
|
||||
3 gpio_defaults[10] gpio_defaults[9] 0
|
||||
4 gpio_defaults[8] gpio_defaults[9] 0
|
||||
*RES
|
||||
1 *77:LO gpio_defaults[9] 16.5338
|
||||
*END
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "gpio_logic_high"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*1 gpio_logic1
|
||||
*2 FILLER_0_3
|
||||
*3 FILLER_0_7
|
||||
*4 FILLER_0_9
|
||||
*5 FILLER_1_11
|
||||
*6 FILLER_1_3
|
||||
*7 FILLER_2_3
|
||||
*8 FILLER_2_7
|
||||
*9 FILLER_2_9
|
||||
*10 FILLER_3_3
|
||||
*11 FILLER_4_3
|
||||
*12 FILLER_4_7
|
||||
*13 FILLER_4_9
|
||||
*14 PHY_0
|
||||
*15 PHY_1
|
||||
*16 PHY_2
|
||||
*17 PHY_3
|
||||
*18 PHY_4
|
||||
*19 PHY_5
|
||||
*20 PHY_6
|
||||
*21 PHY_7
|
||||
*22 PHY_8
|
||||
*23 PHY_9
|
||||
*24 TAP_10
|
||||
*25 TAP_11
|
||||
*26 TAP_12
|
||||
*27 gpio_logic_high
|
||||
|
||||
*PORTS
|
||||
gpio_logic1 O
|
||||
|
||||
*D_NET *1 0.000513616
|
||||
*CONN
|
||||
*P gpio_logic1 O
|
||||
*I *27:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_logic1 0.000256808
|
||||
2 *27:HI 0.000256808
|
||||
*RES
|
||||
1 *27:HI gpio_logic1 21.9631
|
||||
*END
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,204 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "mgmt_protect_hv"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*1 mprj2_vdd_logic1
|
||||
*2 mprj_vdd_logic1
|
||||
*9 mprj2_vdd_logic1_h
|
||||
*10 mprj_vdd_logic1_h
|
||||
*11 mprj2_logic_high_hvl
|
||||
*12 mprj2_logic_high_lv
|
||||
*13 mprj_logic_high_hvl
|
||||
*14 mprj_logic_high_lv
|
||||
*15 FILLER_0_0
|
||||
*16 FILLER_0_8
|
||||
*17 FILLER_0_16
|
||||
*18 FILLER_0_24
|
||||
*19 FILLER_0_32
|
||||
*20 FILLER_0_40
|
||||
*21 FILLER_0_48
|
||||
*22 FILLER_0_56
|
||||
*23 FILLER_0_64
|
||||
*24 FILLER_0_72
|
||||
*25 FILLER_0_80
|
||||
*26 FILLER_0_88
|
||||
*27 FILLER_0_96
|
||||
*28 FILLER_0_104
|
||||
*29 FILLER_0_112
|
||||
*30 FILLER_0_120
|
||||
*31 FILLER_0_128
|
||||
*32 FILLER_0_136
|
||||
*33 FILLER_0_144
|
||||
*34 FILLER_0_152
|
||||
*35 FILLER_0_160
|
||||
*36 FILLER_0_168
|
||||
*37 FILLER_0_176
|
||||
*38 FILLER_0_184
|
||||
*39 FILLER_0_192
|
||||
*40 FILLER_0_200
|
||||
*41 FILLER_0_208
|
||||
*42 FILLER_0_216
|
||||
*43 FILLER_0_224
|
||||
*44 FILLER_0_232
|
||||
*45 FILLER_0_240
|
||||
*46 FILLER_0_248
|
||||
*47 FILLER_0_256
|
||||
*48 FILLER_0_264
|
||||
*49 FILLER_0_272
|
||||
*50 FILLER_0_280
|
||||
*51 FILLER_0_288
|
||||
*52 FILLER_0_296
|
||||
*53 FILLER_0_300
|
||||
*54 FILLER_1_0
|
||||
*55 FILLER_1_8
|
||||
*56 FILLER_1_16
|
||||
*57 FILLER_1_24
|
||||
*58 FILLER_1_32
|
||||
*59 FILLER_1_40
|
||||
*60 FILLER_1_48
|
||||
*61 FILLER_1_56
|
||||
*62 FILLER_1_64
|
||||
*63 FILLER_1_72
|
||||
*64 FILLER_1_80
|
||||
*65 FILLER_1_88
|
||||
*66 FILLER_1_92
|
||||
*67 FILLER_1_94
|
||||
*68 FILLER_1_117
|
||||
*69 FILLER_1_125
|
||||
*70 FILLER_1_133
|
||||
*71 FILLER_1_141
|
||||
*72 FILLER_1_149
|
||||
*73 FILLER_1_157
|
||||
*74 FILLER_1_165
|
||||
*75 FILLER_1_189
|
||||
*76 FILLER_1_197
|
||||
*77 FILLER_1_205
|
||||
*78 FILLER_1_213
|
||||
*79 FILLER_1_221
|
||||
*80 FILLER_1_229
|
||||
*81 FILLER_1_237
|
||||
*82 FILLER_1_245
|
||||
*83 FILLER_1_253
|
||||
*84 FILLER_1_261
|
||||
*85 FILLER_1_269
|
||||
*86 FILLER_1_277
|
||||
*87 FILLER_1_285
|
||||
*88 FILLER_1_293
|
||||
*89 FILLER_1_301
|
||||
*90 FILLER_2_0
|
||||
*91 FILLER_2_8
|
||||
*92 FILLER_2_16
|
||||
*93 FILLER_2_24
|
||||
*94 FILLER_2_32
|
||||
*95 FILLER_2_40
|
||||
*96 FILLER_2_48
|
||||
*97 FILLER_2_56
|
||||
*98 FILLER_2_64
|
||||
*99 FILLER_2_72
|
||||
*100 FILLER_2_80
|
||||
*101 FILLER_2_88
|
||||
*102 FILLER_2_96
|
||||
*103 FILLER_2_117
|
||||
*104 FILLER_2_125
|
||||
*105 FILLER_2_133
|
||||
*106 FILLER_2_141
|
||||
*107 FILLER_2_149
|
||||
*108 FILLER_2_157
|
||||
*109 FILLER_2_165
|
||||
*110 FILLER_2_169
|
||||
*111 FILLER_2_171
|
||||
*112 FILLER_2_189
|
||||
*113 FILLER_2_197
|
||||
*114 FILLER_2_205
|
||||
*115 FILLER_2_213
|
||||
*116 FILLER_2_221
|
||||
*117 FILLER_2_229
|
||||
*118 FILLER_2_237
|
||||
*119 FILLER_2_245
|
||||
*120 FILLER_2_253
|
||||
*121 FILLER_2_261
|
||||
*122 FILLER_2_269
|
||||
*123 FILLER_2_277
|
||||
*124 FILLER_2_285
|
||||
*125 FILLER_2_293
|
||||
*126 FILLER_2_301
|
||||
|
||||
*PORTS
|
||||
mprj2_vdd_logic1 O
|
||||
mprj_vdd_logic1 O
|
||||
|
||||
*D_NET *1 0.00894054
|
||||
*CONN
|
||||
*P mprj2_vdd_logic1 O
|
||||
*I *12:X O *D sky130_fd_sc_hvl__lsbufhv2lv_1
|
||||
*CAP
|
||||
1 mprj2_vdd_logic1 0.000164685
|
||||
2 *12:X 0.000136495
|
||||
3 *1:9 0.00433377
|
||||
4 *1:8 0.00430558
|
||||
5 *1:9 *2:5 0
|
||||
*RES
|
||||
1 *12:X *1:8 21.1315
|
||||
2 *1:8 *1:9 104.917
|
||||
3 *1:9 mprj2_vdd_logic1 10.6698
|
||||
*END
|
||||
|
||||
*D_NET *2 0.005901
|
||||
*CONN
|
||||
*P mprj_vdd_logic1 O
|
||||
*I *14:X O *D sky130_fd_sc_hvl__lsbufhv2lv_1
|
||||
*CAP
|
||||
1 mprj_vdd_logic1 0.000279428
|
||||
2 *14:X 0
|
||||
3 *2:5 0.00291451
|
||||
4 *2:4 0.00263509
|
||||
5 *2:5 *9:7 7.19686e-05
|
||||
6 *1:9 *2:5 0
|
||||
*RES
|
||||
1 *14:X *2:4 9.24915
|
||||
2 *2:4 *2:5 63.2489
|
||||
3 *2:5 mprj_vdd_logic1 14.285
|
||||
*END
|
||||
|
||||
*D_NET *9 0.00401189
|
||||
*CONN
|
||||
*I *12:A I *D sky130_fd_sc_hvl__lsbufhv2lv_1
|
||||
*I *11:HI O *D sky130_fd_sc_hvl__conb_1
|
||||
*CAP
|
||||
1 *12:A 0.000185088
|
||||
2 *11:HI 0
|
||||
3 *9:7 0.00194467
|
||||
4 *9:4 0.00175958
|
||||
5 *12:A *10:8 5.05783e-05
|
||||
6 *2:5 *9:7 7.19686e-05
|
||||
*RES
|
||||
1 *11:HI *9:4 9.24915
|
||||
2 *9:4 *9:7 47.4938
|
||||
3 *9:7 *12:A 17.9577
|
||||
*END
|
||||
|
||||
*D_NET *10 0.00370034
|
||||
*CONN
|
||||
*I *14:A I *D sky130_fd_sc_hvl__lsbufhv2lv_1
|
||||
*I *13:HI O *D sky130_fd_sc_hvl__conb_1
|
||||
*CAP
|
||||
1 *14:A 0.00172779
|
||||
2 *13:HI 9.70922e-05
|
||||
3 *10:8 0.00182488
|
||||
4 *12:A *10:8 5.05783e-05
|
||||
*RES
|
||||
1 *13:HI *10:8 20.6796
|
||||
2 *10:8 *14:A 48.192
|
||||
*END
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "mprj2_logic_high"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*1 HI
|
||||
*2 FILLER_0_109
|
||||
*3 FILLER_0_113
|
||||
*4 FILLER_0_125
|
||||
*5 FILLER_0_137
|
||||
*6 FILLER_0_141
|
||||
*7 FILLER_0_15
|
||||
*8 FILLER_0_153
|
||||
*9 FILLER_0_165
|
||||
*10 FILLER_0_169
|
||||
*11 FILLER_0_181
|
||||
*12 FILLER_0_193
|
||||
*13 FILLER_0_197
|
||||
*14 FILLER_0_209
|
||||
*15 FILLER_0_213
|
||||
*16 FILLER_0_27
|
||||
*17 FILLER_0_29
|
||||
*18 FILLER_0_3
|
||||
*19 FILLER_0_41
|
||||
*20 FILLER_0_53
|
||||
*21 FILLER_0_57
|
||||
*22 FILLER_0_69
|
||||
*23 FILLER_0_81
|
||||
*24 FILLER_0_85
|
||||
*25 FILLER_0_97
|
||||
*26 FILLER_1_107
|
||||
*27 FILLER_1_111
|
||||
*28 FILLER_1_113
|
||||
*29 FILLER_1_125
|
||||
*30 FILLER_1_137
|
||||
*31 FILLER_1_141
|
||||
*32 FILLER_1_15
|
||||
*33 FILLER_1_153
|
||||
*34 FILLER_1_165
|
||||
*35 FILLER_1_169
|
||||
*36 FILLER_1_181
|
||||
*37 FILLER_1_193
|
||||
*38 FILLER_1_197
|
||||
*39 FILLER_1_209
|
||||
*40 FILLER_1_213
|
||||
*41 FILLER_1_27
|
||||
*42 FILLER_1_29
|
||||
*43 FILLER_1_3
|
||||
*44 FILLER_1_41
|
||||
*45 FILLER_1_53
|
||||
*46 FILLER_1_57
|
||||
*47 FILLER_1_69
|
||||
*48 FILLER_1_81
|
||||
*49 FILLER_1_85
|
||||
*50 FILLER_1_91
|
||||
*51 FILLER_1_95
|
||||
*52 PHY_0
|
||||
*53 PHY_1
|
||||
*54 PHY_2
|
||||
*55 PHY_3
|
||||
*56 TAP_10
|
||||
*57 TAP_11
|
||||
*58 TAP_12
|
||||
*59 TAP_13
|
||||
*60 TAP_14
|
||||
*61 TAP_15
|
||||
*62 TAP_16
|
||||
*63 TAP_17
|
||||
*64 TAP_4
|
||||
*65 TAP_5
|
||||
*66 TAP_6
|
||||
*67 TAP_7
|
||||
*68 TAP_8
|
||||
*69 TAP_9
|
||||
*70 inst
|
||||
|
||||
*PORTS
|
||||
HI O
|
||||
|
||||
*D_NET *1 0.00667596
|
||||
*CONN
|
||||
*P HI O
|
||||
*I *70:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 HI 0.00333798
|
||||
2 *70:HI 0.00333798
|
||||
*RES
|
||||
1 *70:HI HI 24.0614
|
||||
*END
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,65 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "xres_buf"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*1 A
|
||||
*2 X
|
||||
*3 lvlshiftdown
|
||||
*4 ANTENNA_lvlshiftdown_A
|
||||
*5 FILLER_0_0
|
||||
*6 FILLER_0_8
|
||||
*7 FILLER_0_16
|
||||
*8 FILLER_0_24
|
||||
*9 FILLER_0_28
|
||||
*10 FILLER_0_30
|
||||
*11 FILLER_1_0
|
||||
*12 FILLER_1_8
|
||||
*13 FILLER_1_12
|
||||
*14 FILLER_1_30
|
||||
*15 FILLER_2_0
|
||||
*16 FILLER_2_8
|
||||
*17 FILLER_2_10
|
||||
*18 FILLER_2_30
|
||||
|
||||
*PORTS
|
||||
A I
|
||||
X O
|
||||
|
||||
*D_NET *1 0.000990495
|
||||
*CONN
|
||||
*P A I
|
||||
*I *3:A I *D sky130_fd_sc_hvl__lsbufhv2lv_1
|
||||
*I *4:DIODE I *D sky130_fd_sc_hvl__diode_2
|
||||
*CAP
|
||||
1 A 0.000411399
|
||||
2 *3:A 0
|
||||
3 *4:DIODE 8.38483e-05
|
||||
4 *1:12 0.000495247
|
||||
*RES
|
||||
1 A *1:12 14.3355
|
||||
2 *1:12 *4:DIODE 11.1541
|
||||
3 *1:12 *3:A 9.24915
|
||||
*END
|
||||
|
||||
*D_NET *2 0.00147572
|
||||
*CONN
|
||||
*P X O
|
||||
*I *3:X O *D sky130_fd_sc_hvl__lsbufhv2lv_1
|
||||
*CAP
|
||||
1 X 0.00073786
|
||||
2 *3:X 0.00073786
|
||||
*RES
|
||||
1 *3:X X 32.9072
|
||||
*END
|
||||
Loading…
Reference in New Issue