Add clock redirect test

verilog/dv/cocotb/caravel_tests.py

@@ -27,6 +27,7 @@ from tests.bitbang.bitbang_tests_cpu import *
 from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import *
 from tests.housekeeping.housekeeping_spi.user_pass_thru import *
 from tests.housekeeping.general.pll import *
+from tests.housekeeping.general.sys_ctrl import *
 from tests.temp_partial_test.partial import *
 from tests.hello_world.helloWorld import *
 from tests.cpu.cpu_stress import *

verilog/dv/cocotb/tests.json

@@ -220,5 +220,12 @@
             "GL":["r_gl","nightly","weekly","tape_out"],
             "GL_SDF":["r_sdf","weekly","tape_out"],
             "description":"Check pll diffrent configuration"}
+
+        ,"clock_redirect" :{"level":0, 
+            "SW":true,
+            "RTL":["r_rtl","setup","nightly","weekly","tape_out"],
+            "GL":["r_gl","nightly","weekly","tape_out"],
+            "GL_SDF":["r_sdf","weekly","tape_out"],
+            "description":"check clock redirect is working as expected"}
     }
 }

verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c

@@ -0,0 +1,18 @@
+#include <defs.h>
+#include <stub.c>
+// --------------------------------------------------------
+
+void main(){
+    reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
+    reg_debug_1  = 0x0;
+    reg_debug_2  = 0x0;
+
+    /* Monitor pins must be set to output */
+    reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_debug_1 =0xAA;
+    return; 
+    }

verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py

@@ -0,0 +1,88 @@
+import random
+import cocotb
+from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
+import cocotb.log
+from cpu import RiskV
+from defsParser import Regs
+from cocotb.result import TestSuccess
+from tests.common_functions.test_functions import *
+from tests.bitbang.bitbang_functions import *
+from caravel import GPIO_MODE
+from cocotb.binary import BinaryValue
+from tests.housekeeping.housekeeping_spi.spi_access_functions import *
+
+reg = Regs()
+caravel_clock = 0
+user_clock = 0
+core_clock = 0
+@cocotb.test()
+@repot_test
+async def clock_redirect(dut):
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
+    cpu = RiskV(dut)
+    cpu.cpu_force_reset()
+    cpu.cpu_release_reset()
+    # calculate core clock
+    await  cocotb.start(calculate_clk_period(dut.uut.clock,"core clock"))  
+    await ClockCycles(caravelEnv.clk,110)
+    cocotb.log.info(f"[TEST]  core clock requency = {round(1000000/core_clock,2)} MHz period = {core_clock}ps")
+    await wait_reg1(cpu,caravelEnv,0xAa)
+    # check clk redirect working 
+    #user clock
+    clock_name = "user clock"
+    await write_reg_spi(caravelEnv,0x1b,0x0) # disable user clock output redirect
+    await  cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))  
+    await ClockCycles(caravelEnv.clk,110)
+    if user_clock  != 0:
+        cocotb.log.error(f"[TEST] Error: {clock_name} is directed while clk2_output_dest is disabled")
+    else: 
+        cocotb.log.info(f"[TEST] Pass: {clock_name} has not directed when reg clk2_output_dest is disabled")
+
+    await write_reg_spi(caravelEnv,0x1b,0x4) # enable user clock output redirect
+    await  cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))  
+    await ClockCycles(caravelEnv.clk,110)
+    if user_clock  != core_clock:
+        cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {user_clock} and core clock = {core_clock}")
+    else: 
+        cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
+
+    #caravel clock
+    clock_name = "caravel clock"
+    await write_reg_spi(caravelEnv,0x1b,0x0) # disable caravel clock output redirect
+    await  cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))  
+    await ClockCycles(caravelEnv.clk,110)
+    if caravel_clock  != 0:
+        cocotb.log.error(f"[TEST] Error: {clock_name} is directed while clk2_output_dest is disabled")
+    else: 
+        cocotb.log.info(f"[TEST] Pass: {clock_name} has not directed when reg clk2_output_dest is disabled")
+
+    await write_reg_spi(caravelEnv,0x1b,0x4) # enable caravel clock output redirect
+    await  cocotb.start(calculate_clk_period(dut.bin15_monitor,clock_name))  
+    await ClockCycles(caravelEnv.clk,110)
+    if caravel_clock  != core_clock:
+        cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {caravel_clock} and core clock = {core_clock}")
+    else: 
+        cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
+
+
+async def calculate_clk_period(clk,name):
+    await RisingEdge(clk)
+    initial_time = cocotb.simulator.get_sim_time()
+    initial_time = (initial_time[0] <<32) | (initial_time[1])
+    for i in range(100):
+        await RisingEdge(clk)
+    end_time = cocotb.simulator.get_sim_time()
+    end_time = (end_time[0] <<32) | (end_time[1])
+    val = (end_time - initial_time) / 100
+    cocotb.log.debug(f"[TEST] clock of {name} is {val}")
+    if name == "caravel clock":
+        global caravel_clock
+        caravel_clock = val
+    elif name == "user clock":
+        global user_clock
+        user_clock = val 
+    elif name == "core clock":
+        global core_clock
+        core_clock = val         
+    return val
+