Merge branch 'caravel-redesign-2' of https://github.com/efabless/caravel into caravel-redesign-2

This commit is contained in:
mo-hosni 2023-02-27 10:41:17 -08:00
commit 25ec1cb8eb
1 changed files with 2 additions and 0 deletions

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@ -24,6 +24,7 @@ f2242e1f295ee5efeacea51698f706a2cfd97c28 verilog/rtl/chip_io_alt.v
653b230c7cbf092a6210ba7820bc942f312e53f3 verilog/rtl/debug_regs.v
2a7b5d508735fd485f8adcb3f8766ea3830091c2 verilog/rtl/digital_pll.v
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
f59fbff4794516ddae686d0e9c785aafebdd2224 verilog/rtl/empty_macro.v
51d906134dabd5bcc9c84324f639230a76bf3d25 verilog/rtl/gpio_control_block.v
6aae2132de98430b8195c4f32a9da6329b86b024 verilog/rtl/gpio_defaults_block.v
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
@ -31,6 +32,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
45ea4a2d466d6d70e9e86011a62c1bd3f706ef99 verilog/rtl/gpio_signal_buffering_alt.v
7ba9d7552eb3bbe4c7c11e2b8464be3c09d91e0b verilog/rtl/housekeeping.v
34c6ab585986a00216c72f2f1fea0e5a8523867b verilog/rtl/housekeeping_spi.v
9fa366d3ac47b18c175131396248e7e7c81e3eb1 verilog/rtl/manual_power_connections.v
0a00fd77505b29c1367b2c21d0bbc940fc50ab01 verilog/rtl/mgmt_protect.v
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v