mirror of https://github.com/efabless/caravel.git
add bitbang_spi_o tests
This commit is contained in:
M0stafaRady
parent
199d5c0f5c
commit
1c48f527b8
|
|
@ -192,6 +192,12 @@ class RiskV:
|
||||||
def read_debug_reg2(self):
|
def read_debug_reg2(self):
|
||||||
return self.debug_hdl.debug_reg_2.value.integer
|
return self.debug_hdl.debug_reg_2.value.integer
|
||||||
|
|
||||||
|
# writing debug registers using backdoor because in GL cpu can't be disabled for now because of different netlist names
|
||||||
|
def write_debug_reg1_backdoor(self,data):
|
||||||
|
self.debug_hdl.debug_reg_1.value = data
|
||||||
|
def write_debug_reg2_backdoor(self,data):
|
||||||
|
self.debug_hdl.debug_reg_2.value = data
|
||||||
|
|
||||||
async def force_reset_fun(self):
|
async def force_reset_fun(self):
|
||||||
first_time_force = True
|
first_time_force = True
|
||||||
first_time_release = True
|
first_time_release = True
|
||||||
|
|
|
||||||
|
|
@ -12,7 +12,7 @@
|
||||||
03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
|
03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
|
||||||
17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
|
17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
|
||||||
73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
|
73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
|
||||||
13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00
|
13 06 46 69 63 0C B5 00 83 26 06 00 23 20 D5 00
|
||||||
13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00
|
13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00
|
||||||
93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00
|
93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00
|
||||||
6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30
|
6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30
|
||||||
|
|
@ -43,5 +43,77 @@ B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00
|
||||||
83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE
|
83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE
|
||||||
83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00
|
83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00
|
||||||
83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00
|
83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00
|
||||||
13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00
|
13 01 01 FE 23 2E 81 00 13 04 01 02 B7 47 00 F0
|
||||||
03 24 C1 00 13 01 01 01 67 80 00 00
|
93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30
|
||||||
|
93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF
|
||||||
|
23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00
|
||||||
|
13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B
|
||||||
|
37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26
|
||||||
|
93 87 07 0B 37 27 00 00 13 07 97 80 23 A0 E7 00
|
||||||
|
B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 97 80
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00
|
||||||
|
13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A
|
||||||
|
37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26
|
||||||
|
93 87 07 0A 37 27 00 00 13 07 97 80 23 A0 E7 00
|
||||||
|
B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 97 80
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00
|
||||||
|
13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 09
|
||||||
|
37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26
|
||||||
|
93 87 07 09 37 27 00 00 13 07 97 80 23 A0 E7 00
|
||||||
|
B7 07 00 26 93 87 C7 08 37 27 00 00 13 07 97 80
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 87 08 37 27 00 00
|
||||||
|
13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 08
|
||||||
|
37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26
|
||||||
|
93 87 07 08 37 27 00 00 13 07 97 80 23 A0 E7 00
|
||||||
|
B7 07 00 26 93 87 C7 07 37 27 00 00 13 07 97 80
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 87 07 37 27 00 00
|
||||||
|
13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 07
|
||||||
|
37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26
|
||||||
|
93 87 07 07 37 27 00 00 13 07 97 80 23 A0 E7 00
|
||||||
|
B7 07 00 26 93 87 C7 06 37 27 00 00 13 07 97 80
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 87 06 37 27 00 00
|
||||||
|
13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 06
|
||||||
|
37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26
|
||||||
|
93 87 07 06 37 27 00 00 13 07 97 80 23 A0 E7 00
|
||||||
|
B7 07 00 26 93 87 C7 05 37 27 00 00 13 07 97 80
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 87 05 37 27 00 00
|
||||||
|
13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 05
|
||||||
|
37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26
|
||||||
|
93 87 07 05 37 27 00 00 13 07 97 80 23 A0 E7 00
|
||||||
|
B7 07 00 26 93 87 C7 04 37 27 00 00 13 07 97 80
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00
|
||||||
|
13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 04
|
||||||
|
37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26
|
||||||
|
93 87 07 04 37 27 00 00 13 07 97 80 23 A0 E7 00
|
||||||
|
B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 97 80
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00
|
||||||
|
13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 03
|
||||||
|
37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26
|
||||||
|
93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00
|
||||||
|
B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 37 80
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00
|
||||||
|
13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02
|
||||||
|
37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 10 30
|
||||||
|
93 87 87 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00
|
||||||
|
B7 07 10 30 93 87 C7 FF 03 A7 07 00 93 07 F0 0F
|
||||||
|
E3 18 F7 FE B7 07 00 26 93 87 C7 00 23 A0 07 00
|
||||||
|
B7 07 00 26 93 87 07 01 23 A0 07 00 93 07 00 02
|
||||||
|
23 26 F4 FE 23 24 04 FE 6F 00 80 06 B7 07 00 26
|
||||||
|
93 87 07 01 03 27 C4 FE 23 A0 E7 00 13 07 50 02
|
||||||
|
83 27 84 FE 33 07 F7 40 B7 07 10 30 93 87 C7 FF
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 07 01 23 A0 07 00
|
||||||
|
B7 07 10 30 93 87 C7 FF 23 A0 07 00 83 27 C4 FE
|
||||||
|
93 D7 17 40 23 26 F4 FE 83 27 C4 FE 93 E7 07 02
|
||||||
|
23 26 F4 FE 83 27 84 FE 93 87 17 00 23 24 F4 FE
|
||||||
|
03 27 84 FE 93 07 40 00 E3 DA E7 F8 B7 07 00 80
|
||||||
|
23 26 F4 FE 23 24 04 FE 6F 00 80 08 B7 07 00 26
|
||||||
|
93 87 07 01 13 07 F0 03 23 A0 E7 00 B7 07 00 26
|
||||||
|
93 87 C7 00 03 27 C4 FE 23 A0 E7 00 13 07 00 02
|
||||||
|
83 27 84 FE 33 07 F7 40 B7 07 10 30 93 87 C7 FF
|
||||||
|
23 A0 E7 00 B7 07 00 26 93 87 07 01 23 A0 07 00
|
||||||
|
B7 07 00 26 93 87 C7 00 23 A0 07 00 B7 07 10 30
|
||||||
|
93 87 C7 FF 23 A0 07 00 83 27 C4 FE 93 D7 17 40
|
||||||
|
23 26 F4 FE 03 27 C4 FE B7 07 00 80 B3 67 F7 00
|
||||||
|
23 26 F4 FE 83 27 84 FE 93 87 17 00 23 24 F4 FE
|
||||||
|
03 27 84 FE 93 07 F0 01 E3 DA E7 F6 13 00 00 00
|
||||||
|
13 00 00 00 03 24 C1 01 13 01 01 02 67 80 00 00
|
||||||
|
|
|
||||||
|
|
@ -12,11 +12,11 @@
|
||||||
03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
|
03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
|
||||||
17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
|
17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
|
||||||
73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
|
73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
|
||||||
13 06 C6 3C 63 0C B5 00 83 26 06 00 23 20 D5 00
|
13 06 C6 41 63 0C B5 00 83 26 06 00 23 20 D5 00
|
||||||
13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00
|
13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00
|
||||||
93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00
|
93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00
|
||||||
6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30
|
6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30
|
||||||
EF 00 40 28 6F 00 00 00 13 01 01 FF 23 26 81 00
|
EF 00 40 2D 6F 00 00 00 13 01 01 FF 23 26 81 00
|
||||||
13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01
|
13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01
|
||||||
67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01
|
67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01
|
||||||
13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00
|
13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00
|
||||||
|
|
@ -48,14 +48,19 @@ E3 08 F7 FE B7 67 00 F0 93 87 07 80 03 47 F4 FE
|
||||||
83 27 C4 FE 13 87 17 00 23 26 E4 FE 83 C7 07 00
|
83 27 C4 FE 13 87 17 00 23 26 E4 FE 83 C7 07 00
|
||||||
13 85 07 00 EF F0 DF F6 83 27 C4 FE 83 C7 07 00
|
13 85 07 00 EF F0 DF F6 83 27 C4 FE 83 C7 07 00
|
||||||
E3 90 07 FE 13 00 00 00 13 00 00 00 83 20 C1 01
|
E3 90 07 FE 13 00 00 00 13 00 00 00 83 20 C1 01
|
||||||
03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE
|
03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FD
|
||||||
23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE
|
23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC
|
||||||
13 00 00 00 EF F0 9F EF 13 07 05 00 93 07 10 00
|
13 00 00 00 EF F0 9F EF 13 07 05 00 93 07 10 00
|
||||||
E3 0A F7 FE B7 67 00 F0 93 87 07 80 83 A7 07 00
|
E3 0A F7 FE B7 67 00 F0 93 87 07 80 83 A7 07 00
|
||||||
03 27 C4 FE 03 47 07 00 63 9C E7 00 B7 07 10 30
|
03 27 C4 FD 03 47 07 00 63 9C E7 00 B7 07 10 30
|
||||||
93 87 87 FF 13 07 B0 01 23 A0 E7 00 6F 00 40 01
|
93 87 87 FF 13 07 B0 01 23 A0 E7 00 6F 00 40 01
|
||||||
B7 07 10 30 93 87 87 FF 13 07 E0 01 23 A0 E7 00
|
B7 07 10 30 93 87 87 FF 13 07 E0 01 23 A0 E7 00
|
||||||
13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02
|
B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE
|
||||||
|
B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE
|
||||||
|
B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE
|
||||||
|
B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE
|
||||||
|
B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE
|
||||||
|
13 00 00 00 83 20 C1 02 03 24 81 02 13 01 01 03
|
||||||
67 80 00 00 13 01 01 FF 23 26 11 00 23 24 81 00
|
67 80 00 00 13 01 01 FF 23 26 11 00 23 24 81 00
|
||||||
13 04 01 01 B7 47 00 F0 93 87 07 80 13 07 10 00
|
13 04 01 01 B7 47 00 F0 93 87 07 80 13 07 10 00
|
||||||
23 A0 E7 00 B7 07 10 30 93 87 87 FF 23 A0 07 00
|
23 A0 E7 00 B7 07 10 30 93 87 87 FF 23 A0 07 00
|
||||||
|
|
@ -66,12 +71,12 @@ B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00
|
||||||
B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE
|
B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE
|
||||||
B7 67 00 F0 13 07 10 00 23 A0 E7 00 B7 07 10 30
|
B7 67 00 F0 13 07 10 00 23 A0 E7 00 B7 07 10 30
|
||||||
93 87 87 FF 13 07 A0 0A 23 A0 E7 00 B7 07 00 10
|
93 87 87 FF 13 07 A0 0A 23 A0 E7 00 B7 07 00 10
|
||||||
13 85 87 48 EF F0 9F EE B7 07 10 30 93 87 87 FF
|
13 85 87 4D EF F0 9F E9 B7 07 10 30 93 87 87 FF
|
||||||
13 07 B0 0B 23 A0 E7 00 B7 07 00 10 13 85 C7 48
|
13 07 B0 0B 23 A0 E7 00 B7 07 00 10 13 85 C7 4D
|
||||||
EF F0 DF EC B7 07 10 30 93 87 87 FF 13 07 C0 0C
|
EF F0 DF E7 B7 07 10 30 93 87 87 FF 13 07 C0 0C
|
||||||
23 A0 E7 00 B7 07 00 10 13 85 07 49 EF F0 1F EB
|
23 A0 E7 00 B7 07 00 10 13 85 07 4E EF F0 1F E6
|
||||||
13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01
|
13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01
|
||||||
67 80 00 00
|
67 80 00 00
|
||||||
@00000484
|
@000004D4
|
||||||
00 00 00 00 42 00 00 00 4D 00 00 00 41 00 00 00
|
00 00 00 00 42 00 00 00 4D 00 00 00 41 00 00 00
|
||||||
00 00 00 00
|
00 00 00 00
|
||||||
|
|
|
||||||
|
|
@ -64,12 +64,12 @@
|
||||||
"GL_SDF":["weekly","tape_out"],
|
"GL_SDF":["weekly","tape_out"],
|
||||||
"description":" configure gpio[0:37] as mgmt input using bitbang and check them"}
|
"description":" configure gpio[0:37] as mgmt input using bitbang and check them"}
|
||||||
|
|
||||||
,"bitbang_spi" :{"level":0,
|
,"bitbang_spi_o" :{"level":0,
|
||||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||||
"GL_SDF":["weekly","tape_out"],
|
"GL_SDF":["weekly","tape_out"],
|
||||||
"SW":false,
|
"SW":true,
|
||||||
"description":"Same as bitbang_no_cpu_all but configure the gpio using the SPI not the firmware"}
|
"description":"Same as bitbang_cpu_all but configure the gpio using the SPI not the firmware"}
|
||||||
|
|
||||||
,"hk_regs_wr_wb" :{"level":0,
|
,"hk_regs_wr_wb" :{"level":0,
|
||||||
"SW":false,
|
"SW":false,
|
||||||
|
|
|
||||||
|
|
@ -1,10 +0,0 @@
|
||||||
#include <defs.h>
|
|
||||||
#include <stub.c>
|
|
||||||
|
|
||||||
// Empty C code
|
|
||||||
|
|
||||||
void main()
|
|
||||||
{
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,78 @@
|
||||||
|
#include <defs.h>
|
||||||
|
#include <stub.c>
|
||||||
|
|
||||||
|
// Empty C code
|
||||||
|
|
||||||
|
void main()
|
||||||
|
{
|
||||||
|
int i,j;
|
||||||
|
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||||
|
reg_debug_1 = 0x0;
|
||||||
|
reg_debug_2 = 0x0;
|
||||||
|
|
||||||
|
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_4 = 0x1803;
|
||||||
|
reg_mprj_io_3 = 0x1803;
|
||||||
|
reg_mprj_io_2 = 0x1803;
|
||||||
|
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||||
|
|
||||||
|
reg_debug_1 = 0xFF; // finish configuration
|
||||||
|
while (reg_debug_2 != 0xFF); // finish bit bang
|
||||||
|
reg_mprj_datal = 0x0;
|
||||||
|
reg_mprj_datah = 0x0;
|
||||||
|
i = 0x20;
|
||||||
|
for (j = 0; j < 5; j++) {
|
||||||
|
reg_mprj_datah = i;
|
||||||
|
reg_debug_2 = 37-j;
|
||||||
|
reg_mprj_datah = 0x00000000;
|
||||||
|
reg_debug_2 = 0;
|
||||||
|
i >>=1;
|
||||||
|
i |= 0x20;
|
||||||
|
}
|
||||||
|
i = 0x80000000;
|
||||||
|
for (j = 0; j < 32; j++) {
|
||||||
|
reg_mprj_datah = 0x3f;
|
||||||
|
reg_mprj_datal = i;
|
||||||
|
reg_debug_2 = 32-j;
|
||||||
|
reg_mprj_datah = 0x00;
|
||||||
|
reg_mprj_datal = 0x00000000;
|
||||||
|
reg_debug_2 = 0;
|
||||||
|
i >>=1;
|
||||||
|
i |= 0x80000000;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -92,7 +92,7 @@ def shift(gpio,shift_type):
|
||||||
@cocotb.test()
|
@cocotb.test()
|
||||||
@repot_test
|
@repot_test
|
||||||
async def bitbang_cpu_all_01(dut):
|
async def bitbang_cpu_all_01(dut):
|
||||||
caravelEnv = await test_configure(dut,timeout_cycles=2863378)
|
caravelEnv,clock = await test_configure(dut,timeout_cycles=2863378)
|
||||||
cpu = RiskV(dut)
|
cpu = RiskV(dut)
|
||||||
cpu.cpu_force_reset()
|
cpu.cpu_force_reset()
|
||||||
cpu.cpu_release_reset()
|
cpu.cpu_release_reset()
|
||||||
|
|
@ -113,7 +113,7 @@ async def bitbang_cpu_all_01(dut):
|
||||||
@cocotb.test()
|
@cocotb.test()
|
||||||
@repot_test
|
@repot_test
|
||||||
async def bitbang_cpu_all_0011(dut):
|
async def bitbang_cpu_all_0011(dut):
|
||||||
caravelEnv = await test_configure(dut,timeout_cycles=5065204)
|
caravelEnv,clock = await test_configure(dut,timeout_cycles=5065204)
|
||||||
cpu = RiskV(dut)
|
cpu = RiskV(dut)
|
||||||
cpu.cpu_force_reset()
|
cpu.cpu_force_reset()
|
||||||
cpu.cpu_release_reset()
|
cpu.cpu_release_reset()
|
||||||
|
|
@ -134,7 +134,7 @@ async def bitbang_cpu_all_0011(dut):
|
||||||
@cocotb.test()
|
@cocotb.test()
|
||||||
@repot_test
|
@repot_test
|
||||||
async def bitbang_cpu_all_1100(dut):
|
async def bitbang_cpu_all_1100(dut):
|
||||||
caravelEnv = await test_configure(dut,timeout_cycles=10000000000)
|
caravelEnv,clock = await test_configure(dut,timeout_cycles=10000000000)
|
||||||
cpu = RiskV(dut)
|
cpu = RiskV(dut)
|
||||||
cpu.cpu_force_reset()
|
cpu.cpu_force_reset()
|
||||||
cpu.cpu_release_reset()
|
cpu.cpu_release_reset()
|
||||||
|
|
@ -174,7 +174,7 @@ def shift_2(gpio,shift_type):
|
||||||
@cocotb.test()
|
@cocotb.test()
|
||||||
@repot_test
|
@repot_test
|
||||||
async def bitbang_cpu_all_i(dut):
|
async def bitbang_cpu_all_i(dut):
|
||||||
caravelEnv = await test_configure(dut,timeout_cycles=1691295)
|
caravelEnv,clock = await test_configure(dut,timeout_cycles=1691295)
|
||||||
cpu = RiskV(dut)
|
cpu = RiskV(dut)
|
||||||
cpu.cpu_force_reset()
|
cpu.cpu_force_reset()
|
||||||
cpu.cpu_release_reset()
|
cpu.cpu_release_reset()
|
||||||
|
|
@ -198,3 +198,68 @@ async def bitbang_cpu_all_i(dut):
|
||||||
await wait_reg2(cpu,caravelEnv,0xFF)
|
await wait_reg2(cpu,caravelEnv,0xFF)
|
||||||
cocotb.log.info(f"[TEST] finish")
|
cocotb.log.info(f"[TEST] finish")
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI."""
|
||||||
|
@cocotb.test()
|
||||||
|
@repot_test
|
||||||
|
async def bitbang_spi_o(dut):
|
||||||
|
caravelEnv,clock = await test_configure(dut,timeout_cycles=639757)
|
||||||
|
cpu = RiskV(dut)
|
||||||
|
cpu.cpu_force_reset()
|
||||||
|
cpu.cpu_release_reset()
|
||||||
|
|
||||||
|
await wait_reg1(cpu,caravelEnv,0xFF) # wait for housekeeping registers configured
|
||||||
|
#Configure all as output except reg_mprj_io_3
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 18 and 19
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 17 and 20
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 16 and 21
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 15 and 22
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 14 and 23
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 13 and 24
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 12 and 25
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 11 and 26
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 10 and 27
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 9 and 28
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 8 and 29
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 7 and 30
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 6 and 31
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 5 and 32
|
||||||
|
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 4 and 33
|
||||||
|
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 3 and 34
|
||||||
|
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 2 and 35
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 1 and 36
|
||||||
|
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 0 and 37
|
||||||
|
await load_spi(caravelEnv) # load
|
||||||
|
|
||||||
|
cpu.write_debug_reg2_backdoor(0xFF)
|
||||||
|
cocotb.log.info("[TEST] finish configuring using bitbang")
|
||||||
|
i= 0x20
|
||||||
|
for j in range(5):
|
||||||
|
await wait_reg2(cpu,caravelEnv,37-j)
|
||||||
|
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} j = {j}')
|
||||||
|
if caravelEnv.monitor_gpio((37,5)).integer != i << 27:
|
||||||
|
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,5))} instead of {bin(i << 28)}')
|
||||||
|
await wait_reg2(cpu,caravelEnv,0)
|
||||||
|
if caravelEnv.monitor_gpio((37,5)).integer != 0:
|
||||||
|
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}')
|
||||||
|
i = i >> 1
|
||||||
|
i |= 0x20
|
||||||
|
|
||||||
|
i= 0x80000000
|
||||||
|
for j in range(32):
|
||||||
|
await wait_reg2(cpu,caravelEnv,32-j)
|
||||||
|
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} j = {j}')
|
||||||
|
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||||
|
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
|
||||||
|
if caravelEnv.monitor_gpio((31,5)).integer != i>>5 :
|
||||||
|
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
|
||||||
|
await wait_reg2(cpu,caravelEnv,0)
|
||||||
|
if caravelEnv.monitor_gpio((37,5)).integer != 0:
|
||||||
|
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}')
|
||||||
|
|
||||||
|
i = i >> 1
|
||||||
|
i |= 0x80000000
|
||||||
|
|
||||||
|
|
||||||
|
await ClockCycles(caravelEnv.clk, 10)
|
||||||
Loading…
Reference in New Issue