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add signoff results for `digital_pll`: 

- signoff summary report
- DRC and LVS reports
- STA timing reports for all corners
- generated lib files for all corners
- generated sdf files for all corners
This commit is contained in:
Passant 2022-10-19 07:05:38 -07:00
parent 8297906630
commit 19ce4a5906
78 changed files with 217080 additions and 54954 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6106
signoff/digital_pll/primetime-signoff/lib/max/digital_pll.ff.lib Normal file
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6106
signoff/digital_pll/primetime-signoff/lib/max/digital_pll.ss.lib Normal file
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6106
signoff/digital_pll/primetime-signoff/lib/max/digital_pll.tt.lib Normal file
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6106
signoff/digital_pll/primetime-signoff/lib/min/digital_pll.ff.lib Normal file
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6106
signoff/digital_pll/primetime-signoff/lib/min/digital_pll.ss.lib Normal file
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6106
signoff/digital_pll/primetime-signoff/lib/min/digital_pll.tt.lib Normal file
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6106
signoff/digital_pll/primetime-signoff/lib/nom/digital_pll.ff.lib Normal file
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6106
signoff/digital_pll/primetime-signoff/lib/nom/digital_pll.ss.lib Normal file
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6106
signoff/digital_pll/primetime-signoff/lib/nom/digital_pll.tt.lib Normal file
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13
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.ff-all_viol.rpt Normal file
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****************************************
Report : constraint
-all_violators
-path slack_only
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:36:37 2022
****************************************
1

101
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.ff-coverage.rpt Normal file
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****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:36:37 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
hold 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
recovery 23 0 ( 0%) 0 ( 0%) 23 (100%)
removal 23 0 ( 0%) 0 ( 0%) 23 (100%)
min_pulse_width 69 46 ( 67%) 0 ( 0%) 23 ( 33%)
out_setup 2 0 ( 0%) 0 ( 0%) 2 (100%)
out_hold 2 0 ( 0%) 0 ( 0%) 2 (100%)
--------------------------------------------------------------------------------
All Checks 165 90 ( 55%) 0 ( 0%) 75 ( 45%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_470_/D CLK(rise) pll_control_clock hold untested no_startpoint_clock
_470_/D CLK(rise) pll_control_clock setup untested no_startpoint_clock
_470_/RESET_B(low) - - min_pulse_width untested no_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_472_/RESET_B(low) - - min_pulse_width untested no_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_471_/RESET_B(low) - - min_pulse_width untested no_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_456_/RESET_B(low) - - min_pulse_width untested no_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_475_/RESET_B(low) - - min_pulse_width untested no_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_476_/RESET_B(low) - - min_pulse_width untested no_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_462_/RESET_B(low) - - min_pulse_width untested no_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_474_/RESET_B(low) - - min_pulse_width untested no_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_457_/RESET_B(low) - - min_pulse_width untested no_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_473_/RESET_B(low) - - min_pulse_width untested no_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_477_/RESET_B(low) - - min_pulse_width untested no_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_461_/RESET_B(low) - - min_pulse_width untested no_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_460_/RESET_B(low) - - min_pulse_width untested no_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_466_/RESET_B(low) - - min_pulse_width untested no_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_467_/RESET_B(low) - - min_pulse_width untested no_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_468_/RESET_B(low) - - min_pulse_width untested no_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_464_/RESET_B(low) - - min_pulse_width untested no_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_469_/RESET_B(low) - - min_pulse_width untested no_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
clockp[0] - - out_hold untested no_endpoint_clock
clockp[0] - - out_setup untested no_endpoint_clock
clockp[1] - - out_hold untested no_endpoint_clock
clockp[1] - - out_setup untested no_endpoint_clock
1

11
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.ff-global.rpt Normal file
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****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:36:37 2022
****************************************
1

3615
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.ff-max_timing.rpt Normal file
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7297
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.ff-min_timing.rpt Normal file
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File diff suppressed because it is too large Load Diff

30
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.ss-all_viol.rpt Normal file
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****************************************
Report : constraint
-all_violators
-path slack_only
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:42 2022
****************************************
max_transition
Required Actual
Pin Transition Transition Slack
-----------------------------------------------------------------
ringosc.iss.reseten0/Z 0.7500 1.8259 -1.0759 (VIOLATED)
ringosc.ibufp00/A 0.7500 1.8241 -1.0741 (VIOLATED)
ANTENNA_ringosc.ibufp00_A/DIODE 0.7500 1.8241 -1.0741 (VIOLATED)
ringosc.dstage[0].id.delaybuf0/A 0.7500 1.8237 -1.0737 (VIOLATED)
ANTENNA_ringosc.dstage[0].id.delaybuf0_A/DIODE 0.7500 1.8237 -1.0737 (VIOLATED)
ringosc.iss.delayen0/Z 0.7500 1.0418 -0.2918 (VIOLATED)
ringosc.dstage[11].id.delayen0/Z 0.7500 1.0416 -0.2916 (VIOLATED)
ringosc.iss.delayenb0/A 0.7500 1.0401 -0.2901 (VIOLATED)
ringosc.iss.delayenb1/A 0.7500 1.0398 -0.2898 (VIOLATED)
ringosc.iss.delaybuf0/A 0.7500 1.0396 -0.2896 (VIOLATED)
1

101
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.ss-coverage.rpt Normal file
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****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:42 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
hold 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
recovery 23 0 ( 0%) 0 ( 0%) 23 (100%)
removal 23 0 ( 0%) 0 ( 0%) 23 (100%)
min_pulse_width 69 46 ( 67%) 0 ( 0%) 23 ( 33%)
out_setup 2 0 ( 0%) 0 ( 0%) 2 (100%)
out_hold 2 0 ( 0%) 0 ( 0%) 2 (100%)
--------------------------------------------------------------------------------
All Checks 165 90 ( 55%) 0 ( 0%) 75 ( 45%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_470_/D CLK(rise) pll_control_clock hold untested no_startpoint_clock
_470_/D CLK(rise) pll_control_clock setup untested no_startpoint_clock
_470_/RESET_B(low) - - min_pulse_width untested no_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_472_/RESET_B(low) - - min_pulse_width untested no_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_471_/RESET_B(low) - - min_pulse_width untested no_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_456_/RESET_B(low) - - min_pulse_width untested no_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_475_/RESET_B(low) - - min_pulse_width untested no_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_476_/RESET_B(low) - - min_pulse_width untested no_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_462_/RESET_B(low) - - min_pulse_width untested no_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_474_/RESET_B(low) - - min_pulse_width untested no_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_457_/RESET_B(low) - - min_pulse_width untested no_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_473_/RESET_B(low) - - min_pulse_width untested no_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_477_/RESET_B(low) - - min_pulse_width untested no_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_461_/RESET_B(low) - - min_pulse_width untested no_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_460_/RESET_B(low) - - min_pulse_width untested no_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_466_/RESET_B(low) - - min_pulse_width untested no_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_467_/RESET_B(low) - - min_pulse_width untested no_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_468_/RESET_B(low) - - min_pulse_width untested no_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_464_/RESET_B(low) - - min_pulse_width untested no_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_469_/RESET_B(low) - - min_pulse_width untested no_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
clockp[0] - - out_hold untested no_endpoint_clock
clockp[0] - - out_setup untested no_endpoint_clock
clockp[1] - - out_hold untested no_endpoint_clock
clockp[1] - - out_setup untested no_endpoint_clock
1

11
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.ss-global.rpt Normal file
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****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:42 2022
****************************************
1

8509
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.ss-max_timing.rpt Normal file
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File diff suppressed because it is too large Load Diff

7305
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.ss-min_timing.rpt Normal file
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File diff suppressed because it is too large Load Diff

25
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.tt-all_viol.rpt Normal file
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****************************************
Report : constraint
-all_violators
-path slack_only
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:00 2022
****************************************
max_transition
Required Actual
Pin Transition Transition Slack
-----------------------------------------------------------------
ringosc.ibufp00/A 0.7500 0.7926 -0.0426 (VIOLATED)
ANTENNA_ringosc.ibufp00_A/DIODE 0.7500 0.7926 -0.0426 (VIOLATED)
ringosc.dstage[0].id.delaybuf0/A 0.7500 0.7922 -0.0422 (VIOLATED)
ANTENNA_ringosc.dstage[0].id.delaybuf0_A/DIODE 0.7500 0.7922 -0.0422 (VIOLATED)
ringosc.iss.reseten0/Z 0.7500 0.7912 -0.0412 (VIOLATED)
1

101
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.tt-coverage.rpt Normal file
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****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:00 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
hold 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
recovery 23 0 ( 0%) 0 ( 0%) 23 (100%)
removal 23 0 ( 0%) 0 ( 0%) 23 (100%)
min_pulse_width 69 46 ( 67%) 0 ( 0%) 23 ( 33%)
out_setup 2 0 ( 0%) 0 ( 0%) 2 (100%)
out_hold 2 0 ( 0%) 0 ( 0%) 2 (100%)
--------------------------------------------------------------------------------
All Checks 165 90 ( 55%) 0 ( 0%) 75 ( 45%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_470_/D CLK(rise) pll_control_clock hold untested no_startpoint_clock
_470_/D CLK(rise) pll_control_clock setup untested no_startpoint_clock
_470_/RESET_B(low) - - min_pulse_width untested no_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_472_/RESET_B(low) - - min_pulse_width untested no_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_471_/RESET_B(low) - - min_pulse_width untested no_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_456_/RESET_B(low) - - min_pulse_width untested no_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_475_/RESET_B(low) - - min_pulse_width untested no_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_476_/RESET_B(low) - - min_pulse_width untested no_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_462_/RESET_B(low) - - min_pulse_width untested no_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_474_/RESET_B(low) - - min_pulse_width untested no_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_457_/RESET_B(low) - - min_pulse_width untested no_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_473_/RESET_B(low) - - min_pulse_width untested no_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_477_/RESET_B(low) - - min_pulse_width untested no_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_461_/RESET_B(low) - - min_pulse_width untested no_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_460_/RESET_B(low) - - min_pulse_width untested no_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_466_/RESET_B(low) - - min_pulse_width untested no_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_467_/RESET_B(low) - - min_pulse_width untested no_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_468_/RESET_B(low) - - min_pulse_width untested no_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_464_/RESET_B(low) - - min_pulse_width untested no_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_469_/RESET_B(low) - - min_pulse_width untested no_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
clockp[0] - - out_hold untested no_endpoint_clock
clockp[0] - - out_setup untested no_endpoint_clock
clockp[1] - - out_hold untested no_endpoint_clock
clockp[1] - - out_setup untested no_endpoint_clock
1

11
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.tt-global.rpt Normal file
View File

@ -0,0 +1,11 @@
****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:00 2022
****************************************
1

3643
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.tt-max_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

7289
signoff/digital_pll/primetime-signoff/reports/max/digital_pll.tt-min_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

13
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.ff-all_viol.rpt Normal file
View File

@ -0,0 +1,13 @@
****************************************
Report : constraint
-all_violators
-path slack_only
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:36:57 2022
****************************************
1

101
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.ff-coverage.rpt Normal file
View File

@ -0,0 +1,101 @@
****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:36:57 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
hold 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
recovery 23 0 ( 0%) 0 ( 0%) 23 (100%)
removal 23 0 ( 0%) 0 ( 0%) 23 (100%)
min_pulse_width 69 46 ( 67%) 0 ( 0%) 23 ( 33%)
out_setup 2 0 ( 0%) 0 ( 0%) 2 (100%)
out_hold 2 0 ( 0%) 0 ( 0%) 2 (100%)
--------------------------------------------------------------------------------
All Checks 165 90 ( 55%) 0 ( 0%) 75 ( 45%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_470_/D CLK(rise) pll_control_clock hold untested no_startpoint_clock
_470_/D CLK(rise) pll_control_clock setup untested no_startpoint_clock
_470_/RESET_B(low) - - min_pulse_width untested no_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_472_/RESET_B(low) - - min_pulse_width untested no_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_471_/RESET_B(low) - - min_pulse_width untested no_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_456_/RESET_B(low) - - min_pulse_width untested no_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_475_/RESET_B(low) - - min_pulse_width untested no_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_476_/RESET_B(low) - - min_pulse_width untested no_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_462_/RESET_B(low) - - min_pulse_width untested no_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_474_/RESET_B(low) - - min_pulse_width untested no_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_457_/RESET_B(low) - - min_pulse_width untested no_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_473_/RESET_B(low) - - min_pulse_width untested no_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_477_/RESET_B(low) - - min_pulse_width untested no_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_461_/RESET_B(low) - - min_pulse_width untested no_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_460_/RESET_B(low) - - min_pulse_width untested no_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_466_/RESET_B(low) - - min_pulse_width untested no_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_467_/RESET_B(low) - - min_pulse_width untested no_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_468_/RESET_B(low) - - min_pulse_width untested no_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_464_/RESET_B(low) - - min_pulse_width untested no_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_469_/RESET_B(low) - - min_pulse_width untested no_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
clockp[0] - - out_hold untested no_endpoint_clock
clockp[0] - - out_setup untested no_endpoint_clock
clockp[1] - - out_hold untested no_endpoint_clock
clockp[1] - - out_setup untested no_endpoint_clock
1

11
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.ff-global.rpt Normal file
View File

@ -0,0 +1,11 @@
****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:36:57 2022
****************************************
1

3615
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.ff-max_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

7295
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.ff-min_timing.rpt Normal file
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File diff suppressed because it is too large Load Diff

30
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.ss-all_viol.rpt Normal file
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@ -0,0 +1,30 @@
****************************************
Report : constraint
-all_violators
-path slack_only
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:55 2022
****************************************
max_transition
Required Actual
Pin Transition Transition Slack
-----------------------------------------------------------------
ringosc.iss.reseten0/Z 0.7500 1.6569 -0.9069 (VIOLATED)
ANTENNA_ringosc.ibufp00_A/DIODE 0.7500 1.6566 -0.9066 (VIOLATED)
ringosc.ibufp00/A 0.7500 1.6566 -0.9066 (VIOLATED)
ringosc.dstage[0].id.delaybuf0/A 0.7500 1.6565 -0.9065 (VIOLATED)
ANTENNA_ringosc.dstage[0].id.delaybuf0_A/DIODE 0.7500 1.6564 -0.9064 (VIOLATED)
ringosc.iss.delaybuf0/A 0.7500 1.0210 -0.2710 (VIOLATED)
ringosc.iss.delayenb0/A 0.7500 1.0210 -0.2710 (VIOLATED)
ringosc.iss.delayenb1/A 0.7500 1.0210 -0.2710 (VIOLATED)
ringosc.dstage[11].id.delayen0/Z 0.7500 1.0210 -0.2710 (VIOLATED)
ringosc.iss.delayen0/Z 0.7500 0.9419 -0.1919 (VIOLATED)
1

101
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.ss-coverage.rpt Normal file
View File

@ -0,0 +1,101 @@
****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:55 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
hold 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
recovery 23 0 ( 0%) 0 ( 0%) 23 (100%)
removal 23 0 ( 0%) 0 ( 0%) 23 (100%)
min_pulse_width 69 46 ( 67%) 0 ( 0%) 23 ( 33%)
out_setup 2 0 ( 0%) 0 ( 0%) 2 (100%)
out_hold 2 0 ( 0%) 0 ( 0%) 2 (100%)
--------------------------------------------------------------------------------
All Checks 165 90 ( 55%) 0 ( 0%) 75 ( 45%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_470_/D CLK(rise) pll_control_clock hold untested no_startpoint_clock
_470_/D CLK(rise) pll_control_clock setup untested no_startpoint_clock
_470_/RESET_B(low) - - min_pulse_width untested no_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_472_/RESET_B(low) - - min_pulse_width untested no_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_471_/RESET_B(low) - - min_pulse_width untested no_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_456_/RESET_B(low) - - min_pulse_width untested no_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_475_/RESET_B(low) - - min_pulse_width untested no_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_476_/RESET_B(low) - - min_pulse_width untested no_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_462_/RESET_B(low) - - min_pulse_width untested no_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_474_/RESET_B(low) - - min_pulse_width untested no_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_457_/RESET_B(low) - - min_pulse_width untested no_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_473_/RESET_B(low) - - min_pulse_width untested no_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_477_/RESET_B(low) - - min_pulse_width untested no_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_461_/RESET_B(low) - - min_pulse_width untested no_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_460_/RESET_B(low) - - min_pulse_width untested no_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_466_/RESET_B(low) - - min_pulse_width untested no_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_467_/RESET_B(low) - - min_pulse_width untested no_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_468_/RESET_B(low) - - min_pulse_width untested no_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_464_/RESET_B(low) - - min_pulse_width untested no_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_469_/RESET_B(low) - - min_pulse_width untested no_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
clockp[0] - - out_hold untested no_endpoint_clock
clockp[0] - - out_setup untested no_endpoint_clock
clockp[1] - - out_hold untested no_endpoint_clock
clockp[1] - - out_setup untested no_endpoint_clock
1

11
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.ss-global.rpt Normal file
View File

@ -0,0 +1,11 @@
****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:55 2022
****************************************
1

8509
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.ss-max_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

7303
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.ss-min_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

13
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.tt-all_viol.rpt Normal file
View File

@ -0,0 +1,13 @@
****************************************
Report : constraint
-all_violators
-path slack_only
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:15 2022
****************************************
1

101
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.tt-coverage.rpt Normal file
View File

@ -0,0 +1,101 @@
****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:15 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
hold 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
recovery 23 0 ( 0%) 0 ( 0%) 23 (100%)
removal 23 0 ( 0%) 0 ( 0%) 23 (100%)
min_pulse_width 69 46 ( 67%) 0 ( 0%) 23 ( 33%)
out_setup 2 0 ( 0%) 0 ( 0%) 2 (100%)
out_hold 2 0 ( 0%) 0 ( 0%) 2 (100%)
--------------------------------------------------------------------------------
All Checks 165 90 ( 55%) 0 ( 0%) 75 ( 45%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_470_/D CLK(rise) pll_control_clock hold untested no_startpoint_clock
_470_/D CLK(rise) pll_control_clock setup untested no_startpoint_clock
_470_/RESET_B(low) - - min_pulse_width untested no_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_472_/RESET_B(low) - - min_pulse_width untested no_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_471_/RESET_B(low) - - min_pulse_width untested no_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_456_/RESET_B(low) - - min_pulse_width untested no_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_475_/RESET_B(low) - - min_pulse_width untested no_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_476_/RESET_B(low) - - min_pulse_width untested no_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_462_/RESET_B(low) - - min_pulse_width untested no_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_474_/RESET_B(low) - - min_pulse_width untested no_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_457_/RESET_B(low) - - min_pulse_width untested no_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_473_/RESET_B(low) - - min_pulse_width untested no_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_477_/RESET_B(low) - - min_pulse_width untested no_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_461_/RESET_B(low) - - min_pulse_width untested no_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_460_/RESET_B(low) - - min_pulse_width untested no_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_466_/RESET_B(low) - - min_pulse_width untested no_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_467_/RESET_B(low) - - min_pulse_width untested no_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_468_/RESET_B(low) - - min_pulse_width untested no_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_464_/RESET_B(low) - - min_pulse_width untested no_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_469_/RESET_B(low) - - min_pulse_width untested no_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
clockp[0] - - out_hold untested no_endpoint_clock
clockp[0] - - out_setup untested no_endpoint_clock
clockp[1] - - out_hold untested no_endpoint_clock
clockp[1] - - out_setup untested no_endpoint_clock
1

11
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.tt-global.rpt Normal file
View File

@ -0,0 +1,11 @@
****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:15 2022
****************************************
1

3645
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.tt-max_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

7295
signoff/digital_pll/primetime-signoff/reports/min/digital_pll.tt-min_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

13
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.ff-all_viol.rpt Normal file
View File

@ -0,0 +1,13 @@
****************************************
Report : constraint
-all_violators
-path slack_only
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:36:16 2022
****************************************
1

101
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.ff-coverage.rpt Normal file
View File

@ -0,0 +1,101 @@
****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:36:16 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
hold 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
recovery 23 0 ( 0%) 0 ( 0%) 23 (100%)
removal 23 0 ( 0%) 0 ( 0%) 23 (100%)
min_pulse_width 69 46 ( 67%) 0 ( 0%) 23 ( 33%)
out_setup 2 0 ( 0%) 0 ( 0%) 2 (100%)
out_hold 2 0 ( 0%) 0 ( 0%) 2 (100%)
--------------------------------------------------------------------------------
All Checks 165 90 ( 55%) 0 ( 0%) 75 ( 45%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_470_/D CLK(rise) pll_control_clock hold untested no_startpoint_clock
_470_/D CLK(rise) pll_control_clock setup untested no_startpoint_clock
_470_/RESET_B(low) - - min_pulse_width untested no_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_472_/RESET_B(low) - - min_pulse_width untested no_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_471_/RESET_B(low) - - min_pulse_width untested no_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_456_/RESET_B(low) - - min_pulse_width untested no_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_475_/RESET_B(low) - - min_pulse_width untested no_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_476_/RESET_B(low) - - min_pulse_width untested no_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_462_/RESET_B(low) - - min_pulse_width untested no_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_474_/RESET_B(low) - - min_pulse_width untested no_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_457_/RESET_B(low) - - min_pulse_width untested no_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_473_/RESET_B(low) - - min_pulse_width untested no_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_477_/RESET_B(low) - - min_pulse_width untested no_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_461_/RESET_B(low) - - min_pulse_width untested no_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_460_/RESET_B(low) - - min_pulse_width untested no_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_466_/RESET_B(low) - - min_pulse_width untested no_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_467_/RESET_B(low) - - min_pulse_width untested no_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_468_/RESET_B(low) - - min_pulse_width untested no_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_464_/RESET_B(low) - - min_pulse_width untested no_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_469_/RESET_B(low) - - min_pulse_width untested no_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
clockp[0] - - out_hold untested no_endpoint_clock
clockp[0] - - out_setup untested no_endpoint_clock
clockp[1] - - out_hold untested no_endpoint_clock
clockp[1] - - out_setup untested no_endpoint_clock
1

11
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.ff-global.rpt Normal file
View File

@ -0,0 +1,11 @@
****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:36:16 2022
****************************************
1

3613
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.ff-max_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

7297
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.ff-min_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

30
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.ss-all_viol.rpt Normal file
View File

@ -0,0 +1,30 @@
****************************************
Report : constraint
-all_violators
-path slack_only
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:28 2022
****************************************
max_transition
Required Actual
Pin Transition Transition Slack
-----------------------------------------------------------------
ringosc.iss.reseten0/Z 0.7500 1.7270 -0.9770 (VIOLATED)
ringosc.ibufp00/A 0.7500 1.7262 -0.9762 (VIOLATED)
ANTENNA_ringosc.ibufp00_A/DIODE 0.7500 1.7262 -0.9762 (VIOLATED)
ringosc.dstage[0].id.delaybuf0/A 0.7500 1.7260 -0.9760 (VIOLATED)
ANTENNA_ringosc.dstage[0].id.delaybuf0_A/DIODE 0.7500 1.7260 -0.9760 (VIOLATED)
ringosc.iss.delaybuf0/A 0.7500 1.0263 -0.2763 (VIOLATED)
ringosc.iss.delayenb0/A 0.7500 1.0263 -0.2763 (VIOLATED)
ringosc.iss.delayenb1/A 0.7500 1.0263 -0.2763 (VIOLATED)
ringosc.dstage[11].id.delayen0/Z 0.7500 1.0263 -0.2763 (VIOLATED)
ringosc.iss.delayen0/Z 0.7500 0.9831 -0.2331 (VIOLATED)
1

101
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.ss-coverage.rpt Normal file
View File

@ -0,0 +1,101 @@
****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:28 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
hold 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
recovery 23 0 ( 0%) 0 ( 0%) 23 (100%)
removal 23 0 ( 0%) 0 ( 0%) 23 (100%)
min_pulse_width 69 46 ( 67%) 0 ( 0%) 23 ( 33%)
out_setup 2 0 ( 0%) 0 ( 0%) 2 (100%)
out_hold 2 0 ( 0%) 0 ( 0%) 2 (100%)
--------------------------------------------------------------------------------
All Checks 165 90 ( 55%) 0 ( 0%) 75 ( 45%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_470_/D CLK(rise) pll_control_clock hold untested no_startpoint_clock
_470_/D CLK(rise) pll_control_clock setup untested no_startpoint_clock
_470_/RESET_B(low) - - min_pulse_width untested no_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_472_/RESET_B(low) - - min_pulse_width untested no_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_471_/RESET_B(low) - - min_pulse_width untested no_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_456_/RESET_B(low) - - min_pulse_width untested no_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_475_/RESET_B(low) - - min_pulse_width untested no_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_476_/RESET_B(low) - - min_pulse_width untested no_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_462_/RESET_B(low) - - min_pulse_width untested no_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_474_/RESET_B(low) - - min_pulse_width untested no_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_457_/RESET_B(low) - - min_pulse_width untested no_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_473_/RESET_B(low) - - min_pulse_width untested no_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_477_/RESET_B(low) - - min_pulse_width untested no_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_461_/RESET_B(low) - - min_pulse_width untested no_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_460_/RESET_B(low) - - min_pulse_width untested no_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_466_/RESET_B(low) - - min_pulse_width untested no_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_467_/RESET_B(low) - - min_pulse_width untested no_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_468_/RESET_B(low) - - min_pulse_width untested no_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_464_/RESET_B(low) - - min_pulse_width untested no_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_469_/RESET_B(low) - - min_pulse_width untested no_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
clockp[0] - - out_hold untested no_endpoint_clock
clockp[0] - - out_setup untested no_endpoint_clock
clockp[1] - - out_hold untested no_endpoint_clock
clockp[1] - - out_setup untested no_endpoint_clock
1

11
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.ss-global.rpt Normal file
View File

@ -0,0 +1,11 @@
****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:35:28 2022
****************************************
1

8509
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.ss-max_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

7301
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.ss-min_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

13
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.tt-all_viol.rpt Normal file
View File

@ -0,0 +1,13 @@
****************************************
Report : constraint
-all_violators
-path slack_only
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:34:45 2022
****************************************
1

101
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.tt-coverage.rpt Normal file
View File

@ -0,0 +1,101 @@
****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:34:45 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
hold 23 22 ( 96%) 0 ( 0%) 1 ( 4%)
recovery 23 0 ( 0%) 0 ( 0%) 23 (100%)
removal 23 0 ( 0%) 0 ( 0%) 23 (100%)
min_pulse_width 69 46 ( 67%) 0 ( 0%) 23 ( 33%)
out_setup 2 0 ( 0%) 0 ( 0%) 2 (100%)
out_hold 2 0 ( 0%) 0 ( 0%) 2 (100%)
--------------------------------------------------------------------------------
All Checks 165 90 ( 55%) 0 ( 0%) 75 ( 45%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_470_/D CLK(rise) pll_control_clock hold untested no_startpoint_clock
_470_/D CLK(rise) pll_control_clock setup untested no_startpoint_clock
_470_/RESET_B(low) - - min_pulse_width untested no_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_470_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_472_/RESET_B(low) - - min_pulse_width untested no_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_472_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_471_/RESET_B(low) - - min_pulse_width untested no_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_471_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_456_/RESET_B(low) - - min_pulse_width untested no_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_456_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_475_/RESET_B(low) - - min_pulse_width untested no_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_475_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_476_/RESET_B(low) - - min_pulse_width untested no_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_476_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_462_/RESET_B(low) - - min_pulse_width untested no_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_462_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_474_/RESET_B(low) - - min_pulse_width untested no_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_474_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_457_/RESET_B(low) - - min_pulse_width untested no_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_457_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_473_/RESET_B(low) - - min_pulse_width untested no_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_473_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_477_/RESET_B(low) - - min_pulse_width untested no_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_477_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_461_/RESET_B(low) - - min_pulse_width untested no_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_461_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_460_/RESET_B(low) - - min_pulse_width untested no_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_460_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_466_/RESET_B(low) - - min_pulse_width untested no_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_466_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_467_/RESET_B(low) - - min_pulse_width untested no_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_467_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_468_/RESET_B(low) - - min_pulse_width untested no_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_468_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_464_/RESET_B(low) - - min_pulse_width untested no_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_464_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
_469_/RESET_B(low) - - min_pulse_width untested no_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock recovery untested no_startpoint_clock
_469_/RESET_B(rise) CLK(rise) pll_control_clock removal untested no_startpoint_clock
clockp[0] - - out_hold untested no_endpoint_clock
clockp[0] - - out_setup untested no_endpoint_clock
clockp[1] - - out_hold untested no_endpoint_clock
clockp[1] - - out_setup untested no_endpoint_clock
1

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signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.tt-global.rpt Normal file
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****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : digital_pll
Version: T-2022.03-SP3
Date : Tue Oct 18 15:34:45 2022
****************************************
1

3645
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.tt-max_timing.rpt Normal file
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7293
signoff/digital_pll/primetime-signoff/reports/nom/digital_pll.tt-min_timing.rpt Normal file
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4783
signoff/digital_pll/primetime-signoff/sdf/max/digital_pll.ff.sdf Normal file
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4783
signoff/digital_pll/primetime-signoff/sdf/max/digital_pll.tt.sdf Normal file
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4783
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signoff/digital_pll/primetime-signoff/sdf/min/digital_pll.ss.sdf Normal file
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signoff/digital_pll/primetime-signoff/sdf/nom/digital_pll.ff.sdf Normal file
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signoff/digital_pll/signoff.rpt Normal file
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Klayout MR DRC: Passed
Layout Vs Schematic: Passed
digital_pll-nom-s-sta STA: Passed (max_tran)
digital_pll-min-s-sta STA: Passed (max_tran)
digital_pll-max-t-sta STA: Passed (max_tran)
digital_pll-min-t-sta STA: Passed
digital_pll-min-f-sta STA: Passed
digital_pll-max-f-sta STA: Passed
digital_pll-nom-t-sta STA: Passed
digital_pll-max-s-sta STA: Passed (max_tran)
digital_pll-nom-f-sta STA: Passed

2498
signoff/digital_pll/standalone_pvr/digital_pll.lvs.json Normal file
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1530
signoff/digital_pll/standalone_pvr/digital_pll.lvs.report Normal file
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0
signoff/digital_pll/standalone_pvr/digital_pll.unflattened Normal file
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873
signoff/digital_pll/standalone_pvr/digital_pll_klayout_drc.xml Normal file
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<?xml version="1.0" encoding="utf-8"?>
<report-database>
<description>SKY130 DRC runset</description>
<original-file/>
<generator>drc: script='tech-files/sky130A_mr.drc'</generator>
<top-cell>digital_pll</top-cell>
<tags>
</tags>
<categories>
<category>
<name>dnwell.2</name>
<description>dnwell.2 : min. dnwell width : 3.0um</description>
<categories>
</categories>
</category>
<category>
<name>nwell.1</name>
<description>nwell.1 : min. nwell width : 0.84um</description>
<categories>
</categories>
</category>
<category>
<name>nwell.2a</name>
<description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
<categories>
</categories>
</category>
<category>
<name>nwell.6</name>
<description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
<categories>
</categories>
</category>
<category>
<name>hvtp.1</name>
<description>hvtp.1 : min. hvtp width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>hvtp.2</name>
<description>hvtp.2 : min. hvtp spacing : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>hvtr.1</name>
<description>hvtr.1 : min. hvtr width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>hvtr.2</name>
<description>hvtr.2 : min. hvtr spacing : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>hvtr.2_a</name>
<description>hvtr.2_a : hvtr must not overlap hvtp</description>
<categories>
</categories>
</category>
<category>
<name>lvtn.1a</name>
<description>lvtn.1a : min. lvtn width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>lvtn.2</name>
<description>lvtn.2 : min. lvtn spacing : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>ncm.1</name>
<description>ncm.1 : min. ncm width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>ncm.2a</name>
<description>ncm.2a : min. ncm spacing : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>difftap.1</name>
<description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>difftap.1_a</name>
<description>difftap.1_a : min. diff width in periphery : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>difftap.1_b</name>
<description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>difftap.1_c</name>
<description>difftap.1_c : min. tap width in periphery : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>difftap.3</name>
<description>difftap.3 : min. difftap spacing : 0.27um</description>
<categories>
</categories>
</category>
<category>
<name>tunm.1</name>
<description>tunm.1 : min. tunm width : 0.41um</description>
<categories>
</categories>
</category>
<category>
<name>tunm.2</name>
<description>tunm.2 : min. tunm spacing : 0.5um</description>
<categories>
</categories>
</category>
<category>
<name>poly.1a</name>
<description>poly.1a : min. poly width : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>poly.2</name>
<description>poly.2 : min. poly spacing : 0.21um</description>
<categories>
</categories>
</category>
<category>
<name>rpm.1a</name>
<description>rpm.1a : min. rpm width : 1.27um</description>
<categories>
</categories>
</category>
<category>
<name>rpm.2</name>
<description>rpm.2 : min. rpm spacing : 0.84um</description>
<categories>
</categories>
</category>
<category>
<name>urpm.1a</name>
<description>urpm.1a : min. rpm width : 1.27um</description>
<categories>
</categories>
</category>
<category>
<name>urpm.2</name>
<description>urpm.2 : min. rpm spacing : 0.84um</description>
<categories>
</categories>
</category>
<category>
<name>npc.1</name>
<description>npc.1 : min. npc width : 0.27um</description>
<categories>
</categories>
</category>
<category>
<name>npc.2</name>
<description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
<categories>
</categories>
</category>
<category>
<name>nsd.1</name>
<description>nsd.1 : min. nsdm width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>nsd.2</name>
<description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>psd.1</name>
<description>psd.1 : min. psdm width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>psd.2</name>
<description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>licon.1</name>
<description>licon.1 : licon should be rectangle</description>
<categories>
</categories>
</category>
<category>
<name>licon.1_a/b</name>
<description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>licon.13</name>
<description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
<categories>
</categories>
</category>
<category>
<name>licon.13_a</name>
<description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
<categories>
</categories>
</category>
<category>
<name>licon.17</name>
<description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
<categories>
</categories>
</category>
<category>
<name>capm.1</name>
<description>capm.1 : min. capm width : 1.0um</description>
<categories>
</categories>
</category>
<category>
<name>capm.2a</name>
<description>capm.2a : min. capm spacing : 0.84um</description>
<categories>
</categories>
</category>
<category>
<name>capm.2b</name>
<description>capm.2b : min. capm spacing : 1.2um</description>
<categories>
</categories>
</category>
<category>
<name>capm.2b_a</name>
<description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
<categories>
</categories>
</category>
<category>
<name>capm.3</name>
<description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>capm.3_a</name>
<description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>capm.4</name>
<description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>capm.5</name>
<description>capm.5 : min. capm spacing to via3 : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>capm.11</name>
<description>capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.1</name>
<description>cap2m.1 : min. cap2m width : 1.0um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.2a</name>
<description>cap2m.2a : min. cap2m spacing : 0.84um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.2b</name>
<description>cap2m.2b : min. cap2m spacing : 1.2um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.2b_a</name>
<description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.3</name>
<description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.3_a</name>
<description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.4</name>
<description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.5</name>
<description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.11</name>
<description>cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um</description>
<categories>
</categories>
</category>
<category>
<name>li.1</name>
<description>li.1 : min. li width : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>li.3</name>
<description>li.3 : min. li spacing : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>li.5</name>
<description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
<categories>
</categories>
</category>
<category>
<name>li.6</name>
<description>li.6 : min. li area : 0.0561um²</description>
<categories>
</categories>
</category>
<category>
<name>ct.1</name>
<description>ct.1: non-ring mcon should be rectangular</description>
<categories>
</categories>
</category>
<category>
<name>ct.1_a</name>
<description>ct.1_a : minimum width of mcon : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>ct.1_b</name>
<description>ct.1_b : maximum length of mcon : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>ct.2</name>
<description>ct.2 : min. mcon spacing : 0.19um</description>
<categories>
</categories>
</category>
<category>
<name>ct.3</name>
<description>ct.3 : min. width of ring-shaped mcon : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>ct.3_a</name>
<description>ct.3_a : max. width of ring-shaped mcon : 0.175um</description>
<categories>
</categories>
</category>
<category>
<name>ct.3_b</name>
<description>ct.3_b: ring-shaped mcon must be enclosed by areaid_sl</description>
<categories>
</categories>
</category>
<category>
<name>ct.4</name>
<description>ct.4 : mcon should covered by li</description>
<categories>
</categories>
</category>
<category>
<name>m1.1</name>
<description>m1.1 : min. m1 width : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>m1.2</name>
<description>m1.2 : min. m1 spacing : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>m1.3ab</name>
<description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
<categories>
</categories>
</category>
<category>
<name>791_m1.4</name>
<description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
<categories>
</categories>
</category>
<category>
<name>m1.4</name>
<description>m1.4 : mcon periphery must be enclosed by m1</description>
<categories>
</categories>
</category>
<category>
<name>m1.4a</name>
<description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
<categories>
</categories>
</category>
<category>
<name>m1.4a_a</name>
<description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
<categories>
</categories>
</category>
<category>
<name>m1.6</name>
<description>m1.6 : min. m1 area : 0.083um²</description>
<categories>
</categories>
</category>
<category>
<name>m1.7</name>
<description>m1.7 : min. m1 with holes area : 0.14um²</description>
<categories>
</categories>
</category>
<category>
<name>m1.5</name>
<description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
<categories>
</categories>
</category>
<category>
<name>via.1a</name>
<description>via.1a : via outside of moduleCut should be rectangular</description>
<categories>
</categories>
</category>
<category>
<name>via.1a_a</name>
<description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>via.1a_b</name>
<description>via.1a_b : maximum length of via : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>via.2</name>
<description>via.2 : min. via spacing : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>via.3</name>
<description>via.3 : min. width of ring-shaped via : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via.3_a</name>
<description>via.3_a : max. width of ring-shaped via : 0.205um</description>
<categories>
</categories>
</category>
<category>
<name>via.3_b</name>
<description>via.3_b: ring-shaped via must be enclosed by areaid_sl</description>
<categories>
</categories>
</category>
<category>
<name>via.4a</name>
<description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
<categories>
</categories>
</category>
<category>
<name>via.4a_a</name>
<description>via.4a_a : 0.15um via must be enclosed by met1</description>
<categories>
</categories>
</category>
<category>
<name>via.5a</name>
<description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
<categories>
</categories>
</category>
<category>
<name>m2.1</name>
<description>m2.1 : min. m2 width : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>m2.2</name>
<description>m2.2 : min. m2 spacing : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>m2.3ab</name>
<description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
<categories>
</categories>
</category>
<category>
<name>m2.6</name>
<description>m2.6 : min. m2 area : 0.0676um²</description>
<categories>
</categories>
</category>
<category>
<name>m2.7</name>
<description>m2.7 : min. m2 holes area : 0.14um²</description>
<categories>
</categories>
</category>
<category>
<name>m2.4</name>
<description>m2.4 : min. m2 enclosure of via : 0.055um</description>
<categories>
</categories>
</category>
<category>
<name>m2.4_a</name>
<description>m2.4_a : via in periphery must be enclosed by met2</description>
<categories>
</categories>
</category>
<category>
<name>m2.5</name>
<description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
<categories>
</categories>
</category>
<category>
<name>via2.1a</name>
<description>via2.1a : via2 outside of moduleCut should be rectangular</description>
<categories>
</categories>
</category>
<category>
<name>via2.1a_a</name>
<description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via2.1a_b</name>
<description>via2.1a_b : maximum length of via2 : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via2.2</name>
<description>via2.2 : min. via2 spacing : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via2.3</name>
<description>via2.3 : min. width of ring-shaped via2 : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via2.3_a</name>
<description>via2.3_a : max. width of ring-shaped via2 : 0.205um</description>
<categories>
</categories>
</category>
<category>
<name>via2.3_b</name>
<description>via2.3_b: ring-shaped via2 must be enclosed by areaid_sl</description>
<categories>
</categories>
</category>
<category>
<name>via2.4</name>
<description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
<categories>
</categories>
</category>
<category>
<name>via2.4_a</name>
<description>via2.4_a : via must be enclosed by met2</description>
<categories>
</categories>
</category>
<category>
<name>via2.5</name>
<description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
<categories>
</categories>
</category>
<category>
<name>m3.1</name>
<description>m3.1 : min. m3 width : 0.3um</description>
<categories>
</categories>
</category>
<category>
<name>m3.2</name>
<description>m3.2 : min. m3 spacing : 0.3um</description>
<categories>
</categories>
</category>
<category>
<name>m3.3cd</name>
<description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
<categories>
</categories>
</category>
<category>
<name>m3.4</name>
<description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
<categories>
</categories>
</category>
<category>
<name>m3.4_a</name>
<description>m3.4_a : via2 must be enclosed by met3</description>
<categories>
</categories>
</category>
<category>
<name>via3.1</name>
<description>via3.1 : via3 outside of moduleCut should be rectangular</description>
<categories>
</categories>
</category>
<category>
<name>via3.1_a</name>
<description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via3.1_b</name>
<description>via3.1_b : maximum length of via3 : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via3.2</name>
<description>via3.2 : min. via3 spacing : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via3.4</name>
<description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
<categories>
</categories>
</category>
<category>
<name>via3.4_a</name>
<description>via3.4_a : non-ring via3 must be enclosed by met3</description>
<categories>
</categories>
</category>
<category>
<name>via3.5</name>
<description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
<categories>
</categories>
</category>
<category>
<name>m4.1</name>
<description>m4.1 : min. m4 width : 0.3um</description>
<categories>
</categories>
</category>
<category>
<name>m4.2</name>
<description>m4.2 : min. m4 spacing : 0.3um</description>
<categories>
</categories>
</category>
<category>
<name>m4.4a</name>
<description>m4.4a : min. m4 area : 0.240um²</description>
<categories>
</categories>
</category>
<category>
<name>m4.5ab</name>
<description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
<categories>
</categories>
</category>
<category>
<name>m4.3</name>
<description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
<categories>
</categories>
</category>
<category>
<name>m4.3_a</name>
<description>m4.3_a : via3 must be enclosed by met4</description>
<categories>
</categories>
</category>
<category>
<name>via4.1</name>
<description>via4.1 : via4 outside of moduleCut should be rectangular</description>
<categories>
</categories>
</category>
<category>
<name>via4.1_a</name>
<description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
<categories>
</categories>
</category>
<category>
<name>via4.1_b</name>
<description>via4.1_b : maximum length of via4 : 0.8um</description>
<categories>
</categories>
</category>
<category>
<name>via4.2</name>
<description>via4.2 : min. via4 spacing : 0.8um</description>
<categories>
</categories>
</category>
<category>
<name>via4.3</name>
<description>via4.3 : min. width of ring-shaped via4 : 0.8um</description>
<categories>
</categories>
</category>
<category>
<name>via4.3_a</name>
<description>via4.3_a : max. width of ring-shaped via4 : 0.805um</description>
<categories>
</categories>
</category>
<category>
<name>via4.3_b</name>
<description>via4.3_b: ring-shaped via4 must be enclosed by areaid_sl</description>
<categories>
</categories>
</category>
<category>
<name>via4.4</name>
<description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
<categories>
</categories>
</category>
<category>
<name>via4.4_a</name>
<description>via4.4_a : m4 must enclose all via4</description>
<categories>
</categories>
</category>
<category>
<name>m5.1</name>
<description>m5.1 : min. m5 width : 1.6um</description>
<categories>
</categories>
</category>
<category>
<name>m5.2</name>
<description>m5.2 : min. m5 spacing : 1.6um</description>
<categories>
</categories>
</category>
<category>
<name>m5.3</name>
<description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
<categories>
</categories>
</category>
<category>
<name>m5.3_a</name>
<description>m5.3_a : via must be enclosed by m5</description>
<categories>
</categories>
</category>
<category>
<name>m5.4</name>
<description>m5.4 : min. m5 area : 4.0um²</description>
<categories>
</categories>
</category>
<category>
<name>pad.2</name>
<description>pad.2 : min. pad spacing : 1.27um</description>
<categories>
</categories>
</category>
<category>
<name>hvi.1</name>
<description>hvi.1 : min. hvi width : 0.6um</description>
<categories>
</categories>
</category>
<category>
<name>hvi.2a</name>
<description>hvi.2a : min. hvi spacing : 0.7um</description>
<categories>
</categories>
</category>
<category>
<name>hvntm.1</name>
<description>hvntm.1 : min. hvntm width : 0.7um</description>
<categories>
</categories>
</category>
<category>
<name>hvntm.2</name>
<description>hvntm.2 : min. hvntm spacing : 0.7um</description>
<categories>
</categories>
</category>
</categories>
<cells>
<cell>
<name>digital_pll</name>
<variant/>
<references>
</references>
</cell>
</cells>
<items>
</items>
</report-database>

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signoff/digital_pll/standalone_pvr/lvs_summary.rpt Normal file
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Layout Vs Schematic Passed

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signoff/digital_pll/standalone_pvr/primetime-signoff/lib/max/digital_pll.ff.lib
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signoff/digital_pll/standalone_pvr/primetime-signoff/lib/max/digital_pll.ss.lib
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signoff/digital_pll/standalone_pvr/primetime-signoff/lib/max/digital_pll.tt.lib
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signoff/digital_pll/standalone_pvr/primetime-signoff/lib/min/digital_pll.ff.lib
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signoff/digital_pll/standalone_pvr/primetime-signoff/lib/min/digital_pll.ss.lib
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signoff/digital_pll/standalone_pvr/primetime-signoff/lib/min/digital_pll.tt.lib
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signoff/digital_pll/standalone_pvr/primetime-signoff/lib/nom/digital_pll.ff.lib
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signoff/digital_pll/standalone_pvr/primetime-signoff/lib/nom/digital_pll.ss.lib
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signoff/digital_pll/standalone_pvr/primetime-signoff/lib/nom/digital_pll.tt.lib
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