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add signoff results for `caravel_clocking`: 

- signoff summary report
- DRC and LVS reports
- STA timing reports for all corners
- generated lib files for all corners
- generated sdf files for all corners
This commit is contained in:
Passant 2022-10-19 07:03:39 -07:00
parent ac471a1a2f
commit 8297906630
78 changed files with 378991 additions and 13203 deletions
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signoff/caravel_clocking/primetime-signoff/lib/max/caravel_clocking.ff.lib Normal file
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signoff/caravel_clocking/primetime-signoff/lib/max/caravel_clocking.ss.lib Normal file
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signoff/caravel_clocking/primetime-signoff/lib/max/caravel_clocking.tt.lib Normal file
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signoff/caravel_clocking/primetime-signoff/lib/min/caravel_clocking.ff.lib Normal file
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signoff/caravel_clocking/primetime-signoff/lib/min/caravel_clocking.ss.lib Normal file
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signoff/caravel_clocking/primetime-signoff/lib/min/caravel_clocking.tt.lib Normal file
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signoff/caravel_clocking/primetime-signoff/lib/nom/caravel_clocking.ff.lib Normal file
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signoff/caravel_clocking/primetime-signoff/lib/nom/caravel_clocking.ss.lib Normal file
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signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.ff-all_viol.rpt Normal file
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****************************************
Report : constraint
-all_violators
-path slack_only
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:58 2022
****************************************
min_delay/hold ('clock_gating_default' group)
Endpoint Slack
-----------------------------------------------------------------
_304_/A3 -5.7242 (VIOLATED)
_308_/A1 -5.7197 (VIOLATED)
_304_/A1 -5.7165 (VIOLATED)
_308_/A3 -5.7104 (VIOLATED)
_301_/A_N -5.4234 (VIOLATED)
_305_/A_N -5.4156 (VIOLATED)
clock_gating_hold
Endpoint Slack
-----------------------------------------------------------------
_304_/A3 -5.7242 (VIOLATED)
_308_/A1 -5.7197 (VIOLATED)
_304_/A1 -5.7165 (VIOLATED)
_308_/A3 -5.7104 (VIOLATED)
_301_/A_N -5.4234 (VIOLATED)
_305_/A_N -5.4156 (VIOLATED)
1

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signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.ff-coverage.rpt Normal file
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****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:58 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
hold 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
recovery 53 0 ( 0%) 0 ( 0%) 53 (100%)
removal 53 0 ( 0%) 0 ( 0%) 53 (100%)
min_pulse_width 170 120 ( 71%) 0 ( 0%) 50 ( 29%)
clock_gating_setup 8 8 (100%) 0 ( 0%) 0 ( 0%)
clock_gating_hold 8 2 ( 25%) 6 ( 75%) 0 ( 0%)
out_setup 1 1 (100%) 0 ( 0%) 0 ( 0%)
out_hold 1 1 (100%) 0 ( 0%) 0 ( 0%)
--------------------------------------------------------------------------------
All Checks 412 234 ( 57%) 6 ( 1%) 172 ( 42%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_437_/RESET_B(low) - - min_pulse_width untested no_clock
_437_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_437_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_438_/SET_B(low) - - min_pulse_width untested no_clock
_438_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_438_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_439_/RESET_B(low) - - min_pulse_width untested no_clock
_439_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_439_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_436_/D CLK(rise) - hold untested constant_disabled
_436_/D CLK(rise) - setup untested constant_disabled
_436_/RESET_B(low) - - min_pulse_width untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_415_/RESET_B(low) - - min_pulse_width untested no_clock
_415_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_415_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_434_/D CLK(rise) - hold untested constant_disabled
_434_/D CLK(rise) - setup untested constant_disabled
_434_/RESET_B(low) - - min_pulse_width untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_413_/RESET_B(low) - - min_pulse_width untested no_clock
_413_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_413_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_412_/D CLK(rise) pll_clk hold untested false_paths
_412_/D CLK(rise) pll_clk setup untested false_paths
_412_/RESET_B(low) - - min_pulse_width untested no_clock
_412_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_412_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/D CLK(rise) - hold untested constant_disabled
_411_/D CLK(rise) - setup untested constant_disabled
_411_/SET_B(low) - - min_pulse_width untested no_clock
_411_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_435_/D CLK(rise) - hold untested constant_disabled
_435_/D CLK(rise) - setup untested constant_disabled
_435_/SET_B(low) - - min_pulse_width untested no_clock
_435_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_435_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(low) - - min_pulse_width untested no_clock
_410_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_433_/RESET_B(low) - - min_pulse_width untested no_clock
_433_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_433_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_460_/D CLK(rise) - hold untested constant_disabled
_460_/D CLK(rise) - setup untested constant_disabled
_460_/RESET_B(low) - - min_pulse_width untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_409_/SET_B(low) - - min_pulse_width untested no_clock
_409_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_447_/SET_B(low) - - min_pulse_width untested no_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_456_/SET_B(low) - - min_pulse_width untested no_clock
_456_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_456_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_422_/SET_B(low) - - min_pulse_width untested no_clock
_422_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_422_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_424_/SET_B(low) - - min_pulse_width untested no_clock
_424_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_424_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_461_/D CLK(rise) - hold untested constant_disabled
_461_/D CLK(rise) - setup untested constant_disabled
_461_/SET_B(low) - - min_pulse_width untested no_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_462_/D CLK(rise) - hold untested constant_disabled
_462_/D CLK(rise) - setup untested constant_disabled
_462_/RESET_B(low) - - min_pulse_width untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_464_/SET_B(low) - - min_pulse_width untested no_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_420_/RESET_B(low) - - min_pulse_width untested no_clock
_420_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_420_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_444_/SET_B(low) - - min_pulse_width untested no_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_419_/SET_B(low) - - min_pulse_width untested no_clock
_419_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_419_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_431_/SET_B(low) - - min_pulse_width untested no_clock
_431_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_431_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_445_/RESET_B(low) - - min_pulse_width untested no_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_432_/RESET_B(low) - - min_pulse_width untested no_clock
_432_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_432_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_457_/SET_B(low) - - min_pulse_width untested no_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_414_/SET_B(low) - - min_pulse_width untested no_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_449_/SET_B(low) - - min_pulse_width untested no_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_446_/RESET_B(low) - - min_pulse_width untested no_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_429_/SET_B(low) - - min_pulse_width untested no_clock
_429_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_429_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_451_/SET_B(low) - - min_pulse_width untested no_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_450_/RESET_B(low) - - min_pulse_width untested no_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_430_/RESET_B(low) - - min_pulse_width untested no_clock
_430_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_430_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_452_/RESET_B(low) - - min_pulse_width untested no_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_426_/SET_B(low) - - min_pulse_width untested no_clock
_426_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_426_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_421_/RESET_B(low) - - min_pulse_width untested no_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_425_/RESET_B(low) - - min_pulse_width untested no_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_427_/RESET_B(low) - - min_pulse_width untested no_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_423_/RESET_B(low) - - min_pulse_width untested no_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_453_/RESET_B(low) - - min_pulse_width untested no_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_428_/RESET_B(low) - - min_pulse_width untested no_clock
_428_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_428_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_454_/SET_B(low) - - min_pulse_width untested no_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_448_/RESET_B(low) - - min_pulse_width untested no_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
1

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signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.ff-global.rpt Normal file
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****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:58 2022
****************************************
Hold violations for paths in **clock_gating_default**
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -5.7242 -5.7242 0.0000 0.0000 0.0000
TNS -33.7098 -33.7098 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
1

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****************************************
Report : constraint
-all_violators
-path slack_only
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:05 2022
****************************************
max_delay/setup ('pll_clk' group)
Endpoint Slack
-----------------------------------------------------------------
_427_/D -1.9802 (VIOLATED)
_425_/D -1.9793 (VIOLATED)
_426_/D -1.5583 (VIOLATED)
_421_/D -0.5634 (VIOLATED)
_423_/D -0.5125 (VIOLATED)
_422_/D -0.1438 (VIOLATED)
max_delay/setup ('pll_clk90' group)
Endpoint Slack
-----------------------------------------------------------------
_452_/D -1.9989 (VIOLATED)
_450_/D -1.9909 (VIOLATED)
_451_/D -1.5672 (VIOLATED)
_448_/D -0.5589 (VIOLATED)
_446_/D -0.4255 (VIOLATED)
_447_/D -0.2108 (VIOLATED)
_449_/D -0.1782 (VIOLATED)
min_delay/hold ('clock_gating_default' group)
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -4.9160 (VIOLATED)
_304_/A1 -4.9097 (VIOLATED)
_304_/A3 -4.8188 (VIOLATED)
_308_/A3 -4.7671 (VIOLATED)
_301_/A_N -4.1797 (VIOLATED)
_305_/A_N -4.1499 (VIOLATED)
clock_gating_hold
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -4.9160 (VIOLATED)
_304_/A1 -4.9097 (VIOLATED)
_304_/A3 -4.8188 (VIOLATED)
_308_/A3 -4.7671 (VIOLATED)
_301_/A_N -4.1797 (VIOLATED)
_305_/A_N -4.1499 (VIOLATED)
max_transition
Required Actual
Pin Transition Transition Slack
-----------------------------------------------------------------
_212_/S 0.7500 0.9738 -0.2238 (VIOLATED)
_214_/S 0.7500 0.9738 -0.2238 (VIOLATED)
_216_/S 0.7500 0.9738 -0.2238 (VIOLATED)
_284_/A1 0.7500 0.9738 -0.2238 (VIOLATED)
_285_/A1 0.7500 0.9738 -0.2238 (VIOLATED)
_277_/Y 0.7500 0.9738 -0.2238 (VIOLATED)
_229_/S 0.7500 0.9533 -0.2033 (VIOLATED)
_231_/S 0.7500 0.9533 -0.2033 (VIOLATED)
_233_/S 0.7500 0.9533 -0.2033 (VIOLATED)
_269_/A1 0.7500 0.9533 -0.2033 (VIOLATED)
_270_/A1 0.7500 0.9533 -0.2033 (VIOLATED)
_262_/Y 0.7500 0.9533 -0.2033 (VIOLATED)
1

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****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:05 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 59 38 ( 64%) 13 ( 22%) 8 ( 14%)
hold 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
recovery 53 0 ( 0%) 0 ( 0%) 53 (100%)
removal 53 0 ( 0%) 0 ( 0%) 53 (100%)
min_pulse_width 170 120 ( 71%) 0 ( 0%) 50 ( 29%)
clock_gating_setup 8 8 (100%) 0 ( 0%) 0 ( 0%)
clock_gating_hold 8 2 ( 25%) 6 ( 75%) 0 ( 0%)
out_setup 1 1 (100%) 0 ( 0%) 0 ( 0%)
out_hold 1 1 (100%) 0 ( 0%) 0 ( 0%)
--------------------------------------------------------------------------------
All Checks 412 221 ( 54%) 19 ( 5%) 172 ( 42%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_437_/RESET_B(low) - - min_pulse_width untested no_clock
_437_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_437_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_438_/SET_B(low) - - min_pulse_width untested no_clock
_438_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_438_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_439_/RESET_B(low) - - min_pulse_width untested no_clock
_439_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_439_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_436_/D CLK(rise) - hold untested constant_disabled
_436_/D CLK(rise) - setup untested constant_disabled
_436_/RESET_B(low) - - min_pulse_width untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_415_/RESET_B(low) - - min_pulse_width untested no_clock
_415_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_415_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_434_/D CLK(rise) - hold untested constant_disabled
_434_/D CLK(rise) - setup untested constant_disabled
_434_/RESET_B(low) - - min_pulse_width untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_413_/RESET_B(low) - - min_pulse_width untested no_clock
_413_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_413_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_412_/D CLK(rise) pll_clk hold untested false_paths
_412_/D CLK(rise) pll_clk setup untested false_paths
_412_/RESET_B(low) - - min_pulse_width untested no_clock
_412_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_412_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/D CLK(rise) - hold untested constant_disabled
_411_/D CLK(rise) - setup untested constant_disabled
_411_/SET_B(low) - - min_pulse_width untested no_clock
_411_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_435_/D CLK(rise) - hold untested constant_disabled
_435_/D CLK(rise) - setup untested constant_disabled
_435_/SET_B(low) - - min_pulse_width untested no_clock
_435_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_435_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(low) - - min_pulse_width untested no_clock
_410_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_433_/RESET_B(low) - - min_pulse_width untested no_clock
_433_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_433_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_460_/D CLK(rise) - hold untested constant_disabled
_460_/D CLK(rise) - setup untested constant_disabled
_460_/RESET_B(low) - - min_pulse_width untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_409_/SET_B(low) - - min_pulse_width untested no_clock
_409_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_447_/SET_B(low) - - min_pulse_width untested no_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_456_/SET_B(low) - - min_pulse_width untested no_clock
_456_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_456_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_422_/SET_B(low) - - min_pulse_width untested no_clock
_422_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_422_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_424_/SET_B(low) - - min_pulse_width untested no_clock
_424_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_424_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_461_/D CLK(rise) - hold untested constant_disabled
_461_/D CLK(rise) - setup untested constant_disabled
_461_/SET_B(low) - - min_pulse_width untested no_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_462_/D CLK(rise) - hold untested constant_disabled
_462_/D CLK(rise) - setup untested constant_disabled
_462_/RESET_B(low) - - min_pulse_width untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_464_/SET_B(low) - - min_pulse_width untested no_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_420_/RESET_B(low) - - min_pulse_width untested no_clock
_420_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_420_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_444_/SET_B(low) - - min_pulse_width untested no_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_419_/SET_B(low) - - min_pulse_width untested no_clock
_419_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_419_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_431_/SET_B(low) - - min_pulse_width untested no_clock
_431_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_431_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_445_/RESET_B(low) - - min_pulse_width untested no_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_432_/RESET_B(low) - - min_pulse_width untested no_clock
_432_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_432_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_457_/SET_B(low) - - min_pulse_width untested no_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_414_/SET_B(low) - - min_pulse_width untested no_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_449_/SET_B(low) - - min_pulse_width untested no_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_446_/RESET_B(low) - - min_pulse_width untested no_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_429_/SET_B(low) - - min_pulse_width untested no_clock
_429_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_429_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_451_/SET_B(low) - - min_pulse_width untested no_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_450_/RESET_B(low) - - min_pulse_width untested no_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_430_/RESET_B(low) - - min_pulse_width untested no_clock
_430_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_430_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_452_/RESET_B(low) - - min_pulse_width untested no_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_426_/SET_B(low) - - min_pulse_width untested no_clock
_426_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_426_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_421_/RESET_B(low) - - min_pulse_width untested no_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_425_/RESET_B(low) - - min_pulse_width untested no_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_427_/RESET_B(low) - - min_pulse_width untested no_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_423_/RESET_B(low) - - min_pulse_width untested no_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_453_/RESET_B(low) - - min_pulse_width untested no_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_428_/RESET_B(low) - - min_pulse_width untested no_clock
_428_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_428_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_454_/SET_B(low) - - min_pulse_width untested no_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_448_/RESET_B(low) - - min_pulse_width untested no_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
1

38
signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.ss-global.rpt Normal file
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@ -0,0 +1,38 @@
****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:05 2022
****************************************
Setup violations for paths in pll_clk90
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -1.9989 -1.9989 0.0000 0.0000 0.0000
TNS -6.9304 -6.9304 0.0000 0.0000 0.0000
NUM 7 7 0 0 0
---------------------------------------------------------
Setup violations for paths in pll_clk
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -1.9802 -1.9802 0.0000 0.0000 0.0000
TNS -6.7375 -6.7375 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
Hold violations for paths in **clock_gating_default**
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -4.9160 -4.9160 0.0000 0.0000 0.0000
TNS -27.7412 -27.7412 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
1

21047
signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.ss-max_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

19669
signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.ss-min_timing.rpt Normal file
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File diff suppressed because it is too large Load Diff

37
signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.tt-all_viol.rpt Normal file
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@ -0,0 +1,37 @@
****************************************
Report : constraint
-all_violators
-path slack_only
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:26 2022
****************************************
min_delay/hold ('clock_gating_default' group)
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -5.5867 (VIOLATED)
_304_/A1 -5.5826 (VIOLATED)
_304_/A3 -5.5824 (VIOLATED)
_308_/A3 -5.5624 (VIOLATED)
_301_/A_N -5.1872 (VIOLATED)
_305_/A_N -5.1800 (VIOLATED)
clock_gating_hold
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -5.5867 (VIOLATED)
_304_/A1 -5.5826 (VIOLATED)
_304_/A3 -5.5824 (VIOLATED)
_308_/A3 -5.5624 (VIOLATED)
_301_/A_N -5.1872 (VIOLATED)
_305_/A_N -5.1800 (VIOLATED)
1

200
signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.tt-coverage.rpt Normal file
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@ -0,0 +1,200 @@
****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:26 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
hold 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
recovery 53 0 ( 0%) 0 ( 0%) 53 (100%)
removal 53 0 ( 0%) 0 ( 0%) 53 (100%)
min_pulse_width 170 120 ( 71%) 0 ( 0%) 50 ( 29%)
clock_gating_setup 8 8 (100%) 0 ( 0%) 0 ( 0%)
clock_gating_hold 8 2 ( 25%) 6 ( 75%) 0 ( 0%)
out_setup 1 1 (100%) 0 ( 0%) 0 ( 0%)
out_hold 1 1 (100%) 0 ( 0%) 0 ( 0%)
--------------------------------------------------------------------------------
All Checks 412 234 ( 57%) 6 ( 1%) 172 ( 42%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_437_/RESET_B(low) - - min_pulse_width untested no_clock
_437_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_437_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_438_/SET_B(low) - - min_pulse_width untested no_clock
_438_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_438_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_439_/RESET_B(low) - - min_pulse_width untested no_clock
_439_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_439_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_436_/D CLK(rise) - hold untested constant_disabled
_436_/D CLK(rise) - setup untested constant_disabled
_436_/RESET_B(low) - - min_pulse_width untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_415_/RESET_B(low) - - min_pulse_width untested no_clock
_415_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_415_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_434_/D CLK(rise) - hold untested constant_disabled
_434_/D CLK(rise) - setup untested constant_disabled
_434_/RESET_B(low) - - min_pulse_width untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_413_/RESET_B(low) - - min_pulse_width untested no_clock
_413_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_413_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_412_/D CLK(rise) pll_clk hold untested false_paths
_412_/D CLK(rise) pll_clk setup untested false_paths
_412_/RESET_B(low) - - min_pulse_width untested no_clock
_412_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_412_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/D CLK(rise) - hold untested constant_disabled
_411_/D CLK(rise) - setup untested constant_disabled
_411_/SET_B(low) - - min_pulse_width untested no_clock
_411_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_435_/D CLK(rise) - hold untested constant_disabled
_435_/D CLK(rise) - setup untested constant_disabled
_435_/SET_B(low) - - min_pulse_width untested no_clock
_435_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_435_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(low) - - min_pulse_width untested no_clock
_410_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_433_/RESET_B(low) - - min_pulse_width untested no_clock
_433_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_433_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_460_/D CLK(rise) - hold untested constant_disabled
_460_/D CLK(rise) - setup untested constant_disabled
_460_/RESET_B(low) - - min_pulse_width untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_409_/SET_B(low) - - min_pulse_width untested no_clock
_409_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_447_/SET_B(low) - - min_pulse_width untested no_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_456_/SET_B(low) - - min_pulse_width untested no_clock
_456_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_456_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_422_/SET_B(low) - - min_pulse_width untested no_clock
_422_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_422_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_424_/SET_B(low) - - min_pulse_width untested no_clock
_424_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_424_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_461_/D CLK(rise) - hold untested constant_disabled
_461_/D CLK(rise) - setup untested constant_disabled
_461_/SET_B(low) - - min_pulse_width untested no_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_462_/D CLK(rise) - hold untested constant_disabled
_462_/D CLK(rise) - setup untested constant_disabled
_462_/RESET_B(low) - - min_pulse_width untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_464_/SET_B(low) - - min_pulse_width untested no_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_420_/RESET_B(low) - - min_pulse_width untested no_clock
_420_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_420_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_444_/SET_B(low) - - min_pulse_width untested no_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_419_/SET_B(low) - - min_pulse_width untested no_clock
_419_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_419_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_431_/SET_B(low) - - min_pulse_width untested no_clock
_431_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_431_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_445_/RESET_B(low) - - min_pulse_width untested no_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_432_/RESET_B(low) - - min_pulse_width untested no_clock
_432_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_432_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_457_/SET_B(low) - - min_pulse_width untested no_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_414_/SET_B(low) - - min_pulse_width untested no_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_449_/SET_B(low) - - min_pulse_width untested no_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_446_/RESET_B(low) - - min_pulse_width untested no_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_429_/SET_B(low) - - min_pulse_width untested no_clock
_429_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_429_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_451_/SET_B(low) - - min_pulse_width untested no_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_450_/RESET_B(low) - - min_pulse_width untested no_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_430_/RESET_B(low) - - min_pulse_width untested no_clock
_430_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_430_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_452_/RESET_B(low) - - min_pulse_width untested no_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_426_/SET_B(low) - - min_pulse_width untested no_clock
_426_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_426_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_421_/RESET_B(low) - - min_pulse_width untested no_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_425_/RESET_B(low) - - min_pulse_width untested no_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_427_/RESET_B(low) - - min_pulse_width untested no_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_423_/RESET_B(low) - - min_pulse_width untested no_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_453_/RESET_B(low) - - min_pulse_width untested no_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_428_/RESET_B(low) - - min_pulse_width untested no_clock
_428_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_428_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_454_/SET_B(low) - - min_pulse_width untested no_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_448_/RESET_B(low) - - min_pulse_width untested no_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
1

20
signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.tt-global.rpt Normal file
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****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:26 2022
****************************************
Hold violations for paths in **clock_gating_default**
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -5.5867 -5.5867 0.0000 0.0000 0.0000
TNS -32.6814 -32.6814 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
1

16101
signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.tt-max_timing.rpt Normal file
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19625
signoff/caravel_clocking/primetime-signoff/reports/max/caravel_clocking.tt-min_timing.rpt Normal file
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37
signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.ff-all_viol.rpt Normal file
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****************************************
Report : constraint
-all_violators
-path slack_only
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:39:17 2022
****************************************
min_delay/hold ('clock_gating_default' group)
Endpoint Slack
-----------------------------------------------------------------
_304_/A3 -5.7230 (VIOLATED)
_308_/A1 -5.7226 (VIOLATED)
_304_/A1 -5.7210 (VIOLATED)
_308_/A3 -5.7151 (VIOLATED)
_301_/A_N -5.4516 (VIOLATED)
_305_/A_N -5.4391 (VIOLATED)
clock_gating_hold
Endpoint Slack
-----------------------------------------------------------------
_304_/A3 -5.7230 (VIOLATED)
_308_/A1 -5.7226 (VIOLATED)
_304_/A1 -5.7210 (VIOLATED)
_308_/A3 -5.7151 (VIOLATED)
_301_/A_N -5.4516 (VIOLATED)
_305_/A_N -5.4391 (VIOLATED)
1

200
signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.ff-coverage.rpt Normal file
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****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:39:17 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
hold 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
recovery 53 0 ( 0%) 0 ( 0%) 53 (100%)
removal 53 0 ( 0%) 0 ( 0%) 53 (100%)
min_pulse_width 170 120 ( 71%) 0 ( 0%) 50 ( 29%)
clock_gating_setup 8 8 (100%) 0 ( 0%) 0 ( 0%)
clock_gating_hold 8 2 ( 25%) 6 ( 75%) 0 ( 0%)
out_setup 1 1 (100%) 0 ( 0%) 0 ( 0%)
out_hold 1 1 (100%) 0 ( 0%) 0 ( 0%)
--------------------------------------------------------------------------------
All Checks 412 234 ( 57%) 6 ( 1%) 172 ( 42%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_437_/RESET_B(low) - - min_pulse_width untested no_clock
_437_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_437_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_438_/SET_B(low) - - min_pulse_width untested no_clock
_438_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_438_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_439_/RESET_B(low) - - min_pulse_width untested no_clock
_439_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_439_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_436_/D CLK(rise) - hold untested constant_disabled
_436_/D CLK(rise) - setup untested constant_disabled
_436_/RESET_B(low) - - min_pulse_width untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_415_/RESET_B(low) - - min_pulse_width untested no_clock
_415_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_415_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_434_/D CLK(rise) - hold untested constant_disabled
_434_/D CLK(rise) - setup untested constant_disabled
_434_/RESET_B(low) - - min_pulse_width untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_413_/RESET_B(low) - - min_pulse_width untested no_clock
_413_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_413_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_412_/D CLK(rise) pll_clk hold untested false_paths
_412_/D CLK(rise) pll_clk setup untested false_paths
_412_/RESET_B(low) - - min_pulse_width untested no_clock
_412_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_412_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/D CLK(rise) - hold untested constant_disabled
_411_/D CLK(rise) - setup untested constant_disabled
_411_/SET_B(low) - - min_pulse_width untested no_clock
_411_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_435_/D CLK(rise) - hold untested constant_disabled
_435_/D CLK(rise) - setup untested constant_disabled
_435_/SET_B(low) - - min_pulse_width untested no_clock
_435_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_435_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(low) - - min_pulse_width untested no_clock
_410_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_433_/RESET_B(low) - - min_pulse_width untested no_clock
_433_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_433_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_460_/D CLK(rise) - hold untested constant_disabled
_460_/D CLK(rise) - setup untested constant_disabled
_460_/RESET_B(low) - - min_pulse_width untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_409_/SET_B(low) - - min_pulse_width untested no_clock
_409_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_447_/SET_B(low) - - min_pulse_width untested no_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_456_/SET_B(low) - - min_pulse_width untested no_clock
_456_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_456_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_422_/SET_B(low) - - min_pulse_width untested no_clock
_422_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_422_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_424_/SET_B(low) - - min_pulse_width untested no_clock
_424_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_424_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_461_/D CLK(rise) - hold untested constant_disabled
_461_/D CLK(rise) - setup untested constant_disabled
_461_/SET_B(low) - - min_pulse_width untested no_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_462_/D CLK(rise) - hold untested constant_disabled
_462_/D CLK(rise) - setup untested constant_disabled
_462_/RESET_B(low) - - min_pulse_width untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_464_/SET_B(low) - - min_pulse_width untested no_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_420_/RESET_B(low) - - min_pulse_width untested no_clock
_420_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_420_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_444_/SET_B(low) - - min_pulse_width untested no_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_419_/SET_B(low) - - min_pulse_width untested no_clock
_419_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_419_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_431_/SET_B(low) - - min_pulse_width untested no_clock
_431_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_431_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_445_/RESET_B(low) - - min_pulse_width untested no_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_432_/RESET_B(low) - - min_pulse_width untested no_clock
_432_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_432_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_457_/SET_B(low) - - min_pulse_width untested no_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_414_/SET_B(low) - - min_pulse_width untested no_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_449_/SET_B(low) - - min_pulse_width untested no_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_446_/RESET_B(low) - - min_pulse_width untested no_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_429_/SET_B(low) - - min_pulse_width untested no_clock
_429_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_429_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_451_/SET_B(low) - - min_pulse_width untested no_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_450_/RESET_B(low) - - min_pulse_width untested no_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_430_/RESET_B(low) - - min_pulse_width untested no_clock
_430_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_430_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_452_/RESET_B(low) - - min_pulse_width untested no_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_426_/SET_B(low) - - min_pulse_width untested no_clock
_426_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_426_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_421_/RESET_B(low) - - min_pulse_width untested no_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_425_/RESET_B(low) - - min_pulse_width untested no_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_427_/RESET_B(low) - - min_pulse_width untested no_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_423_/RESET_B(low) - - min_pulse_width untested no_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_453_/RESET_B(low) - - min_pulse_width untested no_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_428_/RESET_B(low) - - min_pulse_width untested no_clock
_428_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_428_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_454_/SET_B(low) - - min_pulse_width untested no_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_448_/RESET_B(low) - - min_pulse_width untested no_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
1

20
signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.ff-global.rpt Normal file
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@ -0,0 +1,20 @@
****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:39:17 2022
****************************************
Hold violations for paths in **clock_gating_default**
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -5.7230 -5.7230 0.0000 0.0000 0.0000
TNS -33.7723 -33.7723 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
1

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signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.ff-max_timing.rpt Normal file
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signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.ff-min_timing.rpt Normal file
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78
signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.ss-all_viol.rpt Normal file
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****************************************
Report : constraint
-all_violators
-path slack_only
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:18 2022
****************************************
max_delay/setup ('pll_clk' group)
Endpoint Slack
-----------------------------------------------------------------
_425_/D -1.7904 (VIOLATED)
_427_/D -1.7896 (VIOLATED)
_426_/D -1.3778 (VIOLATED)
_421_/D -0.3876 (VIOLATED)
_423_/D -0.3842 (VIOLATED)
_422_/D -0.0018 (VIOLATED)
max_delay/setup ('pll_clk90' group)
Endpoint Slack
-----------------------------------------------------------------
_450_/D -1.7781 (VIOLATED)
_452_/D -1.7766 (VIOLATED)
_451_/D -1.3602 (VIOLATED)
_448_/D -0.4170 (VIOLATED)
_446_/D -0.3017 (VIOLATED)
_447_/D -0.0203 (VIOLATED)
min_delay/hold ('clock_gating_default' group)
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -4.9260 (VIOLATED)
_304_/A1 -4.9196 (VIOLATED)
_304_/A3 -4.8094 (VIOLATED)
_308_/A3 -4.7843 (VIOLATED)
_301_/A_N -4.2992 (VIOLATED)
_305_/A_N -4.2364 (VIOLATED)
clock_gating_hold
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -4.9260 (VIOLATED)
_304_/A1 -4.9196 (VIOLATED)
_304_/A3 -4.8094 (VIOLATED)
_308_/A3 -4.7843 (VIOLATED)
_301_/A_N -4.2992 (VIOLATED)
_305_/A_N -4.2364 (VIOLATED)
max_transition
Required Actual
Pin Transition Transition Slack
-----------------------------------------------------------------
_212_/S 0.7500 0.9179 -0.1679 (VIOLATED)
_214_/S 0.7500 0.9179 -0.1679 (VIOLATED)
_216_/S 0.7500 0.9179 -0.1679 (VIOLATED)
_284_/A1 0.7500 0.9179 -0.1679 (VIOLATED)
_285_/A1 0.7500 0.9179 -0.1679 (VIOLATED)
_277_/Y 0.7500 0.9179 -0.1679 (VIOLATED)
_229_/S 0.7500 0.8949 -0.1449 (VIOLATED)
_231_/S 0.7500 0.8949 -0.1449 (VIOLATED)
_233_/S 0.7500 0.8949 -0.1449 (VIOLATED)
_269_/A1 0.7500 0.8949 -0.1449 (VIOLATED)
_270_/A1 0.7500 0.8949 -0.1449 (VIOLATED)
_262_/Y 0.7500 0.8949 -0.1449 (VIOLATED)
1

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****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:18 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 59 39 ( 66%) 12 ( 20%) 8 ( 14%)
hold 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
recovery 53 0 ( 0%) 0 ( 0%) 53 (100%)
removal 53 0 ( 0%) 0 ( 0%) 53 (100%)
min_pulse_width 170 120 ( 71%) 0 ( 0%) 50 ( 29%)
clock_gating_setup 8 8 (100%) 0 ( 0%) 0 ( 0%)
clock_gating_hold 8 2 ( 25%) 6 ( 75%) 0 ( 0%)
out_setup 1 1 (100%) 0 ( 0%) 0 ( 0%)
out_hold 1 1 (100%) 0 ( 0%) 0 ( 0%)
--------------------------------------------------------------------------------
All Checks 412 222 ( 54%) 18 ( 4%) 172 ( 42%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_437_/RESET_B(low) - - min_pulse_width untested no_clock
_437_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_437_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_438_/SET_B(low) - - min_pulse_width untested no_clock
_438_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_438_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_439_/RESET_B(low) - - min_pulse_width untested no_clock
_439_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_439_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_436_/D CLK(rise) - hold untested constant_disabled
_436_/D CLK(rise) - setup untested constant_disabled
_436_/RESET_B(low) - - min_pulse_width untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_415_/RESET_B(low) - - min_pulse_width untested no_clock
_415_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_415_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_434_/D CLK(rise) - hold untested constant_disabled
_434_/D CLK(rise) - setup untested constant_disabled
_434_/RESET_B(low) - - min_pulse_width untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_413_/RESET_B(low) - - min_pulse_width untested no_clock
_413_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_413_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_412_/D CLK(rise) pll_clk hold untested false_paths
_412_/D CLK(rise) pll_clk setup untested false_paths
_412_/RESET_B(low) - - min_pulse_width untested no_clock
_412_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_412_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/D CLK(rise) - hold untested constant_disabled
_411_/D CLK(rise) - setup untested constant_disabled
_411_/SET_B(low) - - min_pulse_width untested no_clock
_411_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_435_/D CLK(rise) - hold untested constant_disabled
_435_/D CLK(rise) - setup untested constant_disabled
_435_/SET_B(low) - - min_pulse_width untested no_clock
_435_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_435_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(low) - - min_pulse_width untested no_clock
_410_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_433_/RESET_B(low) - - min_pulse_width untested no_clock
_433_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_433_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_460_/D CLK(rise) - hold untested constant_disabled
_460_/D CLK(rise) - setup untested constant_disabled
_460_/RESET_B(low) - - min_pulse_width untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_409_/SET_B(low) - - min_pulse_width untested no_clock
_409_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_447_/SET_B(low) - - min_pulse_width untested no_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_456_/SET_B(low) - - min_pulse_width untested no_clock
_456_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_456_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_422_/SET_B(low) - - min_pulse_width untested no_clock
_422_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_422_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_424_/SET_B(low) - - min_pulse_width untested no_clock
_424_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_424_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_461_/D CLK(rise) - hold untested constant_disabled
_461_/D CLK(rise) - setup untested constant_disabled
_461_/SET_B(low) - - min_pulse_width untested no_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_462_/D CLK(rise) - hold untested constant_disabled
_462_/D CLK(rise) - setup untested constant_disabled
_462_/RESET_B(low) - - min_pulse_width untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_464_/SET_B(low) - - min_pulse_width untested no_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_420_/RESET_B(low) - - min_pulse_width untested no_clock
_420_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_420_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_444_/SET_B(low) - - min_pulse_width untested no_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_419_/SET_B(low) - - min_pulse_width untested no_clock
_419_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_419_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_431_/SET_B(low) - - min_pulse_width untested no_clock
_431_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_431_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_445_/RESET_B(low) - - min_pulse_width untested no_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_432_/RESET_B(low) - - min_pulse_width untested no_clock
_432_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_432_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_457_/SET_B(low) - - min_pulse_width untested no_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_414_/SET_B(low) - - min_pulse_width untested no_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_449_/SET_B(low) - - min_pulse_width untested no_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_446_/RESET_B(low) - - min_pulse_width untested no_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_429_/SET_B(low) - - min_pulse_width untested no_clock
_429_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_429_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_451_/SET_B(low) - - min_pulse_width untested no_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_450_/RESET_B(low) - - min_pulse_width untested no_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_430_/RESET_B(low) - - min_pulse_width untested no_clock
_430_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_430_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_452_/RESET_B(low) - - min_pulse_width untested no_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_426_/SET_B(low) - - min_pulse_width untested no_clock
_426_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_426_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_421_/RESET_B(low) - - min_pulse_width untested no_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_425_/RESET_B(low) - - min_pulse_width untested no_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_427_/RESET_B(low) - - min_pulse_width untested no_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_423_/RESET_B(low) - - min_pulse_width untested no_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_453_/RESET_B(low) - - min_pulse_width untested no_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_428_/RESET_B(low) - - min_pulse_width untested no_clock
_428_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_428_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_454_/SET_B(low) - - min_pulse_width untested no_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_448_/RESET_B(low) - - min_pulse_width untested no_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
1

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****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:18 2022
****************************************
Setup violations for paths in pll_clk90
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -1.7781 -1.7781 0.0000 0.0000 0.0000
TNS -5.6539 -5.6539 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
Setup violations for paths in pll_clk
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -1.7904 -1.7904 0.0000 0.0000 0.0000
TNS -5.7314 -5.7314 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
Hold violations for paths in **clock_gating_default**
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -4.9260 -4.9260 0.0000 0.0000 0.0000
TNS -27.9749 -27.9749 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
1

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19671
signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.ss-min_timing.rpt Normal file
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37
signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.tt-all_viol.rpt Normal file
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****************************************
Report : constraint
-all_violators
-path slack_only
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:40 2022
****************************************
min_delay/hold ('clock_gating_default' group)
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -5.5908 (VIOLATED)
_304_/A1 -5.5877 (VIOLATED)
_304_/A3 -5.5796 (VIOLATED)
_308_/A3 -5.5693 (VIOLATED)
_301_/A_N -5.2353 (VIOLATED)
_305_/A_N -5.2178 (VIOLATED)
clock_gating_hold
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -5.5908 (VIOLATED)
_304_/A1 -5.5877 (VIOLATED)
_304_/A3 -5.5796 (VIOLATED)
_308_/A3 -5.5693 (VIOLATED)
_301_/A_N -5.2353 (VIOLATED)
_305_/A_N -5.2178 (VIOLATED)
1

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****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:40 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
hold 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
recovery 53 0 ( 0%) 0 ( 0%) 53 (100%)
removal 53 0 ( 0%) 0 ( 0%) 53 (100%)
min_pulse_width 170 120 ( 71%) 0 ( 0%) 50 ( 29%)
clock_gating_setup 8 8 (100%) 0 ( 0%) 0 ( 0%)
clock_gating_hold 8 2 ( 25%) 6 ( 75%) 0 ( 0%)
out_setup 1 1 (100%) 0 ( 0%) 0 ( 0%)
out_hold 1 1 (100%) 0 ( 0%) 0 ( 0%)
--------------------------------------------------------------------------------
All Checks 412 234 ( 57%) 6 ( 1%) 172 ( 42%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_437_/RESET_B(low) - - min_pulse_width untested no_clock
_437_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_437_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_438_/SET_B(low) - - min_pulse_width untested no_clock
_438_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_438_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_439_/RESET_B(low) - - min_pulse_width untested no_clock
_439_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_439_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_436_/D CLK(rise) - hold untested constant_disabled
_436_/D CLK(rise) - setup untested constant_disabled
_436_/RESET_B(low) - - min_pulse_width untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_415_/RESET_B(low) - - min_pulse_width untested no_clock
_415_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_415_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_434_/D CLK(rise) - hold untested constant_disabled
_434_/D CLK(rise) - setup untested constant_disabled
_434_/RESET_B(low) - - min_pulse_width untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_413_/RESET_B(low) - - min_pulse_width untested no_clock
_413_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_413_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_412_/D CLK(rise) pll_clk hold untested false_paths
_412_/D CLK(rise) pll_clk setup untested false_paths
_412_/RESET_B(low) - - min_pulse_width untested no_clock
_412_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_412_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/D CLK(rise) - hold untested constant_disabled
_411_/D CLK(rise) - setup untested constant_disabled
_411_/SET_B(low) - - min_pulse_width untested no_clock
_411_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_435_/D CLK(rise) - hold untested constant_disabled
_435_/D CLK(rise) - setup untested constant_disabled
_435_/SET_B(low) - - min_pulse_width untested no_clock
_435_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_435_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(low) - - min_pulse_width untested no_clock
_410_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_433_/RESET_B(low) - - min_pulse_width untested no_clock
_433_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_433_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_460_/D CLK(rise) - hold untested constant_disabled
_460_/D CLK(rise) - setup untested constant_disabled
_460_/RESET_B(low) - - min_pulse_width untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_409_/SET_B(low) - - min_pulse_width untested no_clock
_409_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_447_/SET_B(low) - - min_pulse_width untested no_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_456_/SET_B(low) - - min_pulse_width untested no_clock
_456_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_456_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_422_/SET_B(low) - - min_pulse_width untested no_clock
_422_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_422_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_424_/SET_B(low) - - min_pulse_width untested no_clock
_424_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_424_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_461_/D CLK(rise) - hold untested constant_disabled
_461_/D CLK(rise) - setup untested constant_disabled
_461_/SET_B(low) - - min_pulse_width untested no_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_462_/D CLK(rise) - hold untested constant_disabled
_462_/D CLK(rise) - setup untested constant_disabled
_462_/RESET_B(low) - - min_pulse_width untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_464_/SET_B(low) - - min_pulse_width untested no_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_420_/RESET_B(low) - - min_pulse_width untested no_clock
_420_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_420_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_444_/SET_B(low) - - min_pulse_width untested no_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_419_/SET_B(low) - - min_pulse_width untested no_clock
_419_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_419_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_431_/SET_B(low) - - min_pulse_width untested no_clock
_431_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_431_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_445_/RESET_B(low) - - min_pulse_width untested no_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_432_/RESET_B(low) - - min_pulse_width untested no_clock
_432_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_432_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_457_/SET_B(low) - - min_pulse_width untested no_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_414_/SET_B(low) - - min_pulse_width untested no_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_449_/SET_B(low) - - min_pulse_width untested no_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_446_/RESET_B(low) - - min_pulse_width untested no_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_429_/SET_B(low) - - min_pulse_width untested no_clock
_429_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_429_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_451_/SET_B(low) - - min_pulse_width untested no_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_450_/RESET_B(low) - - min_pulse_width untested no_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_430_/RESET_B(low) - - min_pulse_width untested no_clock
_430_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_430_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_452_/RESET_B(low) - - min_pulse_width untested no_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_426_/SET_B(low) - - min_pulse_width untested no_clock
_426_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_426_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_421_/RESET_B(low) - - min_pulse_width untested no_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_425_/RESET_B(low) - - min_pulse_width untested no_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_427_/RESET_B(low) - - min_pulse_width untested no_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_423_/RESET_B(low) - - min_pulse_width untested no_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_453_/RESET_B(low) - - min_pulse_width untested no_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_428_/RESET_B(low) - - min_pulse_width untested no_clock
_428_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_428_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_454_/SET_B(low) - - min_pulse_width untested no_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_448_/RESET_B(low) - - min_pulse_width untested no_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
1

20
signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.tt-global.rpt Normal file
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@ -0,0 +1,20 @@
****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:40 2022
****************************************
Hold violations for paths in **clock_gating_default**
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -5.5908 -5.5908 0.0000 0.0000 0.0000
TNS -32.7805 -32.7805 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
1

15345
signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.tt-max_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

19625
signoff/caravel_clocking/primetime-signoff/reports/min/caravel_clocking.tt-min_timing.rpt Normal file
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File diff suppressed because it is too large Load Diff

37
signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.ff-all_viol.rpt Normal file
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@ -0,0 +1,37 @@
****************************************
Report : constraint
-all_violators
-path slack_only
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:38 2022
****************************************
min_delay/hold ('clock_gating_default' group)
Endpoint Slack
-----------------------------------------------------------------
_304_/A3 -5.7237 (VIOLATED)
_308_/A1 -5.7225 (VIOLATED)
_304_/A1 -5.7207 (VIOLATED)
_308_/A3 -5.7149 (VIOLATED)
_301_/A_N -5.4453 (VIOLATED)
_305_/A_N -5.4304 (VIOLATED)
clock_gating_hold
Endpoint Slack
-----------------------------------------------------------------
_304_/A3 -5.7237 (VIOLATED)
_308_/A1 -5.7225 (VIOLATED)
_304_/A1 -5.7207 (VIOLATED)
_308_/A3 -5.7149 (VIOLATED)
_301_/A_N -5.4453 (VIOLATED)
_305_/A_N -5.4304 (VIOLATED)
1

200
signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.ff-coverage.rpt Normal file
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@ -0,0 +1,200 @@
****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:38 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
hold 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
recovery 53 0 ( 0%) 0 ( 0%) 53 (100%)
removal 53 0 ( 0%) 0 ( 0%) 53 (100%)
min_pulse_width 170 120 ( 71%) 0 ( 0%) 50 ( 29%)
clock_gating_setup 8 8 (100%) 0 ( 0%) 0 ( 0%)
clock_gating_hold 8 2 ( 25%) 6 ( 75%) 0 ( 0%)
out_setup 1 1 (100%) 0 ( 0%) 0 ( 0%)
out_hold 1 1 (100%) 0 ( 0%) 0 ( 0%)
--------------------------------------------------------------------------------
All Checks 412 234 ( 57%) 6 ( 1%) 172 ( 42%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_437_/RESET_B(low) - - min_pulse_width untested no_clock
_437_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_437_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_438_/SET_B(low) - - min_pulse_width untested no_clock
_438_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_438_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_439_/RESET_B(low) - - min_pulse_width untested no_clock
_439_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_439_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_436_/D CLK(rise) - hold untested constant_disabled
_436_/D CLK(rise) - setup untested constant_disabled
_436_/RESET_B(low) - - min_pulse_width untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_415_/RESET_B(low) - - min_pulse_width untested no_clock
_415_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_415_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_434_/D CLK(rise) - hold untested constant_disabled
_434_/D CLK(rise) - setup untested constant_disabled
_434_/RESET_B(low) - - min_pulse_width untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_413_/RESET_B(low) - - min_pulse_width untested no_clock
_413_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_413_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_412_/D CLK(rise) pll_clk hold untested false_paths
_412_/D CLK(rise) pll_clk setup untested false_paths
_412_/RESET_B(low) - - min_pulse_width untested no_clock
_412_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_412_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/D CLK(rise) - hold untested constant_disabled
_411_/D CLK(rise) - setup untested constant_disabled
_411_/SET_B(low) - - min_pulse_width untested no_clock
_411_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_435_/D CLK(rise) - hold untested constant_disabled
_435_/D CLK(rise) - setup untested constant_disabled
_435_/SET_B(low) - - min_pulse_width untested no_clock
_435_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_435_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(low) - - min_pulse_width untested no_clock
_410_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_433_/RESET_B(low) - - min_pulse_width untested no_clock
_433_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_433_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_460_/D CLK(rise) - hold untested constant_disabled
_460_/D CLK(rise) - setup untested constant_disabled
_460_/RESET_B(low) - - min_pulse_width untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_409_/SET_B(low) - - min_pulse_width untested no_clock
_409_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_447_/SET_B(low) - - min_pulse_width untested no_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_456_/SET_B(low) - - min_pulse_width untested no_clock
_456_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_456_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_422_/SET_B(low) - - min_pulse_width untested no_clock
_422_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_422_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_424_/SET_B(low) - - min_pulse_width untested no_clock
_424_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_424_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_461_/D CLK(rise) - hold untested constant_disabled
_461_/D CLK(rise) - setup untested constant_disabled
_461_/SET_B(low) - - min_pulse_width untested no_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_462_/D CLK(rise) - hold untested constant_disabled
_462_/D CLK(rise) - setup untested constant_disabled
_462_/RESET_B(low) - - min_pulse_width untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_464_/SET_B(low) - - min_pulse_width untested no_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_420_/RESET_B(low) - - min_pulse_width untested no_clock
_420_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_420_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_444_/SET_B(low) - - min_pulse_width untested no_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_419_/SET_B(low) - - min_pulse_width untested no_clock
_419_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_419_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_431_/SET_B(low) - - min_pulse_width untested no_clock
_431_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_431_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_445_/RESET_B(low) - - min_pulse_width untested no_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_432_/RESET_B(low) - - min_pulse_width untested no_clock
_432_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_432_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_457_/SET_B(low) - - min_pulse_width untested no_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_414_/SET_B(low) - - min_pulse_width untested no_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_449_/SET_B(low) - - min_pulse_width untested no_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_446_/RESET_B(low) - - min_pulse_width untested no_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_429_/SET_B(low) - - min_pulse_width untested no_clock
_429_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_429_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_451_/SET_B(low) - - min_pulse_width untested no_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_450_/RESET_B(low) - - min_pulse_width untested no_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_430_/RESET_B(low) - - min_pulse_width untested no_clock
_430_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_430_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_452_/RESET_B(low) - - min_pulse_width untested no_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_426_/SET_B(low) - - min_pulse_width untested no_clock
_426_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_426_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_421_/RESET_B(low) - - min_pulse_width untested no_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_425_/RESET_B(low) - - min_pulse_width untested no_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_427_/RESET_B(low) - - min_pulse_width untested no_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_423_/RESET_B(low) - - min_pulse_width untested no_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_453_/RESET_B(low) - - min_pulse_width untested no_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_428_/RESET_B(low) - - min_pulse_width untested no_clock
_428_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_428_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_454_/SET_B(low) - - min_pulse_width untested no_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_448_/RESET_B(low) - - min_pulse_width untested no_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
1

20
signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.ff-global.rpt Normal file
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****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:38:38 2022
****************************************
Hold violations for paths in **clock_gating_default**
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -5.7237 -5.7237 0.0000 0.0000 0.0000
TNS -33.7575 -33.7575 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
1

9863
signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.ff-max_timing.rpt Normal file
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19629
signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.ff-min_timing.rpt Normal file
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78
signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.ss-all_viol.rpt Normal file
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****************************************
Report : constraint
-all_violators
-path slack_only
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:53 2022
****************************************
max_delay/setup ('pll_clk' group)
Endpoint Slack
-----------------------------------------------------------------
_425_/D -1.8536 (VIOLATED)
_427_/D -1.8529 (VIOLATED)
_426_/D -1.4399 (VIOLATED)
_421_/D -0.4231 (VIOLATED)
_423_/D -0.4179 (VIOLATED)
_422_/D -0.0414 (VIOLATED)
max_delay/setup ('pll_clk90' group)
Endpoint Slack
-----------------------------------------------------------------
_450_/D -1.8437 (VIOLATED)
_452_/D -1.8422 (VIOLATED)
_451_/D -1.4243 (VIOLATED)
_448_/D -0.4542 (VIOLATED)
_446_/D -0.3344 (VIOLATED)
_447_/D -0.0657 (VIOLATED)
min_delay/hold ('clock_gating_default' group)
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -4.9261 (VIOLATED)
_304_/A1 -4.9187 (VIOLATED)
_304_/A3 -4.8120 (VIOLATED)
_308_/A3 -4.7838 (VIOLATED)
_301_/A_N -4.2744 (VIOLATED)
_305_/A_N -4.2078 (VIOLATED)
clock_gating_hold
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -4.9261 (VIOLATED)
_304_/A1 -4.9187 (VIOLATED)
_304_/A3 -4.8120 (VIOLATED)
_308_/A3 -4.7838 (VIOLATED)
_301_/A_N -4.2744 (VIOLATED)
_305_/A_N -4.2078 (VIOLATED)
max_transition
Required Actual
Pin Transition Transition Slack
-----------------------------------------------------------------
_212_/S 0.7500 0.9454 -0.1954 (VIOLATED)
_214_/S 0.7500 0.9454 -0.1954 (VIOLATED)
_216_/S 0.7500 0.9454 -0.1954 (VIOLATED)
_284_/A1 0.7500 0.9454 -0.1954 (VIOLATED)
_285_/A1 0.7500 0.9454 -0.1954 (VIOLATED)
_277_/Y 0.7500 0.9454 -0.1954 (VIOLATED)
_229_/S 0.7500 0.9215 -0.1715 (VIOLATED)
_231_/S 0.7500 0.9215 -0.1715 (VIOLATED)
_233_/S 0.7500 0.9215 -0.1715 (VIOLATED)
_269_/A1 0.7500 0.9215 -0.1715 (VIOLATED)
_270_/A1 0.7500 0.9215 -0.1715 (VIOLATED)
_262_/Y 0.7500 0.9215 -0.1715 (VIOLATED)
1

200
signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.ss-coverage.rpt Normal file
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****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:53 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 59 39 ( 66%) 12 ( 20%) 8 ( 14%)
hold 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
recovery 53 0 ( 0%) 0 ( 0%) 53 (100%)
removal 53 0 ( 0%) 0 ( 0%) 53 (100%)
min_pulse_width 170 120 ( 71%) 0 ( 0%) 50 ( 29%)
clock_gating_setup 8 8 (100%) 0 ( 0%) 0 ( 0%)
clock_gating_hold 8 2 ( 25%) 6 ( 75%) 0 ( 0%)
out_setup 1 1 (100%) 0 ( 0%) 0 ( 0%)
out_hold 1 1 (100%) 0 ( 0%) 0 ( 0%)
--------------------------------------------------------------------------------
All Checks 412 222 ( 54%) 18 ( 4%) 172 ( 42%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_437_/RESET_B(low) - - min_pulse_width untested no_clock
_437_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_437_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_438_/SET_B(low) - - min_pulse_width untested no_clock
_438_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_438_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_439_/RESET_B(low) - - min_pulse_width untested no_clock
_439_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_439_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_436_/D CLK(rise) - hold untested constant_disabled
_436_/D CLK(rise) - setup untested constant_disabled
_436_/RESET_B(low) - - min_pulse_width untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_415_/RESET_B(low) - - min_pulse_width untested no_clock
_415_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_415_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_434_/D CLK(rise) - hold untested constant_disabled
_434_/D CLK(rise) - setup untested constant_disabled
_434_/RESET_B(low) - - min_pulse_width untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_413_/RESET_B(low) - - min_pulse_width untested no_clock
_413_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_413_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_412_/D CLK(rise) pll_clk hold untested false_paths
_412_/D CLK(rise) pll_clk setup untested false_paths
_412_/RESET_B(low) - - min_pulse_width untested no_clock
_412_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_412_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/D CLK(rise) - hold untested constant_disabled
_411_/D CLK(rise) - setup untested constant_disabled
_411_/SET_B(low) - - min_pulse_width untested no_clock
_411_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_435_/D CLK(rise) - hold untested constant_disabled
_435_/D CLK(rise) - setup untested constant_disabled
_435_/SET_B(low) - - min_pulse_width untested no_clock
_435_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_435_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(low) - - min_pulse_width untested no_clock
_410_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_433_/RESET_B(low) - - min_pulse_width untested no_clock
_433_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_433_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_460_/D CLK(rise) - hold untested constant_disabled
_460_/D CLK(rise) - setup untested constant_disabled
_460_/RESET_B(low) - - min_pulse_width untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_409_/SET_B(low) - - min_pulse_width untested no_clock
_409_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_447_/SET_B(low) - - min_pulse_width untested no_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_456_/SET_B(low) - - min_pulse_width untested no_clock
_456_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_456_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_422_/SET_B(low) - - min_pulse_width untested no_clock
_422_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_422_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_424_/SET_B(low) - - min_pulse_width untested no_clock
_424_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_424_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_461_/D CLK(rise) - hold untested constant_disabled
_461_/D CLK(rise) - setup untested constant_disabled
_461_/SET_B(low) - - min_pulse_width untested no_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_462_/D CLK(rise) - hold untested constant_disabled
_462_/D CLK(rise) - setup untested constant_disabled
_462_/RESET_B(low) - - min_pulse_width untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_464_/SET_B(low) - - min_pulse_width untested no_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_420_/RESET_B(low) - - min_pulse_width untested no_clock
_420_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_420_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_444_/SET_B(low) - - min_pulse_width untested no_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_419_/SET_B(low) - - min_pulse_width untested no_clock
_419_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_419_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_431_/SET_B(low) - - min_pulse_width untested no_clock
_431_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_431_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_445_/RESET_B(low) - - min_pulse_width untested no_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_432_/RESET_B(low) - - min_pulse_width untested no_clock
_432_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_432_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_457_/SET_B(low) - - min_pulse_width untested no_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_414_/SET_B(low) - - min_pulse_width untested no_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_449_/SET_B(low) - - min_pulse_width untested no_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_446_/RESET_B(low) - - min_pulse_width untested no_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_429_/SET_B(low) - - min_pulse_width untested no_clock
_429_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_429_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_451_/SET_B(low) - - min_pulse_width untested no_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_450_/RESET_B(low) - - min_pulse_width untested no_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_430_/RESET_B(low) - - min_pulse_width untested no_clock
_430_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_430_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_452_/RESET_B(low) - - min_pulse_width untested no_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_426_/SET_B(low) - - min_pulse_width untested no_clock
_426_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_426_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_421_/RESET_B(low) - - min_pulse_width untested no_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_425_/RESET_B(low) - - min_pulse_width untested no_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_427_/RESET_B(low) - - min_pulse_width untested no_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_423_/RESET_B(low) - - min_pulse_width untested no_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_453_/RESET_B(low) - - min_pulse_width untested no_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_428_/RESET_B(low) - - min_pulse_width untested no_clock
_428_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_428_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_454_/SET_B(low) - - min_pulse_width untested no_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_448_/RESET_B(low) - - min_pulse_width untested no_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
1

38
signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.ss-global.rpt Normal file
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****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:53 2022
****************************************
Setup violations for paths in pll_clk90
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -1.8437 -1.8437 0.0000 0.0000 0.0000
TNS -5.9643 -5.9643 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
Setup violations for paths in pll_clk
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -1.8536 -1.8536 0.0000 0.0000 0.0000
TNS -6.0288 -6.0288 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
Hold violations for paths in **clock_gating_default**
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -4.9261 -4.9261 0.0000 0.0000 0.0000
TNS -27.9228 -27.9228 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
1

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19669
signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.ss-min_timing.rpt Normal file
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signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.tt-all_viol.rpt Normal file
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****************************************
Report : constraint
-all_violators
-path slack_only
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:12 2022
****************************************
min_delay/hold ('clock_gating_default' group)
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -5.5907 (VIOLATED)
_304_/A1 -5.5875 (VIOLATED)
_304_/A3 -5.5808 (VIOLATED)
_308_/A3 -5.5690 (VIOLATED)
_301_/A_N -5.2242 (VIOLATED)
_305_/A_N -5.2053 (VIOLATED)
clock_gating_hold
Endpoint Slack
-----------------------------------------------------------------
_308_/A1 -5.5907 (VIOLATED)
_304_/A1 -5.5875 (VIOLATED)
_304_/A3 -5.5808 (VIOLATED)
_308_/A3 -5.5690 (VIOLATED)
_301_/A_N -5.2242 (VIOLATED)
_305_/A_N -5.2053 (VIOLATED)
1

200
signoff/caravel_clocking/primetime-signoff/reports/nom/caravel_clocking.tt-coverage.rpt Normal file
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****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:12 2022
****************************************
Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
setup 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
hold 59 51 ( 86%) 0 ( 0%) 8 ( 14%)
recovery 53 0 ( 0%) 0 ( 0%) 53 (100%)
removal 53 0 ( 0%) 0 ( 0%) 53 (100%)
min_pulse_width 170 120 ( 71%) 0 ( 0%) 50 ( 29%)
clock_gating_setup 8 8 (100%) 0 ( 0%) 0 ( 0%)
clock_gating_hold 8 2 ( 25%) 6 ( 75%) 0 ( 0%)
out_setup 1 1 (100%) 0 ( 0%) 0 ( 0%)
out_hold 1 1 (100%) 0 ( 0%) 0 ( 0%)
--------------------------------------------------------------------------------
All Checks 412 234 ( 57%) 6 ( 1%) 172 ( 42%)
Constrained Related Check
Pin Pin Clock Type Slack Reason
--------------------------------------------------------------------------------
_437_/RESET_B(low) - - min_pulse_width untested no_clock
_437_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_437_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_438_/SET_B(low) - - min_pulse_width untested no_clock
_438_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_438_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_439_/RESET_B(low) - - min_pulse_width untested no_clock
_439_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_439_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_436_/D CLK(rise) - hold untested constant_disabled
_436_/D CLK(rise) - setup untested constant_disabled
_436_/RESET_B(low) - - min_pulse_width untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_436_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_415_/RESET_B(low) - - min_pulse_width untested no_clock
_415_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_415_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_434_/D CLK(rise) - hold untested constant_disabled
_434_/D CLK(rise) - setup untested constant_disabled
_434_/RESET_B(low) - - min_pulse_width untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_434_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_413_/RESET_B(low) - - min_pulse_width untested no_clock
_413_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_413_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_459_/RESET_B(low) - - min_pulse_width untested no_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_459_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_412_/D CLK(rise) pll_clk hold untested false_paths
_412_/D CLK(rise) pll_clk setup untested false_paths
_412_/RESET_B(low) - - min_pulse_width untested no_clock
_412_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_412_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/D CLK(rise) - hold untested constant_disabled
_411_/D CLK(rise) - setup untested constant_disabled
_411_/SET_B(low) - - min_pulse_width untested no_clock
_411_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_411_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_435_/D CLK(rise) - hold untested constant_disabled
_435_/D CLK(rise) - setup untested constant_disabled
_435_/SET_B(low) - - min_pulse_width untested no_clock
_435_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_435_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(low) - - min_pulse_width untested no_clock
_410_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_410_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_433_/RESET_B(low) - - min_pulse_width untested no_clock
_433_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_433_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_460_/D CLK(rise) - hold untested constant_disabled
_460_/D CLK(rise) - setup untested constant_disabled
_460_/RESET_B(low) - - min_pulse_width untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_460_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_409_/SET_B(low) - - min_pulse_width untested no_clock
_409_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk recovery untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_409_/SET_B(rise) CLK(rise) ext_clk removal untested no_startpoint_clock
_447_/SET_B(low) - - min_pulse_width untested no_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_447_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_456_/SET_B(low) - - min_pulse_width untested no_clock
_456_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_456_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_422_/SET_B(low) - - min_pulse_width untested no_clock
_422_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_422_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_424_/SET_B(low) - - min_pulse_width untested no_clock
_424_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_424_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_461_/D CLK(rise) - hold untested constant_disabled
_461_/D CLK(rise) - setup untested constant_disabled
_461_/SET_B(low) - - min_pulse_width untested no_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_461_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_462_/D CLK(rise) - hold untested constant_disabled
_462_/D CLK(rise) - setup untested constant_disabled
_462_/RESET_B(low) - - min_pulse_width untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - recovery untested constant_disabled
_462_/RESET_B(rise) CLK(rise) - removal untested constant_disabled
_463_/RESET_B(low) - - min_pulse_width untested no_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_463_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_464_/SET_B(low) - - min_pulse_width untested no_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_464_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_465_/RESET_B(low) - - min_pulse_width untested no_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_465_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_420_/RESET_B(low) - - min_pulse_width untested no_clock
_420_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_420_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_458_/RESET_B(low) - - min_pulse_width untested no_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_458_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_444_/SET_B(low) - - min_pulse_width untested no_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_444_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_419_/SET_B(low) - - min_pulse_width untested no_clock
_419_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_419_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_431_/SET_B(low) - - min_pulse_width untested no_clock
_431_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_431_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_445_/RESET_B(low) - - min_pulse_width untested no_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_445_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_432_/RESET_B(low) - - min_pulse_width untested no_clock
_432_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_432_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_457_/SET_B(low) - - min_pulse_width untested no_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_457_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_414_/SET_B(low) - - min_pulse_width untested no_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_414_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_449_/SET_B(low) - - min_pulse_width untested no_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_449_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_446_/RESET_B(low) - - min_pulse_width untested no_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_446_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_429_/SET_B(low) - - min_pulse_width untested no_clock
_429_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_429_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_451_/SET_B(low) - - min_pulse_width untested no_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_451_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_450_/RESET_B(low) - - min_pulse_width untested no_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_450_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_430_/RESET_B(low) - - min_pulse_width untested no_clock
_430_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_430_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_452_/RESET_B(low) - - min_pulse_width untested no_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_452_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
_426_/SET_B(low) - - min_pulse_width untested no_clock
_426_/SET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_426_/SET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_421_/RESET_B(low) - - min_pulse_width untested no_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_421_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_425_/RESET_B(low) - - min_pulse_width untested no_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_425_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_427_/RESET_B(low) - - min_pulse_width untested no_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_427_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_455_/RESET_B(low) - - min_pulse_width untested no_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_455_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_423_/RESET_B(low) - - min_pulse_width untested no_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk recovery untested no_startpoint_clock
_423_/RESET_B(rise) CLK_N(fall) pll_clk removal untested no_startpoint_clock
_453_/RESET_B(low) - - min_pulse_width untested no_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_453_/RESET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_428_/RESET_B(low) - - min_pulse_width untested no_clock
_428_/RESET_B(rise) CLK(rise) pll_clk recovery untested no_startpoint_clock
_428_/RESET_B(rise) CLK(rise) pll_clk removal untested no_startpoint_clock
_454_/SET_B(low) - - min_pulse_width untested no_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 recovery untested no_startpoint_clock
_454_/SET_B(rise) CLK(rise) pll_clk90 removal untested no_startpoint_clock
_448_/RESET_B(low) - - min_pulse_width untested no_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 recovery untested no_startpoint_clock
_448_/RESET_B(rise) CLK_N(fall) pll_clk90 removal untested no_startpoint_clock
1

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****************************************
Report : global_timing
-format { narrow }
-separate_all_groups
Design : caravel_clocking
Version: T-2022.03-SP3
Date : Tue Oct 18 15:37:12 2022
****************************************
Hold violations for paths in **clock_gating_default**
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -5.5907 -5.5907 0.0000 0.0000 0.0000
TNS -32.7575 -32.7575 0.0000 0.0000 0.0000
NUM 6 6 0 0 0
---------------------------------------------------------
1

15465
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19625
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4651
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Klayout MR DRC: Passed
Layout Vs Schematic: Passed
caravel_clocking-max-t-sta STA: Failed
caravel_clocking-max-f-sta STA: Failed
caravel_clocking-min-t-sta STA: Failed
caravel_clocking-nom-s-sta STA: Failed
caravel_clocking-nom-f-sta STA: Failed
caravel_clocking-min-s-sta STA: Failed
caravel_clocking-nom-t-sta STA: Failed
caravel_clocking-max-s-sta STA: Failed
caravel_clocking-min-f-sta STA: Failed

2718
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1612
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0
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<?xml version="1.0" encoding="utf-8"?>
<report-database>
<description>SKY130 DRC runset</description>
<original-file/>
<generator>drc: script='tech-files/sky130A_mr.drc'</generator>
<top-cell>caravel_clocking</top-cell>
<tags>
</tags>
<categories>
<category>
<name>dnwell.2</name>
<description>dnwell.2 : min. dnwell width : 3.0um</description>
<categories>
</categories>
</category>
<category>
<name>nwell.1</name>
<description>nwell.1 : min. nwell width : 0.84um</description>
<categories>
</categories>
</category>
<category>
<name>nwell.2a</name>
<description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
<categories>
</categories>
</category>
<category>
<name>nwell.6</name>
<description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
<categories>
</categories>
</category>
<category>
<name>hvtp.1</name>
<description>hvtp.1 : min. hvtp width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>hvtp.2</name>
<description>hvtp.2 : min. hvtp spacing : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>hvtr.1</name>
<description>hvtr.1 : min. hvtr width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>hvtr.2</name>
<description>hvtr.2 : min. hvtr spacing : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>hvtr.2_a</name>
<description>hvtr.2_a : hvtr must not overlap hvtp</description>
<categories>
</categories>
</category>
<category>
<name>lvtn.1a</name>
<description>lvtn.1a : min. lvtn width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>lvtn.2</name>
<description>lvtn.2 : min. lvtn spacing : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>ncm.1</name>
<description>ncm.1 : min. ncm width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>ncm.2a</name>
<description>ncm.2a : min. ncm spacing : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>difftap.1</name>
<description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>difftap.1_a</name>
<description>difftap.1_a : min. diff width in periphery : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>difftap.1_b</name>
<description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>difftap.1_c</name>
<description>difftap.1_c : min. tap width in periphery : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>difftap.3</name>
<description>difftap.3 : min. difftap spacing : 0.27um</description>
<categories>
</categories>
</category>
<category>
<name>tunm.1</name>
<description>tunm.1 : min. tunm width : 0.41um</description>
<categories>
</categories>
</category>
<category>
<name>tunm.2</name>
<description>tunm.2 : min. tunm spacing : 0.5um</description>
<categories>
</categories>
</category>
<category>
<name>poly.1a</name>
<description>poly.1a : min. poly width : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>poly.2</name>
<description>poly.2 : min. poly spacing : 0.21um</description>
<categories>
</categories>
</category>
<category>
<name>rpm.1a</name>
<description>rpm.1a : min. rpm width : 1.27um</description>
<categories>
</categories>
</category>
<category>
<name>rpm.2</name>
<description>rpm.2 : min. rpm spacing : 0.84um</description>
<categories>
</categories>
</category>
<category>
<name>urpm.1a</name>
<description>urpm.1a : min. rpm width : 1.27um</description>
<categories>
</categories>
</category>
<category>
<name>urpm.2</name>
<description>urpm.2 : min. rpm spacing : 0.84um</description>
<categories>
</categories>
</category>
<category>
<name>npc.1</name>
<description>npc.1 : min. npc width : 0.27um</description>
<categories>
</categories>
</category>
<category>
<name>npc.2</name>
<description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
<categories>
</categories>
</category>
<category>
<name>nsd.1</name>
<description>nsd.1 : min. nsdm width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>nsd.2</name>
<description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>psd.1</name>
<description>psd.1 : min. psdm width : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>psd.2</name>
<description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
<categories>
</categories>
</category>
<category>
<name>licon.1</name>
<description>licon.1 : licon should be rectangle</description>
<categories>
</categories>
</category>
<category>
<name>licon.1_a/b</name>
<description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>licon.13</name>
<description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
<categories>
</categories>
</category>
<category>
<name>licon.13_a</name>
<description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
<categories>
</categories>
</category>
<category>
<name>licon.17</name>
<description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
<categories>
</categories>
</category>
<category>
<name>capm.1</name>
<description>capm.1 : min. capm width : 1.0um</description>
<categories>
</categories>
</category>
<category>
<name>capm.2a</name>
<description>capm.2a : min. capm spacing : 0.84um</description>
<categories>
</categories>
</category>
<category>
<name>capm.2b</name>
<description>capm.2b : min. capm spacing : 1.2um</description>
<categories>
</categories>
</category>
<category>
<name>capm.2b_a</name>
<description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
<categories>
</categories>
</category>
<category>
<name>capm.3</name>
<description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>capm.3_a</name>
<description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>capm.4</name>
<description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>capm.5</name>
<description>capm.5 : min. capm spacing to via3 : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>capm.11</name>
<description>capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.1</name>
<description>cap2m.1 : min. cap2m width : 1.0um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.2a</name>
<description>cap2m.2a : min. cap2m spacing : 0.84um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.2b</name>
<description>cap2m.2b : min. cap2m spacing : 1.2um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.2b_a</name>
<description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.3</name>
<description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.3_a</name>
<description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.4</name>
<description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.5</name>
<description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>cap2m.11</name>
<description>cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um</description>
<categories>
</categories>
</category>
<category>
<name>li.1</name>
<description>li.1 : min. li width : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>li.3</name>
<description>li.3 : min. li spacing : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>li.5</name>
<description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
<categories>
</categories>
</category>
<category>
<name>li.6</name>
<description>li.6 : min. li area : 0.0561um²</description>
<categories>
</categories>
</category>
<category>
<name>ct.1</name>
<description>ct.1: non-ring mcon should be rectangular</description>
<categories>
</categories>
</category>
<category>
<name>ct.1_a</name>
<description>ct.1_a : minimum width of mcon : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>ct.1_b</name>
<description>ct.1_b : maximum length of mcon : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>ct.2</name>
<description>ct.2 : min. mcon spacing : 0.19um</description>
<categories>
</categories>
</category>
<category>
<name>ct.3</name>
<description>ct.3 : min. width of ring-shaped mcon : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>ct.3_a</name>
<description>ct.3_a : max. width of ring-shaped mcon : 0.175um</description>
<categories>
</categories>
</category>
<category>
<name>ct.3_b</name>
<description>ct.3_b: ring-shaped mcon must be enclosed by areaid_sl</description>
<categories>
</categories>
</category>
<category>
<name>ct.4</name>
<description>ct.4 : mcon should covered by li</description>
<categories>
</categories>
</category>
<category>
<name>m1.1</name>
<description>m1.1 : min. m1 width : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>m1.2</name>
<description>m1.2 : min. m1 spacing : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>m1.3ab</name>
<description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
<categories>
</categories>
</category>
<category>
<name>791_m1.4</name>
<description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
<categories>
</categories>
</category>
<category>
<name>m1.4</name>
<description>m1.4 : mcon periphery must be enclosed by m1</description>
<categories>
</categories>
</category>
<category>
<name>m1.4a</name>
<description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
<categories>
</categories>
</category>
<category>
<name>m1.4a_a</name>
<description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
<categories>
</categories>
</category>
<category>
<name>m1.6</name>
<description>m1.6 : min. m1 area : 0.083um²</description>
<categories>
</categories>
</category>
<category>
<name>m1.7</name>
<description>m1.7 : min. m1 with holes area : 0.14um²</description>
<categories>
</categories>
</category>
<category>
<name>m1.5</name>
<description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
<categories>
</categories>
</category>
<category>
<name>via.1a</name>
<description>via.1a : via outside of moduleCut should be rectangular</description>
<categories>
</categories>
</category>
<category>
<name>via.1a_a</name>
<description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>via.1a_b</name>
<description>via.1a_b : maximum length of via : 0.15um</description>
<categories>
</categories>
</category>
<category>
<name>via.2</name>
<description>via.2 : min. via spacing : 0.17um</description>
<categories>
</categories>
</category>
<category>
<name>via.3</name>
<description>via.3 : min. width of ring-shaped via : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via.3_a</name>
<description>via.3_a : max. width of ring-shaped via : 0.205um</description>
<categories>
</categories>
</category>
<category>
<name>via.3_b</name>
<description>via.3_b: ring-shaped via must be enclosed by areaid_sl</description>
<categories>
</categories>
</category>
<category>
<name>via.4a</name>
<description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
<categories>
</categories>
</category>
<category>
<name>via.4a_a</name>
<description>via.4a_a : 0.15um via must be enclosed by met1</description>
<categories>
</categories>
</category>
<category>
<name>via.5a</name>
<description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
<categories>
</categories>
</category>
<category>
<name>m2.1</name>
<description>m2.1 : min. m2 width : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>m2.2</name>
<description>m2.2 : min. m2 spacing : 0.14um</description>
<categories>
</categories>
</category>
<category>
<name>m2.3ab</name>
<description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
<categories>
</categories>
</category>
<category>
<name>m2.6</name>
<description>m2.6 : min. m2 area : 0.0676um²</description>
<categories>
</categories>
</category>
<category>
<name>m2.7</name>
<description>m2.7 : min. m2 holes area : 0.14um²</description>
<categories>
</categories>
</category>
<category>
<name>m2.4</name>
<description>m2.4 : min. m2 enclosure of via : 0.055um</description>
<categories>
</categories>
</category>
<category>
<name>m2.4_a</name>
<description>m2.4_a : via in periphery must be enclosed by met2</description>
<categories>
</categories>
</category>
<category>
<name>m2.5</name>
<description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
<categories>
</categories>
</category>
<category>
<name>via2.1a</name>
<description>via2.1a : via2 outside of moduleCut should be rectangular</description>
<categories>
</categories>
</category>
<category>
<name>via2.1a_a</name>
<description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via2.1a_b</name>
<description>via2.1a_b : maximum length of via2 : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via2.2</name>
<description>via2.2 : min. via2 spacing : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via2.3</name>
<description>via2.3 : min. width of ring-shaped via2 : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via2.3_a</name>
<description>via2.3_a : max. width of ring-shaped via2 : 0.205um</description>
<categories>
</categories>
</category>
<category>
<name>via2.3_b</name>
<description>via2.3_b: ring-shaped via2 must be enclosed by areaid_sl</description>
<categories>
</categories>
</category>
<category>
<name>via2.4</name>
<description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
<categories>
</categories>
</category>
<category>
<name>via2.4_a</name>
<description>via2.4_a : via must be enclosed by met2</description>
<categories>
</categories>
</category>
<category>
<name>via2.5</name>
<description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
<categories>
</categories>
</category>
<category>
<name>m3.1</name>
<description>m3.1 : min. m3 width : 0.3um</description>
<categories>
</categories>
</category>
<category>
<name>m3.2</name>
<description>m3.2 : min. m3 spacing : 0.3um</description>
<categories>
</categories>
</category>
<category>
<name>m3.3cd</name>
<description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
<categories>
</categories>
</category>
<category>
<name>m3.4</name>
<description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
<categories>
</categories>
</category>
<category>
<name>m3.4_a</name>
<description>m3.4_a : via2 must be enclosed by met3</description>
<categories>
</categories>
</category>
<category>
<name>via3.1</name>
<description>via3.1 : via3 outside of moduleCut should be rectangular</description>
<categories>
</categories>
</category>
<category>
<name>via3.1_a</name>
<description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via3.1_b</name>
<description>via3.1_b : maximum length of via3 : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via3.2</name>
<description>via3.2 : min. via3 spacing : 0.2um</description>
<categories>
</categories>
</category>
<category>
<name>via3.4</name>
<description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
<categories>
</categories>
</category>
<category>
<name>via3.4_a</name>
<description>via3.4_a : non-ring via3 must be enclosed by met3</description>
<categories>
</categories>
</category>
<category>
<name>via3.5</name>
<description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
<categories>
</categories>
</category>
<category>
<name>m4.1</name>
<description>m4.1 : min. m4 width : 0.3um</description>
<categories>
</categories>
</category>
<category>
<name>m4.2</name>
<description>m4.2 : min. m4 spacing : 0.3um</description>
<categories>
</categories>
</category>
<category>
<name>m4.4a</name>
<description>m4.4a : min. m4 area : 0.240um²</description>
<categories>
</categories>
</category>
<category>
<name>m4.5ab</name>
<description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
<categories>
</categories>
</category>
<category>
<name>m4.3</name>
<description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
<categories>
</categories>
</category>
<category>
<name>m4.3_a</name>
<description>m4.3_a : via3 must be enclosed by met4</description>
<categories>
</categories>
</category>
<category>
<name>via4.1</name>
<description>via4.1 : via4 outside of moduleCut should be rectangular</description>
<categories>
</categories>
</category>
<category>
<name>via4.1_a</name>
<description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
<categories>
</categories>
</category>
<category>
<name>via4.1_b</name>
<description>via4.1_b : maximum length of via4 : 0.8um</description>
<categories>
</categories>
</category>
<category>
<name>via4.2</name>
<description>via4.2 : min. via4 spacing : 0.8um</description>
<categories>
</categories>
</category>
<category>
<name>via4.3</name>
<description>via4.3 : min. width of ring-shaped via4 : 0.8um</description>
<categories>
</categories>
</category>
<category>
<name>via4.3_a</name>
<description>via4.3_a : max. width of ring-shaped via4 : 0.805um</description>
<categories>
</categories>
</category>
<category>
<name>via4.3_b</name>
<description>via4.3_b: ring-shaped via4 must be enclosed by areaid_sl</description>
<categories>
</categories>
</category>
<category>
<name>via4.4</name>
<description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
<categories>
</categories>
</category>
<category>
<name>via4.4_a</name>
<description>via4.4_a : m4 must enclose all via4</description>
<categories>
</categories>
</category>
<category>
<name>m5.1</name>
<description>m5.1 : min. m5 width : 1.6um</description>
<categories>
</categories>
</category>
<category>
<name>m5.2</name>
<description>m5.2 : min. m5 spacing : 1.6um</description>
<categories>
</categories>
</category>
<category>
<name>m5.3</name>
<description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
<categories>
</categories>
</category>
<category>
<name>m5.3_a</name>
<description>m5.3_a : via must be enclosed by m5</description>
<categories>
</categories>
</category>
<category>
<name>m5.4</name>
<description>m5.4 : min. m5 area : 4.0um²</description>
<categories>
</categories>
</category>
<category>
<name>pad.2</name>
<description>pad.2 : min. pad spacing : 1.27um</description>
<categories>
</categories>
</category>
<category>
<name>hvi.1</name>
<description>hvi.1 : min. hvi width : 0.6um</description>
<categories>
</categories>
</category>
<category>
<name>hvi.2a</name>
<description>hvi.2a : min. hvi spacing : 0.7um</description>
<categories>
</categories>
</category>
<category>
<name>hvntm.1</name>
<description>hvntm.1 : min. hvntm width : 0.7um</description>
<categories>
</categories>
</category>
<category>
<name>hvntm.2</name>
<description>hvntm.2 : min. hvntm spacing : 0.7um</description>
<categories>
</categories>
</category>
</categories>
<cells>
<cell>
<name>caravel_clocking</name>
<variant/>
<references>
</references>
</cell>
</cells>
<items>
</items>
</report-database>

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