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Fix power guards

This commit is contained in:
M0stafaRady 2023-06-12 09:28:56 -07:00
parent 0738d1bc19
commit 082e52c41d
3 changed files with 15 additions and 6 deletions
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2
verilog/rtl/chip_io.v
View File

@ -276,8 +276,10 @@ module chip_io(
wire [6:0] vssd_const_zero; // Constant value for management pins wire [6:0] vssd_const_zero; // Constant value for management pins
constant_block constant_value_inst [6:0] ( constant_block constant_value_inst [6:0] (
`ifdef USE_POWER_PINS
.vccd(vccd), .vccd(vccd),
.vssd(vssd), .vssd(vssd),
`endif // USE_POWER_PINS
.one(vccd_const_one), .one(vccd_const_one),
.zero(vssd_const_zero) .zero(vssd_const_zero)
); );

4
verilog/rtl/pads.v
View File

@ -45,7 +45,7 @@
`define MGMT_ABUTMENT_PINS \ `define MGMT_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\ .AMUXBUS_A(analog_a),\
.AMUXBUS_B(analog_b),\ .AMUXBUS_B(analog_b), `ifdef USE_POWER_PINS \
.VSSA(vssa),\ .VSSA(vssa),\
.VDDA(vdda),\ .VDDA(vdda),\
.VSWITCH(vddio),\ .VSWITCH(vddio),\
@ -55,7 +55,7 @@
.VCCD(vccd),\ .VCCD(vccd),\
.VSSIO(vssio),\ .VSSIO(vssio),\
.VSSD(vssd),\ .VSSD(vssd),\
.VSSIO_Q(vssio_q), .VSSIO_Q(vssio_q), `endif
`else `else
`define USER1_ABUTMENT_PINS `define USER1_ABUTMENT_PINS
`define USER2_ABUTMENT_PINS `define USER2_ABUTMENT_PINS

7
verilog/rtl/simple_por.v
View File

@ -44,12 +44,19 @@ module simple_por(
// down. Note that this is sped way up for verilog simulation; the // down. Note that this is sped way up for verilog simulation; the
// actual circuit is set to a 15ms delay. // actual circuit is set to a 15ms delay.
`ifdef USE_POWER_PINS
always @(posedge vdd3v3) begin always @(posedge vdd3v3) begin
`else
initial begin
`endif
#500 inode <= 1'b1; #500 inode <= 1'b1;
end end
`ifdef USE_POWER_PINS
always @(negedge vdd3v3) begin always @(negedge vdd3v3) begin
#500 inode <= 1'b0; #500 inode <= 1'b0;
end end
`endif
// Instantiate two shmitt trigger buffers in series // Instantiate two shmitt trigger buffers in series