diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index a9626868..34b4c3e8 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -276,8 +276,10 @@ module chip_io(
     wire [6:0] vssd_const_zero;	// Constant value for management pins
 
     constant_block constant_value_inst [6:0] (
+	`ifdef USE_POWER_PINS
 	.vccd(vccd),
 	.vssd(vssd),
+	`endif // USE_POWER_PINS
 	.one(vccd_const_one),
 	.zero(vssd_const_zero)
     );
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index 623fc818..aad49243 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -45,7 +45,7 @@
 
 	`define MGMT_ABUTMENT_PINS \
 	.AMUXBUS_A(analog_a),\
-	.AMUXBUS_B(analog_b),\
+	.AMUXBUS_B(analog_b), `ifdef USE_POWER_PINS \
 	.VSSA(vssa),\
 	.VDDA(vdda),\
 	.VSWITCH(vddio),\
@@ -55,7 +55,7 @@
 	.VCCD(vccd),\
 	.VSSIO(vssio),\
 	.VSSD(vssd),\
-	.VSSIO_Q(vssio_q),
+	.VSSIO_Q(vssio_q), `endif
 `else 
 	`define USER1_ABUTMENT_PINS 
 	`define USER2_ABUTMENT_PINS 
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index 0521c656..67f12b36 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -44,12 +44,19 @@ module simple_por(
     // down.  Note that this is sped way up for verilog simulation;  the
     // actual circuit is set to a 15ms delay.
 
-    always @(posedge vdd3v3) begin
+    `ifdef USE_POWER_PINS
+        always @(posedge vdd3v3) begin
+    `else
+        initial begin
+    `endif
 	#500 inode <= 1'b1;
     end
-    always @(negedge vdd3v3) begin
-	#500 inode <= 1'b0;
-    end
+
+    `ifdef USE_POWER_PINS
+        always @(negedge vdd3v3) begin
+        #500 inode <= 1'b0;
+        end
+    `endif
 
     // Instantiate two shmitt trigger buffers in series