mirror of https://github.com/efabless/caravel.git
244 lines
8.8 KiB
Plaintext
244 lines
8.8 KiB
Plaintext
|
(DELAYFILE
|
||
|
|
(SDFVERSION "3.0")
|
||
|
|
(DESIGN "spare_logic_block")
|
||
|
|
(DATE "Sun Nov 28 13:27:22 2021")
|
||
|
|
(VENDOR "Parallax")
|
||
|
|
(PROGRAM "STA")
|
||
|
|
(VERSION "2.3.0")
|
||
|
|
(DIVIDER /)
|
||
|
|
(VOLTAGE 1.800::1.800)
|
||
|
|
(PROCESS "1.000::1.000")
|
||
|
|
(TEMPERATURE 25.000::25.000)
|
||
|
|
(TIMESCALE 1ns)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "spare_logic_block")
|
||
|
|
(INSTANCE)
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(INTERCONNECT spare_logic_biginv/Y spare_xib (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[0\]/LO spare_xz[0] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[0\]/LO spare_logic_inv\[0\]/A (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[10\]/LO spare_xz[10] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[10\]/LO spare_logic_nor\[1\]/A (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[11\]/LO spare_xz[11] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[11\]/LO spare_logic_nor\[0\]/B (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[12\]/LO spare_xz[12] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[12\]/LO spare_logic_nor\[1\]/B (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[13\]/LO spare_xz[13] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[13\]/LO spare_logic_mux\[0\]/A0 (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[14\]/LO spare_xz[14] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[14\]/LO spare_logic_mux\[1\]/A0 (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[15\]/LO spare_xz[15] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[15\]/LO spare_logic_mux\[0\]/A1 (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[16\]/LO spare_xz[16] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[16\]/LO spare_logic_mux\[1\]/A1 (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[17\]/LO spare_xz[17] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[17\]/LO spare_logic_mux\[0\]/S (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[18\]/LO spare_xz[18] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[18\]/LO spare_logic_mux\[1\]/S (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[19\]/LO spare_xz[19] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[19\]/LO spare_logic_flop\[0\]/D (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[1\]/LO spare_xz[1] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[1\]/LO spare_logic_inv\[1\]/A (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[20\]/LO spare_xz[20] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[20\]/LO spare_logic_flop\[1\]/D (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[21\]/LO spare_xz[21] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[21\]/LO spare_logic_flop\[0\]/CLK (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[22\]/LO spare_xz[22] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[22\]/LO spare_logic_flop\[1\]/CLK (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[23\]/LO spare_xz[23] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[23\]/LO spare_logic_flop\[0\]/SET_B (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[24\]/LO spare_xz[24] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[24\]/LO spare_logic_flop\[1\]/SET_B (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[25\]/LO spare_xz[25] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[25\]/LO spare_logic_flop\[0\]/RESET_B (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[26\]/LO spare_xz[26] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[26\]/LO spare_logic_flop\[1\]/RESET_B (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[2\]/LO spare_xz[2] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[2\]/LO spare_logic_inv\[2\]/A (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[3\]/LO spare_xz[3] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[3\]/LO spare_logic_inv\[3\]/A (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[4\]/LO spare_xz[4] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[4\]/LO spare_logic_biginv/A (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[5\]/LO spare_xz[5] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[5\]/LO spare_logic_nand\[0\]/A (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[6\]/LO spare_xz[6] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[6\]/LO spare_logic_nand\[1\]/A (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[7\]/LO spare_xz[7] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[7\]/LO spare_logic_nand\[0\]/B (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[8\]/LO spare_xz[8] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[8\]/LO spare_logic_nand\[1\]/B (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[9\]/LO spare_xz[9] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_const\[9\]/LO spare_logic_nor\[0\]/A (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_flop\[0\]/Q spare_xfq[0] (0.001::0.001))
|
||
|
|
(INTERCONNECT spare_logic_flop\[0\]/Q_N spare_xfqn[0] (0.001::0.001))
|
||
|
|
(INTERCONNECT spare_logic_flop\[1\]/Q spare_xfq[1] (0.001::0.001))
|
||
|
|
(INTERCONNECT spare_logic_flop\[1\]/Q_N spare_xfqn[1] (0.001::0.001))
|
||
|
|
(INTERCONNECT spare_logic_inv\[0\]/Y spare_xi[0] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_inv\[1\]/Y spare_xi[1] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_inv\[2\]/Y spare_xi[2] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_inv\[3\]/Y spare_xi[3] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_mux\[0\]/X spare_xmx[0] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_mux\[1\]/X spare_xmx[1] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_nand\[0\]/Y spare_xna[0] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_nand\[1\]/Y spare_xna[1] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_nor\[0\]/Y spare_xno[0] (0.000::0.000))
|
||
|
|
(INTERCONNECT spare_logic_nor\[1\]/Y spare_xno[1] (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__inv_8")
|
||
|
|
(INSTANCE spare_logic_biginv)
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A Y (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||
|
|
(INSTANCE spare_logic_flop\[0\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH RESET_B Q_N (0.000::0.000))
|
||
|
|
(IOPATH RESET_B Q () (0.000::0.000))
|
||
|
|
(IOPATH SET_B Q_N () (0.000::0.000))
|
||
|
|
(IOPATH SET_B Q (0.000::0.000))
|
||
|
|
(IOPATH CLK Q_N (0.000::0.000))
|
||
|
|
(IOPATH CLK Q (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(TIMINGCHECK
|
||
|
|
(REMOVAL (posedge SET_B) (posedge CLK) (0.000::0.000))
|
||
|
|
(RECOVERY (posedge SET_B) (posedge CLK) (0.000::0.000))
|
||
|
|
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000::0.000))
|
||
|
|
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000::0.000))
|
||
|
|
(HOLD D (posedge CLK) (0.000::0.000))
|
||
|
|
(SETUP D (posedge CLK) (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||
|
|
(INSTANCE spare_logic_flop\[1\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH RESET_B Q_N (0.000::0.000))
|
||
|
|
(IOPATH RESET_B Q () (0.000::0.000))
|
||
|
|
(IOPATH SET_B Q_N () (0.000::0.000))
|
||
|
|
(IOPATH SET_B Q (0.000::0.000))
|
||
|
|
(IOPATH CLK Q_N (0.000::0.000))
|
||
|
|
(IOPATH CLK Q (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(TIMINGCHECK
|
||
|
|
(REMOVAL (posedge SET_B) (posedge CLK) (0.000::0.000))
|
||
|
|
(RECOVERY (posedge SET_B) (posedge CLK) (0.000::0.000))
|
||
|
|
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000::0.000))
|
||
|
|
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000::0.000))
|
||
|
|
(HOLD D (posedge CLK) (0.000::0.000))
|
||
|
|
(SETUP D (posedge CLK) (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||
|
|
(INSTANCE spare_logic_inv\[0\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A Y (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||
|
|
(INSTANCE spare_logic_inv\[1\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A Y (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||
|
|
(INSTANCE spare_logic_inv\[2\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A Y (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||
|
|
(INSTANCE spare_logic_inv\[3\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A Y (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||
|
|
(INSTANCE spare_logic_mux\[0\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A0 X (0.000::0.000))
|
||
|
|
(IOPATH A1 X (0.000::0.000))
|
||
|
|
(IOPATH S X (0.000::0.000))
|
||
|
|
(IOPATH S X (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||
|
|
(INSTANCE spare_logic_mux\[1\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A0 X (0.000::0.000))
|
||
|
|
(IOPATH A1 X (0.000::0.000))
|
||
|
|
(IOPATH S X (0.000::0.000))
|
||
|
|
(IOPATH S X (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||
|
|
(INSTANCE spare_logic_nand\[0\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A Y (0.000::0.000))
|
||
|
|
(IOPATH B Y (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||
|
|
(INSTANCE spare_logic_nand\[1\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A Y (0.000::0.000))
|
||
|
|
(IOPATH B Y (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||
|
|
(INSTANCE spare_logic_nor\[0\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A Y (0.000::0.000))
|
||
|
|
(IOPATH B Y (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
(CELL
|
||
|
|
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||
|
|
(INSTANCE spare_logic_nor\[1\])
|
||
|
|
(DELAY
|
||
|
|
(ABSOLUTE
|
||
|
|
(IOPATH A Y (0.000::0.000))
|
||
|
|
(IOPATH B Y (0.000::0.000))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|
||
|
|
)
|