mirror of https://github.com/efabless/caravel.git
67 lines
4.2 KiB
Plaintext
67 lines
4.2 KiB
Plaintext
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# input clock pins
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create_clock [get_ports {"ext_clk"} ] -name "ext_clk" -period 25
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create_clock [get_ports {"pll_clk"} ] -name "pll_clk" -period 6.6666666666667
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create_clock [get_ports {"pll_clk90"} ] -name "pll_clk90" -period 6.6666666666667
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# divided PLL clocks
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create_generated_clock -name pll_clk_divided -source [get_ports pll_clk] -divide_by 2 [get_pins _351_/Y]
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create_generated_clock -name pll_clk90_divided -source [get_ports pll_clk90] -divide_by 2 [get_pins _354_/Y]
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# output clock pins, mux selected
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create_generated_clock -name core_ext_clk -source [get_ports ext_clk] -divide_by 1 [get_pins _412_/X]
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create_generated_clock -name core_ext_clk_pll -source [get_ports pll_clk] -divide_by 1 [get_pins _412_/X]
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create_generated_clock -name core_clk -source [get_pins _412_/X] -divide_by 1 [get_pins _393_/X]
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create_generated_clock -name core_clk_pll -source [get_pins _351_/Y] -divide_by 1 [get_pins _393_/X]
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create_generated_clock -name user_clk -source [get_pins _412_/X] -divide_by 1 [get_pins _394_/X]
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create_generated_clock -name user_clk_pll -source [get_pins _354_/Y] -divide_by 1 [get_pins _394_/X]
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# logically exclusive clocks, the generated pll clocks and the ext core clk
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set_clock_groups -logically_exclusive -group core_ext_clk -group core_ext_clk_pll
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set_clock_groups -logically_exclusive -group core_clk -group core_clk_pll
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set_clock_groups -logically_exclusive -group user_clk -group user_clk_pll
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set ext_clk_input_delay_value [expr 25 * $::env(IO_PCT)]
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set ext_clk_output_delay_value [expr 25 * $::env(IO_PCT)]
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set pll_clk_input_delay_value [expr 6.6666666666667 * $::env(IO_PCT)]
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set pll_clk_output_delay_value [expr 6.6666666666667 * $::env(IO_PCT)]
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puts "\[INFO\]: Setting output delay to: $ext_clk_output_delay_value"
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puts "\[INFO\]: Setting input delay to: $ext_clk_input_delay_value"
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {ext_clk_sel}]
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#set_input_delay $input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[0]}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[1]}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[2]}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[0]}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[1]}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[2]}]
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#set_output_delay $output_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {core_clk}]
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set_output_delay $ext_clk_output_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb_sync}]
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#set_output_delay $output_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {user_clk}]
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set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
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# TODO set this as parameter
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set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
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set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
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puts "\[INFO\]: Setting load to: $cap_load"
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set_load $cap_load [all_outputs]
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puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
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set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
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set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
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puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {ext_clk}]
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {pll_clk}]
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {pll_clk90}]
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {core_clk}]
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puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {ext_clk}]
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {pll_clk}]
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {pll_clk90}]
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {core_clk}]
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