2021-11-15 07:50:43 -06:00
|
|
|
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
2021-11-20 09:28:59 -06:00
|
|
|
0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow_completed,0h2m46s,-1,89000.0,0.006,44500.0,67.18,584.66,267,0,0,0,0,0,0,0,0,0,0,-1,4949,1821,-3.73,-5.41,-1,-4.99,-1,-24.41,-36.68,-1,-28.88,-1,3295625.0,0.0,26.02,16.28,3.8,0.0,0.0,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,72,71,6,40,77,0,117,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.7,0,sky130_fd_sc_hd,0,3
|
