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caravel/signoff/caravel_clocking/openlane-signoff/32-caravel_clocking.lef.log

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reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Circuit 1 cell sky130_fd_sc_hd__fill_1 and Circuit 2 cell sky130_fd_sc_hd__fill_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__fill_1 is a placeholder, treated as a black box.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__fill_1 |Circuit 2: sky130_fd_sc_hd__fill_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__fill_1 and sky130_fd_sc_hd__fill_1 are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__tapvpwrvgnd_1 and Circuit 2 cell sky130_fd_sc_hd__tapvpwrvgnd_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__tapvpwrvgnd_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__tapvpwrvgnd_1 |Circuit 2: sky130_fd_sc_hd__tapvpwrvgnd_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__tapvpwrvgnd_1 and sky130_fd_sc_hd__tapvpwrvgnd_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__decap_4 and Circuit 2 cell sky130_fd_sc_hd__decap_4 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__decap_4 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__decap_4 and sky130_fd_sc_hd__decap_4 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__dfrtp_1 and Circuit 2 cell sky130_fd_sc_hd__dfrtp_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__dfrtp_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__dfrtp_1 |Circuit 2: sky130_fd_sc_hd__dfrtp_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
CLK |CLK
D |D
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
RESET_B |RESET_B
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Q |Q
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__dfrtp_1 and sky130_fd_sc_hd__dfrtp_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nor2_1 and Circuit 2 cell sky130_fd_sc_hd__nor2_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nor2_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nor2_1 |Circuit 2: sky130_fd_sc_hd__nor2_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
B |B
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nor2_1 and sky130_fd_sc_hd__nor2_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nand2_1 and Circuit 2 cell sky130_fd_sc_hd__nand2_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nand2_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nand2_1 |Circuit 2: sky130_fd_sc_hd__nand2_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
B |B
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nand2_1 and sky130_fd_sc_hd__nand2_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__decap_3 and Circuit 2 cell sky130_fd_sc_hd__decap_3 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__decap_3 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__decap_3 and sky130_fd_sc_hd__decap_3 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__o21ai_1 and Circuit 2 cell sky130_fd_sc_hd__o21ai_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o21ai_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o21ai_1 |Circuit 2: sky130_fd_sc_hd__o21ai_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A1 |A1
A2 |A2
B1 |B1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o21ai_1 and sky130_fd_sc_hd__o21ai_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__fill_2 and Circuit 2 cell sky130_fd_sc_hd__fill_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__fill_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__fill_2 |Circuit 2: sky130_fd_sc_hd__fill_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__fill_2 and sky130_fd_sc_hd__fill_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nor3b_2 and Circuit 2 cell sky130_fd_sc_hd__nor3b_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nor3b_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nor3b_2 |Circuit 2: sky130_fd_sc_hd__nor3b_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
B |B
C_N |C_N
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nor3b_2 and sky130_fd_sc_hd__nor3b_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_ef_sc_hd__decap_12 and Circuit 2 cell sky130_ef_sc_hd__decap_12 are black boxes.
Warning: Equate pins: cell sky130_ef_sc_hd__decap_12 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_ef_sc_hd__decap_12 |Circuit 2: sky130_ef_sc_hd__decap_12
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_ef_sc_hd__decap_12 and sky130_ef_sc_hd__decap_12 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__clkbuf_16 and Circuit 2 cell sky130_fd_sc_hd__clkbuf_16 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__clkbuf_16 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__dfstp_2 and Circuit 2 cell sky130_fd_sc_hd__dfstp_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__dfstp_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__dfstp_2 |Circuit 2: sky130_fd_sc_hd__dfstp_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CLK |CLK
D |D
SET_B |SET_B
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Q |Q
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__dfstp_2 and sky130_fd_sc_hd__dfstp_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__decap_8 and Circuit 2 cell sky130_fd_sc_hd__decap_8 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__decap_8 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__decap_8 and sky130_fd_sc_hd__decap_8 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nand2b_1 and Circuit 2 cell sky130_fd_sc_hd__nand2b_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nand2b_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nand2b_1 |Circuit 2: sky130_fd_sc_hd__nand2b_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A_N |A_N
B |B
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nand2b_1 and sky130_fd_sc_hd__nand2b_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__diode_2 and Circuit 2 cell sky130_fd_sc_hd__diode_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__diode_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
DIODE |DIODE
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__decap_6 and Circuit 2 cell sky130_fd_sc_hd__decap_6 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__decap_6 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__decap_6 and sky130_fd_sc_hd__decap_6 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nand4bb_1 and Circuit 2 cell sky130_fd_sc_hd__nand4bb_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nand4bb_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nand4bb_1 |Circuit 2: sky130_fd_sc_hd__nand4bb_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A_N |A_N
B_N |B_N
C |C
D |D
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nand4bb_1 and sky130_fd_sc_hd__nand4bb_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__dfstp_1 and Circuit 2 cell sky130_fd_sc_hd__dfstp_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__dfstp_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__dfstp_1 |Circuit 2: sky130_fd_sc_hd__dfstp_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CLK |CLK
D |D
SET_B |SET_B
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Q |Q
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__dfstp_1 and sky130_fd_sc_hd__dfstp_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__mux2_1 and Circuit 2 cell sky130_fd_sc_hd__mux2_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__mux2_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A0 |A0
A1 |A1
S |S
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
X |X
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__mux2_1 and sky130_fd_sc_hd__mux2_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__o21a_1 and Circuit 2 cell sky130_fd_sc_hd__o21a_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o21a_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o21a_1 |Circuit 2: sky130_fd_sc_hd__o21a_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A1 |A1
A2 |A2
B1 |B1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
X |X
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o21a_1 and sky130_fd_sc_hd__o21a_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__dfrtp_2 and Circuit 2 cell sky130_fd_sc_hd__dfrtp_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__dfrtp_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__dfrtp_2 |Circuit 2: sky130_fd_sc_hd__dfrtp_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CLK |CLK
D |D
RESET_B |RESET_B
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Q |Q
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__dfrtp_2 and sky130_fd_sc_hd__dfrtp_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__o2bb2ai_1 and Circuit 2 cell sky130_fd_sc_hd__o2bb2ai_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o2bb2ai_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o2bb2ai_1 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A1_N |A1_N
A2_N |A2_N
B1 |B1
B2 |B2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o2bb2ai_1 and sky130_fd_sc_hd__o2bb2ai_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Circuit 1 cell sky130_fd_sc_hd__inv_2 and Circuit 2 cell sky130_fd_sc_hd__inv_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__inv_2 is a placeholder, treated as a black box.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2
-------------------------------------------|-------------------------------------------
A |A
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__inv_2 and sky130_fd_sc_hd__inv_2 are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nor3_1 and Circuit 2 cell sky130_fd_sc_hd__nor3_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nor3_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nor3_1 |Circuit 2: sky130_fd_sc_hd__nor3_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A |A
B |B
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
C |C
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nor3_1 and sky130_fd_sc_hd__nor3_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__buf_12 and Circuit 2 cell sky130_fd_sc_hd__buf_12 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__buf_12 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__buf_12 |Circuit 2: sky130_fd_sc_hd__buf_12
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__buf_12 and sky130_fd_sc_hd__buf_12 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__a21oi_1 and Circuit 2 cell sky130_fd_sc_hd__a21oi_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__a21oi_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__a21oi_1 |Circuit 2: sky130_fd_sc_hd__a21oi_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A1 |A1
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A2 |A2
B1 |B1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__a21oi_1 and sky130_fd_sc_hd__a21oi_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__xnor2_1 and Circuit 2 cell sky130_fd_sc_hd__xnor2_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__xnor2_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__xnor2_1 |Circuit 2: sky130_fd_sc_hd__xnor2_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A |A
B |B
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__xnor2_1 and sky130_fd_sc_hd__xnor2_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__o2111ai_2 and Circuit 2 cell sky130_fd_sc_hd__o2111ai_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o2111ai_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o2111ai_2 |Circuit 2: sky130_fd_sc_hd__o2111ai_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A1 |A1
A2 |A2
B1 |B1
C1 |C1
D1 |D1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o2111ai_2 and sky130_fd_sc_hd__o2111ai_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__o31ai_2 and Circuit 2 cell sky130_fd_sc_hd__o31ai_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o31ai_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o31ai_2 |Circuit 2: sky130_fd_sc_hd__o31ai_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A1 |A1
A2 |A2
A3 |A3
B1 |B1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o31ai_2 and sky130_fd_sc_hd__o31ai_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__and2_1 and Circuit 2 cell sky130_fd_sc_hd__and2_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__and2_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
B |B
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
X |X
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__and2_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__a41oi_1 and Circuit 2 cell sky130_fd_sc_hd__a41oi_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__a41oi_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__a41oi_1 |Circuit 2: sky130_fd_sc_hd__a41oi_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A1 |A1
A2 |A2
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A3 |A3
A4 |A4
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
B1 |B1
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__a41oi_1 and sky130_fd_sc_hd__a41oi_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__clkinv_4 and Circuit 2 cell sky130_fd_sc_hd__clkinv_4 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__clkinv_4 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__clkinv_4 |Circuit 2: sky130_fd_sc_hd__clkinv_4
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__clkinv_4 and sky130_fd_sc_hd__clkinv_4 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nand2b_2 and Circuit 2 cell sky130_fd_sc_hd__nand2b_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nand2b_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nand2b_2 |Circuit 2: sky130_fd_sc_hd__nand2b_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A_N |A_N
B |B
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nand2b_2 and sky130_fd_sc_hd__nand2b_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__clkinv_2 and Circuit 2 cell sky130_fd_sc_hd__clkinv_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__clkinv_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__clkinv_2 |Circuit 2: sky130_fd_sc_hd__clkinv_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__clkinv_2 and sky130_fd_sc_hd__clkinv_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__clkbuf_2 and Circuit 2 cell sky130_fd_sc_hd__clkbuf_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__clkbuf_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
X |X
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__clkbuf_2 and sky130_fd_sc_hd__clkbuf_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__dfrtn_1 and Circuit 2 cell sky130_fd_sc_hd__dfrtn_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__dfrtn_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__dfrtn_1 |Circuit 2: sky130_fd_sc_hd__dfrtn_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CLK_N |CLK_N
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
D |D
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
RESET_B |RESET_B
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Q |Q
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__dfrtn_1 and sky130_fd_sc_hd__dfrtn_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__inv_4 and Circuit 2 cell sky130_fd_sc_hd__inv_4 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__inv_4 is a placeholder, treated as a black box.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__inv_4 |Circuit 2: sky130_fd_sc_hd__inv_4
-------------------------------------------|-------------------------------------------
A |A
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__inv_4 and sky130_fd_sc_hd__inv_4 are equivalent.
Circuit 1 cell sky130_fd_sc_hd__o2111ai_1 and Circuit 2 cell sky130_fd_sc_hd__o2111ai_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o2111ai_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o2111ai_1 |Circuit 2: sky130_fd_sc_hd__o2111ai_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A1 |A1
A2 |A2
B1 |B1
C1 |C1
D1 |D1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o2111ai_1 and sky130_fd_sc_hd__o2111ai_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__clkbuf_4 and Circuit 2 cell sky130_fd_sc_hd__clkbuf_4 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__clkbuf_4 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A |A
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nand3_1 and Circuit 2 cell sky130_fd_sc_hd__nand3_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nand3_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nand3_1 |Circuit 2: sky130_fd_sc_hd__nand3_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A |A
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
B |B
C |C
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nand3_1 and sky130_fd_sc_hd__nand3_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Circuit 1 cell sky130_fd_sc_hd__o31a_1 and Circuit 2 cell sky130_fd_sc_hd__o31a_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o31a_1 is a placeholder, treated as a black box.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o31a_1 |Circuit 2: sky130_fd_sc_hd__o31a_1
-------------------------------------------|-------------------------------------------
A1 |A1
A2 |A2
A3 |A3
B1 |B1
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o31a_1 and sky130_fd_sc_hd__o31a_1 are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nor3_2 and Circuit 2 cell sky130_fd_sc_hd__nor3_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nor3_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nor3_2 |Circuit 2: sky130_fd_sc_hd__nor3_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A |A
B |B
C |C
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nor3_2 and sky130_fd_sc_hd__nor3_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__dlymetal6s2s_1 and Circuit 2 cell sky130_fd_sc_hd__dlymetal6s2s_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__dlymetal6s2s_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__dlymetal6s2s_1 |Circuit 2: sky130_fd_sc_hd__dlymetal6s2s_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
X |X
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__dlymetal6s2s_1 and sky130_fd_sc_hd__dlymetal6s2s_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__o21bai_1 and Circuit 2 cell sky130_fd_sc_hd__o21bai_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o21bai_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o21bai_1 |Circuit 2: sky130_fd_sc_hd__o21bai_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A1 |A1
A2 |A2
B1_N |B1_N
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o21bai_1 and sky130_fd_sc_hd__o21bai_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Circuit 1 cell sky130_fd_sc_hd__dfrtp_4 and Circuit 2 cell sky130_fd_sc_hd__dfrtp_4 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__dfrtp_4 is a placeholder, treated as a black box.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfrtp_4 |Circuit 2: sky130_fd_sc_hd__dfrtp_4
-------------------------------------------|-------------------------------------------
CLK |CLK
D |D
RESET_B |RESET_B
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Q |Q
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfrtp_4 and sky130_fd_sc_hd__dfrtp_4 are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__clkbuf_1 and Circuit 2 cell sky130_fd_sc_hd__clkbuf_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__clkbuf_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__clkbuf_1 |Circuit 2: sky130_fd_sc_hd__clkbuf_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A |A
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
X |X
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__clkbuf_1 and sky130_fd_sc_hd__clkbuf_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Circuit 1 cell sky130_fd_sc_hd__buf_4 and Circuit 2 cell sky130_fd_sc_hd__buf_4 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__buf_4 is a placeholder, treated as a black box.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4
-------------------------------------------|-------------------------------------------
A |A
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__buf_4 and sky130_fd_sc_hd__buf_4 are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__conb_1 and Circuit 2 cell sky130_fd_sc_hd__conb_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__conb_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
LO |LO
HI |(no matching pin)
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__conb_1 and sky130_fd_sc_hd__conb_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__dfxtp_1 and Circuit 2 cell sky130_fd_sc_hd__dfxtp_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__dfxtp_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CLK |CLK
D |D
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Q |Q
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__dfxtp_1 and sky130_fd_sc_hd__dfxtp_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nand3b_1 and Circuit 2 cell sky130_fd_sc_hd__nand3b_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nand3b_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nand3b_1 |Circuit 2: sky130_fd_sc_hd__nand3b_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A_N |A_N
B |B
C |C
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nand3b_1 and sky130_fd_sc_hd__nand3b_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__a31o_1 and Circuit 2 cell sky130_fd_sc_hd__a31o_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__a31o_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__a31o_1 |Circuit 2: sky130_fd_sc_hd__a31o_1
-------------------------------------------|-------------------------------------------
A1 |A1
A2 |A2
A3 |A3
B1 |B1
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a31o_1 and sky130_fd_sc_hd__a31o_1 are equivalent.
Circuit 1 cell sky130_fd_sc_hd__o22a_1 and Circuit 2 cell sky130_fd_sc_hd__o22a_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o22a_1 is a placeholder, treated as a black box.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o22a_1 |Circuit 2: sky130_fd_sc_hd__o22a_1
-------------------------------------------|-------------------------------------------
A1 |A1
A2 |A2
B1 |B1
B2 |B2
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o22a_1 and sky130_fd_sc_hd__o22a_1 are equivalent.
Circuit 1 cell sky130_fd_sc_hd__buf_2 and Circuit 2 cell sky130_fd_sc_hd__buf_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__buf_2 is a placeholder, treated as a black box.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__buf_2 |Circuit 2: sky130_fd_sc_hd__buf_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A |A
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
X |X
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__buf_2 and sky130_fd_sc_hd__buf_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__o31ai_1 and Circuit 2 cell sky130_fd_sc_hd__o31ai_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o31ai_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o31ai_1 |Circuit 2: sky130_fd_sc_hd__o31ai_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A1 |A1
A2 |A2
A3 |A3
B1 |B1
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o31ai_1 and sky130_fd_sc_hd__o31ai_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__o211ai_4 and Circuit 2 cell sky130_fd_sc_hd__o211ai_4 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o211ai_4 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o211ai_4 |Circuit 2: sky130_fd_sc_hd__o211ai_4
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A1 |A1
A2 |A2
B1 |B1
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
C1 |C1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o211ai_4 and sky130_fd_sc_hd__o211ai_4 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__o21ai_2 and Circuit 2 cell sky130_fd_sc_hd__o21ai_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o21ai_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o21ai_2 |Circuit 2: sky130_fd_sc_hd__o21ai_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A1 |A1
A2 |A2
B1 |B1
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o21ai_2 and sky130_fd_sc_hd__o21ai_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__o21a_2 and Circuit 2 cell sky130_fd_sc_hd__o21a_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__o21a_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__o21a_2 |Circuit 2: sky130_fd_sc_hd__o21a_2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A1 |A1
A2 |A2
B1 |B1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
X |X
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__o21a_2 and sky130_fd_sc_hd__o21a_2 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nor2_2 and Circuit 2 cell sky130_fd_sc_hd__nor2_2 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nor2_2 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nor2_2 |Circuit 2: sky130_fd_sc_hd__nor2_2
-------------------------------------------|-------------------------------------------
A |A
B |B
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor2_2 and sky130_fd_sc_hd__nor2_2 are equivalent.
Circuit 1 cell sky130_fd_sc_hd__a21o_1 and Circuit 2 cell sky130_fd_sc_hd__a21o_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__a21o_1 is a placeholder, treated as a black box.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a21o_1 |Circuit 2: sky130_fd_sc_hd__a21o_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
A1 |A1
A2 |A2
B1 |B1
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__a21o_1 and sky130_fd_sc_hd__a21o_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__nor4_1 and Circuit 2 cell sky130_fd_sc_hd__nor4_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__nor4_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__nor4_1 |Circuit 2: sky130_fd_sc_hd__nor4_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A |A
B |B
C |C
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
D |D
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Y |Y
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__nor4_1 and sky130_fd_sc_hd__nor4_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1 cell sky130_fd_sc_hd__a2bb2o_1 and Circuit 2 cell sky130_fd_sc_hd__a2bb2o_1 are black boxes.
Warning: Equate pins: cell sky130_fd_sc_hd__a2bb2o_1 is a placeholder, treated as a black box.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit pins:
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Circuit 1: sky130_fd_sc_hd__a2bb2o_1 |Circuit 2: sky130_fd_sc_hd__a2bb2o_1
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
A1_N |A1_N
A2_N |A2_N
B1 |B1
B2 |B2
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
X |X
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Device classes sky130_fd_sc_hd__a2bb2o_1 and sky130_fd_sc_hd__a2bb2o_1 are equivalent.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Class caravel_clocking (0): Merged 1191 parallel devices.
Class caravel_clocking (1): Merged 1191 parallel devices.
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Subcircuit summary:
Circuit 1: caravel_clocking |Circuit 2: caravel_clocking
-------------------------------------------|-------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
sky130_fd_sc_hd__fill_1 (282->1) |sky130_fd_sc_hd__fill_1 (282->1)
sky130_fd_sc_hd__tapvpwrvgnd_1 (262->1) |sky130_fd_sc_hd__tapvpwrvgnd_1 (262->1)
sky130_fd_sc_hd__decap_4 (120->1) |sky130_fd_sc_hd__decap_4 (120->1)
sky130_fd_sc_hd__dfrtp_1 (17) |sky130_fd_sc_hd__dfrtp_1 (17)
sky130_fd_sc_hd__nor2_1 (13) |sky130_fd_sc_hd__nor2_1 (13)
sky130_fd_sc_hd__nand2_1 (10) |sky130_fd_sc_hd__nand2_1 (10)
sky130_fd_sc_hd__decap_3 (146->1) |sky130_fd_sc_hd__decap_3 (146->1)
sky130_fd_sc_hd__o21ai_1 (18) |sky130_fd_sc_hd__o21ai_1 (18)
sky130_fd_sc_hd__fill_2 (151->1) |sky130_fd_sc_hd__fill_2 (151->1)
sky130_fd_sc_hd__nor3b_2 (2) |sky130_fd_sc_hd__nor3b_2 (2)
sky130_ef_sc_hd__decap_12 (80->1) |sky130_ef_sc_hd__decap_12 (80->1)
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
sky130_fd_sc_hd__clkbuf_16 (22) |sky130_fd_sc_hd__clkbuf_16 (22)
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
sky130_fd_sc_hd__dfstp_2 (4) |sky130_fd_sc_hd__dfstp_2 (4)
sky130_fd_sc_hd__decap_8 (72->1) |sky130_fd_sc_hd__decap_8 (72->1)
sky130_fd_sc_hd__nand2b_1 (14) |sky130_fd_sc_hd__nand2b_1 (14)
sky130_fd_sc_hd__diode_2 (61->17) |sky130_fd_sc_hd__diode_2 (61->17)
sky130_fd_sc_hd__decap_6 (42->1) |sky130_fd_sc_hd__decap_6 (42->1)
sky130_fd_sc_hd__nand4bb_1 (2) |sky130_fd_sc_hd__nand4bb_1 (2)
sky130_fd_sc_hd__dfstp_1 (17) |sky130_fd_sc_hd__dfstp_1 (17)
sky130_fd_sc_hd__mux2_1 (52) |sky130_fd_sc_hd__mux2_1 (52)
sky130_fd_sc_hd__o21a_1 (5) |sky130_fd_sc_hd__o21a_1 (5)
sky130_fd_sc_hd__dfrtp_2 (2) |sky130_fd_sc_hd__dfrtp_2 (2)
sky130_fd_sc_hd__o2bb2ai_1 (2) |sky130_fd_sc_hd__o2bb2ai_1 (2)
sky130_fd_sc_hd__inv_2 (8) |sky130_fd_sc_hd__inv_2 (8)
sky130_fd_sc_hd__nor3_1 (6) |sky130_fd_sc_hd__nor3_1 (6)
sky130_fd_sc_hd__buf_12 (1) |sky130_fd_sc_hd__buf_12 (1)
sky130_fd_sc_hd__a21oi_1 (4) |sky130_fd_sc_hd__a21oi_1 (4)
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
sky130_fd_sc_hd__xnor2_1 (10) |sky130_fd_sc_hd__xnor2_1 (10)
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
sky130_fd_sc_hd__o2111ai_2 (1) |sky130_fd_sc_hd__o2111ai_2 (1)
sky130_fd_sc_hd__o31ai_2 (2) |sky130_fd_sc_hd__o31ai_2 (2)
sky130_fd_sc_hd__and2_1 (4) |sky130_fd_sc_hd__and2_1 (4)
sky130_fd_sc_hd__a41oi_1 (2) |sky130_fd_sc_hd__a41oi_1 (2)
sky130_fd_sc_hd__clkinv_4 (5) |sky130_fd_sc_hd__clkinv_4 (5)
sky130_fd_sc_hd__nand2b_2 (2) |sky130_fd_sc_hd__nand2b_2 (2)
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
sky130_fd_sc_hd__clkinv_2 (4) |sky130_fd_sc_hd__clkinv_2 (4)
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
sky130_fd_sc_hd__clkbuf_2 (2) |sky130_fd_sc_hd__clkbuf_2 (2)
sky130_fd_sc_hd__dfrtn_1 (8) |sky130_fd_sc_hd__dfrtn_1 (8)
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
sky130_fd_sc_hd__inv_4 (9) |sky130_fd_sc_hd__inv_4 (9)
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
sky130_fd_sc_hd__o2111ai_1 (1) |sky130_fd_sc_hd__o2111ai_1 (1)
sky130_fd_sc_hd__clkbuf_4 (4) |sky130_fd_sc_hd__clkbuf_4 (4)
sky130_fd_sc_hd__nand3_1 (2) |sky130_fd_sc_hd__nand3_1 (2)
sky130_fd_sc_hd__o31a_1 (2) |sky130_fd_sc_hd__o31a_1 (2)
sky130_fd_sc_hd__nor3_2 (2) |sky130_fd_sc_hd__nor3_2 (2)
sky130_fd_sc_hd__dlymetal6s2s_1 (1) |sky130_fd_sc_hd__dlymetal6s2s_1 (1)
sky130_fd_sc_hd__o21bai_1 (2) |sky130_fd_sc_hd__o21bai_1 (2)
sky130_fd_sc_hd__dfrtp_4 (2) |sky130_fd_sc_hd__dfrtp_4 (2)
sky130_fd_sc_hd__clkbuf_1 (8) |sky130_fd_sc_hd__clkbuf_1 (8)
sky130_fd_sc_hd__buf_4 (10) |sky130_fd_sc_hd__buf_4 (10)
sky130_fd_sc_hd__conb_1 (1) |sky130_fd_sc_hd__conb_1 (1)
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
sky130_fd_sc_hd__dfxtp_1 (7) |sky130_fd_sc_hd__dfxtp_1 (7)
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
sky130_fd_sc_hd__nand3b_1 (4) |sky130_fd_sc_hd__nand3b_1 (4)
sky130_fd_sc_hd__a31o_1 (2) |sky130_fd_sc_hd__a31o_1 (2)
sky130_fd_sc_hd__o22a_1 (2) |sky130_fd_sc_hd__o22a_1 (2)
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
sky130_fd_sc_hd__buf_2 (1) |sky130_fd_sc_hd__buf_2 (1)
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
sky130_fd_sc_hd__o31ai_1 (2) |sky130_fd_sc_hd__o31ai_1 (2)
sky130_fd_sc_hd__o211ai_4 (2) |sky130_fd_sc_hd__o211ai_4 (2)
sky130_fd_sc_hd__o21ai_2 (2) |sky130_fd_sc_hd__o21ai_2 (2)
sky130_fd_sc_hd__o21a_2 (1) |sky130_fd_sc_hd__o21a_2 (1)
sky130_fd_sc_hd__nor2_2 (2) |sky130_fd_sc_hd__nor2_2 (2)
sky130_fd_sc_hd__a21o_1 (2) |sky130_fd_sc_hd__a21o_1 (2)
sky130_fd_sc_hd__nor4_1 (2) |sky130_fd_sc_hd__nor4_1 (2)
sky130_fd_sc_hd__a2bb2o_1 (2) |sky130_fd_sc_hd__a2bb2o_1 (2)
Number of devices: 339 |Number of devices: 339
Number of nets: 329 |Number of nets: 329
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: caravel_clocking |Circuit 2: caravel_clocking
-------------------------------------------|-------------------------------------------
user_clk |user_clk
resetb_sync |resetb_sync
core_clk |core_clk
sel[0] |sel[0]
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
sel[2] |sel[2]
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
sel2[1] |sel2[1]
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
resetb |resetb
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
ext_reset |ext_reset
sel2[0] |sel2[0]
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
sel2[2] |sel2[2]
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
sel[1] |sel[1]
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
ext_clk_sel |ext_clk_sel
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
pll_clk90 |pll_clk90
ext_clk |ext_clk
pll_clk |pll_clk
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes caravel_clocking and caravel_clocking are equivalent.
Final result: Circuits match uniquely.
.