mirror of https://github.com/efabless/caravel.git
68 lines
2.2 KiB
Tcl
68 lines
2.2 KiB
Tcl
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set script_dir [file dirname [file normalize [info script]]]
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set ::env(DESIGN_NAME) chip_io
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set ::env(DESIGN_IS_PADFRAME) 1
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set ::env(STD_CELL_LIBRARY_OPT) $::env(STD_CELL_LIBRARY)
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set ::env(VERILOG_FILES) "\
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$script_dir/../../verilog/rtl/defines.v\
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$script_dir/../../verilog/rtl/pads.v\
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$script_dir/../../verilog/rtl/mprj_io.v\
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$script_dir/../../verilog/rtl/chip_io.v"
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set ::env(USE_GPIO_PADS) 1
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# The removal of this line is pending the IO verilog files being parsable by yosys...
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set ::env(VERILOG_FILES_BLACKBOX) "\
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$script_dir/../../verilog/stubs/sky130_fd_io__top_xres4v2.v\
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$script_dir/../../verilog/stubs/sky130_fd_io__top_ground_lvc_wpad.v\
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$script_dir/../../verilog/stubs/sky130_fd_io__top_power_lvc_wpad.v"
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set ::env(GPIO_PADS_VERILOG) "\
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$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
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## Synthesis
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set ::env(SYNTH_FLAT_TOP) 1
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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## Floorplan
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set ::env(FP_SIZING) absolute
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set fd [open "$script_dir/../chip_dimensions.txt" "r"]
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set ::env(DIE_AREA) [read $fd]
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close $fd
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## Diode Insertion
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set ::env(DIODE_INSERTION_STRATEGY) 0
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## Routing
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set ::env(GLB_RT_MAXLAYER) 4
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set ::env(GLB_RT_UNIDIRECTIONAL) 0
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set ::env(GLB_RT_ALLOW_CONGESTION) 1
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set ::env(GLB_RT_OVERFLOW_ITERS) 150
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## LVS
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set ::env(LVS_CONNECT_BY_LABEL) 1
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# "There are areas of ntap and ptap and/or low voltage and high voltage that magic can't parse properly from the GDS. \
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Those aren't parts of devices, so they don't affect the extraction, but they may raise overlap errors". Tim E.
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set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 0
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set ::env(MAGIC_WRITE_FULL_LEF) 1
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