mirror of https://github.com/efabless/caravel.git
113 lines
3.0 KiB
YAML
113 lines
3.0 KiB
YAML
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- status: 0 - openlane design prep
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runtime_s: 1.79
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runtime_ts: 0h0m1s786ms
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- status: 1 - synthesis - yosys
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runtime_s: 44.16
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runtime_ts: 0h0m44s164ms
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- status: 2 - sta - openroad
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runtime_s: 0.94
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runtime_ts: 0h0m0s937ms
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- status: 3 - floorplan initialization - openroad
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runtime_s: 0.62
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runtime_ts: 0h0m0s618ms
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- status: 4 - io_place - openlane
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runtime_s: 0.42
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runtime_ts: 0h0m0s418ms
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- status: 5 - tap/decap insertion - openroad
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runtime_s: 0.5
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runtime_ts: 0h0m0s499ms
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- status: 6 - pdn generation - openroad
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runtime_s: 0.75
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runtime_ts: 0h0m0s750ms
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- status: 7 - global placement - openroad
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runtime_s: 14.1
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runtime_ts: 0h0m14s102ms
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- status: 8 - resizer design optimizations - openroad
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runtime_s: 2.43
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runtime_ts: 0h0m2s426ms
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- status: 9 - detailed placement - openroad
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runtime_s: 0.68
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runtime_ts: 0h0m0s678ms
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- status: 10 - cts - openroad
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runtime_s: 27.91
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runtime_ts: 0h0m27s910ms
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- status: 11 - resizer timing optimizations - openroad
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runtime_s: 5.86
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runtime_ts: 0h0m5s857ms
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- status: 12 - resizer timing optimizations - openroad
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runtime_s: 41.94
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runtime_ts: 0h0m41s942ms
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- status: 13 - detailed placement - openroad
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runtime_s: 0.76
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runtime_ts: 0h0m0s757ms
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- status: 15 - write verilog - openroad
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runtime_s: 0.53
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runtime_ts: 0h0m0s528ms
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- status: 15 - global routing - openroad
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runtime_s: 0.63
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runtime_ts: 0h0m0s633ms
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- status: 16 - fill insertion - openroad
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runtime_s: 0.84
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runtime_ts: 0h0m0s839ms
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- status: 17 - detailed_routing - openroad
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runtime_s: 260.09
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runtime_ts: 0h4m20s88ms
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- status: 18 - wire lengths - openlane
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runtime_s: 0.68
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runtime_ts: 0h0m0s678ms
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- status: 19 - parasitics extraction - openroad
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runtime_s: 4.69
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runtime_ts: 0h0m4s689ms
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- status: 20 - sta - openroad
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runtime_s: 42.32
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runtime_ts: 0h0m42s317ms
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- status: 21 - parasitics extraction - openroad
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runtime_s: 4.56
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runtime_ts: 0h0m4s559ms
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- status: 22 - sta - openroad
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runtime_s: 43.94
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runtime_ts: 0h0m43s944ms
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- status: 23 - parasitics extraction - openroad
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runtime_s: 4.53
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runtime_ts: 0h0m4s528ms
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- status: 24 - sta - openroad
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runtime_s: 42.63
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runtime_ts: 0h0m42s625ms
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- status: 25 - sta - openroad
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runtime_s: 7.98
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runtime_ts: 0h0m7s976ms
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- status: 26 - ir drop report - openroad
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runtime_s: 1.3
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runtime_ts: 0h0m1s300ms
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- status: 27 - gdsii - magic
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runtime_s: 22.78
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runtime_ts: 0h0m22s778ms
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- status: 28 - spice extraction - magic
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runtime_s: 39.47
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runtime_ts: 0h0m39s466ms
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- status: 30 - write verilog - openroad
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runtime_s: 0.64
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runtime_ts: 0h0m0s642ms
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- status: 30 - write powered verilog - openlane
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runtime_s: 0.76
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runtime_ts: 0h0m0s758ms
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- status: 31 - lvs - netgen
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runtime_s: 1.63
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runtime_ts: 0h0m1s631ms
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- status: 32 - drc - magic
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runtime_s: 93.29
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runtime_ts: 0h1m33s290ms
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- status: 33 - antenna check - openroad
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runtime_s: 1.48
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runtime_ts: 0h0m1s480ms
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- status: 34 - erc - circuit validity checker
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runtime_s: 0.33
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runtime_ts: 0h0m0s331ms
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---
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- status: routed
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runtime_s: 413.0
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runtime_ts: 0h6m53s0ms
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- status: flow completed
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runtime_s: 728.0
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runtime_ts: 0h12m8s0ms
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