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caravel/mag/run_caravel_lvs.sh

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Corrected an error in verilog/gl/chip_io_alt.v, which was missing connections to the core side VCCD1 and VSSD1 on the clamped3 pads. Also added scripts for running LVS on chip_io to the mag/ directory, and revised the scripts so that they will only re-run extraction if there is no netlist file in the mag/ directory.
2021-12-07 09:06:35 -06:00
#!/bin/bash
Modifications done as part of LVS on the caravel top level.
2021-11-21 21:07:16 -06:00
#
Corrected a statement in the LVS scripts in the mag/ directory that is Makefile syntax, not bash syntax, and will cause the script to produce an incorrect LVS result without generating a syntax error.
2021-12-17 21:27:32 -06:00
echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
Added other blocks that were modified to put in the isolated substrate regions, although this does not completely resolve the substrate-related LVS error.
2022-04-09 13:29:19 -05:00
echo ${PDK:=sky130A} > /dev/null
Revised the LVS run scripts to use $PDK_ROOT instead of a hard- coded path.
2021-12-07 09:32:22 -06:00
Corrected an error in verilog/gl/chip_io_alt.v, which was missing connections to the core side VCCD1 and VSSD1 on the clamped3 pads. Also added scripts for running LVS on chip_io to the mag/ directory, and revised the scripts so that they will only re-run extraction if there is no netlist file in the mag/ directory.
2021-12-07 09:06:35 -06:00
if [ ! -f caravel.spice ]; then
Introduction of PDK variable (#39) * added PDK_VARIENT variable * changed variable name to PDK * resolve issue Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-08 11:05:58 -05:00
magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
Reworked part of the layouts of both caravel and caravan to move the clocking subcircuit from inside the pad area near the "clock" pin to under the DLL. This prevents the DLL from having its outputs travel all the way across the chip to reach the clocking cell and then have the multiplexed clock travel all the way back, especially as the DLL outputs are high-speed signals (up to 150 MHz).
2021-12-02 19:45:39 -06:00
drc off
crashbackups stop
load caravel
select top cell
expand
extract do local
extract all
ext2spice lvs
ext2spice
EOF
Changed the user project wrapper and user analog project wrapper to be abstract views, and modified the LVS scripts accordingly (they no longer need a special version of the netgen setup script). LVS was verified on both caravel and caravan using this setup.
2021-12-07 21:21:49 -06:00
rm -f *.ext
Corrected an error in verilog/gl/chip_io_alt.v, which was missing connections to the core side VCCD1 and VSSD1 on the clamped3 pads. Also added scripts for running LVS on chip_io to the mag/ directory, and revised the scripts so that they will only re-run extraction if there is no netlist file in the mag/ directory.
2021-12-07 09:06:35 -06:00
fi
Reworked part of the layouts of both caravel and caravan to move the clocking subcircuit from inside the pad area near the "clock" pin to under the DLL. This prevents the DLL from having its outputs travel all the way across the chip to reach the clocking cell and then have the multiplexed clock travel all the way back, especially as the DLL outputs are high-speed signals (up to 150 MHz).
2021-12-02 19:45:39 -06:00
Modifications done as part of LVS on the caravel top level.
2021-11-21 21:07:16 -06:00
export NETGEN_COLUMNS=60
Introduction of PDK variable (#39) * added PDK_VARIENT variable * changed variable name to PDK * resolve issue Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-08 11:05:58 -05:00
netgen -batch lvs "caravel.spice caravel" "../verilog/gl/caravel.v caravel" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl comp.out