riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
caravel/signoff/caravel_clocking/openlane-signoff/caravel_clocking.rpt

52 lines
2.4 KiB
Plaintext
Raw Normal View History

reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CVC: Log output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_18_05_55/reports/signoff/caravel_clocking.rpt
CVC: Error output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_18_05_55/reports/signoff/caravel_clocking.rpt.error.gz
CVC: Debug output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_18_05_55/reports/signoff/caravel_clocking.rpt.debug.gz
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
CVC: Circuit Validation Check Version 1.1.0
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CVC: Start: Tue Oct 18 12:56:39 2022
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Using the following parameters for CVC (Circuit Validation Check) from /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/cvcrc
CVC_TOP = 'caravel_clocking'
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CVC_NETLIST = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_18_05_55/tmp/signoff/caravel_clocking.cdl'
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
CVC_MODE = 'caravel_clocking'
CVC_MODEL_FILE = '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/models'
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CVC_POWER_FILE = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_18_05_55/tmp/signoff/caravel_clocking.power'
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
CVC_FUSE_FILE = ''
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CVC_REPORT_FILE = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_18_05_55/reports/signoff/caravel_clocking.rpt'
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
CVC_REPORT_TITLE = 'CVC $CVC_TOP'
CVC_CIRCUIT_ERROR_LIMIT = '100'
CVC_SEARCH_LIMIT = '100'
CVC_LEAK_LIMIT = '0.0002'
CVC_SOI = 'false'
CVC_SCRC = 'false'
CVC_VTH_GATES = 'false'
CVC_MIN_VTH_GATES = 'false'
CVC_IGNORE_VTH_FLOATING = 'false'
CVC_IGNORE_NO_LEAK_FLOATING = 'false'
CVC_LEAK_OVERVOLTAGE = 'true'
CVC_LOGIC_DIODES = 'false'
CVC_ANALOG_GATES = 'true'
CVC_BACKUP_RESULTS = 'false'
CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
CVC_SHORT_ERROR_THRESHOLD = '0'
CVC_BIAS_ERROR_THRESHOLD = '0'
CVC_FORWARD_ERROR_THRESHOLD = '0'
CVC_FLOATING_ERROR_THRESHOLD = '0'
CVC_GATE_ERROR_THRESHOLD = '0'
CVC_LEAK?_ERROR_THRESHOLD = '0'
CVC_EXPECTED_ERROR_THRESHOLD = '0'
CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
CVC_CELL_ERROR_LIMIT_FILE = ''
CVC_CELL_CHECKSUM_FILE = ''
CVC_LARGE_CIRCUIT_SIZE = '10000000'
CVC_NET_CHECK_FILE = ''
CVC_MODEL_CHECK_FILE = ''
End of parameters
CVC: Reading device model settings...
CVC: Reading power settings...
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
CVC: Parsing netlist /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_18_05_55/tmp/signoff/caravel_clocking.cdl
Cdl fixed data size 37306
Usage CDL: Time: 0 Memory: 7376 I/O: 8 Swap: 0
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
CVC: Counting and linking...