mirror of https://github.com/efabless/caravel.git
57 lines
2.2 KiB
ReStructuredText
57 lines
2.2 KiB
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<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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Interrupts (IRQ)
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================
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The interrupt vector is set to memory address ``0`` (bottom of SRAM).
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The program counter switches to this location when an interrupt is received.
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To enable interrupts, it is necessary to copy an interrupt handler to memory location ``0``.
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The `PicoRV32 <https://github.com/cliffordwolf/picorv32>`_ defines 32 IRQ channels, of which the Caravel chip uses only a handful, as described in the :ref:`cpu_irq_channel_definitions`.
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All IRQ channels not in the :ref:`cpu_irq_channel_definitions` always have value zero.
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.. list-table:: CPU IRQ channel definitions
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:name: cpu_irq_channel_definitions
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:header-rows: 1
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:widths: auto
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* - IRQ channel
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- description
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* - 4
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- :doc:`uart` data available
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* - 5
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- IRQ external pin (:ref:`IRQ E5 pin <irq>`)
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* - 6
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- :doc:`housekeeping-spi` IRQ
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* - 7
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- Assignable interrupt (see :ref:`reg_irq7_source`)
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* - 9
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- SPI controller data available, when enabled (see :ref:`reg_spi_config`)
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* - 10
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- Timer 0 expired, when enabled (see :ref:`reg_timer0_config`)
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* - 11
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- Timer 1 expired, when enabled (see :ref:`reg_timer1_config`)
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The Caravel PicoRV32 implementation does not enable IRQ QREGS (see `PicoRV32 description <https://github.com/cliffordwolf/picorv32>`__).
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The handling of interrupts is beyond the scope of this document
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(see `RISC-V instruction set description <https://riscv.org/technical/specifications/>`_).
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All interrupts are masked and must be enabled in software.
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