2021-11-04 09:19:12 -05:00
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,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
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2021-11-04 10:58:58 -05:00
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0,/project/openlane/gpio_control_block,gpio_control_block,gpio_control_block,flow_completed,0h2m34s,-1,21008.403361344535,0.0119,10504.201680672268,78.72,502.84,125,0,0,0,0,0,0,0,0,0,-1,-1,6391,1178,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,4686917.0,0.0,12.7,12.38,26.08,-1,16.48,81,109,48,76,0,0,0,66,0,0,0,0,0,0,0,4,24,44,4,34,25,0,59,38.46153846153846,26,25,AREA 0,5,50,1,15.5,15.5,0.91,0.05,sky130_fd_sc_hd,0,3
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