mirror of https://github.com/efabless/caravel.git
44 lines
1.4 KiB
Tcl
44 lines
1.4 KiB
Tcl
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set script_dir [file dirname [file normalize [info script]]]
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source $script_dir/fixed_wrapper_cfgs.tcl
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source $script_dir/default_wrapper_cfgs.tcl
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set ::env(DESIGN_NAME) user_project_wrapper
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set ::env(FP_PDN_CHECK_NODES) 0
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set ::env(FP_PDN_ENABLE_RAILS) 0
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set ::env(GLB_RT_OBS) "met1 0 0 $::env(DIE_AREA),\
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met2 0 0 $::env(DIE_AREA),\
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met3 0 0 $::env(DIE_AREA),\
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met4 0 0 $::env(DIE_AREA),\
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met5 0 0 $::env(DIE_AREA)"
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set ::env(CLOCK_PORT) "user_clock2"
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set ::env(CLOCK_NET) "mprj.clk"
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set ::env(CLOCK_PERIOD) "10"
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set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
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set ::env(DIODE_INSERTION_STRATEGY) 0
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set ::env(MAGIC_WRITE_FULL_LEF) 0
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set ::env(VERILOG_FILES) "\
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$script_dir/../../verilog/rtl/defines.v \
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$script_dir/../../verilog/rtl/__user_project_wrapper.v"
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