caravel/openlane/caravel_clocking/pin_order.cfg

#E
ext_clk_sel
sel.*
ext_reset

#W
porb

#N
resetb
ext_clk
core_clk
user_clk
resetb_sync
pll_clk
pll_clk90
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 07:50:43 -06:00			`#E`
			`ext_clk_sel`
			`sel.*`
			`ext_reset`

reharden caravel_clocking. 2023-02-27 12:26:19 -06:00			`#W`
			`porb`

[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 07:50:43 -06:00			`#N`
[DATA] Update caravel_clocking module floorplan 2021-11-18 17:26:29 -06:00			`resetb`
			`ext_clk`
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 07:50:43 -06:00			`core_clk`
			`user_clk`
[DATA] Update caravel_clocking module floorplan 2021-11-18 17:26:29 -06:00			`resetb_sync`
			`pll_clk`
			`pll_clk90`