2022-10-10 06:50:45 -05:00
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from interfaces.defsParser import Regs
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2022-09-30 03:42:36 -05:00
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reg = Regs()
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"""
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reg_mprj_xfer contain
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bit 0 : busy
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bit 1 : bitbang enable
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bit 2 : bitbang reset active low
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bit 3 : bitbang load registers
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bit 4 : bitbang clock
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bit 5 : serial data 1
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bit 6 : serial data 2
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"""
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"""shift the 2 registers with 2 ones"""
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async def clock11(cpu):
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reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x66) # 0110_0110
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x76) # 0111_0110
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"""shift the 2 registers with 2 zeros"""
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async def clock00(cpu):
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reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # 0000_0110
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x16) # 0001_0110
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"""shift the 2 registers with 1 in the left side and zero in right side"""
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async def clock01(cpu):
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reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x26) # 0010_0110
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x36) # 0011_0110
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"""shift the 2 registers with 1 in the left side and zero in right side"""
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async def clock10(cpu):
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reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x46) # 0100_0110
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x56) # 0101_0110
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"""enable the serial loader bit to load registers"""
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async def load(cpu):
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reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x0e) # enable loader
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
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"""Enable bit-bang mode and clear registers"""
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async def clear_registers(cpu):
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reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x04) # reset
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await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
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"""
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--------------------------------------------------------
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Clock in an input + output configuration. The value
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passed in "ddhold" is the number of data-dependent hold
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violations up to this point.
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--------------------------------------------------------
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* Clock in data on the left side. Assume standard hold
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* violation, so clock in 12 times and assume that the
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* next data to be clocked will start with "1", enforced
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* by the code.
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*
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* Left side = GPIOs 37 to 19
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"""
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async def clock_in_left_short(cpu,ddhold):
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await clock10(cpu)
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await clock10(cpu)
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for i in range(9):
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if ddhold != 0:
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await clock10(cpu)
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ddhold -=1
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else:
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await clock00(cpu)
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await clock00(cpu)
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async def clock_in_right_short(cpu,ddhold):
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await clock01(cpu)
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await clock01(cpu)
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for i in range(9):
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if ddhold != 0:
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await clock01(cpu)
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ddhold -=1
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else:
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await clock00(cpu)
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await clock00(cpu)
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async def clock_in_left_standard(cpu,ddhold):
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await clock10(cpu)
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await clock10(cpu)
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for i in range(7):
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if ddhold != 0:
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await clock10(cpu)
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ddhold -=1
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else:
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await clock00(cpu)
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await clock10(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock10(cpu)
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"""right output left input"""
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async def clock_in_right_o_left_i_standard(cpu,ddhold):
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await clock11(cpu)
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await clock11(cpu)
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for i in range(7):
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if ddhold != 0:
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await clock01(cpu)
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ddhold -=1
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else:
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await clock00(cpu)
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await clock10(cpu)
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await clock00(cpu)
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await clock01(cpu)
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await clock11(cpu)
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"""right input left output"""
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async def clock_in_right_i_left_o_standard(cpu,ddhold):
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await clock11(cpu)
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await clock11(cpu)
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for i in range(7):
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if ddhold != 0:
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await clock10(cpu)
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ddhold -=1
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else:
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await clock00(cpu)
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await clock01(cpu)
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await clock00(cpu)
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await clock10(cpu)
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await clock11(cpu)
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"""right input left output"""
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async def clock_in_right_i_left_i_standard(cpu,ddhold):
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await clock11(cpu)
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await clock11(cpu)
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for i in range(7):
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if ddhold != 0:
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await clock01(cpu)
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ddhold -=1
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else:
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await clock00(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock11(cpu)
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await clock11(cpu)
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"""right output left output"""
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async def clock_in_right_o_left_o_standard(cpu,ddhold):
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await clock11(cpu)
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await clock11(cpu)
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for i in range(7):
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if ddhold != 0:
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await clock01(cpu)
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ddhold -=1
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else:
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await clock00(cpu)
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await clock11(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock11(cpu)
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async def clock_in_end_output(cpu):
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# Right side: GPIO 0 configured disabled
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# /Left side: GPIO 37 configured as output
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await clock11(cpu)
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await clock11(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock00(cpu)
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await clock01(cpu)
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await clock11(cpu)
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await load(cpu)
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reg_mprj_io_37_addr = reg.get_addr('reg_mprj_io_37')
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await cpu.drive_data2address(reg_mprj_io_37_addr,0x1809)
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async def clock11_spi(caravelEnv):
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await caravelEnv.enable_csb()
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await caravelEnv.hk_write_byte(0x80) # Write stream command
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await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
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await caravelEnv.hk_write_byte(0x66) # Data = 0x01 (enable bit-bang mode)
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await caravelEnv.disable_csb()
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await caravelEnv.enable_csb()
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await caravelEnv.hk_write_byte(0x80) # Write stream command
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await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
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await caravelEnv.hk_write_byte(0x76) # 11
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await caravelEnv.disable_csb()
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async def clock00_spi(caravelEnv):
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await caravelEnv.enable_csb()
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await caravelEnv.hk_write_byte(0x80) # Write stream command
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await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
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await caravelEnv.hk_write_byte(0x06) # Data = 0x01 (enable bit-bang mode)
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await caravelEnv.disable_csb()
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await caravelEnv.enable_csb()
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await caravelEnv.hk_write_byte(0x80) # Write stream command
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await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
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await caravelEnv.hk_write_byte(0x16) # 00
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await caravelEnv.disable_csb()
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async def clock01_spi(caravelEnv):
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await caravelEnv.enable_csb()
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await caravelEnv.hk_write_byte(0x80) # Write stream command
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await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
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await caravelEnv.hk_write_byte(0x26) # Data = 0x01 (enable bit-bang mode)
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await caravelEnv.disable_csb()
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await caravelEnv.enable_csb()
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await caravelEnv.hk_write_byte(0x80) # Write stream command
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await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
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await caravelEnv.hk_write_byte(0x36) # 01
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await caravelEnv.disable_csb()
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async def clock10_spi(caravelEnv):
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await caravelEnv.enable_csb()
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await caravelEnv.hk_write_byte(0x80) # Write stream command
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await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
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await caravelEnv.hk_write_byte(0x46) # Data = 0x01 (enable bit-bang mode)
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await caravelEnv.disable_csb()
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await caravelEnv.enable_csb()
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await caravelEnv.hk_write_byte(0x80) # Write stream command
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await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
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await caravelEnv.hk_write_byte(0x56) # 10
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await caravelEnv.disable_csb()
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async def load_spi(caravelEnv):
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await caravelEnv.enable_csb()
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await caravelEnv.hk_write_byte(0x80) # Write stream command
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await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
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await caravelEnv.hk_write_byte(0x0e) # load enable
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await caravelEnv.disable_csb()
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await caravelEnv.enable_csb()
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await caravelEnv.hk_write_byte(0x80) # Write stream command
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await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
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await caravelEnv.hk_write_byte(0x16) # 00
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await caravelEnv.disable_csb()
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"""right output left input"""
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async def clock_in_right_o_left_i_standard_spi(caravelEnv,ddhold):
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await clock11_spi(caravelEnv)
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await clock11_spi(caravelEnv)
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for i in range(7):
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if ddhold != 0:
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await clock01_spi(caravelEnv)
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ddhold -=1
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else:
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await clock00_spi(caravelEnv)
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await clock10_spi(caravelEnv)
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await clock00_spi(caravelEnv)
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await clock01_spi(caravelEnv)
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await clock11_spi(caravelEnv)
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"""right input left output"""
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async def clock_in_right_i_left_o_standard_spi(caravelEnv,ddhold):
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await clock11_spi(caravelEnv)
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await clock11_spi(caravelEnv)
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for i in range(7):
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if ddhold != 0:
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await clock10_spi(caravelEnv)
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ddhold -=1
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else:
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await clock00_spi(caravelEnv)
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await clock01_spi(caravelEnv)
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await clock00_spi(caravelEnv)
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await clock10_spi(caravelEnv)
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await clock11_spi(caravelEnv)
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"""right input left output"""
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async def clock_in_right_i_left_i_standard_spi(caravelEnv,ddhold):
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await clock11_spi(caravelEnv)
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await clock11_spi(caravelEnv)
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for i in range(7):
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|
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if ddhold != 0:
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|
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await clock01_spi(caravelEnv)
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|
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ddhold -=1
|
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|
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else:
|
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|
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await clock00_spi(caravelEnv)
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|
|
|
|
|
|
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|
await clock00_spi(caravelEnv)
|
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|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock11_spi(caravelEnv)
|
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|
|
|
await clock11_spi(caravelEnv)
|
|
|
|
|
|
|
|
|
|
"""right output left output"""
|
|
|
|
|
async def clock_in_right_o_left_o_standard_spi(caravelEnv,ddhold):
|
|
|
|
|
await clock11_spi(caravelEnv)
|
|
|
|
|
await clock11_spi(caravelEnv)
|
|
|
|
|
|
|
|
|
|
for i in range(7):
|
|
|
|
|
if ddhold != 0:
|
|
|
|
|
await clock01_spi(caravelEnv)
|
|
|
|
|
ddhold -=1
|
|
|
|
|
else:
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
|
|
|
|
|
await clock11_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock11_spi(caravelEnv)
|
|
|
|
|
|
|
|
|
|
async def clock_in_end_output_spi(caravelEnv):
|
|
|
|
|
# Right side: GPIO 0 configured disabled
|
|
|
|
|
# /Left side: GPIO 37 configured as output
|
|
|
|
|
await clock11_spi(caravelEnv)
|
|
|
|
|
await clock11_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock00_spi(caravelEnv)
|
|
|
|
|
await clock01_spi(caravelEnv)
|
|
|
|
|
await clock11_spi(caravelEnv)
|
|
|
|
|
await load_spi(caravelEnv)
|
