mirror of https://github.com/efabless/caravel.git
44 lines
1.5 KiB
ReStructuredText
44 lines
1.5 KiB
ReStructuredText
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.. raw:: html
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<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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SRAM
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====
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.. _management-area-sram:
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Management area SRAM
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--------------------
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The Caravel chip has an on-board memory of 256 words of width 32 bits.
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The memory is located at address ``0``.
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There are additional blocks of memory above this area, size and location TDB.
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.. _storage-area-sram:
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Storage area SRAM
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-----------------
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The Caravel chip has a *storage area* SRAM block that is auxiliary space
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that can be used by either the management SoC or the user project, through the Wishbone bus interface.
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The storage area is connected into the user area 2 power supply,
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and so is nominally considered to be part of the user area.
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The storage area may be used as an experimentation area for OpenRAM, so for any user project making use of this space, the user should notify efabless of their requirement for the size and configuration of the SRAM block.
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