riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
caravel/signoff/caravel_clocking/openlane-signoff/26-rcx_sta.power.rpt

15 lines
850 B
Plaintext
Raw Normal View History

reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
===========================================================================
report_power
============================================================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Sequential 3.76e-04 3.65e-05 4.68e-10 4.12e-04 27.0%
Combinational 6.30e-04 4.83e-04 2.19e-09 1.11e-03 73.0%
reharden: caravel_clocking + add custom interactive script to insert a buffer on user_clk output and have a large buffer on core_clk ~ change pdn config to match top level ~ change sdc ~ change openlane configuration
2022-10-13 12:54:04 -05:00
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
reharden: caravel_clocking ~ increase height for more spread decap insertion + add or cells to cell exclude ~ adjust pdn to have an offset half to pitch ~ change placement density in accordance to area ~ change padding to allow for space for decap insertion
2022-10-18 08:18:30 -05:00
Total 1.01e-03 5.20e-04 2.66e-09 1.53e-03 100.0%
65.9% 34.1% 0.0%