mirror of https://github.com/efabless/caravel.git
104 lines
2.6 KiB
Coq
104 lines
2.6 KiB
Coq
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*----------------------------------------------------------------------*/
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/* mgmt_protect_hv: */
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/* */
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/* High voltage (3.3V) part of the mgmt_protect module. Split out into */
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/* a separate module and file so that the synthesis tools can handle it */
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/* separately from the rest, since it uses a different standard cell */
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/* library. See the file mgmt_protect.v for a full description of the */
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/* whole management protection method. */
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/*----------------------------------------------------------------------*/
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module mgmt_protect_hv (
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`ifdef USE_POWER_PINS
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inout vccd,
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inout vssd,
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inout vdda1,
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inout vssa1,
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inout vdda2,
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inout vssa2,
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`endif
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output mprj_vdd_logic1,
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output mprj2_vdd_logic1
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);
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wire mprj_vdd_logic1_h;
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wire mprj2_vdd_logic1_h;
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`ifdef USE_POWER_PINS
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// This is to emulate the substrate shorting grounds together for LVS
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// purposes
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assign vssa2 = vssa1;
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assign vssa1 = vssd;
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`endif
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// Logic high in the VDDA (3.3V) domains
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sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
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`ifdef USE_POWER_PINS
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.VPWR(vdda1),
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.VGND(vssa1),
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.VPB(vdda1),
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.VNB(vssa1),
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`endif
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.HI(mprj_vdd_logic1_h),
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.LO()
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);
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sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl (
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`ifdef USE_POWER_PINS
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.VPWR(vdda2),
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.VGND(vssa2),
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.VPB(vdda2),
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.VNB(vssa2),
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`endif
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.HI(mprj2_vdd_logic1_h),
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.LO()
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);
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// Level shift the logic high signals into the 1.8V domain
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sky130_fd_sc_hvl__lsbufhv2lv_1 mprj_logic_high_lv (
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`ifdef USE_POWER_PINS
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.VPWR(vdda1),
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.VGND(vssd),
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.LVPWR(vccd),
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.VPB(vdda1),
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.VNB(vssd),
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`endif
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.X(mprj_vdd_logic1),
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.A(mprj_vdd_logic1_h)
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);
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sky130_fd_sc_hvl__lsbufhv2lv_1 mprj2_logic_high_lv (
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`ifdef USE_POWER_PINS
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.VPWR(vdda2),
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.VGND(vssd),
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.LVPWR(vccd),
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.VPB(vdda2),
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.VNB(vssd),
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`endif
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.X(mprj2_vdd_logic1),
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.A(mprj2_vdd_logic1_h)
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);
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endmodule
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`default_nettype wire
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