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# Alliance VLSI CAD System
# Copyright (C) 1990, 2002 ASIM/LIP6/UPMC
#
# Home page : http://asim.lip6.fr/alliance/
# E-mail support : mailto:alliance-support@asim.lip6.fr
# ftp site : ftp://asim.lip6.fr/pub/alliance/
#
# NOTE: You can find the latest revision of this file at:
# http://asim.lip6.fr/pub/alliance/unstable/cvstree/alliance/
#
# $Id: FAQ,v 1.7 2002/02/13 16:36:23 czo Exp $
##########################################################
# WARNING: This file needs to rewritten for Alliance 5.0
##########################################################
--------------------------------------------------------------------------------
FAQ (Frequently Asked Questions)
This file contains the basic pointers to
the different documents or manuals found in this release.
--------------------------------------------------------------------------------
Question 1: What is ALLIANCE ?
Question 2: What is ALLIANCE general copyright policy ?
Question 3: How to install ALLIANCE ?
Question 4: How to get started ?
Question 5: What are the differences with the previous releases ?
Question 6: What is the supported VHDL subset ?
Question 7: What is the available online documentation ?
Question 8: How can I get more complete documentation ?
Question 9: Where are defined the symbolic layout rules ?
Question 10: How is performed the mapping to a target process ?
Question 11: What are the supported file formats ?/
Question 12: Where are TAS and YAGLE ?
Question 13: How can I get in touch with the ALLIANCE team ?
Question 14: How can I get Alliance ?
Question 1: What is ALLIANCE ?
------------------------------
Alliance is a free VLSI CAD System.
You can read a general description of the ALLIANCE tools and libraries
in share/doc/overview.pdf or by printing the PostScript file overview.ps
located in the doc directory:
> lpr share/doc/overview.ps
Question 2: What is ALLIANCE general copyright policy ?
-------------------------------------------------------
"Alliance VLSI CAD System" is free Software.
Alliance is available under the terms of the GNU General Public License
GPL (http://www.gnu.org/copyleft/gpl.html). Please read the files
COPYING-2.0 and COPYING.LIB-2.0
You are welcome to use the software package even for commercial
designs without any fee. You are just required to mention :
" Designed with Alliance CAD system,
Copyright (C) 1991, 2000 Universit<69> Pierre et Marie Curie"
> more LICENCE
Question 3: How to install ALLIANCE ?
-------------------------------------
You can compile the sources or use precompiled binary package.
Binary packages are available for :
- i386 Linux
- sparc SunOS 4.1.1
- sparc Solaris 5.7
- i386 FreeBSD 3.3
- i386 Windows NT/95
To install Alliance follow the steps written in README
> more README
Question 4: How to get started ?
--------------------------------
You will find 5 separate tutorials in share/tutorials/ directory :
(Please read overview.ps before)
WARNING : These tutorials are not fully working and must be modified to
work with Alliance 4.0 (especially the dlx), but we have
decided to release them even though they are not fully
functional. They will be upgraded as soon as we have time.
1/ ADDACCU
The design of a very simple chip (adder/accumulator) to get started
with the ALLIANCE tools.
>cd tutorials/addaccu
2/ AMD2901
The design of the 4 bits AMD2901 processor, from the VHDL specification to
the CIF layout, using the ALLIANCE portable standard cells library.
>cd tutorials/amd2901
4/ Synthesis
Building simple door code using the Finite State Machine synthesizer (syf).
>cd tutorials/synth
4/ Data Path
Building simple data paths using on a procedural data path generator
(fpgen) and a data path place and route tool (dpr).
>cd tutorials/fitpath
5/ DlxM
A complete tutorial based on the design of the 32 bit microprocessor DLX.
Question 5: What are the differences with the previous releases ?
----------------------------------------------------------------
The new features of this release are described in the CHANGES file:
> more CHANGES
Question 6: What is the supported VHDL subset ?
-----------------------------------------------
You can find a general presentation of the VHDL subset by issuing the
following commands:
> man vhdl
This gives you an hint about the supported VHDL subset.
There is actually three separate architectures types: "Structural",
"Data-flow", and "Finite-State-Machine"
> man vst
This gives you the VHDL subset supported for structural descriptions.
> man vbe
This gives you the data-flow behavioral subset supported by the simulator
ASIMUT, the logic synthesis tools BOP and SCMAP and the formal proffer PROOF.
> man fsm
This gives you the VHDL subset used for Finite-State-Machine description
and supported by the FSM synthesis tool SYF.
Question 7: What is the available online documentation ?
--------------------------------------------------------
Each tools has its own manual.
All the tools rely on the use of environment variables: all the relevant
variables are listed in the `ENVIRONMENT VARIABLES' section of the manual
page.
1) tools
--------
> man asimut # VHDL simulator
> man bbr # channel router
> man dpr # data-path place & route
> man dreal # real layout viewer
> man druc # design rule checker
> man fpgen # procedural data-path generation language
> man fpmap # logic synthesis tool for FPGA
> man genlib # procedural net-list generation language
> man genpat # procedural pattern generation language
> man genview # interactive block generator debugger
> man graal # graphic layout editor
> man l2p # layout to PostScript translation tool
> man bop # Boolean optimizer
> man lvx # net-list comparator
> man lynx # layout extractor
> man glop # net-list optimizer
> man proof # VHDL description's formal proffer
> man ring # router between core & pads
> man s2r # symbolic layout to real mask expander
> man scmap # standard cell mapping
> man scr # standard cells place & route
> man syf # finite state machine synthesis tool
> man tas # static timing analyzer
> man yagle # functional abstractor
2) cell libraries
-----------------
> man sxlib # new standard cells library (multi layer/overcell routing)
> man sclib # old standard cells library
> man dplib # data path cells library
> man fplib # data path cells library
> man padlib # pad library
> man rsa # fast adder generator
> man bsg # barrel shifter generator
> man amg # multiplier generator
> man rfg # register file generator
> man grog # high speed ROM generator
> man rage # static RAM generator
3) ALLIANCE file formats
------------------------
> man vhdl # VHDL overview
> man vst # VHDL subset for net-list
> man vbe # VHDL subset for data-flow
> man fsm # VHDL subset for finite-state-machine
> man al # internal ALLIANCE netlist
> man ap # internal ALLIANCE symbolic layout
> man pat # internal ALLIANCE pattern description
4) miscellaneous
----------------
> man catal # use of the catalog file
> man prol # technology file
> man mbkenv # main environment variables
Question 8: How can I get more complete documentation ?
-----------------------------------------------------------
All the available documentation for Alliance can be found
at Alliance's web site :
http://www-asim.lip6.fr/alliance/doc/
You can download a copy of this site at
ftp://ftp-asim.lip6.fr/pub/alliance/distribution/doc/
Question 9: Where are defined the symbolic layout rules ?
----------------------------------------------------------
The symbolic layout rules are specified in the Design Rule Checker
documentation:
> man druc
Question 10: How is performed the mapping to a target process ?
---------------------------------------------------------------
The actual conversion is performed by the s2r tool:
> man s2r
If you want to parameterize the S2R tool to a new target technology,
you must write a technology file. The method is described in the
postscript file doc/process_mapping.ps (also available in pdf)
> lpr doc/process_mapping.ps
Question 11: What are the supported file formats ?
--------------------------------------------------
ALLIANCE tools are interfaced to generic data-structures that
support various standard file formats, thanks to a set of
specialized parsers/drivers.
UNIX environment variables are used to select one particular file format.
For a given entity, the file format is defined by the file extension.
1/ symbolic layout view
ALLIANCE .ap INPUT OUTPUT
COMPASS .cp INPUT OUTPUT
2/ physical layout view
CIF .cif OUTPUT
GDSII .gds OUTPUT
3/ netlist view
ALLIANCE .al INPUT OUTPUT
SPICE .spi INPUT OUTPUT
EDIF 2.0 .edi INPUT OUTPUT
VHDL .vst INPUT OUTPUT
COMPASS .hns INPUT OUTPUT
HILO .cct OUTPUT
VERILOG .vlg OUTPUT
4/ behavioral view
VHDL (data-flow) .vbe INPUT OUTPUT
VHDL (FSM) .fsm INPUT
Question 12: Where are TAS and YAGLE ?
--------------------------------------
HITAS (Hierarchical timing analysis) and YAGLE (Functional abstraction)
are now comercially distributed by Avertec (http://www.avertec.com/).
More information can be obtained at their web site. Binaries of these
tools can also be downloaded for non-commercial university research.
Question 13: How can I get in touch with the ALLIANCE team ?
------------------------------------------------------------
Web:
----
at http://www-asim.lip6.fr/alliance/support/
E-mail:
-------
mailto:alliance-support@asim.lip6.fr
Postal Mail:
-----------
Alliance Support
Couloir 55-65, 2<>me <20>tage
ASIM / LIP6
Universit<EFBFBD> Pierre et Marie Curie
4, Place Jussieu 75252 Paris Cedex 05,
France
Fax:
----
+33 1 44 27 72 80
Question 14: How can I get Alliance ?
-------------------------------------
You can get Alliance via anonymous FTP from
ftp://ftp-asim.lip6.fr/pub/alliance/
or by HTTP
http://www-asim.lip6.fr/pub/alliance/
If you can not access to Internet you can also send us a blank CD-ROM
or ZIP100. We will copy it for you.
Alliance Support
Couloir 55-65, 2<>me <20>tage
ASIM / LIP6
Universit<EFBFBD> Pierre et Marie Curie
4, Place Jussieu 75252 Paris Cedex 05,
France
# EOF
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