1999-05-31 12:12:02 -05:00
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# Alliance VLSI CAD System
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2002-02-13 10:36:24 -06:00
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# Copyright (C) 1990, 2002 ASIM/LIP6/UPMC
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1999-05-31 12:12:02 -05:00
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#
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2002-02-13 10:36:24 -06:00
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# Home page : http://asim.lip6.fr/alliance/
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1999-05-31 12:12:02 -05:00
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# E-mail support : mailto:alliance-support@asim.lip6.fr
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2002-02-13 10:36:24 -06:00
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# ftp site : ftp://asim.lip6.fr/pub/alliance/
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1999-05-31 12:12:02 -05:00
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#
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2002-02-13 10:36:24 -06:00
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# NOTE: You can find the latest revision of this file at:
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# http://asim.lip6.fr/pub/alliance/unstable/cvstree/alliance/
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#
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# $Id: FAQ,v 1.7 2002/02/13 16:36:23 czo Exp $
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##########################################################
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# WARNING: This file needs to rewritten for Alliance 5.0
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##########################################################
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1999-05-31 12:12:02 -05:00
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--------------------------------------------------------------------------------
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FAQ (Frequently Asked Questions)
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This file contains the basic pointers to
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the different documents or manuals found in this release.
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2000-01-20 12:17:02 -06:00
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--------------------------------------------------------------------------------
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1999-05-31 12:12:02 -05:00
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Question 1: What is ALLIANCE ?
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Question 2: What is ALLIANCE general copyright policy ?
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Question 3: How to install ALLIANCE ?
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Question 4: How to get started ?
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Question 5: What are the differences with the previous releases ?
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Question 6: What is the supported VHDL subset ?
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Question 7: What is the available online documentation ?
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2000-02-01 08:05:39 -06:00
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Question 8: How can I get more complete documentation ?
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Question 9: Where are defined the symbolic layout rules ?
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Question 10: How is performed the mapping to a target process ?
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Question 11: What are the supported file formats ?/
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2000-01-25 09:36:03 -06:00
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Question 12: Where are TAS and YAGLE ?
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Question 13: How can I get in touch with the ALLIANCE team ?
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Question 14: How can I get Alliance ?
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1999-05-31 12:12:02 -05:00
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Question 1: What is ALLIANCE ?
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------------------------------
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2000-01-20 12:17:02 -06:00
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Alliance is a free VLSI CAD System.
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1999-05-31 12:12:02 -05:00
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You can read a general description of the ALLIANCE tools and libraries
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2000-01-24 11:46:51 -06:00
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in share/doc/overview.pdf or by printing the PostScript file overview.ps
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located in the doc directory:
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1999-05-31 12:12:02 -05:00
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2000-01-20 12:17:02 -06:00
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> lpr share/doc/overview.ps
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1999-05-31 12:12:02 -05:00
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Question 2: What is ALLIANCE general copyright policy ?
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-------------------------------------------------------
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"Alliance VLSI CAD System" is free Software.
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2000-01-24 11:46:51 -06:00
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Alliance is available under the terms of the GNU General Public License
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GPL (http://www.gnu.org/copyleft/gpl.html). Please read the files
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COPYING-2.0 and COPYING.LIB-2.0
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1999-05-31 12:12:02 -05:00
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You are welcome to use the software package even for commercial
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2000-01-24 11:46:51 -06:00
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designs without any fee. You are just required to mention :
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" Designed with Alliance CAD system,
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Copyright (C) 1991, 2000 Universit<69> Pierre et Marie Curie"
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1999-05-31 12:12:02 -05:00
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> more LICENCE
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Question 3: How to install ALLIANCE ?
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-------------------------------------
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2000-01-24 11:46:51 -06:00
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You can compile the sources or use precompiled binary package.
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2000-01-25 09:36:03 -06:00
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Binary packages are available for :
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- i386 Linux
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1999-05-31 12:12:02 -05:00
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- sparc SunOS 4.1.1
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2000-01-24 11:46:51 -06:00
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- sparc Solaris 5.7
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- i386 FreeBSD 3.3
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- i386 Windows NT/95
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1999-05-31 12:12:02 -05:00
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To install Alliance follow the steps written in README
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> more README
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Question 4: How to get started ?
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--------------------------------
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2000-02-01 08:05:39 -06:00
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You will find 5 separate tutorials in share/tutorials/ directory :
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2000-01-24 11:46:51 -06:00
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(Please read overview.ps before)
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WARNING : These tutorials are not fully working and must be modified to
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work with Alliance 4.0 (especially the dlx), but we have
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decided to release them even though they are not fully
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2000-01-25 09:36:03 -06:00
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functional. They will be upgraded as soon as we have time.
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1999-05-31 12:12:02 -05:00
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1/ ADDACCU
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The design of a very simple chip (adder/accumulator) to get started
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with the ALLIANCE tools.
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>cd tutorials/addaccu
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2/ AMD2901
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The design of the 4 bits AMD2901 processor, from the VHDL specification to
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the CIF layout, using the ALLIANCE portable standard cells library.
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>cd tutorials/amd2901
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2000-02-01 08:05:39 -06:00
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4/ Synthesis
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Building simple door code using the Finite State Machine synthesizer (syf).
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>cd tutorials/synth
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4/ Data Path
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Building simple data paths using on a procedural data path generator
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(fpgen) and a data path place and route tool (dpr).
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>cd tutorials/fitpath
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2000-02-01 08:05:39 -06:00
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5/ DlxM
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A complete tutorial based on the design of the 32 bit microprocessor DLX.
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2000-02-01 08:05:39 -06:00
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2000-01-24 11:46:51 -06:00
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1999-05-31 12:12:02 -05:00
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Question 5: What are the differences with the previous releases ?
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----------------------------------------------------------------
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The new features of this release are described in the CHANGES file:
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> more CHANGES
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Question 6: What is the supported VHDL subset ?
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-----------------------------------------------
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You can find a general presentation of the VHDL subset by issuing the
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following commands:
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> man vhdl
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This gives you an hint about the supported VHDL subset.
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There is actually three separate architectures types: "Structural",
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"Data-flow", and "Finite-State-Machine"
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> man vst
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This gives you the VHDL subset supported for structural descriptions.
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> man vbe
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This gives you the data-flow behavioral subset supported by the simulator
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2000-01-25 09:36:03 -06:00
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ASIMUT, the logic synthesis tools BOP and SCMAP and the formal proffer PROOF.
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1999-05-31 12:12:02 -05:00
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> man fsm
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This gives you the VHDL subset used for Finite-State-Machine description
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and supported by the FSM synthesis tool SYF.
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Question 7: What is the available online documentation ?
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--------------------------------------------------------
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Each tools has its own manual.
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All the tools rely on the use of environment variables: all the relevant
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variables are listed in the `ENVIRONMENT VARIABLES' section of the manual
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page.
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1) tools
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--------
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> man asimut # VHDL simulator
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> man bbr # channel router
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> man dpr # data-path place & route
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> man dreal # real layout viewer
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> man druc # design rule checker
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> man fpgen # procedural data-path generation language
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> man fpmap # logic synthesis tool for FPGA
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> man genlib # procedural net-list generation language
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> man genpat # procedural pattern generation language
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> man genview # interactive block generator debugger
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1999-05-31 12:12:02 -05:00
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> man graal # graphic layout editor
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2000-01-25 09:36:03 -06:00
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> man l2p # layout to PostScript translation tool
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> man bop # Boolean optimizer
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1999-05-31 12:12:02 -05:00
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> man lvx # net-list comparator
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> man lynx # layout extractor
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2000-01-25 09:36:03 -06:00
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> man glop # net-list optimizer
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> man proof # VHDL description's formal proffer
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1999-05-31 12:12:02 -05:00
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> man ring # router between core & pads
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> man s2r # symbolic layout to real mask expander
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> man scmap # standard cell mapping
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> man scr # standard cells place & route
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> man syf # finite state machine synthesis tool
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2000-01-25 09:36:03 -06:00
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> man tas # static timing analyzer
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1999-05-31 12:12:02 -05:00
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> man yagle # functional abstractor
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2) cell libraries
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-----------------
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2000-01-24 11:46:51 -06:00
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> man sxlib # new standard cells library (multi layer/overcell routing)
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> man sclib # old standard cells library
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> man dplib # data path cells library
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> man fplib # data path cells library
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> man padlib # pad library
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> man rsa # fast adder generator
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> man bsg # barrel shifter generator
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> man amg # multiplier generator
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> man rfg # register file generator
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> man grog # high speed ROM generator
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> man rage # static RAM generator
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3) ALLIANCE file formats
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------------------------
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> man vhdl # VHDL overview
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> man vst # VHDL subset for net-list
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> man vbe # VHDL subset for data-flow
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> man fsm # VHDL subset for finite-state-machine
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> man al # internal ALLIANCE netlist
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> man ap # internal ALLIANCE symbolic layout
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> man pat # internal ALLIANCE pattern description
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4) miscellaneous
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----------------
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> man catal # use of the catalog file
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> man prol # technology file
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> man mbkenv # main environment variables
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1999-05-31 12:12:02 -05:00
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2000-02-01 08:05:39 -06:00
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Question 8: How can I get more complete documentation ?
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-----------------------------------------------------------
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All the available documentation for Alliance can be found
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at Alliance's web site :
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http://www-asim.lip6.fr/alliance/doc/
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You can download a copy of this site at
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ftp://ftp-asim.lip6.fr/pub/alliance/distribution/doc/
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1999-05-31 12:12:02 -05:00
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2000-02-01 08:05:39 -06:00
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Question 9: Where are defined the symbolic layout rules ?
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1999-05-31 12:12:02 -05:00
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----------------------------------------------------------
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The symbolic layout rules are specified in the Design Rule Checker
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documentation:
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> man druc
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2000-02-01 08:05:39 -06:00
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Question 10: How is performed the mapping to a target process ?
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1999-05-31 12:12:02 -05:00
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---------------------------------------------------------------
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The actual conversion is performed by the s2r tool:
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> man s2r
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If you want to parameterize the S2R tool to a new target technology,
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you must write a technology file. The method is described in the
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2000-01-24 11:46:51 -06:00
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postscript file doc/process_mapping.ps (also available in pdf)
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1999-05-31 12:12:02 -05:00
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2000-01-24 11:46:51 -06:00
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> lpr doc/process_mapping.ps
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1999-05-31 12:12:02 -05:00
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Question 11: What are the supported file formats ?
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--------------------------------------------------
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ALLIANCE tools are interfaced to generic data-structures that
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support various standard file formats, thanks to a set of
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specialized parsers/drivers.
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UNIX environment variables are used to select one particular file format.
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For a given entity, the file format is defined by the file extension.
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1/ symbolic layout view
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ALLIANCE .ap INPUT OUTPUT
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COMPASS .cp INPUT OUTPUT
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2/ physical layout view
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CIF .cif OUTPUT
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GDSII .gds OUTPUT
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3/ netlist view
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ALLIANCE .al INPUT OUTPUT
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SPICE .spi INPUT OUTPUT
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EDIF 2.0 .edi INPUT OUTPUT
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VHDL .vst INPUT OUTPUT
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COMPASS .hns INPUT OUTPUT
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HILO .cct OUTPUT
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VERILOG .vlg OUTPUT
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2000-01-25 09:36:03 -06:00
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4/ behavioral view
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1999-05-31 12:12:02 -05:00
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VHDL (data-flow) .vbe INPUT OUTPUT
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VHDL (FSM) .fsm INPUT
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2000-01-25 09:36:03 -06:00
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Question 12: Where are TAS and YAGLE ?
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--------------------------------------
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HITAS (Hierarchical timing analysis) and YAGLE (Functional abstraction)
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2000-01-25 10:28:57 -06:00
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are now comercially distributed by Avertec (http://www.avertec.com/).
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More information can be obtained at their web site. Binaries of these
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tools can also be downloaded for non-commercial university research.
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2000-01-25 09:36:03 -06:00
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Question 13: How can I get in touch with the ALLIANCE team ?
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1999-05-31 12:12:02 -05:00
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------------------------------------------------------------
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2000-01-24 11:46:51 -06:00
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Web:
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----
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at http://www-asim.lip6.fr/alliance/support/
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E-mail:
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-------
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mailto:alliance-support@asim.lip6.fr
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Postal Mail:
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-----------
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Alliance Support
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Couloir 55-65, 2<>me <20>tage
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ASIM / LIP6
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Universit<EFBFBD> Pierre et Marie Curie
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4, Place Jussieu 75252 Paris Cedex 05,
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France
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Fax:
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----
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+33 1 44 27 72 80
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2000-01-25 09:36:03 -06:00
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Question 14: How can I get Alliance ?
|
2000-01-24 11:46:51 -06:00
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-------------------------------------
|
1999-05-31 12:12:02 -05:00
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2000-01-24 11:46:51 -06:00
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You can get Alliance via anonymous FTP from
|
1999-05-31 12:12:02 -05:00
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|
2000-01-24 11:46:51 -06:00
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ftp://ftp-asim.lip6.fr/pub/alliance/
|
1999-05-31 12:12:02 -05:00
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2000-01-24 11:46:51 -06:00
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or by HTTP
|
1999-05-31 12:12:02 -05:00
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|
2000-01-24 11:46:51 -06:00
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http://www-asim.lip6.fr/pub/alliance/
|
1999-05-31 12:12:02 -05:00
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|
2000-01-24 11:46:51 -06:00
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If you can not access to Internet you can also send us a blank CD-ROM
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or ZIP100. We will copy it for you.
|
1999-05-31 12:12:02 -05:00
|
|
|
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|
2000-01-24 11:46:51 -06:00
|
|
|
|
Alliance Support
|
|
|
|
|
|
Couloir 55-65, 2<>me <20>tage
|
|
|
|
|
|
ASIM / LIP6
|
|
|
|
|
|
Universit<EFBFBD> Pierre et Marie Curie
|
|
|
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|
|
4, Place Jussieu 75252 Paris Cedex 05,
|
|
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|
France
|
1999-05-31 12:12:02 -05:00
|
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# EOF
|
2000-01-25 09:36:03 -06:00
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