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cellules

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# $Id: Makefile.am,v 1.2 2002/04/30 14:57:05 czo Exp $
SUBDIRS = src doc

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dnl $Id: configure.in,v 1.1 2002/04/29 15:51:49 czo Exp $
AC_INIT(doc/sxlib.5)
AM_INIT_AUTOMAKE(cells, 1.1)
AC_PROG_INSTALL
AM_ALLIANCE
AC_OUTPUT([
Makefile
doc/Makefile
src/Makefile
])

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# $Id: Makefile.am,v 1.1 2002/04/29 15:51:57 czo Exp $
man_MANS = sxlib.5
EXTRA_DIST = $(man_MANS)

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.\" $Id: sxlib.5,v 1.1 2002/04/29 15:51:57 czo Exp $
.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: Franck Wajsburt
.TH SXLIB 5 "October 19, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
.SH NAME
.B sxlib - a portable CMOS Standard Cell Library
.so man1/alc_origin.1
.SH DESCRIPTION
\fBsxlib\fP library contains standard cells that have been developed at
UPMC-ASIM/LIP6. This manual gives the list of available cells, with their
behavior, width, maximum delay and input fan-in. This manual gives also
few thumb rules to help the user to well use the cells. The given delay
are the maximum (that means worst case for a generic .35 micron process).
More precise delay can be found in ALLIANCE VHDL behavior files (.vbe file).
Cell-name is built that way <behavior>_<output drive>
(see explanations below).
.nf
Four files are attached to each cell:-
- ALLIANCE Layout ............... cell-name.ap
- ALLIANCE Transistor net-list .. cell-name.al
- ALLIANCE VHDL behavior ........ cell-name.vbe
- Compiled HILO behavior ........ 0000000xx.dat
And few files more:-
- CATAL ......................... ALLIANCE catalog file
- sxlib.cct ..................... Cell definition for HILO CAD tools
- CIRCUIT.idx ................... HILO catalog file
- sxlib.lib ..................... Cell definition for Synopsys CAD tools
- sxlib.db ...................... Compiled cell definition for Synopsys
- sxlib.sdb ..................... Icon definition for Synopys
.fi
.SH PHYSICAL OUTLINE
\fBsxlib\fP uses the symbolic layout promoted by Alliance in order to
provide process independence. All dimensions are in lambda units. The
mapping to a specific process CIF or GDS2 layout must be performed by the
\fBs2r\fP tool (symbolic to real), which uses a value for the lambda
(e.g. 1 lambda=0.3um).
.nf
_________________
50 | VDD |
45 |_________________| x : place of virtual connector.
40 | x |
35 | x x | they are named : name_<y>
30 | x x |
25 | x x | for example : i0_20
20 | x | i0_25
15 | x | i0_30
10 |_________________|
5 | VSS |
0 |_________________|
0 5 10 15 20 25 30
.fi
All cells are 50 lambdas high and \fBN\fP times 5 lambdas wide, where
\fBN\fP is the number of pitches. That is the only physical information
given in the cell list below. Power supplies are in horizontal ALU1 and
are 6 lambdas wide. Connectors are inside the cells, placed on a 5x5 grid.
Half layout design rules are a warranty for any layer on any face, except
for the power supply and NWELL. Cells can be abutted in all directions
whenever the supply is well connected and connectors are always placed on
the 5x5 grid.
.SH DELAY MODEL
Cells have been extracted and simulated by using a generic 0.35um process
in order to give realistic values for the delays and capacitances. We
chose to give only the worst delay for each output signal, though it is not
very realistic (since delay depends on each input, an input can be easily
up to twice faster than another). However, we just wanted to give an idea
of the relative delay.
Furthermore, we added 0.6ns to each output delay in order to take into
account the delay due to the signal commutation. We have supposed the
output drives the maximum capacitance. This capacitance have been computed
as follow. We considered that a good slope signal for this process was
0.8ns. Then we searched for the capacitance required to obtain the same
input and output slope (0.8ns) for the smaller inverter (inv_x1). That was
125fF. We simulated the same inverter without output capacitance. The delay
difference was about 0.6ns. This result is not exactly the same for all
cells, but 0.6ns is a good approximation.
The given delay is then a worst case (70degree, 2.7Volt, slow process,
worst input), an idea of the typical delay can be obtain by dividing worst
delay by 1.5, and best delay by dividing by 2. More detailed data can be
found in GENERIC data included in the VHDL files (.vbe). Examples can be
found at the end of this manual.
At last, to get a very better idea about the real delay without simulating
the spice transistor netlist, it is required to use the TAS (1) tool, which
is a timing static analyzer able to give the longer and the shorter path for
a given process.
.SH OUTPUT DRIVE
The output drive of a cell gives an information on the faculty for the cell
to drive a big capacitance. This faculty depends on the rising and falling
output resistance. The smaller the resistance, the bigger can be the
capacitance. Minimum drive is \fBx1\fP. This corresponds to the smallest
available inverter (inv_x1). \fBx2\fP means the cell is equivalent (from
the driving point of view) at two smaller inverters in parallel, and so
on.
The maximum output drive is \fBx8\fP. It is limited because of the maximum
output slope and the maximum authorized instantaneous current. If it was
bigger the output slope could be very tight and the current too big.
With the 0.35um process, an \fBx1\fP is able to drive about \fB125fF\fP,
\fBx2\fP -> \fB250fF\fP, \fBx4\fP -> \fB500fF\fP,\fBx8\fP -> \fB1000fF\fP.
This is just an indication since if a cell is overloaded, the only
consequence is to increase the propagation time. On the other hand, it is
not very good to under-load a cell because this leads to a signal overshoot.
Actually, for big gate, such as noa3ao322_x1, \fBx1\fP means maximal
driving strength reachable with a single logic layer, that can be much
less than an inv_x1. That is why is the cell list below contains more precise
drive strengh. As you can see noa3ao322_x1 as a output drive strengh of 0.6,
that means 0.6 time an inverter, so say it can drive about 0.6*125fF=75fF.
With the 0.35um process, a \fB1\fP lambda interconnect wire is about
\fB0.15fF\fP, an average cell fan-in is 10fF. Then, if it needs about 50
lambdas to connect 2 cells, an \fBx1\fP cell is able to drive about 7
cells (125/(10+50*.15)=7). With 100 lambdas, 5 cells, with 750 lambdas
only 2 cells. Note that 50 lambdas means cells are very close one from
each other, nearly abutted, 100 lambdas is an average value.
All this are indications. Only a timing analysis on the extracted
transistor net-list from layout can tell if a cell is well used or not
(see tas(1) for informations about static timing analysis).
.SH BEHAVIOR
For most of cells, the user can deduce the cell behavior just by reading its
name. That is very intuitive for \fBinv\fPerter and more complex for and/or
cells. For the last, the name gives the and/or tree structure. The input
order for the VHDL interface component is always the alphabetic order.
.nf
\fBinv\fP : \fBinv\fPersor buffer
\fBbuf\fP : \fBbuf\fPfer
[\fBn\fP]\fBts\fP : [\fBn\fPot] \fBt\fPree-\fBs\fPtate
[\fBn\fP]\fBxr\fP<i> : [\fBn\fPot] \fBx\fPo\fBr\fP <i> inputs
[\fBn\fP]\fBmx\fP<i> : [\fBn\fPot] \fBm\fPultiple\fBx\fPor <i> inputs with coded command
[\fBn\fP][\fBsd\fP]\fBff\fP<i> : [\fBn\fPot] [\fBs\fPtatic|\fBd\fPynamic] \fBf\fPlip-\fBf\fPlop <i> inputs
[\fBn\fP]\fBoa\fP... : [\fBn\fPot] \fBa\fPnd/\fBo\fPr function (see below)
\fBand_or cell (YACC (1) grammar):-\fP
NAME : \fBn\fP OA_CELL -> not OA_CELL
| OA_CELL -> OA_CELL
OA_CELL : OPERATOR INPUTS -> function with INPUTS inputs
| OPERATOR OA_CELLS INPUTS -> function with INPUTS inputs
where some inputs are OA_CELL
OPERATOR : \fBa\fP -> and
| \fBo\fP -> or
| \fBn\fP -> not
OA_CELLS : OA_CELLS OA_CELL -> list of OA_CELL
| OA_CELL -> last OA_CELL of the list
INPUTS : \fBinteger\fP -> number of inputs
The input names are implicit and formed that way \fBi<number>\fP.
They are attributed in order beginning by \fBi0\fP.
\fBnx\fP where x is a number means there are x inverters in parallel. For
example an23 is an \fBand\fP with 3 inputs of which two are inverted, that
is \fBand( not(i0), not(i1), i2)\fP.
\fBExamples:-\fP (some are not in sxlib)
na2 : not( and(i0,i1))
on12 : or( not(i0), i1)
noa2a22 : not( or( and(i0,i1), and(i2,i3)))
noa23 : not( or( and(i0,i1), i3))
noao22a34 : not( or( and( or(i0,i1), i2), and(i3,i4,i5), i6, i7))
Note that xr2 could not be expressed with an and/or formulea even if
.br
xr2 = or( and( not(i0), i1), and( not(i1), i0)) = oan12an122
.br
but the input names are not well distributed.
.fi
.SH CELL LIST
All available cells are listed below. The first column is the pitch width.
The pitch value is 5 lambdas. The height is 50. Area is then <number>*5*50.
The second column is the output drive strenght compared with the \fBinv_x1\fP
output drive strenght (see explanation above in section OUTPUT DRIVE).
The following column is the delay in nano-seconds.
Remember this delay corresponds to the slower
input+0.6ns (see explanation above in section DELAY MODEL).
The last column gives the function behavior with input capacitance.
\fB/\fP means \fBnot\fP, \fB+\fP means \fBor\fP, \fB.\fP
means \fBand\fP, \fB^\fP means \fBxor\fP.
Each input is followed by fan-in capacitance in fF,
(e.g. i0<11> means i0 pin capacitance is 11fF).
For some cells, such as
\fBfulladder\fP, it was not possible to internally connect all inputs.
That means there are several inputs that \fBmust be externally connected\fP.
In the following list, these inputs are followed by a star (*) character in
the equation.
For example, fulladder equation is sout <= (a* . b* . cin*).
a* replaces a0, a1, a2, a3 that must be explicitly connected by the user.
Note also few cells have more than one output. In that case there are
several lines in the list, one by output.
.nf
\fB=================================================================\fP
\fBWIDTH NAME DRIVE DELAY BEHAVIOR with cin\fP
\fB-------------------------------------------------------- INVERSOR\fP
3 inv_x1 1.0 0.7 nq <= /i<8>
3 inv_x2 1.6 0.7 nq <= /i<12>
4 inv_x4 3.6 0.7 nq <= /i<26>
7 inv_x8 8.4 0.7 nq <= /i<54>
\fB---------------------------------------------------------- BUFFER\fP
4 buf_x2 2.1 1.0 q <= i<6>
5 buf_x4 4.3 1.0 q <= i<9>
8 buf_x8 8.4 1.0 q <= i<15>
\fB------------------------------------------------------ THREE STATE\fP
6 nts_x1 1.2 0.8 IF (cmd<14>) nq <= /i<14>
8 nts_x2 2.4 0.9 IF (cmd<18>) nq <= /i<28>
10 ts_x4 4.3 1.1 IF (cmd<19>) q <= i<8>
13 ts_x8 8.4 1.2 IF (cmd<19>) q <= i<8>
\fB-------------------------------------------------------------- AND\fP
4 na2_x1 1.0 0.9 nq <= /(i0<11>.i1<11>)
7 na2_x4 4.3 1.2 nq <= /(i0<10>.i1<10>)
5 na3_x1 0.9 1.0 nq <= /(i0<11>.i1<11>.i2<11>)
8 na3_x4 4.3 1.3 nq <= /(i0<10>.i1<10>.i2<10>)
6 na4_x1 0.7 1.0 nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
10 na4_x4 4.3 1.4 nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
5 a2_x2 2.1 1.0 q <= (i0<9>.i1<11>)
6 a2_x4 4.3 1.1 q <= (i0<9>.i1<11>)
6 a3_x2 2.1 1.1 q <= (i0<10>.i1<10>.i2<10>)
7 a3_x4 4.3 1.2 q <= (i0<10>.i1<10>.i2<10>)
7 a4_x2 2.1 1.2 q <= (i0<10>.i1<10>.i2<10>.i3<10>)
8 a4_x4 4.3 1.3 q <= (i0<10>.i1<10>.i2<10>.i3<10>)
5 an12_x1 1.0 1.0 q <= (/i0<12>).i1<9>
8 an12_x4 4.3 1.1 q <= (/i0<9>).i1<11>
\fB--------------------------------------------------------------- OR\fP
4 no2_x1 1.0 0.9 nq <= /(i0<12>+i1<12>)
8 no2_x4 4.3 1.2 nq <= /(i0<12>+i1<11>)
5 no3_x1 0.8 1.0 nq <= /(i0<12>+i1<12>+i2<12>)
8 no3_x4 4.3 1.3 nq <= /(i0<12>+i1<12>+i2<11>)
6 no4_x1 0.6 1.1 nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
10 no4_x4 4.3 1.4 nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
5 o2_x2 2.1 1.0 q <= (i0<10>+i1<10>)
6 o2_x4 4.3 1.1 q <= (i0<10>+i1<10>)
6 o3_x2 2.1 1.1 q <= (i0<10>+i1<10>+i2<9>)
10 o3_x4 4.3 1.2 q <= (i0<10>+i1<10>+i2<9>)
7 o4_x2 2.1 1.2 q <= (i0<10>+i1<10>+i2<10>+i3<9>)
8 o4_x4 4.3 1.3 q <= (i0<12>+i1<12>+i2<12>+i3<12>)
5 on12_x1 1.0 0.9 q <= (/i0<11>)+i1<9>
8 on12_x4 4.3 1.1 q <= (/i0<9>)+i1<10>
\fB--------------------------------------------------------- AND/OR 3\fP
6 nao22_x1 1.2 0.9 nq <= /((i0<14>+i1<14>).i2<14>)
10 nao22_x4 4.3 1.3 nq <= /((i0<8> +i1<8>) .i2<9>)
6 noa22_x1 1.2 0.9 nq <= /((i0<14>.i1<14>)+i2<14>)
10 noa22_x4 4.3 1.3 nq <= /((i0<8> .i1<8>) +i2<9>)
6 ao22_x2 2.1 1.2 q <= ((i0<8>+i1<8>).i2<9>)
8 ao22_x4 4.3 1.3 q <= ((i0<8>+i1<8>).i2<9>)
6 oa22_x2 2.1 1.2 q <= ((i0<8>.i1<8>)+i2<9>)
8 oa22_x4 4.3 1.3 q <= ((i0<8>.i1<8>)+i2<9>)
\fB--------------------------------------------------------- AND/OR 4\fP
7 nao2o22_x1 1.2 1.0 nq <= /((i0<14>+i1<14>).(i2<14>+i3<14>))
11 nao2o22_x4 4.3 1.4 nq <= /((i0<8> +i1<8>) .(i2<8> +i3<8>))
7 noa2a22_x1 1.2 1.0 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<14>))
11 noa2a22_x4 4.3 1.4 nq <= /((i0<8> .i1<8>) +(i2<8> .i3<8>))
9 ao2o22_x2 2.1 1.2 q <= ((i0<8>+i1<8>).(i2<8>+i3<8>))
10 ao2o22_x4 4.3 1.3 q <= ((i0<8>+i1<8>).(i2<8>+i3<8>))
9 oa2a22_x2 2.1 1.2 q <= ((i0<8>.i1<8>)+(i2<8>.i3<8>))
10 oa2a22_x4 4.3 1.4 q <= ((i0<8>.i1<8>)+(i2<8>.i3<8>))
\fB--------------------------------------------------------- AND/OR 5\fP
7 noa2ao222_x1 0.7 1.1 nq <= /((i0<11>.i1<11>)+((i2<13>+i3<13>).i4<13>))
11 noa2ao222_x4 4.3 1.4 nq <= /((i0<11>.i1<11>)+((i2<11>+i3<11>).i4<11>))
10 oa2ao222_x2 2.1 1.2 q <= ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
11 oa2ao222_x4 4.3 1.3 q <= ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
\fB--------------------------------------------------------- AND/OR 6\fP
10 noa2a2a23_x1 0.8 1.2 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>)
+(i4<14>.i5<14>))
13 noa2a2a23_x4 4.3 1.3 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>)
+(i4<14>.i5<14>))
12 oa2a2a23_x2 2.1 1.4 q <= ((i0<13>.i1<14>) +(i2<14>.i3<14>)
+(i4<14>.i5<14>))
13 oa2a2a23_x4 4.3 1.4 q <= ((i0<13>.i1<14>) +(i2<14>.i3<14>)
+(i4<14>.i5<14>))
\fB--------------------------------------------------------- AND/OR 7\fP
9 noa3ao322_x1 0.6 1.2 nq <= /((i0<13>.i1<13>.i2<12>)
+((i3<13>+i4<13>+i5<13>).i6<13>))
11 noa3ao322_x4 4.3 1.4 nq <= /((i0<10>.i1<9>.i2<9>)
+((i3<9>+i4<9>+i5<9>).i6<9>))
10 oa3ao322_x2 2.1 1.2 q <= /((i0<10>.i1<9>.i2<9>)
+((i3<9>+i4<9>+i5<9>).i6<9>))
11 oa3ao322_x4 4.3 1.3 q <= /((i0<10>.i1<9>.i2<9>)
+((i3<9>+i4<9>+i5<9>).i6<9>))
\fB--------------------------------------------------------- AND/OR 8\fP
14 noa2a2a2a24_x1 0.6 1.4 nq <= /((i0<14>.i1<14>)+(i2<13>.i3<13>)
+(i4<13>.i5<13>)+(i6<14>.i7<14>))
17 noa2a2a2a24_x4 4.3 1.7 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<13>)
+(i4<13>.i5<13>)+(i6<14>.i7<14>))
15 oa2a2a2a24_x2 2.1 1.5 q <= ((i0<14>.i1<14>)+(i2<14>.i3<13>)
+(i4<13>.i5<13>)+(i6<14>.i7<14>))
16 oa2a2a2a24_x4 4.3 1.6 q <= ((i0<14>.i1<14>)+(i2<14>.i3<13>)
+(i4<13>.i5<13>)+(i6<14>.i7<14>))
\fB------------------------------------------------------ MULTIPLEXER\fP
7 nmx2_x1 1.2 1.0 nq <= /((i0<14>./cmd<21>)+(i1<14>.cmd))
12 nmx2_x4 4.3 1.3 nq <= /((i0<8>./cmd<14>)+(i1<9>.cmd))
9 mx2_x2 2.1 1.1 q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
10 mx2_x4 4.3 1.3 q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
12 nmx3_x1 0.4 1.2 nq <= /((i0<9>./cmd0<15>)
+(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
15 nmx3_x4 4.3 1.7 nq <= /((i0<9>./cmd0<15>)
+(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
13 mx3_x2 2.1 1.4 q <= ((i0<9>./cmd0<15>)
+(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
14 mx3_x4 4.3 1.6 q <= ((i0<9>./cmd0<15>)
+(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
\fB-------------------------------------------------------------- XOR\fP
9 nxr2_x1 1.2 1.1 nq <= /(i0<21>^i1<22>)
11 nxr2_x4 4.3 1.2 nq <= /(i0<20>^i1<21>)
9 xr2_x1 1.2 1.0 q <= (i0<21>^i1<22>)
12 xr2_x4 4.3 1.2 q <= (i0<20>^i1<21>)
\fB-------------------------------------------------------- FLIP-FLOP\fP
."25 nsdff2_x4 4.3 1.0 IF RISE(ck<23>)
nq <=/((i0<11>./cmd<13>)+(i1<7>.cmd))
18 sff1_x4 4.3 1.7 IF RISE(ck<8>)
q <= i<8>
24 sff2_x4 4.3 1.9 IF RISE(ck<8>)
q <= ((i0<8>./cmd<16>)+(i1<7>.cmd))
28 sff3_x4 4.3 2.4 IF RISE(ck<8>)
q <= (i0<9>./cmd0<15>)
+(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0)
\fB------------------------------------------------------------ ADDER\fP
16 halfadder_x2 2.1 1.2 sout <= (a<27>^b<22>)
2.1 1.0 cout <= (a.b)
18 halfadder_x4 4.3 1.3 sout <= (a<27>^b<22>)
4.3 1.1 cout <= (a.b)
20 fulladder_x2 2.1 1.8 sout <= (a*<28>^b*<28>^cin*<19>)
2.1 1.4 cout <= (a*.b*+a*.cin*+b*.cin*)
21 fulladder_x4 4.3 2.2 sout <= (a*<28>^b*<28>^cin*<19>)
4.3 1.5 cout <= (a*.b*+a*.cin*+b*.cin*)
\fB---------------------------------------------------------- SPECIAL\fP
3 zero_x0 0 0 nq <= '0'
3 one_x0 0 0 q <= '1'
2 tie_x0 0 0 Body tie cell
1 rowend_x0 0 0 Empty cell
\fB==================================================================\fP
.fi
.SH NEW CELLS
It is possible to add new cells in the library just by providing the 3
files .ap, .al and .vbe in the standard cell directory. The layout view
can be created with the symbolic editor graal. The physical outline is
given above. The net-list view can be automatically generated with the
lynx extractor. The behavioral view must be written by the designer and
checked with the yagle functional abstractor. The file must contain the
generic fields in order to be used by the logic synthesis tools and the
I/Os terminals must be in the same order (alphabetic) in the .vbe and .al
files.
If you develop new cells, please send the corresponding files
to alliance\-support@asim.lip6.fr
.SH VHDL FILES
You can find below the commented VHDL GENERIC for the na2_x4 cell.
.nf
ENTITY na2_x4 IS
GENERIC (
CONSTANT area : NATURAL := 1750; -- lamba * lambda
CONSTANT transistors : NATURAL := 10; -- number of
CONSTANT cin_i0 : NATURAL := 10; -- femto Farad for i0
CONSTANT cin_i1 : NATURAL := 10; -- femto Farad for i1
CONSTANT tplh_i1_nq : NATURAL := 606; -- propag. time in pico-sec
-- from i1 falling
-- to nq rizing
CONSTANT rup_i1_nq : NATURAL := 890; -- resitance in Ohms when nq
-- rizing due to i1 change
CONSTANT tphl_i1_nq : NATURAL := 349; -- propag time when nq falls
CONSTANT rdown_i1_nq : NATURAL := 800; -- resist when nq falls
CONSTANT tplh_i0_nq : NATURAL := 557; -- idem for i0
CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tphl_i0_nq : NATURAL := 408;
CONSTANT rdown_i0_nq : NATURAL := 800
);
PORT (
i0 : in BIT;
i1 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
.fi
.SH SEE ALSO
\fBMBK_CATA_LIB (1), catal(1), scr(1), lynx(1), bop(1), glop(1), scmap(1),
c4map(1), tas(1), yagle(1), genlib(1), ap(1), al(1), vbe(1)\fP
.so man1/alc_bug_report.1

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# $Id: Makefile.am,v 1.1 2002/04/29 15:51:49 czo Exp $
#SUBDIRS = dp_sxlib padlib rflib sxlib
SUBDIRS = sxlib

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alliance/src/cells/src/dp_sxlib/CATAL Normal file
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dp_dff_scan_x4 C
dp_dff_scan_x4_buf C
dp_dff_x4 C
dp_dff_x4_buf C
dp_mux_x2 C
dp_mux_x2_buf C
dp_mux_x4 C
dp_mux_x4_buf C
dp_nmux_x1 C
dp_nmux_x1_buf C
dp_nts_x2 C
dp_nts_x2_buf C
dp_rom2_buf C
dp_rom4_buf C
dp_rom4_nxr2_x4 C
dp_rom4_xr2_x4 C
dp_sff_scan_x4 C
dp_sff_scan_x4_buf C
dp_sff_x4 C
dp_sff_x4_buf C
dp_ts_x4 C
dp_ts_x4_buf C
dp_ts_x8 C
dp_ts_x8_buf C

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alliance/src/cells/src/dp_sxlib/Makefile.am Normal file
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# $Id: Makefile.am,v 1.1 2002/04/29 15:51:49 czo Exp $
dp_sxlib_DATA= CATAL dp_dff_scan_x4.ap dp_dff_scan_x4.vbe dp_dff_scan_x4_buf.ap dp_dff_scan_x4_buf.vbe dp_dff_x4.ap dp_dff_x4.vbe dp_dff_x4_buf.ap dp_dff_x4_buf.vbe dp_mux_x2.ap dp_mux_x2.vbe dp_mux_x2_buf.ap dp_mux_x2_buf.vbe dp_mux_x4.ap dp_mux_x4.vbe dp_mux_x4_buf.ap dp_mux_x4_buf.vbe dp_nmux_x1.ap dp_nmux_x1.vbe dp_nmux_x1_buf.ap dp_nmux_x1_buf.vbe dp_nts_x2.ap dp_nts_x2.vbe dp_nts_x2_buf.ap dp_nts_x2_buf.vbe dp_rom2_buf.ap dp_rom2_buf.vbe dp_rom4_buf.ap dp_rom4_buf.vbe dp_rom4_nxr2_x4.ap dp_rom4_nxr2_x4.vbe dp_rom4_xr2_x4.ap dp_rom4_xr2_x4.vbe dp_sff_scan_x4.ap dp_sff_scan_x4.vbe dp_sff_scan_x4_buf.ap dp_sff_scan_x4_buf.vbe dp_sff_x4.ap dp_sff_x4.vbe dp_sff_x4_buf.ap dp_sff_x4_buf.vbe dp_sxlib.lef dp_ts_x4.ap dp_ts_x4.vbe dp_ts_x4_buf.ap dp_ts_x4_buf.vbe dp_ts_x8.ap dp_ts_x8.vbe dp_ts_x8_buf.ap dp_ts_x8_buf.vbe
EXTRA_DIST=$(dp_sxlib_DATA)

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alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4.ap Normal file
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V ALLIANCE : 6
H dp_dff_scan_x4,P,14/11/2000,10
A 0,0,1000,500
R 600,200,ref_ref,nckx
R 750,200,ref_ref,ckx
R 500,200,ref_ref,scanx
R 400,200,ref_ref,nscanx
R 250,200,ref_ref,nwenx
R 150,200,ref_ref,wenx
R 100,300,ref_ref,i_30
R 100,250,ref_ref,i_25
R 100,200,ref_ref,i_20
R 100,150,ref_ref,i_15
R 100,100,ref_ref,i_10
R 100,400,ref_ref,i_40
R 100,350,ref_ref,i_35
R 900,350,ref_ref,q_35
R 900,200,ref_ref,q_20
R 900,300,ref_ref,q_30
R 900,400,ref_ref,q_40
R 900,100,ref_ref,q_10
R 900,150,ref_ref,q_15
R 900,250,ref_ref,q_25
S 150,200,750,200,20,*,RIGHT,TALU2
S 600,150,640,150,20,*,RIGHT,ALU1
S 600,300,690,300,10,*,RIGHT,ALU1
S 600,150,600,300,10,*,DOWN,ALU1
S 600,200,600,200,20,nckx,LEFT,CALU3
S 740,250,740,350,10,*,DOWN,ALU1
S 670,350,670,400,10,*,DOWN,ALU1
S 670,350,740,350,10,*,RIGHT,ALU1
S 570,50,570,100,20,*,UP,ALU1
S 160,400,260,400,10,*,LEFT,ALU1
S 260,150,260,400,10,*,UP,ALU1
S 310,150,310,300,10,*,UP,ALU1
S 0,400,1000,400,260,*,RIGHT,NWELL
S 220,30,220,110,30,*,DOWN,NDIF
S 210,100,210,350,10,*,UP,ALU1
S 330,50,330,100,20,*,DOWN,ALU1
S 300,90,300,150,10,*,DOWN,POLY
S 250,90,250,150,10,*,DOWN,POLY
S 60,90,60,140,10,*,DOWN,POLY
S 60,140,210,140,10,*,LEFT,POLY
S 60,290,60,340,10,*,DOWN,POLY
S 90,100,120,100,30,*,RIGHT,POLY
S 200,30,200,110,30,*,DOWN,NDIF
S 330,30,330,120,30,*,DOWN,NDIF
S 90,30,90,70,30,*,DOWN,NDIF
S 30,30,30,110,30,*,DOWN,NDIF
S 60,10,60,90,10,*,DOWN,NTRANS
S 250,10,250,90,10,*,DOWN,NTRANS
S 120,10,120,90,10,*,DOWN,NTRANS
S 170,10,170,90,10,*,DOWN,NTRANS
S 300,10,300,90,10,*,DOWN,NTRANS
S 30,200,360,200,10,*,LEFT,POLY
S 150,250,250,250,10,*,RIGHT,POLY
S 60,340,60,470,10,*,UP,PTRANS
S 30,360,30,450,30,*,UP,PDIF
S 90,360,90,450,30,*,UP,PDIF
S 170,340,170,470,10,*,UP,PTRANS
S 120,340,120,470,10,*,UP,PTRANS
S 960,280,960,470,30,*,DOWN,PDIF
S 930,260,930,490,10,*,DOWN,PTRANS
S 810,260,810,490,10,*,DOWN,PTRANS
S 740,280,740,470,30,*,DOWN,PDIF
S 830,280,830,470,30,*,DOWN,PDIF
S 770,260,770,490,10,*,DOWN,PTRANS
S 900,280,900,470,30,*,DOWN,PDIF
S 870,260,870,490,10,*,DOWN,PTRANS
S 330,40,330,120,30,*,DOWN,NDIF
S 740,30,740,120,30,*,DOWN,NDIF
S 930,10,930,140,10,*,UP,NTRANS
S 900,30,900,120,30,*,DOWN,NDIF
S 840,30,840,120,30,*,DOWN,NDIF
S 770,10,770,140,10,*,UP,NTRANS
S 810,10,810,140,10,*,UP,NTRANS
S 870,10,870,140,10,*,UP,NTRANS
S 960,30,960,120,30,*,DOWN,NDIF
S 360,60,360,140,10,*,DOWN,NTRANS
S 600,60,600,140,10,*,UP,NTRANS
S 570,40,570,120,30,*,DOWN,NDIF
S 640,60,640,140,10,*,UP,NTRANS
S 670,80,670,120,30,*,DOWN,NDIF
S 450,80,450,120,50,*,UP,NDIF
S 410,60,410,140,10,*,DOWN,NTRANS
S 540,60,540,140,10,*,DOWN,NTRANS
S 490,60,490,140,10,*,DOWN,NTRANS
S 60,290,210,290,10,*,RIGHT,POLY
S 90,330,120,330,30,*,RIGHT,POLY
S 250,250,250,350,10,*,UP,POLY
S 690,250,770,250,10,*,LEFT,POLY
S 730,140,770,140,10,*,LEFT,POLY
S 930,140,930,260,10,*,DOWN,POLY
S 850,200,930,200,10,*,RIGHT,POLY
S 810,140,810,260,10,*,DOWN,POLY
S 770,250,770,260,10,*,DOWN,POLY
S 870,140,870,260,10,*,DOWN,POLY
S 410,250,490,250,10,*,RIGHT,POLY
S 410,140,410,250,10,*,UP,POLY
S 450,200,600,200,10,*,RIGHT,POLY
S 30,100,30,400,10,*,DOWN,ALU1
S 160,330,160,400,10,*,DOWN,ALU1
S 670,100,690,100,20,*,RIGHT,ALU1
S 740,400,790,400,10,*,RIGHT,ALU1
S 960,300,960,450,20,*,DOWN,ALU1
S 960,50,960,100,20,*,DOWN,ALU1
S 450,100,450,350,10,*,UP,ALU1
S 500,150,500,400,10,*,UP,ALU1
S 400,400,500,400,10,*,LEFT,ALU1
S 790,250,790,400,10,*,DOWN,ALU1
S 690,250,740,250,10,*,RIGHT,ALU1
S 690,100,690,250,10,*,DOWN,ALU1
S 640,200,730,200,10,*,RIGHT,POLY
S 730,140,730,200,10,*,DOWN,POLY
S 690,250,690,300,10,*,UP,POLY
S 690,150,800,150,10,*,RIGHT,ALU1
S 800,150,800,190,10,*,UP,ALU1
S 850,100,850,250,10,*,DOWN,ALU1
S 740,100,850,100,10,*,LEFT,ALU1
S 790,250,850,250,10,*,RIGHT,ALU1
S 840,300,840,450,20,*,DOWN,ALU1
S 150,100,150,250,10,*,UP,ALU1
S 410,310,410,440,10,*,UP,PTRANS
S 490,310,490,440,10,*,UP,PTRANS
S 540,310,540,440,10,*,UP,PTRANS
S 450,330,450,420,50,*,UP,PDIF
S 360,310,360,440,10,*,UP,PTRANS
S 300,310,300,440,10,*,UP,PTRANS
S 330,330,330,420,30,*,UP,PDIF
S 330,350,330,450,20,*,DOWN,ALU1
S 330,360,330,420,30,*,UP,PDIF
S 250,310,250,440,10,*,UP,PTRANS
S 360,140,360,310,10,*,DOWN,POLY
S 490,250,490,310,10,*,DOWN,POLY
S 210,330,210,450,50,*,UP,PDIF
S 570,350,570,450,20,*,DOWN,ALU1
S 640,360,640,490,10,*,DOWN,PTRANS
S 600,360,600,490,10,*,DOWN,PTRANS
S 570,330,570,470,30,*,UP,PDIF
S 670,380,670,470,30,*,DOWN,PDIF
S 600,90,600,360,10,*,DOWN,POLY
S 640,200,640,360,10,*,DOWN,POLY
S 400,300,400,400,10,*,DOWN,ALU1
S 100,100,100,400,20,i,UP,CALU1
S 900,100,900,400,20,q,DOWN,CALU1
S 0,30,1000,30,60,vss,RIGHT,CALU1
S 0,470,1000,470,60,vdd,RIGHT,CALU1
S 550,150,550,300,10,scin,UP,CALU1
S 150,200,150,200,20,wenx,LEFT,CALU3
S 250,200,250,200,20,nwenx,LEFT,CALU3
S 400,200,400,200,20,nscanx,LEFT,CALU3
S 500,200,500,200,20,scanx,LEFT,CALU3
S 750,200,750,200,20,ckx,LEFT,CALU3
S 300,250,900,250,20,q,RIGHT,CALU2
V 600,200,CONT_VIA,*
V 600,200,CONT_VIA2,*
V 150,200,CONT_VIA,*
V 150,200,CONT_VIA2,*
V 670,30,CONT_BODY_P,*
V 570,100,CONT_DIF_N,*
V 570,400,CONT_DIF_P,*
V 330,400,CONT_DIF_P,*
V 260,150,CONT_POLY,*
V 310,150,CONT_POLY,*
V 310,300,CONT_POLY,*
V 310,250,CONT_VIA,*
V 210,100,CONT_DIF_N,*
V 210,150,CONT_POLY,*
V 210,350,CONT_DIF_P,*
V 330,100,CONT_DIF_N,*
V 160,100,CONT_POLY,*
V 100,100,CONT_POLY,*
V 30,200,CONT_POLY,*
V 150,250,CONT_POLY,*
V 90,450,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 840,350,CONT_DIF_P,*
V 960,300,CONT_DIF_P,*
V 960,450,CONT_DIF_P,*
V 840,450,CONT_DIF_P,*
V 840,400,CONT_DIF_P,*
V 900,300,CONT_DIF_P,*
V 960,400,CONT_DIF_P,*
V 960,350,CONT_DIF_P,*
V 740,400,CONT_DIF_P,*
V 570,450,CONT_DIF_P,*
V 450,350,CONT_DIF_P,*
V 90,50,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 330,50,CONT_DIF_N,*
V 960,100,CONT_DIF_N,*
V 960,50,CONT_DIF_N,*
V 840,50,CONT_DIF_N,*
V 900,100,CONT_DIF_N,*
V 740,100,CONT_DIF_N,*
V 570,50,CONT_DIF_N,*
V 450,100,CONT_DIF_N,*
V 330,50,CONT_DIF_N,*
V 670,100,CONT_DIF_N,*
V 510,30,CONT_BODY_P,*
V 390,30,CONT_BODY_P,*
V 450,30,CONT_BODY_P,*
V 210,300,CONT_POLY,*
V 100,330,CONT_POLY,*
V 160,330,CONT_POLY,*
V 550,300,CONT_POLY,*
V 550,150,CONT_POLY,*
V 500,150,CONT_POLY,*
V 850,200,CONT_POLY,*
V 640,150,CONT_POLY,*
V 450,200,CONT_POLY,*
V 900,250,CONT_VIA,*
V 800,200,CONT_POLY,*
V 690,300,CONT_POLY,*
V 750,200,CONT_VIA2,*
V 750,200,CONT_VIA,*
V 740,200,CONT_POLY,*
V 840,300,CONT_DIF_P,*
V 400,200,CONT_VIA2,*
V 400,200,CONT_VIA,*
V 400,200,CONT_POLY,*
V 500,200,CONT_VIA2,*
V 500,200,CONT_VIA,*
V 250,200,CONT_VIA2,*
V 260,200,CONT_VIA,*
V 400,300,CONT_POLY,*
V 450,470,CONT_BODY_N,*
V 510,470,CONT_BODY_N,*
V 390,470,CONT_BODY_N,*
V 330,350,CONT_DIF_P,*
V 330,470,CONT_BODY_N,*
V 570,350,CONT_DIF_P,*
V 670,400,CONT_DIF_P,*
EOF

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alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4.vbe Normal file
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ENTITY dp_dff_scan_x4 IS
PORT (
ckx : in BIT;
nckx : in BIT;
wenx : in BIT;
nwenx : in BIT;
scanx : in BIT;
nscanx : in BIT;
i : in BIT;
scin : in BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_dff_scan_x4;
ARCHITECTURE vbe OF dp_dff_scan_x4 IS
SIGNAL ff : REG_BIT REGISTER;
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on dp_dff_scan_x4"
SEVERITY WARNING;
ASSERT (ckx xor nckx)
REPORT "wrong values for ckx and nckx in dp_dff_scan_x4"
SEVERITY WARNING;
ASSERT (wenx xor nwenx)
REPORT "wrong values for wenx and nwenx in dp_dff_scan_x4"
SEVERITY WARNING;
ASSERT (scanx xor nscanx)
REPORT "wrong values for scanx and nscanx in dp_dff_scan_x4"
SEVERITY WARNING;
label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1')
BEGIN
ff <= GUARDED ((scanx and scin) or (nscanx and ((wenx and i) or (nwenx and ff))));
END BLOCK label0;
q <= ff;
END;

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alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4_buf.ap Normal file
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V ALLIANCE : 6
H dp_dff_scan_x4_buf,P,14/11/2000,10
A 0,0,1000,1000
R 650,400,ref_ref,nckx
R 750,400,ref_ref,ckx
R 500,400,ref_ref,scanx
R 400,400,ref_ref,nscanx
R 250,400,ref_ref,nwenx
R 150,400,ref_ref,wenx
R 950,700,ref_ref,scin
R 900,300,ref_ref,scout
R 900,250,ref_ref,scout
R 900,200,ref_ref,scout
R 900,150,ref_ref,scout
R 900,100,ref_ref,scout
R 900,350,ref_ref,scout
R 900,400,ref_ref,scout
S 150,150,750,150,20,*,RIGHT,TALU2
S 150,400,750,400,20,*,LEFT,TALU2
S 150,600,750,600,20,*,RIGHT,TALU2
S 650,150,650,600,20,nckx,DOWN,CALU3
S 500,150,500,600,20,scanx,DOWN,CALU3
S 400,150,400,600,20,nscanx,DOWN,CALU3
S 250,150,250,600,20,nwenx,DOWN,CALU3
S 150,150,150,600,20,wenx,DOWN,CALU3
S 200,850,200,850,10,wen,LEFT,CALU1
S 450,850,450,850,10,scan,LEFT,CALU1
S 700,850,700,850,10,ck,LEFT,CALU1
S 900,100,900,400,20,scout,UP,CALU1
S 0,470,1000,470,60,vdd,RIGHT,CALU1
S 0,530,1000,530,60,vdd,RIGHT,CALU1
S 0,30,1000,30,60,vss,RIGHT,CALU1
S 0,970,1000,970,60,vss,RIGHT,CALU1
S 950,700,950,700,10,scin,LEFT,CALU1
S 140,220,210,220,20,*,RIGHT,ALU1
S 210,220,290,220,30,*,RIGHT,POLY
S 110,220,170,220,30,*,RIGHT,POLY
S 260,740,260,790,20,*,DOWN,ALU1
S 140,660,140,900,20,*,UP,ALU1
S 110,660,170,660,30,*,RIGHT,POLY
S 320,900,320,970,20,*,UP,ALU1
S 320,50,320,150,20,*,UP,ALU1
S 80,900,80,970,20,*,DOWN,ALU1
S 200,50,200,150,20,*,UP,ALU1
S 80,50,80,150,20,*,UP,ALU1
S 320,280,320,680,20,*,UP,ALU1
S 200,900,200,940,20,*,UP,ALU1
S 140,790,260,790,20,*,RIGHT,ALU1
S 570,280,570,680,20,*,UP,ALU1
S 450,50,450,150,20,*,UP,ALU1
S 570,50,570,150,20,*,UP,ALU1
S 820,50,820,150,20,*,UP,ALU1
S 700,50,700,150,20,*,UP,ALU1
S 390,790,510,790,20,*,RIGHT,ALU1
S 450,900,450,940,20,*,UP,ALU1
S 570,900,570,970,20,*,UP,ALU1
S 700,900,700,940,20,*,UP,ALU1
S 640,790,760,790,20,*,RIGHT,ALU1
S 170,190,170,320,10,*,UP,POLY
S 290,190,290,320,10,*,UP,POLY
S 230,190,230,320,10,*,DOWN,POLY
S 170,850,230,850,30,*,RIGHT,POLY
S 230,820,230,860,10,*,DOWN,POLY
S 170,820,170,870,10,*,DOWN,POLY
S 110,190,110,320,10,*,DOWN,POLY
S 360,190,360,320,10,*,DOWN,POLY
S 480,190,480,320,10,*,DOWN,POLY
S 540,190,540,320,10,*,UP,POLY
S 420,190,420,320,10,*,UP,POLY
S 790,190,790,320,10,*,UP,POLY
S 730,190,730,320,10,*,DOWN,POLY
S 610,190,610,320,10,*,DOWN,POLY
S 670,190,670,320,10,*,UP,POLY
S 420,820,420,870,10,*,DOWN,POLY
S 480,820,480,860,10,*,DOWN,POLY
S 420,850,480,850,30,*,RIGHT,POLY
S 670,850,730,850,30,*,RIGHT,POLY
S 730,820,730,860,10,*,DOWN,POLY
S 670,820,670,870,10,*,DOWN,POLY
S 140,30,140,170,30,*,UP,NDIF
S 200,30,200,170,30,*,UP,NDIF
S 110,10,110,190,10,*,UP,NTRANS
S 170,10,170,190,10,*,DOWN,NTRANS
S 320,30,320,170,30,*,UP,NDIF
S 80,30,80,170,30,*,UP,NDIF
S 290,10,290,190,10,*,DOWN,NTRANS
S 260,30,260,170,30,*,UP,NDIF
S 230,10,230,190,10,*,DOWN,NTRANS
S 140,890,140,960,30,*,UP,NDIF
S 200,890,200,960,30,*,UP,NDIF
S 170,870,170,980,10,*,UP,NTRANS
S 570,30,570,170,30,*,UP,NDIF
S 420,10,420,190,10,*,DOWN,NTRANS
S 360,10,360,190,10,*,UP,NTRANS
S 450,30,450,170,30,*,UP,NDIF
S 390,30,390,170,30,*,UP,NDIF
S 480,10,480,190,10,*,DOWN,NTRANS
S 510,30,510,170,30,*,UP,NDIF
S 540,10,540,190,10,*,DOWN,NTRANS
S 820,30,820,170,30,*,UP,NDIF
S 640,30,640,170,30,*,UP,NDIF
S 700,30,700,170,30,*,UP,NDIF
S 610,10,610,190,10,*,UP,NTRANS
S 670,10,670,190,10,*,DOWN,NTRANS
S 790,10,790,190,10,*,DOWN,NTRANS
S 760,30,760,170,30,*,UP,NDIF
S 730,10,730,190,10,*,DOWN,NTRANS
S 450,890,450,960,30,*,UP,NDIF
S 390,890,390,960,30,*,UP,NDIF
S 640,890,640,960,30,*,UP,NDIF
S 700,890,700,960,30,*,UP,NDIF
S 420,870,420,980,10,*,UP,NTRANS
S 670,870,670,980,10,*,UP,NTRANS
S 260,730,260,800,30,*,UP,PDIF
S 80,340,80,630,30,*,UP,PDIF
S 110,320,110,650,10,*,UP,PTRANS
S 200,340,200,630,30,*,UP,PDIF
S 140,340,140,630,30,*,UP,PDIF
S 170,320,170,650,10,*,UP,PTRANS
S 320,340,320,630,30,*,DOWN,PDIF
S 290,320,290,650,10,*,DOWN,PTRANS
S 260,340,260,630,30,*,UP,PDIF
S 230,320,230,650,10,*,UP,PTRANS
S 140,730,140,800,30,*,UP,PDIF
S 170,710,170,820,10,*,DOWN,PTRANS
S 210,730,210,800,30,*,UP,PDIF
S 230,710,230,820,10,*,DOWN,PTRANS
S 570,340,570,630,30,*,DOWN,PDIF
S 420,320,420,650,10,*,UP,PTRANS
S 390,340,390,630,30,*,UP,PDIF
S 450,340,450,630,30,*,UP,PDIF
S 360,320,360,650,10,*,UP,PTRANS
S 0,500,1000,500,460,*,RIGHT,NWELL
S 480,320,480,650,10,*,UP,PTRANS
S 510,340,510,630,30,*,UP,PDIF
S 540,320,540,650,10,*,DOWN,PTRANS
S 700,340,700,630,30,*,UP,PDIF
S 640,340,640,630,30,*,UP,PDIF
S 670,320,670,650,10,*,UP,PTRANS
S 820,340,820,630,30,*,DOWN,PDIF
S 610,320,610,650,10,*,UP,PTRANS
S 790,320,790,650,10,*,DOWN,PTRANS
S 760,340,760,630,30,*,UP,PDIF
S 730,320,730,650,10,*,UP,PTRANS
S 390,730,390,800,30,*,UP,PDIF
S 510,730,510,800,30,*,UP,PDIF
S 640,730,640,800,30,*,UP,PDIF
S 480,710,480,820,10,*,DOWN,PTRANS
S 460,730,460,800,30,*,UP,PDIF
S 420,710,420,820,10,*,DOWN,PTRANS
S 710,730,710,800,30,*,UP,PDIF
S 730,710,730,820,10,*,DOWN,PTRANS
S 760,730,760,800,30,*,UP,PDIF
S 670,710,670,820,10,*,DOWN,PTRANS
S 510,660,510,790,20,*,DOWN,ALU1
S 760,660,760,790,20,*,DOWN,ALU1
S 640,740,640,900,20,*,UP,ALU1
S 390,740,390,900,20,*,UP,ALU1
S 480,660,540,660,30,*,RIGHT,POLY
S 730,660,790,660,30,*,RIGHT,POLY
S 110,770,830,770,80,*,RIGHT,NWELL
S 440,220,510,220,20,*,RIGHT,ALU1
S 690,220,760,220,20,*,RIGHT,ALU1
S 360,220,440,220,30,*,RIGHT,POLY
S 480,220,540,220,30,*,RIGHT,POLY
S 610,220,690,220,30,*,RIGHT,POLY
S 730,220,790,220,30,*,RIGHT,POLY
S 80,290,80,680,20,*,UP,ALU1
S 510,100,510,400,20,*,UP,ALU1
S 390,100,390,400,20,*,UP,ALU1
S 140,100,140,400,20,*,UP,ALU1
S 260,100,260,400,20,*,UP,ALU1
S 640,100,640,400,20,*,UP,ALU1
S 760,100,760,400,20,*,UP,ALU1
S 700,280,700,740,20,*,DOWN,ALU1
S 450,290,450,740,20,*,UP,ALU1
S 200,290,200,740,20,*,DOWN,ALU1
S 850,820,850,870,10,*,DOWN,POLY
S 820,890,820,960,30,*,UP,NDIF
S 850,710,850,820,10,*,DOWN,PTRANS
S 820,730,820,800,30,*,UP,PDIF
S 820,900,820,950,20,*,UP,ALU1
S 820,280,820,790,20,*,UP,ALU1
S 880,730,880,800,30,*,UP,PDIF
S 880,660,880,900,20,*,DOWN,ALU1
S 850,710,950,710,10,*,RIGHT,POLY
S 850,870,850,940,10,*,UP,NTRANS
S 880,890,880,920,30,*,UP,NDIF
S 870,190,870,320,10,*,DOWN,POLY
S 870,320,870,650,10,*,UP,PTRANS
S 900,30,900,170,30,*,UP,NDIF
S 870,10,870,190,10,*,DOWN,NTRANS
S 900,340,900,630,30,*,UP,PDIF
S 840,30,840,170,30,*,UP,NDIF
S 840,340,840,630,30,*,DOWN,PDIF
S 750,150,750,600,20,ckx,DOWN,CALU3
V 950,700,CONT_POLY,*
V 210,220,CONT_POLY,*
V 140,660,CONT_POLY,*
V 150,400,CONT_VIA2,*
V 150,600,CONT_VIA2,*
V 250,600,CONT_VIA2,*
V 150,150,CONT_VIA2,*
V 250,400,CONT_VIA2,*
V 500,400,CONT_VIA2,*
V 400,150,CONT_VIA2,*
V 500,600,CONT_VIA2,*
V 400,600,CONT_VIA2,*
V 400,400,CONT_VIA2,*
V 750,600,CONT_VIA2,*
V 650,150,CONT_VIA2,*
V 750,400,CONT_VIA2,*
V 650,400,CONT_VIA2,*
V 650,600,CONT_VIA2,*
V 150,150,CONT_VIA,*
V 150,400,CONT_VIA,*
V 150,600,CONT_VIA,*
V 250,600,CONT_VIA,*
V 250,400,CONT_VIA,*
V 400,150,CONT_VIA,*
V 500,400,CONT_VIA,*
V 500,600,CONT_VIA,*
V 400,600,CONT_VIA,*
V 400,400,CONT_VIA,*
V 650,150,CONT_VIA,*
V 650,600,CONT_VIA,*
V 750,600,CONT_VIA,*
V 750,400,CONT_VIA,*
V 650,400,CONT_VIA,*
V 200,850,CONT_POLY,*
V 450,850,CONT_POLY,*
V 700,850,CONT_POLY,*
V 570,970,CONT_BODY_P,*
V 320,970,CONT_BODY_P,*
V 80,970,CONT_BODY_P,*
V 320,900,CONT_BODY_P,*
V 80,900,CONT_BODY_P,*
V 570,900,CONT_BODY_P,*
V 320,100,CONT_DIF_N,*
V 260,100,CONT_DIF_N,*
V 320,50,CONT_DIF_N,*
V 320,150,CONT_DIF_N,*
V 260,150,CONT_DIF_N,*
V 80,50,CONT_DIF_N,*
V 80,150,CONT_DIF_N,*
V 80,100,CONT_DIF_N,*
V 200,100,CONT_DIF_N,*
V 200,50,CONT_DIF_N,*
V 200,150,CONT_DIF_N,*
V 140,900,CONT_DIF_N,*
V 140,150,CONT_DIF_N,*
V 140,100,CONT_DIF_N,*
V 200,900,CONT_DIF_N,*
V 200,950,CONT_DIF_N,*
V 570,50,CONT_DIF_N,*
V 510,100,CONT_DIF_N,*
V 570,100,CONT_DIF_N,*
V 390,100,CONT_DIF_N,*
V 390,150,CONT_DIF_N,*
V 450,150,CONT_DIF_N,*
V 450,50,CONT_DIF_N,*
V 450,100,CONT_DIF_N,*
V 510,150,CONT_DIF_N,*
V 570,150,CONT_DIF_N,*
V 760,100,CONT_DIF_N,*
V 820,50,CONT_DIF_N,*
V 640,150,CONT_DIF_N,*
V 640,100,CONT_DIF_N,*
V 820,100,CONT_DIF_N,*
V 820,150,CONT_DIF_N,*
V 760,150,CONT_DIF_N,*
V 700,100,CONT_DIF_N,*
V 700,50,CONT_DIF_N,*
V 700,150,CONT_DIF_N,*
V 700,900,CONT_DIF_N,*
V 700,950,CONT_DIF_N,*
V 450,950,CONT_DIF_N,*
V 450,900,CONT_DIF_N,*
V 390,900,CONT_DIF_N,*
V 640,900,CONT_DIF_N,*
V 140,790,CONT_DIF_P,*
V 200,740,CONT_DIF_P,*
V 140,740,CONT_DIF_P,*
V 200,290,CONT_BODY_N,*
V 80,290,CONT_BODY_N,*
V 320,290,CONT_BODY_N,*
V 80,600,CONT_DIF_P,*
V 80,350,CONT_DIF_P,*
V 80,550,CONT_DIF_P,*
V 80,500,CONT_DIF_P,*
V 80,450,CONT_DIF_P,*
V 80,400,CONT_DIF_P,*
V 200,350,CONT_DIF_P,*
V 200,450,CONT_DIF_P,*
V 200,550,CONT_DIF_P,*
V 200,400,CONT_DIF_P,*
V 200,500,CONT_DIF_P,*
V 320,400,CONT_DIF_P,*
V 320,350,CONT_DIF_P,*
V 320,450,CONT_DIF_P,*
V 320,500,CONT_DIF_P,*
V 320,550,CONT_DIF_P,*
V 320,600,CONT_DIF_P,*
V 260,400,CONT_DIF_P,*
V 260,350,CONT_DIF_P,*
V 140,350,CONT_DIF_P,*
V 140,400,CONT_DIF_P,*
V 140,600,CONT_DIF_P,*
V 260,600,CONT_DIF_P,*
V 260,790,CONT_DIF_P,*
V 260,740,CONT_DIF_P,*
V 200,680,CONT_BODY_N,*
V 320,680,CONT_BODY_N,*
V 80,680,CONT_BODY_N,*
V 450,550,CONT_DIF_P,*
V 450,450,CONT_DIF_P,*
V 450,350,CONT_DIF_P,*
V 570,290,CONT_BODY_N,*
V 450,290,CONT_BODY_N,*
V 570,600,CONT_DIF_P,*
V 570,550,CONT_DIF_P,*
V 570,500,CONT_DIF_P,*
V 570,450,CONT_DIF_P,*
V 570,350,CONT_DIF_P,*
V 570,400,CONT_DIF_P,*
V 450,500,CONT_DIF_P,*
V 450,400,CONT_DIF_P,*
V 570,680,CONT_BODY_N,*
V 450,680,CONT_BODY_N,*
V 510,600,CONT_DIF_P,*
V 390,600,CONT_DIF_P,*
V 390,400,CONT_DIF_P,*
V 390,350,CONT_DIF_P,*
V 510,350,CONT_DIF_P,*
V 510,400,CONT_DIF_P,*
V 700,350,CONT_DIF_P,*
V 700,450,CONT_DIF_P,*
V 700,550,CONT_DIF_P,*
V 820,500,CONT_DIF_P,*
V 820,550,CONT_DIF_P,*
V 820,600,CONT_DIF_P,*
V 700,290,CONT_BODY_N,*
V 820,290,CONT_BODY_N,*
V 760,600,CONT_DIF_P,*
V 700,680,CONT_BODY_N,*
V 820,680,CONT_BODY_N,*
V 700,400,CONT_DIF_P,*
V 700,500,CONT_DIF_P,*
V 820,400,CONT_DIF_P,*
V 820,350,CONT_DIF_P,*
V 820,450,CONT_DIF_P,*
V 390,790,CONT_DIF_P,*
V 760,400,CONT_DIF_P,*
V 760,350,CONT_DIF_P,*
V 640,350,CONT_DIF_P,*
V 640,400,CONT_DIF_P,*
V 640,600,CONT_DIF_P,*
V 510,740,CONT_DIF_P,*
V 510,790,CONT_DIF_P,*
V 390,740,CONT_DIF_P,*
V 450,740,CONT_DIF_P,*
V 700,740,CONT_DIF_P,*
V 640,740,CONT_DIF_P,*
V 760,790,CONT_DIF_P,*
V 760,740,CONT_DIF_P,*
V 640,790,CONT_DIF_P,*
V 510,660,CONT_POLY,*
V 760,660,CONT_POLY,*
V 700,600,CONT_DIF_P,*
V 450,600,CONT_DIF_P,*
V 200,600,CONT_DIF_P,*
V 440,220,CONT_POLY,*
V 690,220,CONT_POLY,*
V 750,150,CONT_VIA2,*
V 750,150,CONT_VIA,*
V 500,150,CONT_VIA2,*
V 500,150,CONT_VIA,*
V 250,150,CONT_VIA2,*
V 250,150,CONT_VIA,*
V 880,900,CONT_DIF_N,*
V 820,900,CONT_DIF_N,*
V 820,790,CONT_DIF_P,*
V 880,740,CONT_DIF_P,*
V 820,740,CONT_DIF_P,*
V 820,950,CONT_DIF_N,*
V 880,660,CONT_POLY,*
V 880,790,CONT_DIF_P,*
V 900,150,CONT_DIF_N,*
V 900,100,CONT_DIF_N,*
V 900,400,CONT_DIF_P,*
V 900,350,CONT_DIF_P,*
EOF

33
alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4_buf.vbe Normal file
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@ -0,0 +1,33 @@
ENTITY dp_dff_scan_x4_buf IS
PORT (
ck : in BIT;
wen : in BIT;
scan : in BIT;
scin : in BIT;
ckx : out BIT;
nckx : out BIT;
wenx : out BIT;
nwenx : out BIT;
scanx : out BIT;
nscanx : out BIT;
scout : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_dff_scan_x4_buf;
ARCHITECTURE vbe OF dp_dff_scan_x4_buf IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on dp_dff_scan_x4_buf"
SEVERITY WARNING;
ckx <= ck;
nckx <= not ck;
wenx <= wen;
nwenx <= not wen;
scanx <= scan;
nscanx <= not scan;
scout <= scin;
END;

170
alliance/src/cells/src/dp_sxlib/dp_dff_x4.ap Normal file
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@ -0,0 +1,170 @@
V ALLIANCE : 6
H dp_dff_x4,P,26/ 9/2000,100
A 0,0,7000,5000
R 3000,2000,ref_ref,nckx
R 500,4000,ref_ref,i_40
R 500,1000,ref_ref,i_10
R 500,1500,ref_ref,i_15
R 500,2000,ref_ref,i_20
R 500,3500,ref_ref,i_35
R 500,3000,ref_ref,i_30
R 6000,1500,ref_ref,q_15
R 6000,1000,ref_ref,q_10
R 6000,4000,ref_ref,q_40
R 6000,3000,ref_ref,q_30
R 6000,2000,ref_ref,q_20
R 6000,3500,ref_ref,q_35
R 500,2500,ref_ref,i_25
R 6000,2500,ref_ref,q_25
R 1000,2000,ref_ref,wenx
R 2000,2000,ref_ref,nwenx
R 4500,2000,ref_ref,ckx
S 3000,1500,3400,1500,200,*,RIGHT,ALU1
S 3000,3000,3900,3000,200,*,RIGHT,ALU1
S 3000,1500,3000,3000,100,*,DOWN,ALU1
S 3000,2000,3000,2000,200,nckx,LEFT,CALU3
S 4400,2500,4400,3500,100,*,DOWN,ALU1
S 3700,3500,3700,4000,100,*,DOWN,ALU1
S 3700,3500,4400,3500,100,*,RIGHT,ALU1
S 300,3300,300,4600,300,*,UP,PDIF
S 5100,2600,5100,4900,100,*,DOWN,PTRANS
S 6300,2600,6300,4900,100,*,DOWN,PTRANS
S 6600,2800,6600,4700,300,*,DOWN,PDIF
S 0,4000,7000,4000,2600,*,RIGHT,NWELL
S 2400,3100,2400,4400,100,*,UP,PTRANS
S 1900,3100,1900,4400,100,*,UP,PTRANS
S 1100,3100,1100,4400,100,*,UP,PTRANS
S 5700,2600,5700,4900,100,*,DOWN,PTRANS
S 6000,2800,6000,4700,300,*,DOWN,PDIF
S 4700,2600,4700,4900,100,*,DOWN,PTRANS
S 5300,2800,5300,4700,300,*,DOWN,PDIF
S 4400,2800,4400,4700,300,*,DOWN,PDIF
S 3700,3800,3700,4700,300,*,DOWN,PDIF
S 2700,3300,2700,4700,300,*,UP,PDIF
S 3000,3600,3000,4900,100,*,DOWN,PTRANS
S 3400,3600,3400,4900,100,*,DOWN,PTRANS
S 600,3100,600,4400,100,*,UP,PTRANS
S 1500,3300,1500,4200,500,*,UP,PDIF
S 4700,100,4700,1400,100,*,UP,NTRANS
S 6300,100,6300,1400,100,*,UP,NTRANS
S 1900,600,1900,1400,100,*,DOWN,NTRANS
S 2400,600,2400,1400,100,*,DOWN,NTRANS
S 1100,600,1100,1400,100,*,DOWN,NTRANS
S 3400,600,3400,1400,100,*,UP,NTRANS
S 3000,600,3000,1400,100,*,UP,NTRANS
S 600,600,600,1400,100,*,DOWN,NTRANS
S 5700,100,5700,1400,100,*,UP,NTRANS
S 5100,100,5100,1400,100,*,UP,NTRANS
S 4400,300,4400,1200,300,*,DOWN,NDIF
S 300,400,300,1200,300,*,DOWN,NDIF
S 300,300,300,1200,300,*,DOWN,NDIF
S 5400,300,5400,1200,300,*,DOWN,NDIF
S 6000,300,6000,1200,300,*,DOWN,NDIF
S 2700,400,2700,1200,300,*,DOWN,NDIF
S 6600,300,6600,1200,300,*,DOWN,NDIF
S 1500,800,1500,1200,500,*,UP,NDIF
S 3700,800,3700,1200,300,*,DOWN,NDIF
S 5700,1400,5700,2600,100,*,DOWN,POLY
S 4700,2500,4700,2600,100,*,DOWN,POLY
S 5100,1400,5100,2600,100,*,DOWN,POLY
S 5500,2000,6300,2000,100,*,RIGHT,POLY
S 6300,1400,6300,2600,100,*,DOWN,POLY
S 4300,1400,4700,1400,100,*,LEFT,POLY
S 3900,2500,4700,2500,100,*,LEFT,POLY
S 3900,2500,3900,3000,100,*,UP,POLY
S 4300,1400,4300,2000,100,*,DOWN,POLY
S 3400,2000,4300,2000,100,*,RIGHT,POLY
S 1500,2000,3000,2000,100,*,RIGHT,POLY
S 1100,1400,1100,2500,100,*,UP,POLY
S 1100,2500,1900,2500,100,*,RIGHT,POLY
S 3400,2000,3400,3600,100,*,DOWN,POLY
S 3000,900,3000,3600,100,*,DOWN,POLY
S 1900,2500,1900,3100,100,*,DOWN,POLY
S 600,1400,600,3100,100,*,DOWN,POLY
S 2500,1500,2500,3000,100,*,UP,ALU1
S 2700,500,2700,1000,200,*,UP,ALU1
S 1000,4000,2000,4000,100,*,LEFT,ALU1
S 2000,1500,2000,4000,100,*,UP,ALU1
S 1500,1000,1500,3500,100,*,UP,ALU1
S 6600,500,6600,1000,200,*,DOWN,ALU1
S 6600,3000,6600,4500,200,*,DOWN,ALU1
S 4400,4000,4900,4000,100,*,RIGHT,ALU1
S 3700,1000,3900,1000,200,*,RIGHT,ALU1
S 3900,1500,5000,1500,100,*,RIGHT,ALU1
S 3900,1000,3900,2500,100,*,DOWN,ALU1
S 3900,2500,4400,2500,100,*,RIGHT,ALU1
S 4900,2500,4900,4000,100,*,DOWN,ALU1
S 1000,3000,1000,4000,100,*,DOWN,ALU1
S 2700,3500,2700,4500,200,*,DOWN,ALU1
S 5400,3000,5400,4500,200,*,DOWN,ALU1
S 4900,2500,5500,2500,100,*,RIGHT,ALU1
S 4400,1000,5500,1000,100,*,LEFT,ALU1
S 5500,1000,5500,2500,100,*,DOWN,ALU1
S 5000,1500,5000,1900,100,*,UP,ALU1
S 1000,2000,4500,2000,200,*,RIGHT,TALU2
S 0,300,7000,300,600,vss,RIGHT,CALU1
S 0,4700,7000,4700,600,vdd,RIGHT,CALU1
S 500,1000,500,4000,200,i,UP,CALU1
S 6000,1000,6000,4000,200,q,DOWN,CALU1
S 2500,2500,6000,2500,200,q,RIGHT,CALU2
S 1000,2000,1000,2000,200,wenx,LEFT,CALU3
S 2000,2000,2000,2000,200,nwenx,LEFT,CALU3
S 4500,2000,4500,2000,200,ckx,LEFT,CALU3
V 3000,2000,CONT_VIA,*
V 3000,2000,CONT_VIA2,*
V 5400,4000,CONT_DIF_P,*
V 5400,4500,CONT_DIF_P,*
V 6600,4500,CONT_DIF_P,*
V 6600,3000,CONT_DIF_P,*
V 5400,3500,CONT_DIF_P,*
V 900,4700,CONT_BODY_N,*
V 2100,4700,CONT_BODY_N,*
V 1500,4700,CONT_BODY_N,*
V 5400,3000,CONT_DIF_P,*
V 1500,3500,CONT_DIF_P,*
V 2700,4500,CONT_DIF_P,*
V 4400,4000,CONT_DIF_P,*
V 6600,3500,CONT_DIF_P,*
V 3700,4000,CONT_DIF_P,*
V 2700,3500,CONT_DIF_P,*
V 300,4500,CONT_DIF_P,*
V 2700,4000,CONT_DIF_P,*
V 6000,3000,CONT_DIF_P,*
V 6600,4000,CONT_DIF_P,*
V 2700,500,CONT_DIF_N,*
V 4400,1000,CONT_DIF_N,*
V 6000,1000,CONT_DIF_N,*
V 5400,500,CONT_DIF_N,*
V 6600,500,CONT_DIF_N,*
V 6600,1000,CONT_DIF_N,*
V 300,500,CONT_DIF_N,*
V 2700,1000,CONT_DIF_N,*
V 3700,1000,CONT_DIF_N,*
V 300,500,CONT_DIF_N,*
V 1500,1000,CONT_DIF_N,*
V 1500,300,CONT_BODY_P,*
V 900,300,CONT_BODY_P,*
V 2100,300,CONT_BODY_P,*
V 3700,300,CONT_BODY_P,*
V 500,3000,CONT_POLY,*
V 500,1500,CONT_POLY,*
V 3900,3000,CONT_POLY,*
V 5000,2000,CONT_POLY,*
V 1500,2000,CONT_POLY,*
V 3400,1500,CONT_POLY,*
V 5500,2000,CONT_POLY,*
V 2000,1500,CONT_POLY,*
V 2500,1500,CONT_POLY,*
V 2500,3000,CONT_POLY,*
V 1000,3000,CONT_POLY,*
V 1000,2000,CONT_POLY,*
V 4400,2000,CONT_POLY,*
V 4500,2000,CONT_VIA,*
V 6000,2500,CONT_VIA,*
V 2000,2000,CONT_VIA,*
V 1000,2000,CONT_VIA,*
V 2500,2500,CONT_VIA,*
V 2000,2000,CONT_VIA2,*
V 1000,2000,CONT_VIA2,*
V 4500,2000,CONT_VIA2,*
EOF

36
alliance/src/cells/src/dp_sxlib/dp_dff_x4.vbe Normal file
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@ -0,0 +1,36 @@
ENTITY dp_dff_x4 IS
PORT (
ckx : in BIT;
nckx : in BIT;
wenx : in BIT;
nwenx : in BIT;
i : in BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_dff_x4;
ARCHITECTURE vbe OF dp_dff_x4 IS
SIGNAL ff : REG_BIT REGISTER;
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on dp_dff_x4"
SEVERITY WARNING;
ASSERT (ckx xor nckx)
REPORT "wrong values for ckx and nckx in dp_dff_x4"
SEVERITY WARNING;
ASSERT (wenx xor nwenx)
REPORT "wrong values for wenx and nwenx in dp_dff_x4"
SEVERITY WARNING;
label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1')
BEGIN
ff <= GUARDED ((wenx and i) or (nwenx and ff));
END BLOCK label0;
q <= ff;
END;

252
alliance/src/cells/src/dp_sxlib/dp_dff_x4_buf.ap Normal file
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@ -0,0 +1,252 @@
V ALLIANCE : 6
H dp_dff_x4_buf,P,14/11/2000,10
A 0,0,700,1000
R 100,400,ref_ref,wenx
R 200,400,ref_ref,nwenx
R 350,400,ref_ref,nckx
R 450,400,ref_ref,ckx
S 100,600,450,600,20,*,RIGHT,TALU2
S 100,400,450,400,20,*,LEFT,TALU2
S 100,150,450,150,20,*,RIGHT,TALU2
S 450,150,460,150,20,*,RIGHT,ALU1
S 150,220,240,220,30,*,RIGHT,POLY
S 100,220,160,220,20,*,RIGHT,ALU1
S 60,220,120,220,30,*,RIGHT,POLY
S 90,660,90,900,20,*,UP,ALU1
S 210,740,210,790,20,*,DOWN,ALU1
S 60,660,120,660,30,*,RIGHT,POLY
S 0,500,700,500,460,*,RIGHT,NWELL
S 70,770,480,770,80,*,RIGHT,NWELL
S 90,340,90,630,30,*,UP,PDIF
S 120,320,120,650,10,*,UP,PTRANS
S 270,340,270,630,30,*,DOWN,PDIF
S 30,340,30,630,30,*,UP,PDIF
S 210,730,210,800,30,*,UP,PDIF
S 60,320,60,650,10,*,UP,PTRANS
S 180,710,180,820,10,*,DOWN,PTRANS
S 160,730,160,800,30,*,UP,PDIF
S 120,710,120,820,10,*,DOWN,PTRANS
S 90,730,90,800,30,*,UP,PDIF
S 180,320,180,650,10,*,UP,PTRANS
S 210,340,210,630,30,*,UP,PDIF
S 240,320,240,650,10,*,DOWN,PTRANS
S 310,320,310,650,10,*,UP,PTRANS
S 400,340,400,630,30,*,UP,PDIF
S 340,340,340,630,30,*,UP,PDIF
S 370,320,370,650,10,*,UP,PTRANS
S 520,340,520,630,30,*,DOWN,PDIF
S 490,320,490,650,10,*,DOWN,PTRANS
S 460,340,460,630,30,*,UP,PDIF
S 430,320,430,650,10,*,UP,PTRANS
S 340,730,340,800,30,*,UP,PDIF
S 460,730,460,800,30,*,UP,PDIF
S 370,710,370,820,10,*,DOWN,PTRANS
S 410,730,410,800,30,*,UP,PDIF
S 430,710,430,820,10,*,DOWN,PTRANS
S 150,340,150,630,30,*,UP,PDIF
S 60,10,60,190,10,*,UP,NTRANS
S 120,10,120,190,10,*,DOWN,NTRANS
S 150,30,150,170,30,*,UP,NDIF
S 180,10,180,190,10,*,DOWN,NTRANS
S 210,30,210,170,30,*,UP,NDIF
S 240,10,240,190,10,*,DOWN,NTRANS
S 30,30,30,170,30,*,UP,NDIF
S 270,30,270,170,30,*,UP,NDIF
S 90,30,90,170,30,*,UP,NDIF
S 150,890,150,960,30,*,UP,NDIF
S 90,890,90,960,30,*,UP,NDIF
S 120,870,120,980,10,*,UP,NTRANS
S 310,10,310,190,10,*,UP,NTRANS
S 370,10,370,190,10,*,DOWN,NTRANS
S 520,30,520,170,30,*,UP,NDIF
S 430,10,430,190,10,*,DOWN,NTRANS
S 400,30,400,170,30,*,UP,NDIF
S 340,30,340,170,30,*,UP,NDIF
S 490,10,490,190,10,*,DOWN,NTRANS
S 460,30,460,170,30,*,UP,NDIF
S 340,890,340,960,30,*,UP,NDIF
S 400,890,400,960,30,*,UP,NDIF
S 370,870,370,980,10,*,UP,NTRANS
S 490,190,490,320,10,*,UP,POLY
S 120,820,120,870,10,*,DOWN,POLY
S 430,190,430,320,10,*,DOWN,POLY
S 60,190,60,320,10,*,DOWN,POLY
S 370,190,370,320,10,*,UP,POLY
S 120,190,120,320,10,*,UP,POLY
S 370,820,370,870,10,*,DOWN,POLY
S 370,850,430,850,30,*,RIGHT,POLY
S 430,820,430,860,10,*,DOWN,POLY
S 180,820,180,860,10,*,DOWN,POLY
S 120,850,180,850,30,*,RIGHT,POLY
S 310,190,310,320,10,*,DOWN,POLY
S 180,190,180,320,10,*,DOWN,POLY
S 240,190,240,320,10,*,UP,POLY
S 430,660,490,660,30,*,RIGHT,POLY
S 430,220,490,220,30,*,RIGHT,POLY
S 310,220,390,220,30,*,RIGHT,POLY
S 400,280,400,740,20,*,UP,ALU1
S 30,50,30,150,20,*,UP,ALU1
S 210,100,210,400,20,*,UP,ALU1
S 30,350,30,680,20,*,UP,ALU1
S 270,280,270,680,20,*,UP,ALU1
S 270,50,270,150,20,*,UP,ALU1
S 150,900,150,940,20,*,UP,ALU1
S 90,790,210,790,20,*,RIGHT,ALU1
S 340,100,340,400,20,*,UP,ALU1
S 150,50,150,150,20,*,UP,ALU1
S 150,280,150,740,20,*,UP,ALU1
S 30,900,30,970,20,*,DOWN,ALU1
S 520,50,520,150,20,*,UP,ALU1
S 400,50,400,150,20,*,UP,ALU1
S 520,280,520,680,20,*,UP,ALU1
S 460,100,460,400,20,*,UP,ALU1
S 90,100,90,400,20,*,UP,ALU1
S 460,660,460,790,20,*,DOWN,ALU1
S 340,740,340,900,20,*,UP,ALU1
S 520,900,520,970,20,*,UP,ALU1
S 400,900,400,940,20,*,UP,ALU1
S 340,790,460,790,20,*,RIGHT,ALU1
S 270,900,270,970,20,*,UP,ALU1
S 390,220,460,220,20,*,RIGHT,ALU1
S 600,50,600,150,20,*,UP,ALU1
S 0,970,700,970,60,vss,RIGHT,CALU1
S 0,30,700,30,60,vss,RIGHT,CALU1
S 0,530,700,530,60,vdd,RIGHT,CALU1
S 0,470,700,470,60,vdd,RIGHT,CALU1
S 150,850,150,850,10,wen,LEFT,CALU1
S 400,850,400,850,10,ck,LEFT,CALU1
S 100,150,100,600,20,wenx,DOWN,CALU3
S 200,150,200,600,20,nwenx,DOWN,CALU3
S 350,150,350,600,20,nckx,DOWN,CALU3
S 450,150,450,600,20,ckx,DOWN,CALU3
S 200,150,210,150,20,*,RIGHT,ALU1
V 450,150,CONT_VIA,*
V 450,150,CONT_VIA2,*
V 160,220,CONT_POLY,*
V 90,660,CONT_POLY,*
V 90,790,CONT_DIF_P,*
V 30,550,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,600,CONT_DIF_P,*
V 270,290,CONT_BODY_N,*
V 30,290,CONT_BODY_N,*
V 150,290,CONT_BODY_N,*
V 90,740,CONT_DIF_P,*
V 150,740,CONT_DIF_P,*
V 150,500,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 150,550,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,500,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 270,600,CONT_DIF_P,*
V 270,550,CONT_DIF_P,*
V 270,500,CONT_DIF_P,*
V 270,450,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 270,400,CONT_DIF_P,*
V 270,680,CONT_BODY_N,*
V 150,680,CONT_BODY_N,*
V 210,740,CONT_DIF_P,*
V 210,790,CONT_DIF_P,*
V 210,600,CONT_DIF_P,*
V 90,600,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 400,550,CONT_DIF_P,*
V 30,680,CONT_BODY_N,*
V 520,600,CONT_DIF_P,*
V 400,290,CONT_BODY_N,*
V 520,290,CONT_BODY_N,*
V 400,350,CONT_DIF_P,*
V 400,450,CONT_DIF_P,*
V 520,680,CONT_BODY_N,*
V 400,400,CONT_DIF_P,*
V 400,500,CONT_DIF_P,*
V 520,400,CONT_DIF_P,*
V 520,350,CONT_DIF_P,*
V 520,450,CONT_DIF_P,*
V 520,500,CONT_DIF_P,*
V 520,550,CONT_DIF_P,*
V 460,400,CONT_DIF_P,*
V 460,350,CONT_DIF_P,*
V 340,350,CONT_DIF_P,*
V 340,400,CONT_DIF_P,*
V 340,600,CONT_DIF_P,*
V 400,600,CONT_DIF_P,*
V 460,600,CONT_DIF_P,*
V 400,680,CONT_BODY_N,*
V 340,790,CONT_DIF_P,*
V 400,740,CONT_DIF_P,*
V 340,740,CONT_DIF_P,*
V 460,790,CONT_DIF_P,*
V 460,740,CONT_DIF_P,*
V 150,600,CONT_DIF_P,*
V 30,50,CONT_DIF_N,*
V 210,150,CONT_DIF_N,*
V 270,150,CONT_DIF_N,*
V 270,50,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 90,900,CONT_DIF_N,*
V 150,150,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 30,150,CONT_DIF_N,*
V 150,900,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 90,150,CONT_DIF_N,*
V 520,100,CONT_DIF_N,*
V 460,100,CONT_DIF_N,*
V 520,50,CONT_DIF_N,*
V 150,950,CONT_DIF_N,*
V 400,50,CONT_DIF_N,*
V 340,150,CONT_DIF_N,*
V 400,150,CONT_DIF_N,*
V 340,100,CONT_DIF_N,*
V 520,150,CONT_DIF_N,*
V 460,150,CONT_DIF_N,*
V 400,100,CONT_DIF_N,*
V 400,900,CONT_DIF_N,*
V 400,950,CONT_DIF_N,*
V 340,900,CONT_DIF_N,*
V 520,970,CONT_BODY_P,*
V 270,970,CONT_BODY_P,*
V 30,900,CONT_BODY_P,*
V 270,900,CONT_BODY_P,*
V 520,900,CONT_BODY_P,*
V 30,970,CONT_BODY_P,*
V 400,850,CONT_POLY,*
V 150,850,CONT_POLY,*
V 460,660,CONT_POLY,*
V 390,220,CONT_POLY,*
V 200,400,CONT_VIA,*
V 200,600,CONT_VIA,*
V 100,600,CONT_VIA,*
V 100,400,CONT_VIA,*
V 100,150,CONT_VIA,*
V 350,400,CONT_VIA,*
V 350,600,CONT_VIA,*
V 350,150,CONT_VIA,*
V 450,600,CONT_VIA,*
V 450,400,CONT_VIA,*
V 450,600,CONT_VIA2,*
V 350,150,CONT_VIA2,*
V 350,600,CONT_VIA2,*
V 100,150,CONT_VIA2,*
V 100,400,CONT_VIA2,*
V 200,400,CONT_VIA2,*
V 450,400,CONT_VIA2,*
V 350,400,CONT_VIA2,*
V 100,600,CONT_VIA2,*
V 200,600,CONT_VIA2,*
V 600,50,CONT_BODY_P,*
V 600,150,CONT_BODY_P,*
V 200,150,CONT_VIA2,*
V 200,150,CONT_VIA,*
EOF

25
alliance/src/cells/src/dp_sxlib/dp_dff_x4_buf.vbe Normal file
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@ -0,0 +1,25 @@
ENTITY dp_dff_x4_buf IS
PORT (
ck : in BIT;
wen : in BIT;
ckx : out BIT;
nckx : out BIT;
wenx : out BIT;
nwenx : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_dff_x4_buf;
ARCHITECTURE vbe OF dp_dff_x4_buf IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on dp_dff_x4_buf"
SEVERITY WARNING;
ckx <= ck;
nckx <= not ck;
wenx <= wen;
nwenx <= not wen;
END;

109
alliance/src/cells/src/dp_sxlib/dp_mux_x2.ap Normal file
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@ -0,0 +1,109 @@
V ALLIANCE : 6
H dp_mux_x2,P,10/11/2000,100
A 0,0,4000,5000
R 500,4000,ref_ref,q_40
R 500,3500,ref_ref,q_35
R 500,3000,ref_ref,q_30
R 500,2500,ref_ref,q_25
R 500,1500,ref_ref,q_15
R 500,1000,ref_ref,q_10
R 500,2000,ref_ref,q_20
R 1500,2500,ref_ref,i1_25
R 1500,2000,ref_ref,i1_20
R 1500,1500,ref_ref,i1_15
R 3500,1500,ref_ref,i0_15
R 3500,2000,ref_ref,i0_20
R 3500,3500,ref_ref,i0_35
R 3500,3000,ref_ref,i0_30
R 3500,1000,ref_ref,i0_10
R 1500,1000,ref_ref,i1_10
R 1500,4000,ref_ref,i1_40
R 1500,3500,ref_ref,i1_35
R 1500,3000,ref_ref,i1_30
R 3500,2500,ref_ref,i0_25
R 3000,2000,ref_ref,sel0
R 2000,2000,ref_ref,sel1
S 3300,3000,3500,3000,100,*,RIGHT,POLY
S 3300,3000,3300,3100,100,*,DOWN,POLY
S 2900,2000,2900,3100,100,*,DOWN,POLY
S 3600,3300,3600,4200,300,*,UP,PDIF
S 2900,3100,2900,4400,100,*,UP,PTRANS
S 3300,3100,3300,4400,100,*,UP,PTRANS
S 2500,3500,2600,3500,100,*,LEFT,ALU1
S 3000,1500,3000,4000,100,*,UP,ALU1
S 2000,4000,3000,4000,100,*,RIGHT,ALU1
S 2500,3300,2500,4200,500,*,UP,PDIF
S 1700,2900,1700,3100,100,*,DOWN,POLY
S 1700,3100,1700,4400,100,*,UP,PTRANS
S 2100,3100,2100,4400,100,*,UP,PTRANS
S 1500,1000,1500,4000,200,i1,UP,CALU1
S 2000,2000,2000,2000,200,sel1,LEFT,CALU3
S 3000,2000,3000,2000,200,sel0,LEFT,CALU3
S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
S 0,300,4000,300,600,vss,RIGHT,CALU1
S 1000,500,1000,1700,200,*,UP,ALU1
S 1000,3000,1000,4500,200,*,DOWN,ALU1
S 2100,900,2100,2000,100,*,UP,POLY
S 1400,1400,1700,1400,100,*,RIGHT,POLY
S 700,1400,700,2600,100,*,UP,POLY
S 1700,900,1700,1400,100,*,UP,POLY
S 2100,2000,2900,2000,100,*,RIGHT,POLY
S 1200,300,1200,1200,700,*,UP,NDIF
S 700,100,700,1400,100,*,DOWN,NTRANS
S 400,300,400,1200,300,*,UP,NDIF
S 1700,100,1700,900,100,*,DOWN,NTRANS
S 2100,100,2100,900,100,*,DOWN,NTRANS
S 3600,300,3600,700,300,*,DOWN,NDIF
S 2900,100,2900,900,100,*,DOWN,NTRANS
S 3300,100,3300,900,100,*,DOWN,NTRANS
S 2500,300,2500,700,500,*,UP,NDIF
S 400,2800,400,4700,300,*,DOWN,PDIF
S 1000,2800,1000,3300,300,*,UP,PDIF
S 700,2600,700,4900,100,*,UP,PTRANS
S 2500,300,2500,1100,300,*,UP,NDIF
S 3300,900,3500,900,100,*,LEFT,POLY
S 2900,900,2900,1600,100,*,DOWN,POLY
S 2000,2000,3000,2000,200,*,RIGHT,TALU2
S 0,4000,4000,4000,2600,*,RIGHT,NWELL
S 500,1000,500,4000,200,q,UP,CALU1
S 700,2400,2500,2400,100,*,RIGHT,POLY
S 1500,2900,1700,2900,100,*,LEFT,POLY
S 1200,3200,1200,4700,700,*,DOWN,PDIF
S 3500,1000,3500,3500,200,i0,UP,CALU1
S 3600,4000,3600,4700,200,*,DOWN,ALU1
S 2500,1000,2500,2500,100,*,UP,ALU1
S 2000,3000,2100,3000,100,*,RIGHT,ALU1
S 2100,3000,2100,3200,100,*,DOWN,POLY
S 2000,3000,2000,4000,100,*,UP,ALU1
S 2500,2500,2600,2500,100,*,RIGHT,ALU1
S 2600,2500,2600,3500,100,*,UP,ALU1
V 2000,4700,CONT_BODY_N,*
V 3500,3000,CONT_POLY,*
V 3700,4700,CONT_BODY_N,*
V 400,4000,CONT_DIF_P,*
V 400,3500,CONT_DIF_P,*
V 400,3000,CONT_DIF_P,*
V 400,1000,CONT_DIF_N,*
V 3000,2000,CONT_VIA2,*
V 2000,2000,CONT_VIA2,*
V 2000,2000,CONT_VIA,*
V 3000,2000,CONT_VIA,*
V 1500,1500,CONT_POLY,*
V 2000,2000,CONT_POLY,*
V 1000,1700,CONT_BODY_P,*
V 3600,500,CONT_DIF_N,*
V 1000,1000,CONT_DIF_N,*
V 1000,500,CONT_DIF_N,*
V 1000,4000,CONT_DIF_P,*
V 1000,3500,CONT_DIF_P,*
V 1000,3000,CONT_DIF_P,*
V 1000,4500,CONT_DIF_P,*
V 2500,1000,CONT_DIF_N,*
V 3000,1500,CONT_POLY,*
V 3500,1000,CONT_POLY,*
V 2500,2400,CONT_POLY,*
V 1500,2900,CONT_POLY,*
V 3600,4000,CONT_DIF_P,*
V 2500,3500,CONT_DIF_P,*
V 2100,3000,CONT_POLY,*
EOF

26
alliance/src/cells/src/dp_sxlib/dp_mux_x2.vbe Normal file
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@ -0,0 +1,26 @@
ENTITY dp_mux_x2 IS
PORT (
sel0 : in BIT;
sel1 : in BIT;
i0 : in BIT;
i1 : in BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_mux_x2;
ARCHITECTURE vbe OF dp_mux_x2 IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_mux_x2"
SEVERITY WARNING;
ASSERT (sel0 xor sel1)
REPORT "wrong control signals on dp_mux_x2"
SEVERITY WARNING;
q <= (sel0 and i0) or (sel1 and i1);
END;

141
alliance/src/cells/src/dp_sxlib/dp_mux_x2_buf.ap Normal file
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@ -0,0 +1,141 @@
V ALLIANCE : 6
H dp_mux_x2_buf,P,14/11/2000,10
A 0,0,400,1000
R 200,400,ref_ref,sel1
R 300,400,ref_ref,sel0
S 200,600,300,600,20,*,RIGHT,TALU2
S 200,400,300,400,20,*,RIGHT,TALU2
S 200,150,300,150,20,*,RIGHT,TALU2
S 250,850,250,850,10,sel,LEFT,CALU1
S 60,30,60,150,20,*,DOWN,ALU1
S 370,50,370,150,20,*,UP,ALU1
S 190,100,190,400,20,*,UP,ALU1
S 190,660,190,900,20,*,UP,ALU1
S 310,100,310,400,20,*,UP,ALU1
S 190,220,260,220,20,*,RIGHT,ALU1
S 370,900,370,970,20,*,UP,ALU1
S 310,740,310,790,20,*,DOWN,ALU1
S 190,790,310,790,20,*,RIGHT,ALU1
S 250,900,250,940,20,*,UP,ALU1
S 130,350,130,680,20,*,UP,ALU1
S 370,280,370,680,20,*,UP,ALU1
S 130,50,130,150,20,*,UP,ALU1
S 250,50,250,150,20,*,UP,ALU1
S 250,280,250,740,20,*,UP,ALU1
S 130,900,130,970,20,*,DOWN,ALU1
S 250,220,340,220,30,*,RIGHT,POLY
S 160,220,220,220,30,*,RIGHT,POLY
S 280,820,280,860,10,*,DOWN,POLY
S 220,850,280,850,30,*,RIGHT,POLY
S 160,660,220,660,30,*,RIGHT,POLY
S 280,190,280,320,10,*,DOWN,POLY
S 340,190,340,320,10,*,UP,POLY
S 220,190,220,320,10,*,UP,POLY
S 160,190,160,320,10,*,DOWN,POLY
S 220,820,220,870,10,*,DOWN,POLY
S 130,30,130,170,30,*,UP,NDIF
S 370,30,370,170,30,*,UP,NDIF
S 220,10,220,190,10,*,DOWN,NTRANS
S 160,10,160,190,10,*,UP,NTRANS
S 250,30,250,170,30,*,UP,NDIF
S 190,30,190,170,30,*,UP,NDIF
S 250,890,250,960,30,*,UP,NDIF
S 190,890,190,960,30,*,UP,NDIF
S 280,10,280,190,10,*,DOWN,NTRANS
S 310,30,310,170,30,*,UP,NDIF
S 340,10,340,190,10,*,DOWN,NTRANS
S 220,870,220,980,10,*,UP,NTRANS
S 340,320,340,650,10,*,DOWN,PTRANS
S 370,340,370,630,30,*,DOWN,PDIF
S 220,320,220,650,10,*,UP,PTRANS
S 190,340,190,630,30,*,UP,PDIF
S 250,340,250,630,30,*,UP,PDIF
S 160,320,160,650,10,*,UP,PTRANS
S 130,340,130,630,30,*,UP,PDIF
S 310,730,310,800,30,*,UP,PDIF
S 280,710,280,820,10,*,DOWN,PTRANS
S 260,730,260,800,30,*,UP,PDIF
S 220,710,220,820,10,*,DOWN,PTRANS
S 190,730,190,800,30,*,UP,PDIF
S 280,320,280,650,10,*,UP,PTRANS
S 310,340,310,630,30,*,UP,PDIF
S 0,500,400,500,460,*,RIGHT,NWELL
S 200,150,200,600,20,sel1,UP,CALU3
S 300,150,300,600,20,sel0,DOWN,CALU3
S 0,30,400,30,60,vss,RIGHT,CALU1
S 0,970,400,970,60,vss,RIGHT,CALU1
S 0,530,400,530,60,vdd,RIGHT,CALU1
S 0,470,400,470,60,vdd,RIGHT,CALU1
V 300,150,CONT_VIA,*
V 300,150,CONT_VIA2,*
V 60,150,CONT_BODY_P,*
V 60,30,CONT_BODY_P,*
V 200,150,CONT_VIA2,*
V 300,600,CONT_VIA2,*
V 200,600,CONT_VIA2,*
V 200,400,CONT_VIA2,*
V 300,400,CONT_VIA2,*
V 200,150,CONT_VIA,*
V 300,400,CONT_VIA,*
V 300,600,CONT_VIA,*
V 200,600,CONT_VIA,*
V 200,400,CONT_VIA,*
V 190,660,CONT_POLY,*
V 260,220,CONT_POLY,*
V 250,850,CONT_POLY,*
V 130,900,CONT_BODY_P,*
V 370,900,CONT_BODY_P,*
V 130,970,CONT_BODY_P,*
V 370,970,CONT_BODY_P,*
V 130,150,CONT_DIF_N,*
V 130,50,CONT_DIF_N,*
V 310,150,CONT_DIF_N,*
V 370,150,CONT_DIF_N,*
V 370,50,CONT_DIF_N,*
V 310,100,CONT_DIF_N,*
V 370,100,CONT_DIF_N,*
V 250,900,CONT_DIF_N,*
V 190,100,CONT_DIF_N,*
V 190,150,CONT_DIF_N,*
V 190,900,CONT_DIF_N,*
V 250,150,CONT_DIF_N,*
V 250,50,CONT_DIF_N,*
V 250,100,CONT_DIF_N,*
V 130,100,CONT_DIF_N,*
V 250,950,CONT_DIF_N,*
V 190,790,CONT_DIF_P,*
V 130,550,CONT_DIF_P,*
V 130,350,CONT_DIF_P,*
V 130,600,CONT_DIF_P,*
V 370,290,CONT_BODY_N,*
V 130,290,CONT_BODY_N,*
V 250,290,CONT_BODY_N,*
V 190,740,CONT_DIF_P,*
V 250,740,CONT_DIF_P,*
V 250,500,CONT_DIF_P,*
V 250,400,CONT_DIF_P,*
V 250,550,CONT_DIF_P,*
V 250,450,CONT_DIF_P,*
V 250,350,CONT_DIF_P,*
V 130,400,CONT_DIF_P,*
V 130,450,CONT_DIF_P,*
V 130,500,CONT_DIF_P,*
V 310,350,CONT_DIF_P,*
V 310,400,CONT_DIF_P,*
V 370,600,CONT_DIF_P,*
V 370,550,CONT_DIF_P,*
V 370,500,CONT_DIF_P,*
V 370,450,CONT_DIF_P,*
V 370,350,CONT_DIF_P,*
V 370,400,CONT_DIF_P,*
V 370,680,CONT_BODY_N,*
V 250,680,CONT_BODY_N,*
V 310,740,CONT_DIF_P,*
V 310,790,CONT_DIF_P,*
V 310,600,CONT_DIF_P,*
V 190,600,CONT_DIF_P,*
V 190,400,CONT_DIF_P,*
V 190,350,CONT_DIF_P,*
V 130,680,CONT_BODY_N,*
V 60,90,CONT_BODY_P,*
EOF

21
alliance/src/cells/src/dp_sxlib/dp_mux_x2_buf.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY dp_mux_x2_buf IS
PORT (
sel : in BIT;
sel0 : out BIT;
sel1 : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_mux_x2_buf;
ARCHITECTURE vbe OF dp_mux_x2_buf IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_mux_x2_buf"
SEVERITY WARNING;
sel1 <= sel;
sel0 <= not sel;
END;

124
alliance/src/cells/src/dp_sxlib/dp_mux_x4.ap Normal file
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@ -0,0 +1,124 @@
V ALLIANCE : 6
H dp_mux_x4,P,10/11/2000,100
A 0,0,4500,5000
R 3500,2000,ref_ref,sel0
R 2500,2000,ref_ref,sel1
R 1000,4000,ref_ref,q_40
R 1000,3500,ref_ref,q_35
R 1000,3000,ref_ref,q_30
R 1000,2500,ref_ref,q_25
R 1000,2000,ref_ref,q_20
R 1000,1500,ref_ref,q_15
R 1000,1000,ref_ref,q_10
R 4000,2500,ref_ref,i0_25
R 4000,3000,ref_ref,i0_30
R 4000,1000,ref_ref,i0_10
R 2000,1000,ref_ref,i1_10
R 4000,3500,ref_ref,i0_35
R 4000,2000,ref_ref,i0_20
R 4000,1500,ref_ref,i0_15
R 2000,1500,ref_ref,i1_15
R 2000,2000,ref_ref,i1_20
R 2000,2500,ref_ref,i1_25
R 2000,3000,ref_ref,i1_30
R 2000,3500,ref_ref,i1_35
R 2000,4000,ref_ref,i1_40
S 3800,3000,4000,3000,100,*,RIGHT,POLY
S 3800,3000,3800,3100,100,*,DOWN,POLY
S 3400,2000,3400,3100,100,*,DOWN,POLY
S 4100,3300,4100,4200,300,*,UP,PDIF
S 3800,3100,3800,4400,100,*,UP,PTRANS
S 3400,3100,3400,4400,100,*,UP,PTRANS
S 2000,2900,2200,2900,100,*,LEFT,POLY
S 4100,4000,4100,4700,200,*,UP,ALU1
S 1700,3200,1700,4700,700,*,DOWN,PDIF
S 4000,1000,4000,3500,200,i0,UP,CALU1
S 2500,4000,3500,4000,100,*,RIGHT,ALU1
S 300,500,300,1700,200,*,UP,ALU1
S 300,3000,300,4500,200,*,DOWN,ALU1
S 300,300,300,1200,300,*,UP,NDIF
S 600,100,600,1400,100,*,DOWN,NTRANS
S 900,300,900,1200,300,*,UP,NDIF
S 1200,100,1200,1400,100,*,DOWN,NTRANS
S 1700,300,1700,1200,700,*,UP,NDIF
S 1500,3000,1500,4500,200,*,DOWN,ALU1
S 1900,1400,2200,1400,100,*,RIGHT,POLY
S 3800,100,3800,900,100,*,DOWN,NTRANS
S 3400,100,3400,900,100,*,DOWN,NTRANS
S 1500,500,1500,1700,200,*,UP,ALU1
S 4100,300,4100,700,300,*,DOWN,NDIF
S 2600,100,2600,900,100,*,DOWN,NTRANS
S 2200,100,2200,900,100,*,DOWN,NTRANS
S 2600,900,2600,2000,100,*,UP,POLY
S 2200,900,2200,1400,100,*,UP,POLY
S 3000,300,3000,700,500,*,UP,NDIF
S 600,1400,600,2600,100,*,UP,POLY
S 1200,1400,1200,2600,100,*,UP,POLY
S 600,2600,600,4900,100,*,UP,PTRANS
S 1200,2600,1200,4900,100,*,UP,PTRANS
S 300,2800,300,4700,300,*,DOWN,PDIF
S 1500,2800,1500,3300,300,*,UP,PDIF
S 900,2800,900,4700,300,*,DOWN,PDIF
S 2600,2000,3400,2000,100,*,RIGHT,POLY
S 0,4000,4500,4000,2600,*,LEFT,NWELL
S 3000,300,3000,1100,300,*,UP,NDIF
S 2900,300,2900,1100,300,*,UP,NDIF
S 3800,900,4000,900,100,*,LEFT,POLY
S 3500,1500,3500,4000,100,*,UP,ALU1
S 3400,900,3400,1600,100,*,UP,POLY
S 2500,2000,3500,2000,200,*,RIGHT,TALU2
S 2500,2000,2500,2000,200,sel1,LEFT,CALU3
S 3500,2000,3500,2000,200,sel0,LEFT,CALU3
S 1000,1000,1000,4000,200,q,UP,CALU1
S 2000,1000,2000,4000,200,i1,UP,CALU1
S 0,300,4500,300,600,vss,RIGHT,CALU1
S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
S 600,2400,3000,2400,100,*,RIGHT,POLY
S 2200,3100,2200,4400,100,*,UP,PTRANS
S 2600,3100,2600,4400,100,*,UP,PTRANS
S 2200,2900,2200,3100,100,*,DOWN,POLY
S 2600,2900,2600,3200,100,*,DOWN,POLY
S 2500,3000,2500,4000,100,*,UP,ALU1
S 2500,3000,2600,3000,100,*,RIGHT,ALU1
S 3000,3300,3000,4200,500,*,UP,PDIF
S 3000,3500,3100,3500,100,*,LEFT,ALU1
S 3100,2500,3100,3500,100,*,UP,ALU1
S 3000,1000,3000,2500,100,*,UP,ALU1
S 3000,2500,3100,2500,100,*,RIGHT,ALU1
V 4000,3000,CONT_POLY,*
V 4200,4700,CONT_BODY_N,*
V 2500,4700,CONT_BODY_N,*
V 4100,4000,CONT_DIF_P,*
V 2000,2900,CONT_POLY,*
V 900,4000,CONT_DIF_P,*
V 900,3500,CONT_DIF_P,*
V 900,3000,CONT_DIF_P,*
V 900,1000,CONT_DIF_N,*
V 3000,3500,CONT_DIF_P,*
V 3500,2000,CONT_VIA,*
V 3500,2000,CONT_VIA2,*
V 2500,2000,CONT_POLY,*
V 2500,2000,CONT_VIA,*
V 2500,2000,CONT_VIA2,*
V 300,1000,CONT_DIF_N,*
V 300,500,CONT_DIF_N,*
V 300,1700,CONT_BODY_P,*
V 300,4000,CONT_DIF_P,*
V 300,4500,CONT_DIF_P,*
V 300,3000,CONT_DIF_P,*
V 300,3500,CONT_DIF_P,*
V 2000,1500,CONT_POLY,*
V 4100,500,CONT_DIF_N,*
V 1500,3500,CONT_DIF_P,*
V 1500,4000,CONT_DIF_P,*
V 1500,500,CONT_DIF_N,*
V 1500,4500,CONT_DIF_P,*
V 1500,1000,CONT_DIF_N,*
V 1500,3000,CONT_DIF_P,*
V 1500,1700,CONT_BODY_P,*
V 3000,1000,CONT_DIF_N,*
V 3500,1500,CONT_POLY,*
V 4000,1000,CONT_POLY,*
V 3000,2400,CONT_POLY,*
V 2600,3000,CONT_POLY,*
EOF

26
alliance/src/cells/src/dp_sxlib/dp_mux_x4.vbe Normal file
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@ -0,0 +1,26 @@
ENTITY dp_mux_x4 IS
PORT (
sel0 : in BIT;
sel1 : in BIT;
i0 : in BIT;
i1 : in BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_mux_x4;
ARCHITECTURE vbe OF dp_mux_x4 IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_mux_x4"
SEVERITY WARNING;
ASSERT (sel0 xor sel1)
REPORT "wrong control signals on dp_mux_x4"
SEVERITY WARNING;
q <= (sel0 and i0) or (sel1 and i1);
END;

141
alliance/src/cells/src/dp_sxlib/dp_mux_x4_buf.ap Normal file
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@ -0,0 +1,141 @@
V ALLIANCE : 6
H dp_mux_x4_buf,P,14/11/2000,10
A 0,0,450,1000
R 250,400,ref_ref,sel1
R 350,400,ref_ref,sel0
S 250,600,350,600,20,*,RIGHT,TALU2
S 250,400,350,400,20,*,LEFT,TALU2
S 250,150,350,150,20,*,RIGHT,TALU2
S 300,850,300,850,10,sel,LEFT,CALU1
S 250,150,250,600,20,sel1,UP,CALU3
S 350,150,350,600,20,sel0,DOWN,CALU3
S 0,530,450,530,60,vdd,RIGHT,CALU1
S 0,470,450,470,60,vdd,RIGHT,CALU1
S 0,30,450,30,60,vss,RIGHT,CALU1
S 0,970,450,970,60,vss,RIGHT,CALU1
S 0,500,450,500,460,*,RIGHT,NWELL
S 330,710,330,820,10,*,DOWN,PTRANS
S 310,730,310,800,30,*,UP,PDIF
S 270,710,270,820,10,*,DOWN,PTRANS
S 240,730,240,800,30,*,UP,PDIF
S 330,320,330,650,10,*,UP,PTRANS
S 360,340,360,630,30,*,UP,PDIF
S 390,320,390,650,10,*,DOWN,PTRANS
S 420,340,420,630,30,*,DOWN,PDIF
S 270,320,270,650,10,*,UP,PTRANS
S 240,340,240,630,30,*,UP,PDIF
S 300,340,300,630,30,*,UP,PDIF
S 210,320,210,650,10,*,UP,PTRANS
S 180,340,180,630,30,*,UP,PDIF
S 360,730,360,800,30,*,UP,PDIF
S 270,870,270,980,10,*,UP,NTRANS
S 300,890,300,960,30,*,UP,NDIF
S 240,890,240,960,30,*,UP,NDIF
S 330,10,330,190,10,*,DOWN,NTRANS
S 360,30,360,170,30,*,UP,NDIF
S 390,10,390,190,10,*,DOWN,NTRANS
S 180,30,180,170,30,*,UP,NDIF
S 420,30,420,170,30,*,UP,NDIF
S 270,10,270,190,10,*,DOWN,NTRANS
S 210,10,210,190,10,*,UP,NTRANS
S 300,30,300,170,30,*,UP,NDIF
S 240,30,240,170,30,*,UP,NDIF
S 210,190,210,320,10,*,DOWN,POLY
S 270,820,270,870,10,*,DOWN,POLY
S 300,220,390,220,30,*,RIGHT,POLY
S 210,220,270,220,30,*,RIGHT,POLY
S 330,820,330,860,10,*,DOWN,POLY
S 270,850,330,850,30,*,RIGHT,POLY
S 210,660,270,660,30,*,RIGHT,POLY
S 330,190,330,320,10,*,DOWN,POLY
S 390,190,390,320,10,*,UP,POLY
S 270,190,270,320,10,*,UP,POLY
S 300,900,300,940,20,*,UP,ALU1
S 180,350,180,680,20,*,UP,ALU1
S 420,280,420,680,20,*,UP,ALU1
S 180,50,180,150,20,*,UP,ALU1
S 300,50,300,150,20,*,UP,ALU1
S 300,280,300,740,20,*,UP,ALU1
S 180,900,180,970,20,*,DOWN,ALU1
S 420,50,420,150,20,*,UP,ALU1
S 240,100,240,400,20,*,UP,ALU1
S 240,660,240,900,20,*,UP,ALU1
S 360,100,360,400,20,*,UP,ALU1
S 240,220,310,220,20,*,RIGHT,ALU1
S 420,900,420,970,20,*,UP,ALU1
S 360,740,360,790,20,*,DOWN,ALU1
S 240,790,360,790,20,*,RIGHT,ALU1
S 70,30,70,150,20,*,DOWN,ALU1
V 180,680,CONT_BODY_N,*
V 420,680,CONT_BODY_N,*
V 300,680,CONT_BODY_N,*
V 360,740,CONT_DIF_P,*
V 360,790,CONT_DIF_P,*
V 360,600,CONT_DIF_P,*
V 240,600,CONT_DIF_P,*
V 240,400,CONT_DIF_P,*
V 240,350,CONT_DIF_P,*
V 360,350,CONT_DIF_P,*
V 360,400,CONT_DIF_P,*
V 420,600,CONT_DIF_P,*
V 420,550,CONT_DIF_P,*
V 420,500,CONT_DIF_P,*
V 420,450,CONT_DIF_P,*
V 420,350,CONT_DIF_P,*
V 420,400,CONT_DIF_P,*
V 300,500,CONT_DIF_P,*
V 300,400,CONT_DIF_P,*
V 300,550,CONT_DIF_P,*
V 300,450,CONT_DIF_P,*
V 300,350,CONT_DIF_P,*
V 180,400,CONT_DIF_P,*
V 180,450,CONT_DIF_P,*
V 180,500,CONT_DIF_P,*
V 180,550,CONT_DIF_P,*
V 180,350,CONT_DIF_P,*
V 180,600,CONT_DIF_P,*
V 420,290,CONT_BODY_N,*
V 180,290,CONT_BODY_N,*
V 300,290,CONT_BODY_N,*
V 240,740,CONT_DIF_P,*
V 300,740,CONT_DIF_P,*
V 240,790,CONT_DIF_P,*
V 300,950,CONT_DIF_N,*
V 300,900,CONT_DIF_N,*
V 240,100,CONT_DIF_N,*
V 240,150,CONT_DIF_N,*
V 240,900,CONT_DIF_N,*
V 300,150,CONT_DIF_N,*
V 300,50,CONT_DIF_N,*
V 300,100,CONT_DIF_N,*
V 180,100,CONT_DIF_N,*
V 180,150,CONT_DIF_N,*
V 180,50,CONT_DIF_N,*
V 360,150,CONT_DIF_N,*
V 420,150,CONT_DIF_N,*
V 420,50,CONT_DIF_N,*
V 360,100,CONT_DIF_N,*
V 420,100,CONT_DIF_N,*
V 180,900,CONT_BODY_P,*
V 420,900,CONT_BODY_P,*
V 180,970,CONT_BODY_P,*
V 420,970,CONT_BODY_P,*
V 240,660,CONT_POLY,*
V 310,220,CONT_POLY,*
V 300,850,CONT_POLY,*
V 250,400,CONT_VIA,*
V 250,150,CONT_VIA,*
V 350,400,CONT_VIA,*
V 350,600,CONT_VIA,*
V 250,600,CONT_VIA,*
V 350,400,CONT_VIA2,*
V 250,150,CONT_VIA2,*
V 350,600,CONT_VIA2,*
V 250,600,CONT_VIA2,*
V 250,400,CONT_VIA2,*
V 70,30,CONT_BODY_P,*
V 70,150,CONT_BODY_P,*
V 70,90,CONT_BODY_P,*
V 350,150,CONT_VIA2,*
V 350,150,CONT_VIA,*
EOF

21
alliance/src/cells/src/dp_sxlib/dp_mux_x4_buf.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY dp_mux_x4_buf IS
PORT (
sel : in BIT;
sel0 : out BIT;
sel1 : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_mux_x4_buf;
ARCHITECTURE vbe OF dp_mux_x4_buf IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_mux_x4_buf"
SEVERITY WARNING;
sel1 <= sel;
sel0 <= not sel;
END;

80
alliance/src/cells/src/dp_sxlib/dp_nmux_x1.ap Normal file
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@ -0,0 +1,80 @@
V ALLIANCE : 6
H dp_nmux_x1,P,15/11/2000,100
A 0,0,3000,5000
R 500,1500,ref_ref,i1_15
R 500,1000,ref_ref,i1_10
R 1500,1000,ref_ref,nq_10
R 1500,1500,ref_ref,nq_15
R 2500,1000,ref_ref,i0_10
R 2500,1500,ref_ref,i0_15
R 2500,2000,ref_ref,i0_20
R 500,2000,ref_ref,i1_20
R 500,2500,ref_ref,i1_25
R 500,3000,ref_ref,i1_30
R 500,3500,ref_ref,i1_35
R 500,4000,ref_ref,i1_40
R 2500,2500,ref_ref,i0_25
R 2500,4000,ref_ref,i0_40
R 2500,3500,ref_ref,i0_35
R 2500,3000,ref_ref,i0_30
R 1500,3500,ref_ref,nq_35
R 1500,3000,ref_ref,nq_30
R 1500,2500,ref_ref,nq_25
R 1500,2000,ref_ref,nq_20
R 1000,2000,ref_ref,sel1
R 2000,2000,ref_ref,sel0
S 2400,2600,2400,4400,100,*,UP,PTRANS
S 1500,2800,1500,4200,500,*,UP,PDIF
S 1900,2600,1900,4400,100,*,UP,PTRANS
S 1100,2600,1100,4400,100,*,UP,PTRANS
S 600,2600,600,4400,100,*,UP,PTRANS
S 2000,2000,2000,2000,200,sel0,LEFT,CALU3
S 1000,2000,1000,2000,200,sel1,LEFT,CALU3
S 600,1900,600,2600,100,*,UP,POLY
S 2400,1900,2400,2600,100,*,UP,POLY
S 300,400,300,1700,300,*,DOWN,NDIF
S 2700,400,2700,1700,300,*,DOWN,NDIF
S 1900,600,1900,1900,100,*,DOWN,NTRANS
S 1500,800,1500,1700,500,*,UP,NDIF
S 1100,600,1100,1900,100,*,DOWN,NTRANS
S 2400,600,2400,1900,100,*,DOWN,NTRANS
S 600,600,600,1900,100,*,DOWN,NTRANS
S 1500,2600,1900,2600,100,*,RIGHT,POLY
S 1500,2100,1500,2600,100,*,UP,POLY
S 900,2100,1500,2100,100,*,RIGHT,POLY
S 2000,2000,2000,4000,100,*,UP,ALU1
S 1000,4000,2000,4000,100,*,LEFT,ALU1
S 1000,2500,1000,4000,100,*,DOWN,ALU1
S 2700,2800,2700,4500,300,*,UP,PDIF
S 300,2800,300,4500,300,*,UP,PDIF
S 0,4000,3000,4000,2600,*,RIGHT,NWELL
S 1000,2000,2000,2000,200,*,RIGHT,TALU2
S 0,300,3000,300,600,vss,RIGHT,CALU1
S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
S 2500,1000,2500,4000,200,i0,UP,CALU1
S 500,1000,500,4000,200,i1,UP,CALU1
S 1500,1000,1500,3500,200,nq,UP,CALU1
V 1500,4700,CONT_BODY_N,*
V 2100,4700,CONT_BODY_N,*
V 900,4700,CONT_BODY_N,*
V 1500,1500,CONT_DIF_N,*
V 300,500,CONT_DIF_N,*
V 2700,500,CONT_DIF_N,*
V 1500,1000,CONT_DIF_N,*
V 1500,300,CONT_BODY_P,*
V 2000,2000,CONT_POLY,*
V 1000,2000,CONT_VIA2,*
V 1000,2000,CONT_VIA,*
V 2000,2000,CONT_VIA2,*
V 2000,2000,CONT_VIA,*
V 1000,2500,CONT_POLY,*
V 2700,4500,CONT_DIF_P,*
V 1500,3500,CONT_DIF_P,*
V 1500,3000,CONT_DIF_P,*
V 300,4500,CONT_DIF_P,*
V 1000,2000,CONT_POLY,*
V 2500,2000,CONT_POLY,*
V 500,2000,CONT_POLY,*
V 900,300,CONT_BODY_P,*
V 2100,300,CONT_BODY_P,*
EOF

26
alliance/src/cells/src/dp_sxlib/dp_nmux_x1.vbe Normal file
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@ -0,0 +1,26 @@
ENTITY dp_nmux_x1 IS
PORT (
sel0 : in BIT;
sel1 : in BIT;
i0 : in BIT;
i1 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_nmux_x1;
ARCHITECTURE vbe OF dp_nmux_x1 IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_nmux_x1"
SEVERITY WARNING;
ASSERT (sel0 xor sel1)
REPORT "wrong control signals on dp_nmux_x1"
SEVERITY WARNING;
nq <= not ((sel0 and i0) or (sel1 and i1));
END;

137
alliance/src/cells/src/dp_sxlib/dp_nmux_x1_buf.ap Normal file
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@ -0,0 +1,137 @@
V ALLIANCE : 6
H dp_nmux_x1_buf,P,14/11/2000,10
A 0,0,300,1000
R 100,400,ref_ref,sel1
R 200,400,ref_ref,sel0
S 100,600,200,600,20,*,RIGHT,TALU2
S 100,400,200,400,20,*,RIGHT,TALU2
S 100,150,200,150,20,*,RIGHT,TALU2
S 150,850,150,850,10,sel,LEFT,CALU1
S 180,190,180,320,10,*,DOWN,POLY
S 240,190,240,320,10,*,UP,POLY
S 120,190,120,320,10,*,UP,POLY
S 60,190,60,320,10,*,DOWN,POLY
S 150,280,150,740,20,*,UP,ALU1
S 30,900,30,970,20,*,DOWN,ALU1
S 270,900,270,970,20,*,UP,ALU1
S 210,740,210,790,20,*,DOWN,ALU1
S 90,790,210,790,20,*,RIGHT,ALU1
S 120,820,120,870,10,*,DOWN,POLY
S 180,820,180,860,10,*,DOWN,POLY
S 120,850,180,850,30,*,RIGHT,POLY
S 120,870,120,980,10,*,UP,NTRANS
S 150,890,150,960,30,*,UP,NDIF
S 90,890,90,960,30,*,UP,NDIF
S 150,900,150,940,20,*,UP,ALU1
S 210,730,210,800,30,*,UP,PDIF
S 180,710,180,820,10,*,DOWN,PTRANS
S 160,730,160,800,30,*,UP,PDIF
S 120,710,120,820,10,*,DOWN,PTRANS
S 90,730,90,800,30,*,UP,PDIF
S 60,660,120,660,30,*,RIGHT,POLY
S 30,350,30,680,20,*,UP,ALU1
S 270,280,270,680,20,*,UP,ALU1
S 180,320,180,650,10,*,UP,PTRANS
S 210,340,210,630,30,*,UP,PDIF
S 240,320,240,650,10,*,DOWN,PTRANS
S 270,340,270,630,30,*,DOWN,PDIF
S 120,320,120,650,10,*,UP,PTRANS
S 90,340,90,630,30,*,UP,PDIF
S 150,340,150,630,30,*,UP,PDIF
S 60,320,60,650,10,*,UP,PTRANS
S 30,340,30,630,30,*,UP,PDIF
S 30,50,30,150,20,*,UP,ALU1
S 150,50,150,150,20,*,UP,ALU1
S 270,50,270,150,20,*,UP,ALU1
S 180,10,180,190,10,*,DOWN,NTRANS
S 210,30,210,170,30,*,UP,NDIF
S 240,10,240,190,10,*,DOWN,NTRANS
S 30,30,30,170,30,*,UP,NDIF
S 270,30,270,170,30,*,UP,NDIF
S 120,10,120,190,10,*,DOWN,NTRANS
S 60,10,60,190,10,*,UP,NTRANS
S 150,30,150,170,30,*,UP,NDIF
S 90,30,90,170,30,*,UP,NDIF
S 0,500,300,500,460,*,RIGHT,NWELL
S 90,100,90,400,20,*,UP,ALU1
S 90,660,90,900,20,*,UP,ALU1
S 210,100,210,400,20,*,UP,ALU1
S 90,220,160,220,20,*,RIGHT,ALU1
S 150,220,240,220,30,*,RIGHT,POLY
S 60,220,120,220,30,*,RIGHT,POLY
S 0,970,300,970,60,vss,RIGHT,CALU1
S 0,30,300,30,60,vss,RIGHT,CALU1
S 0,530,300,530,60,vdd,RIGHT,CALU1
S 0,470,300,470,60,vdd,RIGHT,CALU1
S 100,150,100,600,20,sel1,UP,CALU3
S 200,150,200,600,20,sel0,DOWN,CALU3
V 200,150,CONT_VIA,*
V 200,150,CONT_VIA2,*
V 30,900,CONT_BODY_P,*
V 270,900,CONT_BODY_P,*
V 90,660,CONT_POLY,*
V 30,680,CONT_BODY_N,*
V 270,680,CONT_BODY_N,*
V 150,680,CONT_BODY_N,*
V 30,970,CONT_BODY_P,*
V 150,950,CONT_DIF_N,*
V 150,900,CONT_DIF_N,*
V 210,740,CONT_DIF_P,*
V 210,790,CONT_DIF_P,*
V 210,600,CONT_DIF_P,*
V 200,600,CONT_VIA,*
V 200,600,CONT_VIA2,*
V 90,600,CONT_DIF_P,*
V 100,600,CONT_VIA,*
V 100,600,CONT_VIA2,*
V 90,400,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 100,400,CONT_VIA,*
V 100,400,CONT_VIA2,*
V 210,350,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 200,400,CONT_VIA,*
V 200,400,CONT_VIA2,*
V 270,600,CONT_DIF_P,*
V 270,550,CONT_DIF_P,*
V 270,500,CONT_DIF_P,*
V 270,450,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 270,400,CONT_DIF_P,*
V 150,500,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 150,550,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,500,CONT_DIF_P,*
V 30,550,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,600,CONT_DIF_P,*
V 270,290,CONT_BODY_N,*
V 30,290,CONT_BODY_N,*
V 150,290,CONT_BODY_N,*
V 90,100,CONT_DIF_N,*
V 90,150,CONT_DIF_N,*
V 90,900,CONT_DIF_N,*
V 150,150,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 30,150,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 90,740,CONT_DIF_P,*
V 150,740,CONT_DIF_P,*
V 100,150,CONT_VIA2,*
V 100,150,CONT_VIA,*
V 210,150,CONT_DIF_N,*
V 270,150,CONT_DIF_N,*
V 270,50,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 90,790,CONT_DIF_P,*
V 270,970,CONT_BODY_P,*
V 160,220,CONT_POLY,*
V 150,850,CONT_POLY,*
EOF

21
alliance/src/cells/src/dp_sxlib/dp_nmux_x1_buf.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY dp_nmux_x1_buf IS
PORT (
sel : in BIT;
sel0 : out BIT;
sel1 : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_nmux_x1_buf;
ARCHITECTURE vbe OF dp_nmux_x1_buf IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_nmux_x1_buf"
SEVERITY WARNING;
sel1 <= sel;
sel0 <= not sel;
END;

75
alliance/src/cells/src/dp_sxlib/dp_nts_x2.ap Normal file
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@ -0,0 +1,75 @@
V ALLIANCE : 6
H dp_nts_x2,P,10/11/2000,100
A 0,0,3000,5000
R 1000,2000,ref_ref,nenx
R 2000,2000,ref_ref,enx
R 1500,2500,ref_ref,nq_25
R 500,3500,ref_ref,i_35
R 500,3000,ref_ref,i_30
R 500,1500,ref_ref,i_15
R 500,1000,ref_ref,i_10
R 500,2500,ref_ref,i_25
R 500,2000,ref_ref,i_20
R 500,4000,ref_ref,i_40
R 1500,1500,ref_ref,nq_15
R 1500,1000,ref_ref,nq_10
R 1500,4000,ref_ref,nq_40
R 1500,3500,ref_ref,nq_35
R 1500,3000,ref_ref,nq_30
R 1500,2000,ref_ref,nq_20
S 2700,3000,2700,4700,200,*,UP,ALU1
S 2700,2800,2700,4200,300,*,DOWN,PDIF
S 2400,2600,2400,4400,100,*,DOWN,PTRANS
S 2700,500,2700,1700,200,*,DOWN,ALU1
S 1000,2000,1000,2500,200,*,DOWN,ALU1
S 2000,1500,2000,2000,200,*,UP,ALU1
S 1000,2500,1800,2500,300,*,RIGHT,POLY
S 500,2000,2400,2000,300,*,RIGHT,POLY
S 600,1400,600,2600,100,*,DOWN,POLY
S 1200,2600,1200,4900,100,*,DOWN,PTRANS
S 300,2800,300,4700,300,*,DOWN,PDIF
S 900,2800,900,4700,300,*,DOWN,PDIF
S 2100,2800,2100,4700,300,*,DOWN,PDIF
S 600,2600,600,4900,100,*,DOWN,PTRANS
S 1500,300,1500,1200,300,*,UP,NDIF
S 900,300,900,1200,300,*,UP,NDIF
S 300,300,300,1200,300,*,UP,NDIF
S 2700,300,2700,1200,300,*,UP,NDIF
S 2100,300,2100,1200,300,*,UP,NDIF
S 600,100,600,1400,100,*,UP,NTRANS
S 2400,100,2400,1400,100,*,UP,NTRANS
S 1200,1500,2000,1500,300,*,RIGHT,POLY
S 1200,100,1200,1400,100,*,UP,NTRANS
S 1800,2600,1800,4900,100,*,DOWN,PTRANS
S 1800,100,1800,1400,100,*,UP,NTRANS
S 0,3900,3000,3900,2400,*,RIGHT,NWELL
S 1400,2800,1400,4700,300,*,DOWN,PDIF
S 1000,2000,2000,2000,200,*,RIGHT,TALU2
S 0,300,3000,300,600,vss,RIGHT,CALU1
S 1500,1000,1500,4000,200,nq,DOWN,CALU1
S 500,1000,500,4000,200,i,UP,CALU1
S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
S 2000,2000,2000,2000,200,enx,LEFT,CALU3
S 1000,2000,1000,2000,200,nenx,LEFT,CALU3
S 2400,1400,2400,2600,100,*,DOWN,POLY
V 2700,4700,CONT_BODY_N,*
V 2700,1000,CONT_DIF_N,*
V 2700,3500,CONT_DIF_P,*
V 2700,4000,CONT_DIF_P,*
V 2700,1700,CONT_BODY_P,*
V 300,4500,CONT_DIF_P,*
V 2000,2000,CONT_VIA,*
V 2000,2000,CONT_VIA2,*
V 1000,2000,CONT_VIA2,*
V 1000,2000,CONT_VIA,*
V 1000,2500,CONT_POLY,*
V 500,2000,CONT_POLY,*
V 2700,500,CONT_DIF_N,*
V 300,500,CONT_DIF_N,*
V 2000,1500,CONT_POLY,*
V 1500,3500,CONT_DIF_P,*
V 1500,3000,CONT_DIF_P,*
V 1500,4000,CONT_DIF_P,*
V 1500,1000,CONT_DIF_N,*
V 2700,3000,CONT_DIF_P,*
EOF

28
alliance/src/cells/src/dp_sxlib/dp_nts_x2.vbe Normal file
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@ -0,0 +1,28 @@
ENTITY dp_nts_x2 IS
PORT (
enx : in BIT;
nenx : in BIT;
i : in BIT;
nq : out MUX_BIT BUS;
vdd : in BIT;
vss : in BIT
);
END dp_nts_x2;
ARCHITECTURE vbe OF dp_nts_x2 IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_nts_x2"
SEVERITY WARNING;
ASSERT (enx xor nenx)
REPORT "wrong control signals on dp_nts_x2"
SEVERITY WARNING;
label0 : BLOCK (enx = '1')
BEGIN
nq <= GUARDED not i;
END BLOCK label0;
END;

137
alliance/src/cells/src/dp_sxlib/dp_nts_x2_buf.ap Normal file
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@ -0,0 +1,137 @@
V ALLIANCE : 6
H dp_nts_x2_buf,P,14/11/2000,10
A 0,0,300,1000
R 200,400,ref_ref,enx
R 100,400,ref_ref,nenx
S 100,600,200,600,20,*,RIGHT,TALU2
S 100,400,200,400,20,*,RIGHT,TALU2
S 100,150,200,150,20,*,RIGHT,TALU2
S 100,150,100,600,20,nenx,UP,CALU3
S 200,150,200,600,20,enx,DOWN,CALU3
S 0,30,300,30,60,vss,RIGHT,CALU1
S 0,530,300,530,60,vdd,RIGHT,CALU1
S 0,470,300,470,60,vdd,RIGHT,CALU1
S 0,970,300,970,60,vss,RIGHT,CALU1
S 140,220,210,220,20,*,RIGHT,ALU1
S 60,220,150,220,30,*,RIGHT,POLY
S 180,220,240,220,30,*,RIGHT,POLY
S 210,660,210,790,20,*,DOWN,ALU1
S 90,740,90,900,20,*,UP,ALU1
S 180,660,240,660,30,*,RIGHT,POLY
S 180,190,180,320,10,*,DOWN,POLY
S 240,190,240,320,10,*,UP,POLY
S 120,190,120,320,10,*,UP,POLY
S 60,190,60,320,10,*,DOWN,POLY
S 150,280,150,740,20,*,UP,ALU1
S 30,900,30,970,20,*,DOWN,ALU1
S 270,900,270,970,20,*,UP,ALU1
S 90,790,210,790,20,*,RIGHT,ALU1
S 120,820,120,870,10,*,DOWN,POLY
S 180,820,180,860,10,*,DOWN,POLY
S 120,850,180,850,30,*,RIGHT,POLY
S 120,870,120,980,10,*,UP,NTRANS
S 150,890,150,960,30,*,UP,NDIF
S 90,890,90,960,30,*,UP,NDIF
S 150,900,150,940,20,*,UP,ALU1
S 210,730,210,800,30,*,UP,PDIF
S 180,710,180,820,10,*,DOWN,PTRANS
S 160,730,160,800,30,*,UP,PDIF
S 120,710,120,820,10,*,DOWN,PTRANS
S 90,730,90,800,30,*,UP,PDIF
S 30,350,30,680,20,*,UP,ALU1
S 270,280,270,680,20,*,UP,ALU1
S 180,320,180,650,10,*,UP,PTRANS
S 210,340,210,630,30,*,UP,PDIF
S 240,320,240,650,10,*,DOWN,PTRANS
S 270,340,270,630,30,*,DOWN,PDIF
S 120,320,120,650,10,*,UP,PTRANS
S 90,340,90,630,30,*,UP,PDIF
S 150,340,150,630,30,*,UP,PDIF
S 60,320,60,650,10,*,UP,PTRANS
S 30,340,30,630,30,*,UP,PDIF
S 30,50,30,150,20,*,UP,ALU1
S 150,50,150,150,20,*,UP,ALU1
S 270,50,270,150,20,*,UP,ALU1
S 180,10,180,190,10,*,DOWN,NTRANS
S 210,30,210,170,30,*,UP,NDIF
S 240,10,240,190,10,*,DOWN,NTRANS
S 30,30,30,170,30,*,UP,NDIF
S 270,30,270,170,30,*,UP,NDIF
S 120,10,120,190,10,*,DOWN,NTRANS
S 60,10,60,190,10,*,UP,NTRANS
S 150,30,150,170,30,*,UP,NDIF
S 90,30,90,170,30,*,UP,NDIF
S 0,500,300,500,460,*,RIGHT,NWELL
S 90,100,90,400,20,*,UP,ALU1
S 210,100,210,400,20,*,UP,ALU1
S 150,850,150,850,10,en,LEFT,CALU1
V 140,220,CONT_POLY,*
V 210,660,CONT_POLY,*
V 200,150,CONT_VIA,*
V 200,150,CONT_VIA2,*
V 30,900,CONT_BODY_P,*
V 270,900,CONT_BODY_P,*
V 30,680,CONT_BODY_N,*
V 270,680,CONT_BODY_N,*
V 150,680,CONT_BODY_N,*
V 30,970,CONT_BODY_P,*
V 150,950,CONT_DIF_N,*
V 150,900,CONT_DIF_N,*
V 210,740,CONT_DIF_P,*
V 210,790,CONT_DIF_P,*
V 210,600,CONT_DIF_P,*
V 200,600,CONT_VIA,*
V 200,600,CONT_VIA2,*
V 90,600,CONT_DIF_P,*
V 100,600,CONT_VIA,*
V 100,600,CONT_VIA2,*
V 90,400,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 100,400,CONT_VIA,*
V 100,400,CONT_VIA2,*
V 210,350,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 200,400,CONT_VIA,*
V 200,400,CONT_VIA2,*
V 270,600,CONT_DIF_P,*
V 270,550,CONT_DIF_P,*
V 270,500,CONT_DIF_P,*
V 270,450,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 270,400,CONT_DIF_P,*
V 150,500,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 150,550,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,500,CONT_DIF_P,*
V 30,550,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,600,CONT_DIF_P,*
V 270,290,CONT_BODY_N,*
V 30,290,CONT_BODY_N,*
V 150,290,CONT_BODY_N,*
V 90,100,CONT_DIF_N,*
V 90,150,CONT_DIF_N,*
V 90,900,CONT_DIF_N,*
V 150,150,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 30,150,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 90,740,CONT_DIF_P,*
V 150,740,CONT_DIF_P,*
V 100,150,CONT_VIA2,*
V 100,150,CONT_VIA,*
V 210,150,CONT_DIF_N,*
V 270,150,CONT_DIF_N,*
V 270,50,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 90,790,CONT_DIF_P,*
V 270,970,CONT_BODY_P,*
V 150,850,CONT_POLY,*
EOF

21
alliance/src/cells/src/dp_sxlib/dp_nts_x2_buf.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY dp_nts_x2_buf IS
PORT (
en : in BIT;
enx : out BIT;
nenx : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_nts_x2_buf;
ARCHITECTURE vbe OF dp_nts_x2_buf IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_nts_x2_buf"
SEVERITY WARNING;
enx <= en;
nenx <= not en;
END;

73
alliance/src/cells/src/dp_sxlib/dp_rom2_buf.ap Normal file
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@ -0,0 +1,73 @@
V ALLIANCE : 6
H dp_rom2_buf,P,14/11/2000,10
A 0,0,250,1000
R 100,400,ref_ref,wenx
S 40,600,160,600,20,*,RIGHT,TALU2
S 40,400,160,400,20,*,RIGHT,TALU2
S 40,150,160,150,20,*,RIGHT,TALU2
S 160,340,160,630,30,*,UP,PDIF
S 70,320,70,650,10,*,UP,PTRANS
S 40,340,40,630,30,*,UP,PDIF
S 130,320,130,650,10,*,UP,PTRANS
S 100,340,100,630,30,*,UP,PDIF
S 130,10,130,190,10,*,DOWN,NTRANS
S 70,10,70,190,10,*,UP,NTRANS
S 100,30,100,170,30,*,UP,NDIF
S 40,30,40,170,30,*,UP,NDIF
S 160,30,160,170,30,*,UP,NDIF
S 70,650,70,710,10,*,DOWN,POLY
S 130,650,130,710,10,*,UP,POLY
S 130,190,130,320,10,*,UP,POLY
S 70,190,70,320,10,*,DOWN,POLY
S 70,220,130,220,30,*,RIGHT,POLY
S 100,100,100,400,20,*,UP,ALU1
S 160,50,160,150,20,*,UP,ALU1
S 40,50,40,150,20,*,UP,ALU1
S 160,280,160,680,20,*,UP,ALU1
S 40,290,40,680,20,*,UP,ALU1
S 100,150,100,600,20,nix,DOWN,CALU3
S 0,470,250,470,60,vdd,RIGHT,CALU1
S 0,530,250,530,60,vdd,RIGHT,CALU1
S 0,500,250,500,460,*,RIGHT,NWELL
S 0,30,250,30,60,vss,RIGHT,CALU1
S 0,970,250,970,60,vss,RIGHT,CALU1
S 220,50,220,150,20,*,UP,ALU1
S 100,700,100,700,10,i,LEFT,CALU1
S 70,700,130,700,30,*,RIGHT,POLY
V 40,550,CONT_DIF_P,*
V 160,450,CONT_DIF_P,*
V 160,550,CONT_DIF_P,*
V 160,400,CONT_DIF_P,*
V 160,500,CONT_DIF_P,*
V 160,290,CONT_BODY_N,*
V 40,290,CONT_BODY_N,*
V 40,600,CONT_DIF_P,*
V 40,350,CONT_DIF_P,*
V 100,350,CONT_DIF_P,*
V 100,400,CONT_DIF_P,*
V 100,600,CONT_DIF_P,*
V 160,680,CONT_BODY_N,*
V 40,500,CONT_DIF_P,*
V 40,450,CONT_DIF_P,*
V 40,400,CONT_DIF_P,*
V 160,350,CONT_DIF_P,*
V 160,600,CONT_DIF_P,*
V 40,680,CONT_BODY_N,*
V 100,100,CONT_DIF_N,*
V 40,150,CONT_DIF_N,*
V 40,100,CONT_DIF_N,*
V 160,50,CONT_DIF_N,*
V 160,100,CONT_DIF_N,*
V 160,150,CONT_DIF_N,*
V 40,50,CONT_DIF_N,*
V 100,150,CONT_DIF_N,*
V 100,600,CONT_VIA,*
V 100,400,CONT_VIA,*
V 100,150,CONT_VIA,*
V 100,600,CONT_VIA2,*
V 100,150,CONT_VIA2,*
V 100,400,CONT_VIA2,*
V 220,30,CONT_BODY_P,*
V 220,150,CONT_BODY_P,*
V 100,700,CONT_POLY,*
EOF

19
alliance/src/cells/src/dp_sxlib/dp_rom2_buf.vbe Normal file
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@ -0,0 +1,19 @@
ENTITY dp_rom2_buf IS
PORT (
i : in BIT;
nix : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_rom2_buf;
ARCHITECTURE vbe OF dp_rom2_buf IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_rom2_buf"
SEVERITY WARNING;
nix <= not i;
END;

248
alliance/src/cells/src/dp_sxlib/dp_rom4_buf.ap Normal file
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@ -0,0 +1,248 @@
V ALLIANCE : 6
H dp_rom4_buf,P, 4/ 8/2000,10
A 0,0,550,1000
R 100,400,ref_ref,i0
R 450,400,ref_ref,ni0
R 350,400,ref_ref,i1
R 200,400,ref_ref,ni1
S 400,850,400,850,10,i1,LEFT,CALU1
S 150,850,150,850,10,i0,LEFT,CALU1
S 400,50,400,150,20,*,UP,ALU1
S 280,50,280,150,20,*,UP,ALU1
S 520,280,520,680,20,*,UP,ALU1
S 400,900,400,940,20,*,UP,ALU1
S 520,900,520,970,20,*,UP,ALU1
S 460,100,460,400,20,*,UP,ALU1
S 340,660,340,900,20,*,UP,ALU1
S 340,100,340,400,20,*,UP,ALU1
S 520,50,520,150,20,*,UP,ALU1
S 280,900,280,970,20,*,DOWN,ALU1
S 400,280,400,740,20,*,UP,ALU1
S 340,790,460,790,20,*,RIGHT,ALU1
S 460,740,460,790,20,*,DOWN,ALU1
S 150,50,150,150,20,*,UP,ALU1
S 30,50,30,150,20,*,UP,ALU1
S 430,820,430,860,10,*,DOWN,POLY
S 370,820,370,870,10,*,DOWN,POLY
S 310,190,310,320,10,*,DOWN,POLY
S 370,190,370,320,10,*,UP,POLY
S 490,190,490,320,10,*,UP,POLY
S 430,190,430,320,10,*,DOWN,POLY
S 310,660,370,660,30,*,RIGHT,POLY
S 370,850,430,850,30,*,RIGHT,POLY
S 460,30,460,170,30,*,UP,NDIF
S 340,890,340,960,30,*,UP,NDIF
S 400,890,400,960,30,*,UP,NDIF
S 400,30,400,170,30,*,UP,NDIF
S 520,30,520,170,30,*,UP,NDIF
S 280,30,280,170,30,*,UP,NDIF
S 340,30,340,170,30,*,UP,NDIF
S 210,30,210,170,30,*,UP,NDIF
S 150,30,150,170,30,*,UP,NDIF
S 30,30,30,170,30,*,UP,NDIF
S 90,30,90,170,30,*,UP,NDIF
S 310,10,310,190,10,*,UP,NTRANS
S 370,10,370,190,10,*,DOWN,NTRANS
S 490,10,490,190,10,*,DOWN,NTRANS
S 430,10,430,190,10,*,DOWN,NTRANS
S 370,870,370,980,10,*,UP,NTRANS
S 120,10,120,190,10,*,DOWN,NTRANS
S 240,10,240,190,10,*,DOWN,NTRANS
S 180,10,180,190,10,*,DOWN,NTRANS
S 60,10,60,190,10,*,UP,NTRANS
S 490,320,490,650,10,*,DOWN,PTRANS
S 460,340,460,630,30,*,UP,PDIF
S 430,320,430,650,10,*,UP,PTRANS
S 340,730,340,800,30,*,UP,PDIF
S 370,710,370,820,10,*,DOWN,PTRANS
S 410,730,410,800,30,*,UP,PDIF
S 430,710,430,820,10,*,DOWN,PTRANS
S 460,730,460,800,30,*,UP,PDIF
S 280,340,280,630,30,*,UP,PDIF
S 310,320,310,650,10,*,UP,PTRANS
S 400,340,400,630,30,*,UP,PDIF
S 340,340,340,630,30,*,UP,PDIF
S 370,320,370,650,10,*,UP,PTRANS
S 520,340,520,630,30,*,DOWN,PDIF
S 0,500,550,500,460,*,RIGHT,NWELL
S 60,660,120,660,30,*,RIGHT,POLY
S 180,320,180,650,10,*,UP,PTRANS
S 210,340,210,630,30,*,UP,PDIF
S 240,320,240,650,10,*,DOWN,PTRANS
S 90,340,90,630,30,*,UP,PDIF
S 150,340,150,630,30,*,UP,PDIF
S 60,320,60,650,10,*,UP,PTRANS
S 30,340,30,630,30,*,UP,PDIF
S 270,340,270,630,30,*,DOWN,PDIF
S 120,320,120,650,10,*,UP,PTRANS
S 150,900,150,940,20,*,UP,ALU1
S 210,740,210,790,20,*,DOWN,ALU1
S 90,790,210,790,20,*,RIGHT,ALU1
S 30,900,30,970,20,*,DOWN,ALU1
S 180,820,180,860,10,*,DOWN,POLY
S 120,820,120,870,10,*,DOWN,POLY
S 120,850,180,850,30,*,RIGHT,POLY
S 150,890,150,960,30,*,UP,NDIF
S 90,890,90,960,30,*,UP,NDIF
S 120,870,120,980,10,*,UP,NTRANS
S 120,710,120,820,10,*,DOWN,PTRANS
S 90,730,90,800,30,*,UP,PDIF
S 210,730,210,800,30,*,UP,PDIF
S 180,710,180,820,10,*,DOWN,PTRANS
S 160,730,160,800,30,*,UP,PDIF
S 90,660,90,900,20,*,UP,ALU1
S 60,190,60,320,10,*,DOWN,POLY
S 120,190,120,320,10,*,DOWN,POLY
S 180,190,180,320,10,*,DOWN,POLY
S 240,190,240,320,10,*,DOWN,POLY
S 450,150,450,600,20,ni0x,DOWN,CALU3
S 350,150,350,600,20,i1x,UP,CALU3
S 100,150,100,600,20,i0x,UP,CALU3
S 200,150,200,600,20,ni1x,UP,CALU3
S 90,100,90,400,20,*,UP,ALU1
S 210,100,210,400,20,*,UP,ALU1
S 30,290,30,680,20,*,UP,ALU1
S 150,280,150,740,20,*,UP,ALU1
S 180,250,270,250,30,*,RIGHT,POLY
S 270,250,340,250,20,*,RIGHT,ALU1
S 400,200,490,200,30,*,RIGHT,POLY
S 100,200,400,200,20,*,RIGHT,ALU2
S 60,250,120,250,30,*,RIGHT,POLY
S 310,200,370,200,30,*,RIGHT,POLY
S 70,580,480,580,460,*,RIGHT,NWELL
S 280,350,280,680,20,*,UP,ALU1
S 0,970,550,970,60,vss,RIGHT,CALU1
S 0,30,550,30,60,vss,RIGHT,CALU1
S 0,470,550,470,60,vdd,RIGHT,CALU1
S 0,530,550,530,60,vdd,RIGHT,CALU1
S 100,600,450,600,20,*,RIGHT,TALU2
S 100,400,450,400,20,*,RIGHT,TALU2
S 100,200,400,200,20,*,RIGHT,TALU2
S 100,150,450,150,20,*,RIGHT,TALU2
V 450,600,CONT_VIA2,*
V 350,150,CONT_VIA2,*
V 450,400,CONT_VIA2,*
V 450,150,CONT_VIA2,*
V 350,400,CONT_VIA2,*
V 350,600,CONT_VIA2,*
V 200,150,CONT_VIA2,*
V 100,150,CONT_VIA2,*
V 450,600,CONT_VIA,*
V 450,400,CONT_VIA,*
V 350,150,CONT_VIA,*
V 350,400,CONT_VIA,*
V 450,150,CONT_VIA,*
V 350,600,CONT_VIA,*
V 200,150,CONT_VIA,*
V 100,150,CONT_VIA,*
V 400,850,CONT_POLY,*
V 340,660,CONT_POLY,*
V 520,970,CONT_BODY_P,*
V 280,970,CONT_BODY_P,*
V 520,900,CONT_BODY_P,*
V 280,900,CONT_BODY_P,*
V 400,50,CONT_DIF_N,*
V 400,150,CONT_DIF_N,*
V 340,900,CONT_DIF_N,*
V 340,150,CONT_DIF_N,*
V 340,100,CONT_DIF_N,*
V 400,900,CONT_DIF_N,*
V 400,950,CONT_DIF_N,*
V 460,100,CONT_DIF_N,*
V 520,50,CONT_DIF_N,*
V 520,150,CONT_DIF_N,*
V 460,150,CONT_DIF_N,*
V 280,50,CONT_DIF_N,*
V 280,150,CONT_DIF_N,*
V 280,100,CONT_DIF_N,*
V 400,100,CONT_DIF_N,*
V 520,100,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 210,150,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 150,150,CONT_DIF_N,*
V 90,150,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 30,150,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 280,680,CONT_BODY_N,*
V 340,350,CONT_DIF_P,*
V 340,400,CONT_DIF_P,*
V 340,600,CONT_DIF_P,*
V 460,600,CONT_DIF_P,*
V 460,790,CONT_DIF_P,*
V 460,740,CONT_DIF_P,*
V 400,680,CONT_BODY_N,*
V 520,680,CONT_BODY_N,*
V 520,400,CONT_DIF_P,*
V 520,350,CONT_DIF_P,*
V 520,450,CONT_DIF_P,*
V 520,500,CONT_DIF_P,*
V 520,550,CONT_DIF_P,*
V 520,600,CONT_DIF_P,*
V 460,400,CONT_DIF_P,*
V 460,350,CONT_DIF_P,*
V 280,500,CONT_DIF_P,*
V 280,450,CONT_DIF_P,*
V 280,400,CONT_DIF_P,*
V 400,350,CONT_DIF_P,*
V 400,450,CONT_DIF_P,*
V 400,550,CONT_DIF_P,*
V 400,400,CONT_DIF_P,*
V 400,500,CONT_DIF_P,*
V 400,740,CONT_DIF_P,*
V 340,740,CONT_DIF_P,*
V 400,290,CONT_BODY_N,*
V 520,290,CONT_BODY_N,*
V 280,600,CONT_DIF_P,*
V 280,350,CONT_DIF_P,*
V 280,550,CONT_DIF_P,*
V 340,790,CONT_DIF_P,*
V 200,400,CONT_VIA2,*
V 200,600,CONT_VIA2,*
V 100,600,CONT_VIA2,*
V 100,400,CONT_VIA2,*
V 200,400,CONT_VIA,*
V 200,600,CONT_VIA,*
V 100,600,CONT_VIA,*
V 100,400,CONT_VIA,*
V 90,660,CONT_POLY,*
V 30,680,CONT_BODY_N,*
V 210,600,CONT_DIF_P,*
V 90,600,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 150,680,CONT_BODY_N,*
V 150,550,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,500,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 30,600,CONT_DIF_P,*
V 30,290,CONT_BODY_N,*
V 150,290,CONT_BODY_N,*
V 150,500,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 30,550,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 150,850,CONT_POLY,*
V 30,900,CONT_BODY_P,*
V 30,970,CONT_BODY_P,*
V 150,950,CONT_DIF_N,*
V 150,900,CONT_DIF_N,*
V 90,900,CONT_DIF_N,*
V 210,740,CONT_DIF_P,*
V 210,790,CONT_DIF_P,*
V 90,740,CONT_DIF_P,*
V 150,740,CONT_DIF_P,*
V 90,790,CONT_DIF_P,*
V 260,250,CONT_POLY,*
V 410,200,CONT_POLY,*
V 400,200,CONT_VIA,*
V 100,200,CONT_VIA,*
EOF

26
alliance/src/cells/src/dp_sxlib/dp_rom4_buf.vbe Normal file
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@ -0,0 +1,26 @@
ENTITY dp_rom4_buf IS
PORT (
i0 : in BIT;
i1 : in BIT;
i0x : out BIT;
i1x : out BIT;
ni0x : out BIT;
ni1x : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_rom4_buf;
ARCHITECTURE vbe OF dp_rom4_buf IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_rom4_buf"
SEVERITY WARNING;
i0x <= i0;
i1x <= i1;
ni0x <= not i0;
ni1x <= not i1;
END;

124
alliance/src/cells/src/dp_sxlib/dp_rom4_nxr2_x4.ap Normal file
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@ -0,0 +1,124 @@
V ALLIANCE : 6
H dp_rom4_nxr2_x4,P,27/10/2000,100
A 0,0,5500,5000
R 3500,2500,ref_ref,i1x
R 2000,2000,ref_ref,ni1x
R 4500,2000,ref_ref,ni0x
R 1000,2500,ref_ref,i0x
R 5000,3500,ref_ref,q_35
R 5000,4000,ref_ref,q_40
R 5000,2500,ref_ref,q_25
R 5000,2000,ref_ref,q_20
R 5000,1500,ref_ref,q_15
R 5000,1000,ref_ref,q_10
R 5000,3000,ref_ref,q_30
S 1700,1500,2000,1500,200,*,LEFT,ALU1
S 2000,2500,2400,2500,200,*,RIGHT,ALU1
S 2000,1500,2000,2500,100,*,DOWN,ALU1
S 3400,2500,3400,3000,100,*,UP,ALU1
S 3400,2500,3500,2500,100,*,LEFT,ALU1
S 3500,1500,3500,2500,100,*,UP,ALU1
S 3400,1500,3500,1500,100,*,RIGHT,ALU1
S 3400,1000,3400,1500,100,*,DOWN,ALU1
S 2100,3000,3400,3000,100,*,RIGHT,ALU1
S 2100,1000,3400,1000,100,*,RIGHT,ALU1
S 3000,400,3000,1400,100,*,DOWN,NTRANS
S 2400,400,2400,1400,100,*,DOWN,NTRANS
S 1800,400,1800,1400,100,*,DOWN,NTRANS
S 1200,400,1200,1400,100,*,DOWN,NTRANS
S 2100,600,2100,1200,300,*,UP,NDIF
S 1500,600,1500,1200,300,*,UP,NDIF
S 2700,600,2700,1200,300,*,UP,NDIF
S 3900,1000,5000,1000,200,*,LEFT,ALU1
S 3900,3000,5000,3000,200,*,RIGHT,ALU1
S 3900,3000,3900,4000,200,*,DOWN,ALU1
S 3000,2000,4500,2000,200,*,RIGHT,ALU2
S 2000,2000,4500,2000,200,*,RIGHT,TALU2
S 4500,2800,4500,4700,300,*,DOWN,PDIF
S 4200,2600,4200,4900,100,*,UP,PTRANS
S 3600,2600,3600,4900,100,*,UP,PTRANS
S 3900,2800,3900,4700,300,*,DOWN,PDIF
S 3600,100,3600,1400,100,*,DOWN,NTRANS
S 4200,100,4200,1400,100,*,DOWN,NTRANS
S 3900,300,3900,1200,300,*,UP,NDIF
S 4500,300,4500,1200,300,*,UP,NDIF
S 3400,1500,4200,1500,300,*,RIGHT,POLY
S 3600,1400,3600,2600,100,*,DOWN,POLY
S 4200,1400,4200,2600,100,*,DOWN,POLY
S 4500,3500,4500,4500,200,*,DOWN,ALU1
S 5000,1000,5000,4000,200,q,DOWN,CALU1
S 2500,2500,3500,2500,200,*,RIGHT,ALU2
S 1000,2500,3500,2500,200,*,RIGHT,TALU2
S 0,300,5500,300,600,vss,RIGHT,CALU1
S 0,3900,5500,3900,2400,*,LEFT,NWELL
S 0,4700,5500,4700,600,vdd,RIGHT,CALU1
S 900,2800,900,4700,300,*,DOWN,PDIF
S 1800,2600,1800,4400,100,*,UP,PTRANS
S 1500,2800,1500,4200,300,*,DOWN,PDIF
S 2100,2800,2100,4200,300,*,DOWN,PDIF
S 2400,2600,2400,4400,100,*,UP,PTRANS
S 2700,2800,2700,4200,300,*,DOWN,PDIF
S 3000,2600,3000,4400,100,*,UP,PTRANS
S 1200,2600,1200,4400,100,*,UP,PTRANS
S 3300,2800,3300,4700,300,*,DOWN,PDIF
S 3300,300,3300,1200,300,*,UP,NDIF
S 900,300,900,1200,300,*,UP,NDIF
S 3000,1400,3000,2600,100,*,DOWN,POLY
S 1800,2000,1800,2600,100,*,DOWN,POLY
S 1800,2000,2400,2000,100,*,LEFT,POLY
S 2400,1400,2400,2000,100,*,DOWN,POLY
S 1200,1400,1200,2600,100,*,DOWN,POLY
S 900,3000,900,4500,200,*,DOWN,ALU1
S 2100,3000,2100,4000,100,*,DOWN,ALU1
S 900,500,900,1700,200,*,DOWN,ALU1
S 3300,3500,3300,4500,200,*,DOWN,ALU1
S 2000,2000,2500,2000,200,*,RIGHT,ALU2
S 4500,2000,4500,2000,200,ni0x,LEFT,CALU3
S 2000,2000,2000,2000,200,ni1x,LEFT,CALU3
S 1000,2500,1000,2500,200,i0x,LEFT,CALU3
S 3500,2500,3500,2500,200,i1x,LEFT,CALU3
V 300,300,CONT_BODY_P,*
V 5200,300,CONT_BODY_P,*
V 5200,4700,CONT_BODY_N,*
V 300,4700,CONT_BODY_N,*
V 4500,2000,CONT_VIA2,*
V 3500,2500,CONT_VIA2,*
V 3900,3000,CONT_DIF_P,*
V 4500,4500,CONT_DIF_P,*
V 4500,3500,CONT_DIF_P,*
V 4500,4000,CONT_DIF_P,*
V 3900,3500,CONT_DIF_P,*
V 3900,4000,CONT_DIF_P,*
V 4500,500,CONT_DIF_N,*
V 3900,1000,CONT_DIF_N,*
V 3400,1500,CONT_POLY,*
V 900,3000,CONT_DIF_P,*
V 2100,3000,CONT_DIF_P,*
V 3300,4500,CONT_DIF_P,*
V 3300,4000,CONT_DIF_P,*
V 3300,3500,CONT_DIF_P,*
V 900,4500,CONT_DIF_P,*
V 900,3500,CONT_DIF_P,*
V 900,4000,CONT_DIF_P,*
V 2100,4000,CONT_DIF_P,*
V 2700,4700,CONT_BODY_N,*
V 2100,4700,CONT_BODY_N,*
V 1500,4700,CONT_BODY_N,*
V 2100,3500,CONT_DIF_P,*
V 900,500,CONT_DIF_N,*
V 900,1000,CONT_DIF_N,*
V 2100,1000,CONT_DIF_N,*
V 3300,500,CONT_DIF_N,*
V 900,1700,CONT_BODY_P,*
V 3000,2000,CONT_POLY,*
V 1100,2500,CONT_POLY,*
V 1700,1500,CONT_POLY,*
V 2500,2500,CONT_POLY,*
V 2500,2000,CONT_POLY,*
V 3000,2000,CONT_VIA,*
V 2500,2000,CONT_VIA,*
V 2500,2500,CONT_VIA,*
V 1000,2500,CONT_VIA,*
V 2000,2000,CONT_VIA2,*
V 1000,2500,CONT_VIA2,*
EOF

30
alliance/src/cells/src/dp_sxlib/dp_rom4_nxr2_x4.vbe Normal file
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@ -0,0 +1,30 @@
ENTITY dp_rom4_nxr2_x4 IS
PORT (
i0x : in BIT;
i1x : in BIT;
ni0x : in BIT;
ni1x : in BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_rom4_nxr2_x4;
ARCHITECTURE vbe OF dp_rom4_nxr2_x4 IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_rom4_nxr2_x4"
SEVERITY WARNING;
ASSERT (i0x xor ni0x)
REPORT "wrong control signals on dp_rom4_nxr2_x4"
SEVERITY WARNING;
ASSERT (i1x xor ni1x)
REPORT "wrong control signals on dp_rom4_nxr2_x4"
SEVERITY WARNING;
q <= not (i0x xor i1x);
END;

124
alliance/src/cells/src/dp_sxlib/dp_rom4_xr2_x4.ap Normal file
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@ -0,0 +1,124 @@
V ALLIANCE : 6
H dp_rom4_xr2_x4,P,27/10/2000,100
A 0,0,5500,5000
R 4500,2000,ref_ref,ni0x
R 2100,2000,ref_ref,ni1x
R 3500,2500,ref_ref,i1x
R 1000,2500,ref_ref,i0x
R 5000,3000,ref_ref,q_30
R 5000,1000,ref_ref,q_10
R 5000,1500,ref_ref,q_15
R 5000,2000,ref_ref,q_20
R 5000,2500,ref_ref,q_25
R 5000,4000,ref_ref,q_40
R 5000,3500,ref_ref,q_35
S 3400,2500,3400,3000,100,*,UP,ALU1
S 3400,2500,3500,2500,100,*,RIGHT,ALU1
S 3500,1500,3500,2500,100,*,UP,ALU1
S 3400,1500,3500,1500,100,*,RIGHT,ALU1
S 3400,1000,3400,1500,100,*,DOWN,ALU1
S 2000,1500,2500,1500,200,*,LEFT,ALU1
S 1700,2500,2000,2500,200,*,RIGHT,ALU1
S 2000,1500,2000,2500,100,*,DOWN,ALU1
S 2000,2000,2000,2000,200,ni1x,LEFT,CALU3
S 4500,2000,4500,2000,200,ni0x,LEFT,CALU3
S 2000,2000,2500,2000,200,*,RIGHT,ALU2
S 3300,3500,3300,4500,200,*,DOWN,ALU1
S 900,500,900,1700,200,*,DOWN,ALU1
S 2100,3000,2100,4000,100,*,DOWN,ALU1
S 900,3000,900,4500,200,*,DOWN,ALU1
S 1200,1400,1200,2600,100,*,DOWN,POLY
S 1800,2000,2400,2000,100,*,LEFT,POLY
S 3000,1400,3000,2600,100,*,DOWN,POLY
S 900,300,900,1200,300,*,UP,NDIF
S 3300,300,3300,1200,300,*,UP,NDIF
S 3300,2800,3300,4700,300,*,DOWN,PDIF
S 1200,2600,1200,4400,100,*,UP,PTRANS
S 3000,2600,3000,4400,100,*,UP,PTRANS
S 2700,2800,2700,4200,300,*,DOWN,PDIF
S 2400,2600,2400,4400,100,*,UP,PTRANS
S 2100,2800,2100,4200,300,*,DOWN,PDIF
S 1500,2800,1500,4200,300,*,DOWN,PDIF
S 1800,2600,1800,4400,100,*,UP,PTRANS
S 900,2800,900,4700,300,*,DOWN,PDIF
S 0,4700,5500,4700,600,vdd,RIGHT,CALU1
S 0,3900,5500,3900,2400,*,LEFT,NWELL
S 0,300,5500,300,600,vss,RIGHT,CALU1
S 1000,2500,3500,2500,200,*,RIGHT,TALU2
S 5000,1000,5000,4000,200,q,DOWN,CALU1
S 4500,3500,4500,4500,200,*,DOWN,ALU1
S 4200,1400,4200,2600,100,*,DOWN,POLY
S 3600,1400,3600,2600,100,*,DOWN,POLY
S 3400,1500,4200,1500,300,*,RIGHT,POLY
S 4500,300,4500,1200,300,*,UP,NDIF
S 3900,300,3900,1200,300,*,UP,NDIF
S 4200,100,4200,1400,100,*,DOWN,NTRANS
S 3600,100,3600,1400,100,*,DOWN,NTRANS
S 3900,2800,3900,4700,300,*,DOWN,PDIF
S 3600,2600,3600,4900,100,*,UP,PTRANS
S 4200,2600,4200,4900,100,*,UP,PTRANS
S 4500,2800,4500,4700,300,*,DOWN,PDIF
S 2000,2000,4500,2000,200,*,RIGHT,TALU2
S 3000,2000,4500,2000,200,*,RIGHT,ALU2
S 2100,1000,3400,1000,100,*,RIGHT,ALU1
S 2100,3000,3400,3000,100,*,RIGHT,ALU1
S 3900,3000,3900,4000,200,*,DOWN,ALU1
S 3900,3000,5000,3000,200,*,RIGHT,ALU1
S 3900,1000,5000,1000,200,*,LEFT,ALU1
S 2700,600,2700,1200,300,*,UP,NDIF
S 1500,600,1500,1200,300,*,UP,NDIF
S 2100,600,2100,1200,300,*,UP,NDIF
S 1200,400,1200,1400,100,*,DOWN,NTRANS
S 1800,400,1800,1400,100,*,DOWN,NTRANS
S 2400,400,2400,1400,100,*,DOWN,NTRANS
S 3000,400,3000,1400,100,*,DOWN,NTRANS
S 2400,2000,2400,2600,100,*,DOWN,POLY
S 1800,1400,1800,2000,100,*,DOWN,POLY
S 1700,2500,3500,2500,200,*,RIGHT,ALU2
S 3500,2500,3500,2500,200,i1x,LEFT,CALU3
S 1000,2500,1000,2500,200,i0x,LEFT,CALU3
V 1000,2500,CONT_VIA2,*
V 2000,2000,CONT_VIA2,*
V 1000,2500,CONT_VIA,*
V 2500,2000,CONT_VIA,*
V 3000,2000,CONT_VIA,*
V 2500,2000,CONT_POLY,*
V 1100,2500,CONT_POLY,*
V 3000,2000,CONT_POLY,*
V 900,1700,CONT_BODY_P,*
V 3300,500,CONT_DIF_N,*
V 2100,1000,CONT_DIF_N,*
V 900,1000,CONT_DIF_N,*
V 900,500,CONT_DIF_N,*
V 2100,3500,CONT_DIF_P,*
V 1500,4700,CONT_BODY_N,*
V 2100,4700,CONT_BODY_N,*
V 2700,4700,CONT_BODY_N,*
V 2100,4000,CONT_DIF_P,*
V 900,4000,CONT_DIF_P,*
V 900,3500,CONT_DIF_P,*
V 900,4500,CONT_DIF_P,*
V 3300,3500,CONT_DIF_P,*
V 3300,4000,CONT_DIF_P,*
V 3300,4500,CONT_DIF_P,*
V 2100,3000,CONT_DIF_P,*
V 900,3000,CONT_DIF_P,*
V 3400,1500,CONT_POLY,*
V 3900,1000,CONT_DIF_N,*
V 4500,500,CONT_DIF_N,*
V 3900,4000,CONT_DIF_P,*
V 3900,3500,CONT_DIF_P,*
V 4500,4000,CONT_DIF_P,*
V 4500,3500,CONT_DIF_P,*
V 4500,4500,CONT_DIF_P,*
V 3900,3000,CONT_DIF_P,*
V 3500,2500,CONT_VIA2,*
V 4500,2000,CONT_VIA2,*
V 300,4700,CONT_BODY_N,*
V 5200,4700,CONT_BODY_N,*
V 5200,300,CONT_BODY_P,*
V 300,300,CONT_BODY_P,*
V 1700,2500,CONT_POLY,*
V 2500,1500,CONT_POLY,*
V 1700,2500,CONT_VIA,*
EOF

30
alliance/src/cells/src/dp_sxlib/dp_rom4_xr2_x4.vbe Normal file
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@ -0,0 +1,30 @@
ENTITY dp_rom4_xr2_x4 IS
PORT (
i0x : in BIT;
i1x : in BIT;
ni0x : in BIT;
ni1x : in BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_rom4_xr2_x4;
ARCHITECTURE vbe OF dp_rom4_xr2_x4 IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_rom4_xr2_x4"
SEVERITY WARNING;
ASSERT (i0x xor ni0x)
REPORT "wrong control signals on dp_rom4_xr2_x4"
SEVERITY WARNING;
ASSERT (i1x xor ni1x)
REPORT "wrong control signals on dp_rom4_xr2_x4"
SEVERITY WARNING;
q <= i0x xor i1x;
END;

277
alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4.ap Normal file
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@ -0,0 +1,277 @@
V ALLIANCE : 6
H dp_sff_scan_x4,P,14/11/2000,10
A 0,0,1200,500
R 1100,200,ref_ref,q_20
R 1100,100,ref_ref,q_10
R 1100,400,ref_ref,q_40
R 1100,350,ref_ref,q_35
R 1100,300,ref_ref,q_30
R 1100,250,ref_ref,q_25
R 1100,150,ref_ref,q_15
R 100,100,ref_ref,i_10
R 100,300,ref_ref,i_30
R 100,350,ref_ref,i_35
R 100,200,ref_ref,i_20
R 100,150,ref_ref,i_15
R 100,400,ref_ref,i_40
R 150,200,ref_ref,nwenx
R 250,200,ref_ref,wenx
R 400,250,ref_ref,nscanx
R 500,250,ref_ref,scanx
R 650,250,ref_ref,nckx
R 750,250,ref_ref,ckx
S 150,200,250,200,20,*,RIGHT,TALU2
S 250,200,250,200,20,wenx,LEFT,CALU3
S 150,200,150,200,20,nwenx,LEFT,CALU3
S 400,250,400,250,20,nscanx,LEFT,CALU3
S 500,250,500,250,20,scanx,LEFT,CALU3
S 650,250,650,250,20,nckx,LEFT,CALU3
S 750,250,750,250,20,ckx,LEFT,CALU3
S 50,250,350,250,20,*,RIGHT,ALU2
S 1170,300,1170,450,20,*,DOWN,ALU1
S 650,300,700,300,10,*,RIGHT,ALU1
S 700,200,700,300,10,*,UP,ALU1
S 600,150,600,400,10,u,DOWN,ALU1
S 690,350,750,350,10,*,RIGHT,ALU1
S 1170,50,1170,100,20,*,DOWN,ALU1
S 930,400,990,400,10,*,RIGHT,ALU1
S 750,150,820,150,10,*,LEFT,ALU1
S 930,200,930,350,10,*,DOWN,ALU1
S 750,300,820,300,10,*,RIGHT,ALU1
S 1050,300,1050,450,20,*,DOWN,ALU1
S 990,100,990,400,10,z,DOWN,ALU1
S 930,100,990,100,10,*,RIGHT,ALU1
S 690,100,750,100,10,*,RIGHT,ALU1
S 800,100,870,100,10,*,RIGHT,ALU1
S 750,100,750,350,10,x,DOWN,ALU1
S 870,100,870,400,10,y,DOWN,ALU1
S 800,350,870,350,10,*,LEFT,ALU1
S 1050,50,1050,100,20,*,DOWN,ALU1
S 400,100,500,100,10,*,RIGHT,ALU1
S 450,400,600,400,10,*,RIGHT,ALU1
S 500,100,500,300,10,*,DOWN,ALU1
S 450,150,450,400,10,*,DOWN,ALU1
S 800,200,800,250,10,*,DOWN,ALU1
S 400,100,400,150,10,*,UP,ALU1
S 350,150,350,300,10,*,DOWN,ALU1
S 250,300,250,400,10,*,UP,ALU1
S 300,150,300,300,10,*,UP,ALU1
S 150,400,250,400,10,*,RIGHT,ALU1
S 200,100,200,350,10,*,UP,ALU1
S 150,150,150,400,10,*,DOWN,ALU1
S 30,100,30,350,10,*,DOWN,ALU1
S 30,250,50,250,30,*,RIGHT,ALU1
S 810,300,840,300,30,*,RIGHT,POLY
S 930,350,960,350,30,*,RIGHT,POLY
S 780,350,810,350,30,*,RIGHT,POLY
S 810,150,840,150,30,*,RIGHT,POLY
S 720,250,720,310,10,*,DOWN,POLY
S 1140,140,1140,260,10,*,DOWN,POLY
S 900,140,900,200,10,*,DOWN,POLY
S 840,300,840,360,10,*,DOWN,POLY
S 1020,250,1050,250,30,*,RIGHT,POLY
S 900,250,900,360,10,*,DOWN,POLY
S 720,140,720,200,10,*,DOWN,POLY
S 900,200,930,200,30,*,RIGHT,POLY
S 690,200,720,200,30,*,RIGHT,POLY
S 960,140,960,250,10,*,DOWN,POLY
S 1080,140,1080,260,10,*,DOWN,POLY
S 840,90,840,150,10,*,UP,POLY
S 780,100,810,100,30,*,RIGHT,POLY
S 1020,150,1050,150,30,*,RIGHT,POLY
S 500,140,500,250,10,*,DOWN,POLY
S 400,250,500,250,10,*,RIGHT,POLY
S 650,250,960,250,10,nckx,RIGHT,POLY
S 700,200,900,200,10,ckx,RIGHT,POLY
S 660,140,660,250,10,*,UP,POLY
S 400,250,400,310,10,*,DOWN,POLY
S 160,90,160,150,10,*,DOWN,POLY
S 90,300,120,300,30,*,RIGHT,POLY
S 260,90,260,250,10,*,DOWN,POLY
S 90,100,120,100,30,*,RIGHT,POLY
S 300,90,300,150,10,*,DOWN,POLY
S 160,250,160,310,10,*,DOWN,POLY
S 160,250,260,250,10,*,RIGHT,POLY
S 60,200,200,200,10,*,RIGHT,POLY
S 60,90,60,310,10,*,DOWN,POLY
S 1110,30,1110,120,30,*,DOWN,NDIF
S 1170,30,1170,120,30,*,DOWN,NDIF
S 990,80,990,120,30,*,DOWN,NDIF
S 930,80,930,120,30,*,DOWN,NDIF
S 690,80,690,120,30,*,DOWN,NDIF
S 750,30,750,120,30,*,DOWN,NDIF
S 630,80,630,120,30,*,DOWN,NDIF
S 570,40,570,120,30,*,DOWN,NDIF
S 450,80,450,160,30,*,DOWN,NDIF
S 570,40,570,120,30,*,UP,NDIF
S 870,30,870,70,30,*,DOWN,NDIF
S 810,30,810,70,30,*,DOWN,NDIF
S 870,30,870,120,30,*,DOWN,NDIF
S 1050,30,1050,120,30,*,DOWN,NDIF
S 330,30,330,120,30,*,UP,NDIF
S 450,80,450,120,60,*,DOWN,NDIF
S 30,30,30,110,30,*,UP,NDIF
S 200,30,200,110,30,*,DOWN,NDIF
S 90,30,90,70,30,*,DOWN,NDIF
S 220,30,220,70,50,*,DOWN,NDIF
S 720,60,720,140,10,*,UP,NTRANS
S 600,60,600,140,10,*,UP,NTRANS
S 1080,10,1080,140,10,*,UP,NTRANS
S 900,60,900,140,10,*,UP,NTRANS
S 660,60,660,140,10,*,UP,NTRANS
S 1140,10,1140,140,10,*,UP,NTRANS
S 1020,60,1020,140,10,*,UP,NTRANS
S 960,60,960,140,10,*,UP,NTRANS
S 400,60,400,140,10,*,UP,NTRANS
S 360,60,360,140,10,*,UP,NTRANS
S 500,60,500,140,10,*,UP,NTRANS
S 540,60,540,140,10,*,UP,NTRANS
S 840,10,840,90,10,*,UP,NTRANS
S 780,10,780,90,10,*,UP,NTRANS
S 260,10,260,90,10,*,UP,NTRANS
S 300,10,300,90,10,*,UP,NTRANS
S 160,10,160,90,10,*,UP,NTRANS
S 120,10,120,90,10,*,UP,NTRANS
S 60,10,60,90,10,*,UP,NTRANS
S 1140,260,1140,490,10,*,DOWN,PTRANS
S 1170,280,1170,470,30,*,DOWN,PDIF
S 660,310,660,440,10,*,DOWN,PTRANS
S 690,330,690,420,30,*,UP,PDIF
S 720,310,720,440,10,*,DOWN,PTRANS
S 750,330,750,470,30,*,UP,PDIF
S 1080,260,1080,490,10,*,DOWN,PTRANS
S 1050,280,1050,470,30,*,DOWN,PDIF
S 930,380,930,470,30,*,DOWN,PDIF
S 960,360,960,490,10,*,DOWN,PTRANS
S 800,380,800,470,30,*,DOWN,PDIF
S 990,380,990,470,30,*,UP,PDIF
S 1020,360,1020,490,10,*,DOWN,PTRANS
S 780,360,780,490,10,*,DOWN,PTRANS
S 840,360,840,490,10,*,UP,PTRANS
S 1110,280,1110,470,30,*,DOWN,PDIF
S 600,310,600,440,10,*,DOWN,PTRANS
S 630,330,630,420,30,*,UP,PDIF
S 540,310,540,440,10,*,DOWN,PTRANS
S 570,330,570,460,30,*,DOWN,PDIF
S 500,310,500,440,10,*,DOWN,PTRANS
S 860,380,860,470,30,*,DOWN,PDIF
S 900,360,900,490,10,*,DOWN,PTRANS
S 450,330,450,420,60,*,DOWN,PDIF
S 400,310,400,440,10,*,DOWN,PTRANS
S 360,310,360,440,10,*,DOWN,PTRANS
S 330,330,330,460,30,*,DOWN,PDIF
S 160,310,160,440,10,*,DOWN,PTRANS
S 120,310,120,440,10,*,DOWN,PTRANS
S 60,310,60,440,10,*,DOWN,PTRANS
S 30,330,30,420,30,*,DOWN,PDIF
S 0,390,1200,390,240,*,RIGHT,NWELL
S 260,310,260,440,10,*,DOWN,PTRANS
S 300,310,300,440,10,*,DOWN,PTRANS
S 90,330,90,460,30,*,DOWN,PDIF
S 210,330,210,420,60,*,UP,PDIF
S 750,250,800,250,20,*,RIGHT,ALU2
S 1020,240,1020,360,10,*,DOWN,POLY
S 990,200,1040,200,10,*,RIGHT,ALU1
S 1040,200,1140,200,30,*,RIGHT,POLY
S 0,30,1200,30,60,vss,RIGHT,CALU1
S 0,470,1200,470,60,vdd,RIGHT,CALU1
S 50,250,800,250,20,*,RIGHT,TALU2
S 300,200,1100,200,20,q,RIGHT,CALU2
S 550,150,550,300,10,scin,DOWN,CALU1
S 100,100,100,400,20,i,DOWN,CALU1
S 1100,100,1100,400,20,q,DOWN,CALU1
S 1040,150,1100,150,10,*,RIGHT,ALU1
S 1040,250,1100,250,10,*,RIGHT,ALU1
V 650,250,CONT_VIA2,*
V 500,250,CONT_VIA2,*
V 400,250,CONT_VIA2,*
V 250,200,CONT_VIA2,*
V 150,200,CONT_VIA2,*
V 400,250,CONT_VIA,*
V 650,250,CONT_VIA,*
V 800,250,CONT_VIA,*
V 350,250,CONT_VIA,*
V 500,250,CONT_VIA,*
V 300,200,CONT_VIA,*
V 50,250,CONT_VIA,*
V 150,200,CONT_VIA,*
V 250,200,CONT_VIA,*
V 650,300,CONT_POLY,*
V 1040,250,CONT_POLY,*
V 1040,150,CONT_POLY,*
V 820,150,CONT_POLY,*
V 920,200,CONT_POLY,*
V 820,300,CONT_POLY,*
V 700,200,CONT_POLY,*
V 940,350,CONT_POLY,*
V 600,150,CONT_POLY,*
V 650,250,CONT_POLY,*
V 550,300,CONT_POLY,*
V 600,300,CONT_POLY,*
V 550,150,CONT_POLY,*
V 500,300,CONT_POLY,*
V 800,100,CONT_POLY,*
V 800,350,CONT_POLY,*
V 350,150,CONT_POLY,*
V 800,200,CONT_POLY,*
V 400,250,CONT_POLY,*
V 400,150,CONT_POLY,*
V 350,300,CONT_POLY,*
V 250,200,CONT_POLY,*
V 200,200,CONT_POLY,*
V 300,300,CONT_POLY,*
V 150,150,CONT_POLY,*
V 100,300,CONT_POLY,*
V 300,150,CONT_POLY,*
V 250,300,CONT_POLY,*
V 100,100,CONT_POLY,*
V 650,30,CONT_BODY_P,*
V 400,30,CONT_BODY_P,*
V 500,30,CONT_BODY_P,*
V 930,30,CONT_BODY_P,*
V 990,30,CONT_BODY_P,*
V 330,50,CONT_DIF_N,*
V 1050,100,CONT_DIF_N,*
V 1110,100,CONT_DIF_N,*
V 570,50,CONT_DIF_N,*
V 450,150,CONT_DIF_N,*
V 930,100,CONT_DIF_N,*
V 810,50,CONT_DIF_N,*
V 690,100,CONT_DIF_N,*
V 870,100,CONT_DIF_N,*
V 1170,50,CONT_DIF_N,*
V 1050,50,CONT_DIF_N,*
V 1170,100,CONT_DIF_N,*
V 200,100,CONT_DIF_N,*
V 90,50,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 650,470,CONT_BODY_N,*
V 1050,350,CONT_DIF_P,*
V 1050,400,CONT_DIF_P,*
V 1170,450,CONT_DIF_P,*
V 1050,450,CONT_DIF_P,*
V 1050,300,CONT_DIF_P,*
V 1170,400,CONT_DIF_P,*
V 1170,350,CONT_DIF_P,*
V 1110,400,CONT_DIF_P,*
V 930,400,CONT_DIF_P,*
V 810,450,CONT_DIF_P,*
V 1110,350,CONT_DIF_P,*
V 690,350,CONT_DIF_P,*
V 330,450,CONT_DIF_P,*
V 400,470,CONT_BODY_N,*
V 450,350,CONT_DIF_P,*
V 570,450,CONT_DIF_P,*
V 500,470,CONT_BODY_N,*
V 870,400,CONT_DIF_P,*
V 1170,300,CONT_DIF_P,*
V 1110,300,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 250,470,CONT_BODY_N,*
V 150,470,CONT_BODY_N,*
V 200,350,CONT_DIF_P,*
V 90,450,CONT_DIF_P,*
V 750,250,CONT_VIA2,*
V 1040,200,CONT_POLY,*
V 1100,200,CONT_VIA,*
EOF

43
alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4.vbe Normal file
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@ -0,0 +1,43 @@
ENTITY dp_sff_scan_x4 IS
PORT (
ckx : in BIT;
nckx : in BIT;
wenx : in BIT;
nwenx : in BIT;
scanx : in BIT;
nscanx : in BIT;
i : in BIT;
scin : in BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_sff_scan_x4;
ARCHITECTURE vbe OF dp_sff_scan_x4 IS
SIGNAL ff : REG_BIT REGISTER;
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on dp_sff_scan_x4"
SEVERITY WARNING;
ASSERT (ckx xor nckx)
REPORT "wrong values for ckx and nckx in dp_sff_scan_x4"
SEVERITY WARNING;
ASSERT (wenx xor nwenx)
REPORT "wrong values for wenx and nwenx in dp_sff_scan_x4"
SEVERITY WARNING;
ASSERT (scanx xor nscanx)
REPORT "wrong values for scanx and nscanx in dp_sff_scan_x4"
SEVERITY WARNING;
label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1')
BEGIN
ff <= GUARDED ((scanx and scin) or (nscanx and ((wenx and i) or (nwenx and ff))));
END BLOCK label0;
q <= ff;
END;

403
alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4_buf.ap Normal file
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@ -0,0 +1,403 @@
V ALLIANCE : 6
H dp_sff_scan_x4_buf,P,16/11/2000,100
A 0,0,12000,10000
R 9000,6500,ref_ref,scin
R 10500,4000,ref_ref,scout_40
R 10500,3500,ref_ref,scout_35
R 10500,3000,ref_ref,scout_30
R 10500,2500,ref_ref,scout_25
R 10500,2000,ref_ref,scout_20
R 10500,1500,ref_ref,scout_15
R 10500,1000,ref_ref,scout_10
R 1500,4000,ref_ref,nwenx
R 2500,4000,ref_ref,wenx
R 4000,4000,ref_ref,nscanx
R 5000,4000,ref_ref,scanx
R 6500,4000,ref_ref,nckx
R 7500,4000,ref_ref,ckx
S 7500,1500,7500,6000,200,ckx,DOWN,CALU3
S 9000,6500,9000,6500,100,scin,LEFT,CALU1
S 2000,8500,2000,8500,100,wen,LEFT,CALU1
S 4500,8500,4500,8500,100,scan,LEFT,CALU1
S 7000,8500,7000,8500,100,ck,LEFT,CALU1
S 9000,6500,9600,6500,100,*,RIGHT,POLY
S 9600,4300,9600,6500,100,*,DOWN,POLY
S 9300,1400,9300,1700,300,*,UP,NDIF
S 9600,1200,9600,1900,100,*,DOWN,NTRANS
S 9300,3400,9300,4100,300,*,DOWN,PDIF
S 9600,3200,9600,4300,100,*,UP,PTRANS
S 1900,2200,2600,2200,200,*,RIGHT,ALU1
S 1100,2200,1900,2200,300,*,RIGHT,POLY
S 2300,2200,2900,2200,300,*,RIGHT,POLY
S 2600,6600,2600,7900,200,*,DOWN,ALU1
S 1400,7400,1400,9000,200,*,UP,ALU1
S 2300,6600,2900,6600,300,*,RIGHT,POLY
S 0,5000,12000,5000,4600,*,RIGHT,NWELL
S 3200,9000,3200,9700,200,*,UP,ALU1
S 2600,1000,2600,4000,200,*,UP,ALU1
S 1400,1000,1400,4000,200,*,UP,ALU1
S 3200,500,3200,1500,200,*,UP,ALU1
S 800,9000,800,9700,200,*,DOWN,ALU1
S 2000,2800,2000,7400,200,*,UP,ALU1
S 2000,500,2000,1500,200,*,UP,ALU1
S 800,500,800,1500,200,*,UP,ALU1
S 3200,2800,3200,6800,200,*,UP,ALU1
S 800,3500,800,6800,200,*,UP,ALU1
S 2000,9000,2000,9400,200,*,UP,ALU1
S 1400,7900,2600,7900,200,*,RIGHT,ALU1
S 5700,2800,5700,6800,200,*,UP,ALU1
S 4500,500,4500,1500,200,*,UP,ALU1
S 5700,500,5700,1500,200,*,UP,ALU1
S 3900,1000,3900,4000,200,*,UP,ALU1
S 5100,1000,5100,4000,200,*,UP,ALU1
S 8200,2800,8200,6800,200,*,UP,ALU1
S 7600,1000,7600,4000,200,*,UP,ALU1
S 6400,1000,6400,4000,200,*,UP,ALU1
S 8200,500,8200,1500,200,*,UP,ALU1
S 7000,500,7000,1500,200,*,UP,ALU1
S 3900,7900,5100,7900,200,*,RIGHT,ALU1
S 4500,9000,4500,9400,200,*,UP,ALU1
S 5700,9000,5700,9700,200,*,UP,ALU1
S 7000,9000,7000,9400,200,*,UP,ALU1
S 6400,7900,7600,7900,200,*,RIGHT,ALU1
S 1700,1900,1700,3200,100,*,UP,POLY
S 2900,1900,2900,3200,100,*,UP,POLY
S 2300,1900,2300,3200,100,*,DOWN,POLY
S 1700,8500,2300,8500,300,*,RIGHT,POLY
S 2300,8200,2300,8600,100,*,DOWN,POLY
S 1700,8200,1700,8700,100,*,DOWN,POLY
S 1100,1900,1100,3200,100,*,DOWN,POLY
S 3600,1900,3600,3200,100,*,DOWN,POLY
S 4800,1900,4800,3200,100,*,DOWN,POLY
S 5400,1900,5400,3200,100,*,UP,POLY
S 4200,1900,4200,3200,100,*,UP,POLY
S 7900,1900,7900,3200,100,*,UP,POLY
S 7300,1900,7300,3200,100,*,DOWN,POLY
S 6100,1900,6100,3200,100,*,DOWN,POLY
S 6700,1900,6700,3200,100,*,UP,POLY
S 4200,8200,4200,8700,100,*,DOWN,POLY
S 4800,8200,4800,8600,100,*,DOWN,POLY
S 4200,8500,4800,8500,300,*,RIGHT,POLY
S 6700,8500,7300,8500,300,*,RIGHT,POLY
S 7300,8200,7300,8600,100,*,DOWN,POLY
S 6700,8200,6700,8700,100,*,DOWN,POLY
S 1400,300,1400,1700,300,*,UP,NDIF
S 2000,300,2000,1700,300,*,UP,NDIF
S 1100,100,1100,1900,100,*,UP,NTRANS
S 1700,100,1700,1900,100,*,DOWN,NTRANS
S 3200,300,3200,1700,300,*,UP,NDIF
S 800,300,800,1700,300,*,UP,NDIF
S 2900,100,2900,1900,100,*,DOWN,NTRANS
S 2600,300,2600,1700,300,*,UP,NDIF
S 2300,100,2300,1900,100,*,DOWN,NTRANS
S 1400,8900,1400,9600,300,*,UP,NDIF
S 2000,8900,2000,9600,300,*,UP,NDIF
S 1700,8700,1700,9800,100,*,UP,NTRANS
S 5700,300,5700,1700,300,*,UP,NDIF
S 4200,100,4200,1900,100,*,DOWN,NTRANS
S 3600,100,3600,1900,100,*,UP,NTRANS
S 4500,300,4500,1700,300,*,UP,NDIF
S 3900,300,3900,1700,300,*,UP,NDIF
S 4800,100,4800,1900,100,*,DOWN,NTRANS
S 5100,300,5100,1700,300,*,UP,NDIF
S 5400,100,5400,1900,100,*,DOWN,NTRANS
S 8200,300,8200,1700,300,*,UP,NDIF
S 6400,300,6400,1700,300,*,UP,NDIF
S 7000,300,7000,1700,300,*,UP,NDIF
S 6100,100,6100,1900,100,*,UP,NTRANS
S 6700,100,6700,1900,100,*,DOWN,NTRANS
S 7900,100,7900,1900,100,*,DOWN,NTRANS
S 7600,300,7600,1700,300,*,UP,NDIF
S 7300,100,7300,1900,100,*,DOWN,NTRANS
S 4500,8900,4500,9600,300,*,UP,NDIF
S 3900,8900,3900,9600,300,*,UP,NDIF
S 6400,8900,6400,9600,300,*,UP,NDIF
S 7000,8900,7000,9600,300,*,UP,NDIF
S 4200,8700,4200,9800,100,*,UP,NTRANS
S 6700,8700,6700,9800,100,*,UP,NTRANS
S 2600,7300,2600,8000,300,*,UP,PDIF
S 800,3400,800,6300,300,*,UP,PDIF
S 1100,3200,1100,6500,100,*,UP,PTRANS
S 2000,3400,2000,6300,300,*,UP,PDIF
S 1400,3400,1400,6300,300,*,UP,PDIF
S 1700,3200,1700,6500,100,*,UP,PTRANS
S 3200,3400,3200,6300,300,*,DOWN,PDIF
S 2900,3200,2900,6500,100,*,DOWN,PTRANS
S 2600,3400,2600,6300,300,*,UP,PDIF
S 2300,3200,2300,6500,100,*,UP,PTRANS
S 1400,7300,1400,8000,300,*,UP,PDIF
S 1700,7100,1700,8200,100,*,DOWN,PTRANS
S 2100,7300,2100,8000,300,*,UP,PDIF
S 2300,7100,2300,8200,100,*,DOWN,PTRANS
S 5700,3400,5700,6300,300,*,DOWN,PDIF
S 4200,3200,4200,6500,100,*,UP,PTRANS
S 3900,3400,3900,6300,300,*,UP,PDIF
S 4500,3400,4500,6300,300,*,UP,PDIF
S 3600,3200,3600,6500,100,*,UP,PTRANS
S 4800,3200,4800,6500,100,*,UP,PTRANS
S 5100,3400,5100,6300,300,*,UP,PDIF
S 5400,3200,5400,6500,100,*,DOWN,PTRANS
S 7000,3400,7000,6300,300,*,UP,PDIF
S 6400,3400,6400,6300,300,*,UP,PDIF
S 6700,3200,6700,6500,100,*,UP,PTRANS
S 8200,3400,8200,6300,300,*,DOWN,PDIF
S 6100,3200,6100,6500,100,*,UP,PTRANS
S 7900,3200,7900,6500,100,*,DOWN,PTRANS
S 7600,3400,7600,6300,300,*,UP,PDIF
S 7300,3200,7300,6500,100,*,UP,PTRANS
S 3900,7300,3900,8000,300,*,UP,PDIF
S 5100,7300,5100,8000,300,*,UP,PDIF
S 6400,7300,6400,8000,300,*,UP,PDIF
S 4800,7100,4800,8200,100,*,DOWN,PTRANS
S 4600,7300,4600,8000,300,*,UP,PDIF
S 4200,7100,4200,8200,100,*,DOWN,PTRANS
S 7100,7300,7100,8000,300,*,UP,PDIF
S 7300,7100,7300,8200,100,*,DOWN,PTRANS
S 7600,7300,7600,8000,300,*,UP,PDIF
S 6700,7100,6700,8200,100,*,DOWN,PTRANS
S 5100,6600,5100,7900,200,*,DOWN,ALU1
S 7600,6600,7600,7900,200,*,DOWN,ALU1
S 6400,7400,6400,9000,200,*,UP,ALU1
S 3900,7400,3900,9000,200,*,UP,ALU1
S 4800,6600,5400,6600,300,*,RIGHT,POLY
S 7300,6600,7900,6600,300,*,RIGHT,POLY
S 4500,2800,4500,7400,200,*,UP,ALU1
S 7000,2800,7000,7400,200,*,UP,ALU1
S 1100,7700,8300,7700,800,*,RIGHT,NWELL
S 8200,9000,8200,9700,200,*,UP,ALU1
S 4400,2200,5100,2200,200,*,RIGHT,ALU1
S 6900,2200,7600,2200,200,*,RIGHT,ALU1
S 3600,2200,4400,2200,300,*,RIGHT,POLY
S 4800,2200,5400,2200,300,*,RIGHT,POLY
S 6100,2200,6900,2200,300,*,RIGHT,POLY
S 7300,2200,7900,2200,300,*,RIGHT,POLY
S 9300,1500,9300,4000,200,*,UP,ALU1
S 9900,2800,9900,6800,200,*,UP,ALU1
S 9900,500,9900,1500,200,*,UP,ALU1
S 9300,2200,10000,2200,200,*,RIGHT,ALU1
S 10200,1900,10200,3200,100,*,DOWN,POLY
S 9600,1900,9600,3200,100,*,UP,POLY
S 10500,300,10500,1700,300,*,UP,NDIF
S 9900,300,9900,1700,300,*,UP,NDIF
S 10200,100,10200,1900,100,*,DOWN,NTRANS
S 10500,3400,10500,6300,300,*,UP,PDIF
S 10200,3200,10200,6500,100,*,UP,PTRANS
S 9900,3400,9900,6300,300,*,UP,PDIF
S 0,9700,12000,9700,600,vss,RIGHT,CALU1
S 0,300,12000,300,600,vss,RIGHT,CALU1
S 0,4700,12000,4700,600,vdd,RIGHT,CALU1
S 0,5300,12000,5300,600,vdd,RIGHT,CALU1
S 1500,1500,1500,6000,200,nwenx,DOWN,CALU3
S 2500,1500,2500,6000,200,wenx,DOWN,CALU3
S 4000,1500,4000,6000,200,nscanx,DOWN,CALU3
S 5000,1500,5000,6000,200,scanx,DOWN,CALU3
S 6500,1500,6500,6000,200,nckx,DOWN,CALU3
S 10500,1000,10500,4000,200,scout,UP,CALU1
S 1500,1500,7500,1500,200,*,RIGHT,TALU2
S 1500,4000,7500,4000,200,*,LEFT,TALU2
S 1500,6000,7500,6000,200,*,RIGHT,TALU2
V 9000,6500,CONT_POLY,*
V 7500,1500,CONT_VIA,*
V 7500,1500,CONT_VIA2,*
V 5000,1500,CONT_VIA,*
V 5000,1500,CONT_VIA2,*
V 2500,1500,CONT_VIA,*
V 2500,1500,CONT_VIA2,*
V 1900,2200,CONT_POLY,*
V 2600,6600,CONT_POLY,*
V 1500,4000,CONT_VIA2,*
V 1500,6000,CONT_VIA2,*
V 2500,6000,CONT_VIA2,*
V 1500,1500,CONT_VIA2,*
V 2500,4000,CONT_VIA2,*
V 5000,4000,CONT_VIA2,*
V 4000,1500,CONT_VIA2,*
V 5000,6000,CONT_VIA2,*
V 4000,6000,CONT_VIA2,*
V 4000,4000,CONT_VIA2,*
V 7500,6000,CONT_VIA2,*
V 6500,1500,CONT_VIA2,*
V 7500,4000,CONT_VIA2,*
V 6500,4000,CONT_VIA2,*
V 6500,6000,CONT_VIA2,*
V 1500,1500,CONT_VIA,*
V 1500,4000,CONT_VIA,*
V 1500,6000,CONT_VIA,*
V 2500,6000,CONT_VIA,*
V 2500,4000,CONT_VIA,*
V 4000,1500,CONT_VIA,*
V 5000,4000,CONT_VIA,*
V 5000,6000,CONT_VIA,*
V 4000,6000,CONT_VIA,*
V 4000,4000,CONT_VIA,*
V 6500,1500,CONT_VIA,*
V 6500,6000,CONT_VIA,*
V 7500,6000,CONT_VIA,*
V 7500,4000,CONT_VIA,*
V 6500,4000,CONT_VIA,*
V 2000,8500,CONT_POLY,*
V 4500,8500,CONT_POLY,*
V 7000,8500,CONT_POLY,*
V 5700,9700,CONT_BODY_P,*
V 3200,9700,CONT_BODY_P,*
V 800,9700,CONT_BODY_P,*
V 3200,9000,CONT_BODY_P,*
V 800,9000,CONT_BODY_P,*
V 5700,9000,CONT_BODY_P,*
V 3200,1000,CONT_DIF_N,*
V 2600,1000,CONT_DIF_N,*
V 3200,500,CONT_DIF_N,*
V 3200,1500,CONT_DIF_N,*
V 2600,1500,CONT_DIF_N,*
V 800,500,CONT_DIF_N,*
V 800,1500,CONT_DIF_N,*
V 800,1000,CONT_DIF_N,*
V 2000,1000,CONT_DIF_N,*
V 2000,500,CONT_DIF_N,*
V 2000,1500,CONT_DIF_N,*
V 1400,9000,CONT_DIF_N,*
V 1400,1500,CONT_DIF_N,*
V 1400,1000,CONT_DIF_N,*
V 2000,9000,CONT_DIF_N,*
V 2000,9500,CONT_DIF_N,*
V 5700,500,CONT_DIF_N,*
V 5100,1000,CONT_DIF_N,*
V 5700,1000,CONT_DIF_N,*
V 3900,1000,CONT_DIF_N,*
V 3900,1500,CONT_DIF_N,*
V 4500,1500,CONT_DIF_N,*
V 4500,500,CONT_DIF_N,*
V 4500,1000,CONT_DIF_N,*
V 5100,1500,CONT_DIF_N,*
V 5700,1500,CONT_DIF_N,*
V 7600,1000,CONT_DIF_N,*
V 8200,500,CONT_DIF_N,*
V 6400,1500,CONT_DIF_N,*
V 6400,1000,CONT_DIF_N,*
V 8200,1000,CONT_DIF_N,*
V 8200,1500,CONT_DIF_N,*
V 7600,1500,CONT_DIF_N,*
V 7000,1000,CONT_DIF_N,*
V 7000,500,CONT_DIF_N,*
V 7000,1500,CONT_DIF_N,*
V 7000,9000,CONT_DIF_N,*
V 7000,9500,CONT_DIF_N,*
V 4500,9500,CONT_DIF_N,*
V 4500,9000,CONT_DIF_N,*
V 3900,9000,CONT_DIF_N,*
V 6400,9000,CONT_DIF_N,*
V 1400,7900,CONT_DIF_P,*
V 2000,7400,CONT_DIF_P,*
V 1400,7400,CONT_DIF_P,*
V 2000,2900,CONT_BODY_N,*
V 800,2900,CONT_BODY_N,*
V 3200,2900,CONT_BODY_N,*
V 800,6000,CONT_DIF_P,*
V 800,3500,CONT_DIF_P,*
V 800,5500,CONT_DIF_P,*
V 800,5000,CONT_DIF_P,*
V 800,4500,CONT_DIF_P,*
V 800,4000,CONT_DIF_P,*
V 2000,3500,CONT_DIF_P,*
V 2000,4500,CONT_DIF_P,*
V 2000,5500,CONT_DIF_P,*
V 2000,4000,CONT_DIF_P,*
V 2000,5000,CONT_DIF_P,*
V 3200,4000,CONT_DIF_P,*
V 3200,3500,CONT_DIF_P,*
V 3200,4500,CONT_DIF_P,*
V 3200,5000,CONT_DIF_P,*
V 3200,5500,CONT_DIF_P,*
V 3200,6000,CONT_DIF_P,*
V 2600,4000,CONT_DIF_P,*
V 2600,3500,CONT_DIF_P,*
V 1400,3500,CONT_DIF_P,*
V 1400,4000,CONT_DIF_P,*
V 1400,6000,CONT_DIF_P,*
V 2600,6000,CONT_DIF_P,*
V 2600,7900,CONT_DIF_P,*
V 2600,7400,CONT_DIF_P,*
V 2000,6800,CONT_BODY_N,*
V 3200,6800,CONT_BODY_N,*
V 800,6800,CONT_BODY_N,*
V 4500,5500,CONT_DIF_P,*
V 4500,4500,CONT_DIF_P,*
V 4500,3500,CONT_DIF_P,*
V 5700,2900,CONT_BODY_N,*
V 4500,2900,CONT_BODY_N,*
V 5700,6000,CONT_DIF_P,*
V 5700,5500,CONT_DIF_P,*
V 5700,5000,CONT_DIF_P,*
V 5700,4500,CONT_DIF_P,*
V 5700,3500,CONT_DIF_P,*
V 5700,4000,CONT_DIF_P,*
V 4500,5000,CONT_DIF_P,*
V 4500,4000,CONT_DIF_P,*
V 5700,6800,CONT_BODY_N,*
V 4500,6800,CONT_BODY_N,*
V 5100,6000,CONT_DIF_P,*
V 3900,6000,CONT_DIF_P,*
V 3900,4000,CONT_DIF_P,*
V 3900,3500,CONT_DIF_P,*
V 5100,3500,CONT_DIF_P,*
V 5100,4000,CONT_DIF_P,*
V 7000,3500,CONT_DIF_P,*
V 7000,4500,CONT_DIF_P,*
V 7000,5500,CONT_DIF_P,*
V 8200,5000,CONT_DIF_P,*
V 8200,5500,CONT_DIF_P,*
V 8200,6000,CONT_DIF_P,*
V 7000,2900,CONT_BODY_N,*
V 8200,2900,CONT_BODY_N,*
V 7600,6000,CONT_DIF_P,*
V 7000,6800,CONT_BODY_N,*
V 8200,6800,CONT_BODY_N,*
V 7000,4000,CONT_DIF_P,*
V 7000,5000,CONT_DIF_P,*
V 8200,4000,CONT_DIF_P,*
V 8200,3500,CONT_DIF_P,*
V 8200,4500,CONT_DIF_P,*
V 3900,7900,CONT_DIF_P,*
V 7600,4000,CONT_DIF_P,*
V 7600,3500,CONT_DIF_P,*
V 6400,3500,CONT_DIF_P,*
V 6400,4000,CONT_DIF_P,*
V 6400,6000,CONT_DIF_P,*
V 5100,7400,CONT_DIF_P,*
V 5100,7900,CONT_DIF_P,*
V 3900,7400,CONT_DIF_P,*
V 4500,7400,CONT_DIF_P,*
V 7000,7400,CONT_DIF_P,*
V 6400,7400,CONT_DIF_P,*
V 7600,7900,CONT_DIF_P,*
V 7600,7400,CONT_DIF_P,*
V 6400,7900,CONT_DIF_P,*
V 5100,6600,CONT_POLY,*
V 7600,6600,CONT_POLY,*
V 7000,6000,CONT_DIF_P,*
V 4500,6000,CONT_DIF_P,*
V 2000,6000,CONT_DIF_P,*
V 8200,9700,CONT_BODY_P,*
V 8200,9000,CONT_BODY_P,*
V 4400,2200,CONT_POLY,*
V 6900,2200,CONT_POLY,*
V 10000,2200,CONT_POLY,*
V 9300,1500,CONT_DIF_N,*
V 10500,1500,CONT_DIF_N,*
V 9900,1000,CONT_DIF_N,*
V 9900,500,CONT_DIF_N,*
V 9900,1500,CONT_DIF_N,*
V 10500,1000,CONT_DIF_N,*
V 9900,2900,CONT_BODY_N,*
V 9300,3500,CONT_DIF_P,*
V 9300,4000,CONT_DIF_P,*
V 9900,4000,CONT_DIF_P,*
V 9900,5000,CONT_DIF_P,*
V 9900,3500,CONT_DIF_P,*
V 9900,4500,CONT_DIF_P,*
V 9900,5500,CONT_DIF_P,*
V 9900,6800,CONT_BODY_N,*
V 9900,6000,CONT_DIF_P,*
V 10500,4000,CONT_DIF_P,*
V 10500,3500,CONT_DIF_P,*
EOF

33
alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4_buf.vbe Normal file
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@ -0,0 +1,33 @@
ENTITY dp_sff_scan_x4_buf IS
PORT (
ck : in BIT;
wen : in BIT;
scan : in BIT;
scin : in BIT;
ckx : out BIT;
nckx : out BIT;
wenx : out BIT;
nwenx : out BIT;
scanx : out BIT;
nscanx : out BIT;
scout : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_sff_scan_x4_buf;
ARCHITECTURE vbe OF dp_sff_scan_x4_buf IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on dp_sff_scan_x4_buf"
SEVERITY WARNING;
ckx <= ck;
nckx <= not ck;
wenx <= wen;
nwenx <= not wen;
scanx <= scan;
nscanx <= not scan;
scout <= scin;
END;

217
alliance/src/cells/src/dp_sxlib/dp_sff_x4.ap Normal file
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@ -0,0 +1,217 @@
V ALLIANCE : 6
H dp_sff_x4,P, 6/ 9/2000,10
A 0,0,900,500
R 450,250,ref_ref,ckx
R 350,250,ref_ref,nckx
R 200,250,ref_ref,wenx
R 100,250,ref_ref,nwenx
R 800,150,ref_ref,q_15
R 800,250,ref_ref,q_25
R 800,300,ref_ref,q_30
R 800,350,ref_ref,q_35
R 800,400,ref_ref,q_40
R 800,100,ref_ref,q_10
R 50,400,ref_ref,i_40
R 50,100,ref_ref,i_10
R 50,300,ref_ref,i_30
R 50,350,ref_ref,i_35
R 50,250,ref_ref,i_25
R 50,200,ref_ref,i_20
R 50,150,ref_ref,i_15
S 740,150,800,150,10,*,RIGHT,ALU1
S 740,250,800,250,10,*,RIGHT,ALU1
S 690,200,740,200,10,*,RIGHT,ALU1
S 740,200,840,200,30,*,RIGHT,POLY
S 250,200,800,200,20,*,RIGHT,ALU2
S 720,240,720,360,10,*,DOWN,POLY
S 450,250,500,250,20,*,RIGHT,ALU2
S 390,350,450,350,10,*,RIGHT,ALU1
S 300,150,300,400,10,u,DOWN,ALU1
S 400,200,400,300,10,*,UP,ALU1
S 350,300,400,300,10,*,RIGHT,ALU1
S 870,300,870,450,20,*,DOWN,ALU1
S 750,300,750,450,20,*,DOWN,ALU1
S 450,300,520,300,10,*,RIGHT,ALU1
S 630,200,630,350,10,*,DOWN,ALU1
S 450,150,520,150,10,*,LEFT,ALU1
S 630,400,690,400,10,*,RIGHT,ALU1
S 870,50,870,100,20,*,DOWN,ALU1
S 750,50,750,100,20,*,DOWN,ALU1
S 500,350,570,350,10,*,LEFT,ALU1
S 570,100,570,400,10,y,DOWN,ALU1
S 450,100,450,350,10,x,DOWN,ALU1
S 500,100,570,100,10,*,RIGHT,ALU1
S 390,100,450,100,10,*,RIGHT,ALU1
S 630,100,690,100,10,*,RIGHT,ALU1
S 690,100,690,400,10,z,DOWN,ALU1
S 150,150,150,400,10,*,DOWN,ALU1
S 200,100,200,300,10,*,DOWN,ALU1
S 150,400,300,400,10,*,RIGHT,ALU1
S 100,100,200,100,10,*,RIGHT,ALU1
S 540,300,540,360,10,*,DOWN,POLY
S 600,140,600,200,10,*,DOWN,POLY
S 840,140,840,260,10,*,DOWN,POLY
S 420,250,420,310,10,*,DOWN,POLY
S 510,150,540,150,30,*,RIGHT,POLY
S 480,350,510,350,30,*,RIGHT,POLY
S 630,350,660,350,30,*,RIGHT,POLY
S 510,300,540,300,30,*,RIGHT,POLY
S 780,140,780,260,10,*,DOWN,POLY
S 660,140,660,250,10,*,DOWN,POLY
S 390,200,420,200,30,*,RIGHT,POLY
S 600,200,630,200,30,*,RIGHT,POLY
S 420,140,420,200,10,*,DOWN,POLY
S 600,250,600,360,10,*,DOWN,POLY
S 720,250,750,250,30,*,RIGHT,POLY
S 720,150,750,150,30,*,RIGHT,POLY
S 480,100,510,100,30,*,RIGHT,POLY
S 540,90,540,150,10,*,UP,POLY
S 270,40,270,120,30,*,DOWN,NDIF
S 330,80,330,120,30,*,DOWN,NDIF
S 450,30,450,120,30,*,DOWN,NDIF
S 390,80,390,120,30,*,DOWN,NDIF
S 630,80,630,120,30,*,DOWN,NDIF
S 690,80,690,120,30,*,DOWN,NDIF
S 870,30,870,120,30,*,DOWN,NDIF
S 810,30,810,120,30,*,DOWN,NDIF
S 750,30,750,120,30,*,DOWN,NDIF
S 570,30,570,120,30,*,DOWN,NDIF
S 510,30,510,70,30,*,DOWN,NDIF
S 570,30,570,70,30,*,DOWN,NDIF
S 160,80,160,160,50,*,DOWN,NDIF
S 270,40,270,120,30,*,UP,NDIF
S 140,80,140,120,30,*,UP,NDIF
S 660,60,660,140,10,*,UP,NTRANS
S 720,60,720,140,10,*,UP,NTRANS
S 840,10,840,140,10,*,UP,NTRANS
S 360,60,360,140,10,*,UP,NTRANS
S 600,60,600,140,10,*,UP,NTRANS
S 780,10,780,140,10,*,UP,NTRANS
S 300,60,300,140,10,*,UP,NTRANS
S 420,60,420,140,10,*,UP,NTRANS
S 480,10,480,90,10,*,UP,NTRANS
S 540,10,540,90,10,*,UP,NTRANS
S 240,60,240,140,10,*,UP,NTRANS
S 200,60,200,140,10,*,UP,NTRANS
S 750,280,750,470,30,*,DOWN,PDIF
S 780,260,780,490,10,*,DOWN,PTRANS
S 450,330,450,470,30,*,UP,PDIF
S 420,310,420,440,10,*,DOWN,PTRANS
S 390,330,390,420,30,*,UP,PDIF
S 360,310,360,440,10,*,DOWN,PTRANS
S 870,280,870,470,30,*,DOWN,PDIF
S 840,260,840,490,10,*,DOWN,PTRANS
S 810,280,810,470,30,*,DOWN,PDIF
S 540,360,540,490,10,*,UP,PTRANS
S 480,360,480,490,10,*,DOWN,PTRANS
S 720,360,720,490,10,*,DOWN,PTRANS
S 690,380,690,470,30,*,UP,PDIF
S 500,380,500,470,30,*,DOWN,PDIF
S 660,360,660,490,10,*,DOWN,PTRANS
S 630,380,630,470,30,*,DOWN,PDIF
S 600,360,600,490,10,*,DOWN,PTRANS
S 560,380,560,470,30,*,DOWN,PDIF
S 200,310,200,440,10,*,DOWN,PTRANS
S 270,330,270,460,30,*,DOWN,PDIF
S 240,310,240,440,10,*,DOWN,PTRANS
S 0,390,900,390,240,*,RIGHT,NWELL
S 330,330,330,420,30,*,UP,PDIF
S 300,310,300,440,10,*,DOWN,PTRANS
S 250,150,250,300,10,*,DOWN,ALU1
S 100,100,100,150,10,*,UP,ALU1
S 30,40,30,120,30,*,UP,NDIF
S 60,60,60,140,10,*,UP,NTRANS
S 30,330,30,460,30,*,DOWN,PDIF
S 60,310,60,440,10,*,DOWN,PTRANS
S 100,200,200,200,10,*,RIGHT,POLY
S 200,140,200,200,10,*,DOWN,POLY
S 100,310,100,440,10,*,DOWN,PTRANS
S 100,200,100,310,10,*,DOWN,POLY
S 100,60,100,140,10,*,UP,NTRANS
S 150,330,150,420,60,*,DOWN,PDIF
S 150,80,150,160,50,*,DOWN,NDIF
S 500,200,500,250,10,*,DOWN,ALU1
S 360,140,360,250,10,*,UP,POLY
S 400,200,600,200,10,ckx,RIGHT,POLY
S 350,250,660,250,10,nckx,RIGHT,POLY
S 0,30,900,30,60,vss,RIGHT,CALU1
S 0,470,900,470,60,vdd,RIGHT,CALU1
S 250,200,800,200,20,*,RIGHT,TALU2
S 100,250,500,250,20,*,RIGHT,TALU2
S 100,250,100,250,20,nwenx,LEFT,CALU3
S 350,250,350,250,20,nckx,LEFT,CALU3
S 450,250,450,250,20,ckx,LEFT,CALU3
S 200,250,200,250,20,wenx,LEFT,CALU3
S 800,100,800,400,20,q,DOWN,CALU1
S 50,100,50,400,20,i,DOWN,CALU1
V 200,250,CONT_VIA,*
V 200,250,CONT_VIA2,*
V 100,250,CONT_POLY,*
V 100,250,CONT_VIA,*
V 100,250,CONT_VIA2,*
V 800,200,CONT_VIA,*
V 740,200,CONT_POLY,*
V 450,250,CONT_VIA2,*
V 740,250,CONT_POLY,*
V 350,300,CONT_POLY,*
V 350,250,CONT_POLY,*
V 300,150,CONT_POLY,*
V 640,350,CONT_POLY,*
V 400,200,CONT_POLY,*
V 520,300,CONT_POLY,*
V 620,200,CONT_POLY,*
V 520,150,CONT_POLY,*
V 740,150,CONT_POLY,*
V 500,350,CONT_POLY,*
V 500,100,CONT_POLY,*
V 200,300,CONT_POLY,*
V 50,300,CONT_POLY,*
V 50,150,CONT_POLY,*
V 300,300,CONT_POLY,*
V 690,30,CONT_BODY_P,*
V 630,30,CONT_BODY_P,*
V 200,30,CONT_BODY_P,*
V 100,30,CONT_BODY_P,*
V 270,50,CONT_DIF_N,*
V 810,100,CONT_DIF_N,*
V 750,100,CONT_DIF_N,*
V 870,100,CONT_DIF_N,*
V 750,50,CONT_DIF_N,*
V 870,50,CONT_DIF_N,*
V 570,100,CONT_DIF_N,*
V 390,100,CONT_DIF_N,*
V 510,50,CONT_DIF_N,*
V 630,100,CONT_DIF_N,*
V 150,150,CONT_DIF_N,*
V 750,450,CONT_DIF_P,*
V 870,450,CONT_DIF_P,*
V 750,400,CONT_DIF_P,*
V 750,350,CONT_DIF_P,*
V 390,350,CONT_DIF_P,*
V 810,350,CONT_DIF_P,*
V 510,450,CONT_DIF_P,*
V 630,400,CONT_DIF_P,*
V 810,400,CONT_DIF_P,*
V 870,350,CONT_DIF_P,*
V 870,400,CONT_DIF_P,*
V 750,300,CONT_DIF_P,*
V 810,300,CONT_DIF_P,*
V 870,300,CONT_DIF_P,*
V 570,400,CONT_DIF_P,*
V 200,470,CONT_BODY_N,*
V 270,450,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 100,470,CONT_BODY_N,*
V 250,300,CONT_POLY,*
V 250,150,CONT_POLY,*
V 250,200,CONT_VIA,*
V 100,150,CONT_POLY,*
V 30,50,CONT_DIF_N,*
V 30,450,CONT_DIF_P,*
V 500,250,CONT_VIA,*
V 500,200,CONT_POLY,*
V 350,250,CONT_VIA2,*
V 350,250,CONT_VIA,*
V 350,30,CONT_BODY_P,*
V 350,470,CONT_BODY_N,*
EOF

36
alliance/src/cells/src/dp_sxlib/dp_sff_x4.vbe Normal file
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@ -0,0 +1,36 @@
ENTITY dp_sff_x4 IS
PORT (
ckx : in BIT;
nckx : in BIT;
wenx : in BIT;
nwenx : in BIT;
i : in BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_sff_x4;
ARCHITECTURE vbe OF dp_sff_x4 IS
SIGNAL ff : REG_BIT REGISTER;
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on dp_sff_x4"
SEVERITY WARNING;
ASSERT (ckx xor nckx)
REPORT "wrong values for ckx and nckx in dp_sff_x4"
SEVERITY WARNING;
ASSERT (wenx xor nwenx)
REPORT "wrong values for wenx and nwenx in dp_sff_x4"
SEVERITY WARNING;
label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1')
BEGIN
ff <= GUARDED ((wenx and i) or (nwenx and ff));
END BLOCK label0;
q <= ff;
END;

250
alliance/src/cells/src/dp_sxlib/dp_sff_x4_buf.ap Normal file
View File

@ -0,0 +1,250 @@
V ALLIANCE : 6
H dp_sff_x4_buf,P,14/11/2000,10
A 0,0,900,1000
R 100,400,ref_ref,nwenx
R 200,400,ref_ref,wenx
R 350,400,ref_ref,nckx
R 450,400,ref_ref,ckx
S 100,600,450,600,20,*,RIGHT,TALU2
S 100,400,450,400,20,*,LEFT,TALU2
S 100,150,450,150,20,*,RIGHT,TALU2
S 150,850,150,850,10,wen,LEFT,CALU1
S 400,850,400,850,10,ck,LEFT,CALU1
S 350,150,350,600,20,nckx,DOWN,CALU3
S 450,150,450,600,20,ckx,UP,CALU3
S 70,770,480,770,80,*,RIGHT,NWELL
S 90,340,90,630,30,*,UP,PDIF
S 120,320,120,650,10,*,UP,PTRANS
S 270,340,270,630,30,*,DOWN,PDIF
S 30,340,30,630,30,*,UP,PDIF
S 210,730,210,800,30,*,UP,PDIF
S 60,320,60,650,10,*,UP,PTRANS
S 180,710,180,820,10,*,DOWN,PTRANS
S 160,730,160,800,30,*,UP,PDIF
S 120,710,120,820,10,*,DOWN,PTRANS
S 90,730,90,800,30,*,UP,PDIF
S 180,320,180,650,10,*,UP,PTRANS
S 210,340,210,630,30,*,UP,PDIF
S 240,320,240,650,10,*,DOWN,PTRANS
S 310,320,310,650,10,*,UP,PTRANS
S 400,340,400,630,30,*,UP,PDIF
S 340,340,340,630,30,*,UP,PDIF
S 370,320,370,650,10,*,UP,PTRANS
S 520,340,520,630,30,*,DOWN,PDIF
S 490,320,490,650,10,*,DOWN,PTRANS
S 460,340,460,630,30,*,UP,PDIF
S 430,320,430,650,10,*,UP,PTRANS
S 340,730,340,800,30,*,UP,PDIF
S 460,730,460,800,30,*,UP,PDIF
S 370,710,370,820,10,*,DOWN,PTRANS
S 410,730,410,800,30,*,UP,PDIF
S 430,710,430,820,10,*,DOWN,PTRANS
S 150,340,150,630,30,*,UP,PDIF
S 60,10,60,190,10,*,UP,NTRANS
S 120,10,120,190,10,*,DOWN,NTRANS
S 150,30,150,170,30,*,UP,NDIF
S 180,10,180,190,10,*,DOWN,NTRANS
S 210,30,210,170,30,*,UP,NDIF
S 240,10,240,190,10,*,DOWN,NTRANS
S 30,30,30,170,30,*,UP,NDIF
S 270,30,270,170,30,*,UP,NDIF
S 90,30,90,170,30,*,UP,NDIF
S 150,890,150,960,30,*,UP,NDIF
S 90,890,90,960,30,*,UP,NDIF
S 120,870,120,980,10,*,UP,NTRANS
S 310,10,310,190,10,*,UP,NTRANS
S 370,10,370,190,10,*,DOWN,NTRANS
S 520,30,520,170,30,*,UP,NDIF
S 430,10,430,190,10,*,DOWN,NTRANS
S 400,30,400,170,30,*,UP,NDIF
S 340,30,340,170,30,*,UP,NDIF
S 490,10,490,190,10,*,DOWN,NTRANS
S 460,30,460,170,30,*,UP,NDIF
S 340,890,340,960,30,*,UP,NDIF
S 400,890,400,960,30,*,UP,NDIF
S 370,870,370,980,10,*,UP,NTRANS
S 490,190,490,320,10,*,UP,POLY
S 120,820,120,870,10,*,DOWN,POLY
S 430,190,430,320,10,*,DOWN,POLY
S 60,190,60,320,10,*,DOWN,POLY
S 370,190,370,320,10,*,UP,POLY
S 120,190,120,320,10,*,UP,POLY
S 370,820,370,870,10,*,DOWN,POLY
S 370,850,430,850,30,*,RIGHT,POLY
S 430,820,430,860,10,*,DOWN,POLY
S 180,820,180,860,10,*,DOWN,POLY
S 120,850,180,850,30,*,RIGHT,POLY
S 310,190,310,320,10,*,DOWN,POLY
S 180,190,180,320,10,*,DOWN,POLY
S 240,190,240,320,10,*,UP,POLY
S 430,660,490,660,30,*,RIGHT,POLY
S 430,220,490,220,30,*,RIGHT,POLY
S 310,220,390,220,30,*,RIGHT,POLY
S 400,280,400,740,20,*,UP,ALU1
S 30,50,30,150,20,*,UP,ALU1
S 210,100,210,400,20,*,UP,ALU1
S 30,350,30,680,20,*,UP,ALU1
S 270,280,270,680,20,*,UP,ALU1
S 270,50,270,150,20,*,UP,ALU1
S 150,900,150,940,20,*,UP,ALU1
S 90,790,210,790,20,*,RIGHT,ALU1
S 340,100,340,400,20,*,UP,ALU1
S 150,50,150,150,20,*,UP,ALU1
S 150,280,150,740,20,*,UP,ALU1
S 30,900,30,970,20,*,DOWN,ALU1
S 520,50,520,150,20,*,UP,ALU1
S 400,50,400,150,20,*,UP,ALU1
S 520,280,520,680,20,*,UP,ALU1
S 460,100,460,400,20,*,UP,ALU1
S 90,100,90,400,20,*,UP,ALU1
S 460,660,460,790,20,*,DOWN,ALU1
S 340,740,340,900,20,*,UP,ALU1
S 520,900,520,970,20,*,UP,ALU1
S 400,900,400,940,20,*,UP,ALU1
S 340,790,460,790,20,*,RIGHT,ALU1
S 270,900,270,970,20,*,UP,ALU1
S 390,220,460,220,20,*,RIGHT,ALU1
S 600,50,600,150,20,*,UP,ALU1
S 0,500,900,500,460,*,RIGHT,NWELL
S 180,660,240,660,30,*,RIGHT,POLY
S 90,740,90,900,20,*,UP,ALU1
S 210,660,210,790,20,*,DOWN,ALU1
S 180,220,240,220,30,*,RIGHT,POLY
S 60,220,140,220,30,*,RIGHT,POLY
S 150,220,210,220,20,*,RIGHT,ALU1
S 100,150,100,600,20,nwenx,UP,CALU3
S 0,30,900,30,60,vss,RIGHT,CALU1
S 0,530,900,530,60,vdd,RIGHT,CALU1
S 0,470,900,470,60,vdd,RIGHT,CALU1
S 0,970,900,970,60,vss,RIGHT,CALU1
S 200,150,200,600,20,wenx,DOWN,CALU3
V 450,150,CONT_VIA,*
V 450,150,CONT_VIA2,*
V 200,150,CONT_VIA,*
V 200,150,CONT_VIA2,*
V 90,790,CONT_DIF_P,*
V 30,550,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,600,CONT_DIF_P,*
V 270,290,CONT_BODY_N,*
V 30,290,CONT_BODY_N,*
V 150,290,CONT_BODY_N,*
V 90,740,CONT_DIF_P,*
V 150,740,CONT_DIF_P,*
V 150,500,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 150,550,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,500,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 270,600,CONT_DIF_P,*
V 270,550,CONT_DIF_P,*
V 270,500,CONT_DIF_P,*
V 270,450,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 270,400,CONT_DIF_P,*
V 270,680,CONT_BODY_N,*
V 150,680,CONT_BODY_N,*
V 210,740,CONT_DIF_P,*
V 210,790,CONT_DIF_P,*
V 210,600,CONT_DIF_P,*
V 90,600,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 400,550,CONT_DIF_P,*
V 30,680,CONT_BODY_N,*
V 520,600,CONT_DIF_P,*
V 400,290,CONT_BODY_N,*
V 520,290,CONT_BODY_N,*
V 400,350,CONT_DIF_P,*
V 400,450,CONT_DIF_P,*
V 520,680,CONT_BODY_N,*
V 400,400,CONT_DIF_P,*
V 400,500,CONT_DIF_P,*
V 520,400,CONT_DIF_P,*
V 520,350,CONT_DIF_P,*
V 520,450,CONT_DIF_P,*
V 520,500,CONT_DIF_P,*
V 520,550,CONT_DIF_P,*
V 460,400,CONT_DIF_P,*
V 460,350,CONT_DIF_P,*
V 340,350,CONT_DIF_P,*
V 340,400,CONT_DIF_P,*
V 340,600,CONT_DIF_P,*
V 400,600,CONT_DIF_P,*
V 460,600,CONT_DIF_P,*
V 400,680,CONT_BODY_N,*
V 340,790,CONT_DIF_P,*
V 400,740,CONT_DIF_P,*
V 340,740,CONT_DIF_P,*
V 460,790,CONT_DIF_P,*
V 460,740,CONT_DIF_P,*
V 150,600,CONT_DIF_P,*
V 30,50,CONT_DIF_N,*
V 210,150,CONT_DIF_N,*
V 270,150,CONT_DIF_N,*
V 270,50,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 90,900,CONT_DIF_N,*
V 150,150,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 30,150,CONT_DIF_N,*
V 150,900,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 90,150,CONT_DIF_N,*
V 520,100,CONT_DIF_N,*
V 460,100,CONT_DIF_N,*
V 520,50,CONT_DIF_N,*
V 150,950,CONT_DIF_N,*
V 400,50,CONT_DIF_N,*
V 340,150,CONT_DIF_N,*
V 400,150,CONT_DIF_N,*
V 340,100,CONT_DIF_N,*
V 520,150,CONT_DIF_N,*
V 460,150,CONT_DIF_N,*
V 400,100,CONT_DIF_N,*
V 400,900,CONT_DIF_N,*
V 400,950,CONT_DIF_N,*
V 340,900,CONT_DIF_N,*
V 520,970,CONT_BODY_P,*
V 270,970,CONT_BODY_P,*
V 30,900,CONT_BODY_P,*
V 270,900,CONT_BODY_P,*
V 520,900,CONT_BODY_P,*
V 30,970,CONT_BODY_P,*
V 400,850,CONT_POLY,*
V 150,850,CONT_POLY,*
V 460,660,CONT_POLY,*
V 390,220,CONT_POLY,*
V 200,400,CONT_VIA,*
V 200,600,CONT_VIA,*
V 100,600,CONT_VIA,*
V 100,400,CONT_VIA,*
V 100,150,CONT_VIA,*
V 350,400,CONT_VIA,*
V 350,600,CONT_VIA,*
V 350,150,CONT_VIA,*
V 450,600,CONT_VIA,*
V 450,400,CONT_VIA,*
V 450,600,CONT_VIA2,*
V 350,150,CONT_VIA2,*
V 350,600,CONT_VIA2,*
V 100,150,CONT_VIA2,*
V 100,400,CONT_VIA2,*
V 200,400,CONT_VIA2,*
V 450,400,CONT_VIA2,*
V 350,400,CONT_VIA2,*
V 100,600,CONT_VIA2,*
V 200,600,CONT_VIA2,*
V 600,50,CONT_BODY_P,*
V 600,150,CONT_BODY_P,*
V 210,660,CONT_POLY,*
V 140,220,CONT_POLY,*
EOF

25
alliance/src/cells/src/dp_sxlib/dp_sff_x4_buf.vbe Normal file
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@ -0,0 +1,25 @@
ENTITY dp_sff_x4_buf IS
PORT (
ck : in BIT;
wen : in BIT;
ckx : out BIT;
nckx : out BIT;
wenx : out BIT;
nwenx : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_sff_x4_buf;
ARCHITECTURE vbe OF dp_sff_x4_buf IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on dp_sff_x4_buf"
SEVERITY WARNING;
ckx <= ck;
nckx <= not ck;
wenx <= wen;
nwenx <= not wen;
END;

2395
alliance/src/cells/src/dp_sxlib/dp_sxlib.lef Normal file
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File diff suppressed because it is too large Load Diff

110
alliance/src/cells/src/dp_sxlib/dp_ts_x4.ap Normal file
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@ -0,0 +1,110 @@
V ALLIANCE : 6
H dp_ts_x4,P,26/ 9/2000,100
A 0,0,4500,5000
R 1000,1000,ref_ref,q_10
R 1000,1500,ref_ref,q_15
R 1000,2000,ref_ref,q_20
R 1000,2500,ref_ref,q_25
R 1000,3000,ref_ref,q_30
R 1000,3500,ref_ref,q_35
R 1000,4000,ref_ref,q_40
R 1500,1000,ref_ref,i_10
R 1500,3000,ref_ref,i_30
R 1500,3500,ref_ref,i_35
R 1500,4000,ref_ref,i_40
R 1500,1500,ref_ref,i_15
R 1500,2000,ref_ref,i_20
R 1500,2500,ref_ref,i_25
R 2500,2000,ref_ref,nenx
R 3500,2000,ref_ref,enx
S 2000,3500,2400,3500,200,*,RIGHT,ALU1
S 2000,1000,3600,1000,200,*,RIGHT,ALU1
S 3500,2000,3500,2000,200,enx,LEFT,CALU3
S 2500,2000,2500,2000,200,nenx,LEFT,CALU3
S 2000,1000,2000,3500,100,*,DOWN,ALU1
S 2500,1500,2500,3000,100,*,DOWN,ALU1
S 3500,1500,3500,3000,100,*,DOWN,ALU1
S 2000,4000,4200,4000,100,*,RIGHT,ALU1
S 4200,1000,4200,4000,100,*,DOWN,ALU1
S 3500,1500,3700,1500,200,*,RIGHT,ALU1
S 3700,1500,3900,1500,300,*,RIGHT,POLY
S 3300,3000,3500,3000,300,*,RIGHT,POLY
S 2500,3000,2700,3000,300,*,RIGHT,POLY
S 2500,1500,2700,1500,300,*,RIGHT,POLY
S 3900,2000,3900,3100,100,*,UP,POLY
S 3300,1400,3300,2000,100,*,DOWN,POLY
S 1500,2000,3900,2000,100,*,RIGHT,POLY
S 600,1400,2000,1400,100,*,RIGHT,POLY
S 600,2600,1900,2600,100,*,LEFT,POLY
S 1900,2600,1900,4000,100,*,DOWN,POLY
S 0,3900,4500,3900,2400,*,LEFT,NWELL
S 2700,3100,2700,4400,100,*,UP,PTRANS
S 3600,3300,3600,4700,300,*,UP,PDIF
S 4200,3300,4200,4200,300,*,UP,PDIF
S 3900,3100,3900,4400,100,*,UP,PTRANS
S 3000,3300,3000,4200,300,*,UP,PDIF
S 3300,3100,3300,4400,100,*,UP,PTRANS
S 2400,3300,2400,4200,300,*,UP,PDIF
S 2400,800,2400,1200,300,*,UP,NDIF
S 3600,800,3600,1200,300,*,UP,NDIF
S 3000,400,3000,1200,300,*,UP,NDIF
S 3300,600,3300,1400,100,*,UP,NTRANS
S 2700,600,2700,1400,100,*,UP,NTRANS
S 4200,800,4200,1200,300,*,UP,NDIF
S 3900,600,3900,1400,100,*,UP,NTRANS
S 300,500,300,1000,200,*,DOWN,ALU1
S 300,3000,300,4500,200,*,DOWN,ALU1
S 900,2800,900,4700,300,*,UP,PDIF
S 1500,2800,1500,4700,300,*,UP,PDIF
S 1200,2600,1200,4900,100,*,UP,PTRANS
S 300,2800,300,4700,300,*,UP,PDIF
S 600,2600,600,4900,100,*,UP,PTRANS
S 300,300,300,1200,300,*,UP,NDIF
S 1200,100,1200,1400,100,*,UP,NTRANS
S 600,100,600,1400,100,*,UP,NTRANS
S 1500,300,1500,1200,300,*,UP,NDIF
S 900,300,900,1200,300,*,UP,NDIF
S 2500,2000,3500,2000,200,*,RIGHT,TALU2
S 0,300,4500,300,600,vss,RIGHT,CALU1
S 0,4700,4500,4700,600,vdd,LEFT,CALU1
S 1000,1000,1000,4000,200,q,UP,CALU1
S 1500,1000,1500,4000,200,i,UP,CALU1
V 3500,3000,CONT_POLY,*
V 3700,1500,CONT_POLY,*
V 3500,2000,CONT_VIA,*
V 3500,2000,CONT_VIA2,*
V 2500,3000,CONT_POLY,*
V 2500,1500,CONT_POLY,*
V 2500,2000,CONT_VIA,*
V 2500,2000,CONT_VIA2,*
V 1500,2000,CONT_POLY,*
V 2000,1500,CONT_POLY,*
V 2000,1500,CONT_POLY,*
V 2000,4000,CONT_POLY,*
V 2400,3500,CONT_DIF_P,*
V 3000,4000,CONT_DIF_P,*
V 3600,4500,CONT_DIF_P,*
V 4200,4000,CONT_DIF_P,*
V 3000,4700,CONT_BODY_N,*
V 2200,4700,CONT_BODY_N,*
V 4200,4700,CONT_BODY_N,*
V 4200,1000,CONT_DIF_N,*
V 2400,1000,CONT_DIF_N,*
V 3600,1000,CONT_DIF_N,*
V 3000,500,CONT_DIF_N,*
V 3600,300,CONT_BODY_P,*
V 4200,300,CONT_BODY_P,*
V 900,3000,CONT_DIF_P,*
V 2100,300,CONT_BODY_P,*
V 300,1000,CONT_DIF_N,*
V 900,1000,CONT_DIF_N,*
V 900,3500,CONT_DIF_P,*
V 900,4000,CONT_DIF_P,*
V 300,3000,CONT_DIF_P,*
V 1500,4500,CONT_DIF_P,*
V 300,500,CONT_DIF_N,*
V 1500,500,CONT_DIF_N,*
V 300,4500,CONT_DIF_P,*
V 300,3500,CONT_DIF_P,*
V 300,4000,CONT_DIF_P,*
EOF

28
alliance/src/cells/src/dp_sxlib/dp_ts_x4.vbe Normal file
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@ -0,0 +1,28 @@
ENTITY dp_ts_x4 IS
PORT (
enx : in BIT;
nenx : in BIT;
i : in BIT;
q : out MUX_BIT BUS;
vdd : in BIT;
vss : in BIT
);
END dp_ts_x4;
ARCHITECTURE vbe OF dp_ts_x4 IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_ts_x4"
SEVERITY WARNING;
ASSERT (enx xor nenx)
REPORT "wrong control signals on dp_ts_x4"
SEVERITY WARNING;
label0 : BLOCK (enx = '1')
BEGIN
q <= GUARDED i;
END BLOCK label0;
END;

142
alliance/src/cells/src/dp_sxlib/dp_ts_x4_buf.ap Normal file
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@ -0,0 +1,142 @@
V ALLIANCE : 6
H dp_ts_x4_buf,P,15/11/2000,100
A 0,0,4500,10000
R 3500,4000,ref_ref,enx
R 2500,4000,ref_ref,nenx
S 3400,1500,3600,1500,200,*,LEFT,ALU2
S 0,9700,4500,9700,600,vss,RIGHT,CALU1
S 0,300,4500,300,600,vss,RIGHT,CALU1
S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
S 0,5300,4500,5300,600,vdd,RIGHT,CALU1
S 3500,1500,3500,6000,200,enx,DOWN,CALU3
S 2500,1500,2500,6000,200,nenx,DOWN,CALU3
S 0,5000,4500,5000,4600,*,RIGHT,NWELL
S 3300,7100,3300,8200,100,*,DOWN,PTRANS
S 3300,3200,3300,6500,100,*,UP,PTRANS
S 3600,3400,3600,6300,300,*,UP,PDIF
S 3900,3200,3900,6500,100,*,DOWN,PTRANS
S 2400,7300,2400,8000,300,*,UP,PDIF
S 4200,3400,4200,6300,300,*,DOWN,PDIF
S 2700,3200,2700,6500,100,*,UP,PTRANS
S 2400,3400,2400,6300,300,*,UP,PDIF
S 3000,3400,3000,6300,300,*,UP,PDIF
S 2100,3200,2100,6500,100,*,UP,PTRANS
S 1800,3400,1800,6300,300,*,UP,PDIF
S 3600,7300,3600,8000,300,*,UP,PDIF
S 2700,7100,2700,8200,100,*,DOWN,PTRANS
S 3100,7300,3100,8000,300,*,UP,PDIF
S 2700,8700,2700,9800,100,*,UP,NTRANS
S 3300,100,3300,1900,100,*,DOWN,NTRANS
S 2100,100,2100,1900,100,*,UP,NTRANS
S 2700,100,2700,1900,100,*,DOWN,NTRANS
S 3900,100,3900,1900,100,*,DOWN,NTRANS
S 2400,8900,2400,9600,300,*,UP,NDIF
S 2400,300,2400,1700,300,*,UP,NDIF
S 4200,300,4200,1700,300,*,UP,NDIF
S 1800,300,1800,1700,300,*,UP,NDIF
S 3000,8900,3000,9600,300,*,UP,NDIF
S 3000,300,3000,1700,300,*,UP,NDIF
S 3600,300,3600,1700,300,*,UP,NDIF
S 2700,8500,3300,8500,300,*,RIGHT,POLY
S 3300,1900,3300,3200,100,*,DOWN,POLY
S 3900,1900,3900,3200,100,*,UP,POLY
S 2700,1900,2700,3200,100,*,UP,POLY
S 2100,1900,2100,3200,100,*,DOWN,POLY
S 2700,8200,2700,8700,100,*,DOWN,POLY
S 3300,8200,3300,8600,100,*,DOWN,POLY
S 2400,1000,2400,4000,200,*,UP,ALU1
S 3600,1000,3600,4000,200,*,UP,ALU1
S 3000,500,3000,1500,200,*,UP,ALU1
S 2400,7900,3600,7900,200,*,RIGHT,ALU1
S 1800,500,1800,1500,200,*,UP,ALU1
S 4200,2800,4200,6800,200,*,UP,ALU1
S 4200,500,4200,1500,200,*,UP,ALU1
S 4200,9000,4200,9700,200,*,UP,ALU1
S 3000,9000,3000,9400,200,*,UP,ALU1
S 1800,3500,1800,6800,200,*,UP,ALU1
S 700,300,700,1500,200,*,DOWN,ALU1
S 3000,2800,3000,7400,200,*,UP,ALU1
S 1800,9000,1800,9700,200,*,DOWN,ALU1
S 3300,6600,3900,6600,300,*,RIGHT,POLY
S 3600,6600,3600,7900,200,*,UP,ALU1
S 2400,7400,2400,9000,200,*,DOWN,ALU1
S 2100,2200,3000,2200,300,*,RIGHT,POLY
S 3300,2200,3900,2200,300,*,RIGHT,POLY
S 2900,2200,3600,2200,200,*,RIGHT,ALU1
S 3000,8500,3000,8500,100,en,LEFT,CALU1
S 2500,1500,3600,1500,200,*,RIGHT,TALU2
S 2500,4000,3500,4000,200,*,LEFT,TALU2
S 2500,6000,3500,6000,200,*,RIGHT,TALU2
V 3500,1500,CONT_VIA2,*
V 1800,6800,CONT_BODY_N,*
V 4200,6800,CONT_BODY_N,*
V 3000,6800,CONT_BODY_N,*
V 3600,7400,CONT_DIF_P,*
V 3600,7900,CONT_DIF_P,*
V 3600,6000,CONT_DIF_P,*
V 2400,6000,CONT_DIF_P,*
V 2400,4000,CONT_DIF_P,*
V 2400,3500,CONT_DIF_P,*
V 3600,3500,CONT_DIF_P,*
V 3600,4000,CONT_DIF_P,*
V 4200,6000,CONT_DIF_P,*
V 4200,5500,CONT_DIF_P,*
V 4200,5000,CONT_DIF_P,*
V 4200,4500,CONT_DIF_P,*
V 4200,3500,CONT_DIF_P,*
V 4200,4000,CONT_DIF_P,*
V 3000,5000,CONT_DIF_P,*
V 3000,4000,CONT_DIF_P,*
V 3000,5500,CONT_DIF_P,*
V 3000,4500,CONT_DIF_P,*
V 3000,3500,CONT_DIF_P,*
V 1800,4000,CONT_DIF_P,*
V 1800,4500,CONT_DIF_P,*
V 1800,5000,CONT_DIF_P,*
V 1800,5500,CONT_DIF_P,*
V 1800,3500,CONT_DIF_P,*
V 1800,6000,CONT_DIF_P,*
V 4200,2900,CONT_BODY_N,*
V 1800,2900,CONT_BODY_N,*
V 3000,2900,CONT_BODY_N,*
V 2400,7400,CONT_DIF_P,*
V 3000,7400,CONT_DIF_P,*
V 2400,7900,CONT_DIF_P,*
V 3000,500,CONT_DIF_N,*
V 2400,1000,CONT_DIF_N,*
V 2400,1500,CONT_DIF_N,*
V 2400,9000,CONT_DIF_N,*
V 3000,1500,CONT_DIF_N,*
V 4200,1000,CONT_DIF_N,*
V 3000,1000,CONT_DIF_N,*
V 1800,1000,CONT_DIF_N,*
V 1800,1500,CONT_DIF_N,*
V 1800,500,CONT_DIF_N,*
V 3600,1500,CONT_DIF_N,*
V 4200,1500,CONT_DIF_N,*
V 4200,500,CONT_DIF_N,*
V 3600,1000,CONT_DIF_N,*
V 3000,9000,CONT_DIF_N,*
V 3000,9500,CONT_DIF_N,*
V 1800,9000,CONT_BODY_P,*
V 4200,9000,CONT_BODY_P,*
V 1800,9700,CONT_BODY_P,*
V 4200,9700,CONT_BODY_P,*
V 700,300,CONT_BODY_P,*
V 700,1500,CONT_BODY_P,*
V 700,900,CONT_BODY_P,*
V 3000,8500,CONT_POLY,*
V 2500,1500,CONT_VIA,*
V 3500,4000,CONT_VIA,*
V 3600,1500,CONT_VIA,*
V 3500,6000,CONT_VIA,*
V 2500,6000,CONT_VIA,*
V 2500,4000,CONT_VIA,*
V 2500,1500,CONT_VIA2,*
V 3500,4000,CONT_VIA2,*
V 2500,4000,CONT_VIA2,*
V 2500,6000,CONT_VIA2,*
V 3500,6000,CONT_VIA2,*
V 3600,6600,CONT_POLY,*
V 2900,2200,CONT_POLY,*
EOF

21
alliance/src/cells/src/dp_sxlib/dp_ts_x4_buf.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY dp_ts_x4_buf IS
PORT (
en : in BIT;
enx : out BIT;
nenx : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_ts_x4_buf;
ARCHITECTURE vbe OF dp_ts_x4_buf IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_ts_x4_buf"
SEVERITY WARNING;
enx <= en;
nenx <= not en;
END;

126
alliance/src/cells/src/dp_sxlib/dp_ts_x8.ap Normal file
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@ -0,0 +1,126 @@
V ALLIANCE : 6
H dp_ts_x8,P,15/11/2000,100
A 0,0,5500,5000
R 4500,2000,ref_ref,enx
R 3500,2000,ref_ref,nenx
R 1000,1500,ref_ref,q_15
R 1000,4000,ref_ref,q_40
R 1000,3500,ref_ref,q_35
R 500,1500,ref_ref,i_15
R 500,3500,ref_ref,i_35
R 500,3000,ref_ref,i_30
R 500,1000,ref_ref,i_10
R 1000,1000,ref_ref,q_10
R 1000,3000,ref_ref,q_30
R 1000,2500,ref_ref,q_25
R 1000,2000,ref_ref,q_20
R 500,4000,ref_ref,i_40
R 500,2500,ref_ref,i_25
R 500,2000,ref_ref,i_20
S 700,1400,3000,1400,100,*,RIGHT,POLY
S 700,2600,3000,2600,100,*,LEFT,POLY
S 500,1000,500,4000,200,i,UP,CALU1
S 1000,1000,1000,4000,200,q,UP,CALU1
S 0,4700,5500,4700,600,vdd,LEFT,CALU1
S 0,300,5500,300,600,vss,RIGHT,CALU1
S 1000,2000,2200,2000,200,*,RIGHT,ALU1
S 700,2600,700,4900,100,*,UP,PTRANS
S 1300,2600,1300,4900,100,*,UP,PTRANS
S 400,2800,400,4700,300,*,UP,PDIF
S 1000,2800,1000,4700,300,*,UP,PDIF
S 2500,2600,2500,4900,100,*,UP,PTRANS
S 1600,2800,1600,4700,300,*,UP,PDIF
S 1900,2600,1900,4900,100,*,UP,PTRANS
S 2200,2800,2200,4700,300,*,UP,PDIF
S 2800,2800,2800,4700,300,*,UP,PDIF
S 1300,100,1300,1400,100,*,UP,NTRANS
S 700,100,700,1400,100,*,UP,NTRANS
S 2500,100,2500,1400,100,*,UP,NTRANS
S 1900,100,1900,1400,100,*,UP,NTRANS
S 1600,300,1600,1200,300,*,UP,NDIF
S 400,300,400,1200,300,*,UP,NDIF
S 1000,300,1000,1200,300,*,UP,NDIF
S 2800,300,2800,1200,300,*,UP,NDIF
S 2200,300,2200,1200,300,*,UP,NDIF
S 1600,500,1600,1000,200,*,DOWN,ALU1
S 1600,3000,1600,4500,200,*,DOWN,ALU1
S 2200,1000,2200,4000,200,*,UP,ALU1
S 0,3900,5500,3900,2400,*,LEFT,NWELL
S 3700,3100,3700,4400,100,*,UP,PTRANS
S 4600,3300,4600,4700,300,*,UP,PDIF
S 5200,3300,5200,4200,300,*,UP,PDIF
S 4900,3100,4900,4400,100,*,UP,PTRANS
S 4000,3300,4000,4200,300,*,UP,PDIF
S 4300,3100,4300,4400,100,*,UP,PTRANS
S 3400,3300,3400,4200,300,*,UP,PDIF
S 4300,600,4300,1400,100,*,UP,NTRANS
S 3700,600,3700,1400,100,*,UP,NTRANS
S 4900,600,4900,1400,100,*,UP,NTRANS
S 3400,800,3400,1200,300,*,UP,NDIF
S 4600,800,4600,1200,300,*,UP,NDIF
S 4000,400,4000,1200,300,*,UP,NDIF
S 5200,800,5200,1200,300,*,UP,NDIF
S 500,2000,4900,2000,100,*,RIGHT,POLY
S 4700,1500,4900,1500,300,*,RIGHT,POLY
S 4300,3000,4500,3000,300,*,RIGHT,POLY
S 3500,3000,3700,3000,300,*,RIGHT,POLY
S 3500,1500,3700,1500,300,*,RIGHT,POLY
S 4900,2000,4900,3100,100,*,UP,POLY
S 4300,1400,4300,2000,100,*,DOWN,POLY
S 2900,4000,5200,4000,100,*,RIGHT,ALU1
S 2900,1000,2900,1500,100,*,DOWN,ALU1
S 4000,1000,4000,3500,100,*,DOWN,ALU1
S 5200,1000,5200,4000,100,*,DOWN,ALU1
S 3500,1500,3500,3000,200,*,DOWN,ALU1
S 2900,2500,2900,4000,100,*,DOWN,ALU1
S 2900,1000,4600,1000,100,*,RIGHT,ALU1
S 3400,3500,4000,3500,100,*,RIGHT,ALU1
S 4500,1500,4700,1500,200,*,RIGHT,ALU1
S 3500,2000,4500,2000,200,*,RIGHT,TALU2
S 4500,2000,4500,2000,200,enx,LEFT,CALU3
S 3500,2000,3500,2000,200,nenx,LEFT,CALU3
S 4500,1500,4500,3000,200,*,DOWN,ALU1
V 3400,4700,CONT_BODY_N,*
V 3400,300,CONT_BODY_P,*
V 2200,4000,CONT_DIF_P,*
V 2200,3500,CONT_DIF_P,*
V 400,4500,CONT_DIF_P,*
V 1000,3500,CONT_DIF_P,*
V 1000,4000,CONT_DIF_P,*
V 1000,3000,CONT_DIF_P,*
V 2200,3000,CONT_DIF_P,*
V 1600,3000,CONT_DIF_P,*
V 1600,4500,CONT_DIF_P,*
V 2800,4500,CONT_DIF_P,*
V 1600,3500,CONT_DIF_P,*
V 1600,4000,CONT_DIF_P,*
V 1600,1000,CONT_DIF_N,*
V 2200,1000,CONT_DIF_N,*
V 1600,500,CONT_DIF_N,*
V 1000,1000,CONT_DIF_N,*
V 400,500,CONT_DIF_N,*
V 2800,500,CONT_DIF_N,*
V 500,2000,CONT_POLY,*
V 5200,4000,CONT_DIF_P,*
V 4000,4700,CONT_BODY_N,*
V 5200,4700,CONT_BODY_N,*
V 3400,3500,CONT_DIF_P,*
V 4000,4000,CONT_DIF_P,*
V 4600,4500,CONT_DIF_P,*
V 5200,1000,CONT_DIF_N,*
V 3400,1000,CONT_DIF_N,*
V 4600,1000,CONT_DIF_N,*
V 4000,500,CONT_DIF_N,*
V 4600,300,CONT_BODY_P,*
V 5200,300,CONT_BODY_P,*
V 2900,2500,CONT_POLY,*
V 4500,3000,CONT_POLY,*
V 4700,1500,CONT_POLY,*
V 3500,3000,CONT_POLY,*
V 3500,1500,CONT_POLY,*
V 2900,1500,CONT_POLY,*
V 4500,2000,CONT_VIA,*
V 3500,2000,CONT_VIA,*
V 4500,2000,CONT_VIA2,*
V 3500,2000,CONT_VIA2,*
EOF

28
alliance/src/cells/src/dp_sxlib/dp_ts_x8.vbe Normal file
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@ -0,0 +1,28 @@
ENTITY dp_ts_x8 IS
PORT (
enx : in BIT;
nenx : in BIT;
i : in BIT;
q : out MUX_BIT BUS;
vdd : in BIT;
vss : in BIT
);
END dp_ts_x8;
ARCHITECTURE vbe OF dp_ts_x8 IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_ts_x8"
SEVERITY WARNING;
ASSERT (enx xor nenx)
REPORT "wrong control signals on dp_ts_x8"
SEVERITY WARNING;
label0 : BLOCK (enx = '1')
BEGIN
q <= GUARDED i;
END BLOCK label0;
END;

142
alliance/src/cells/src/dp_sxlib/dp_ts_x8_buf.ap Normal file
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@ -0,0 +1,142 @@
V ALLIANCE : 6
H dp_ts_x8_buf,P,14/11/2000,10
A -100,0,450,1000
R 250,400,ref_ref,nenx
R 350,400,ref_ref,enx
S 250,600,350,600,20,*,RIGHT,TALU2
S 250,400,350,400,20,*,RIGHT,TALU2
S 250,150,350,150,20,*,RIGHT,TALU2
S -100,970,450,970,60,vss,RIGHT,CALU1
S -100,30,450,30,60,vss,RIGHT,CALU1
S -100,500,450,500,460,*,RIGHT,NWELL
S -100,470,450,470,60,vdd,RIGHT,CALU1
S -100,530,450,530,60,vdd,RIGHT,CALU1
S 330,220,390,220,30,*,RIGHT,POLY
S 290,220,360,220,20,*,RIGHT,ALU1
S 210,220,300,220,30,*,RIGHT,POLY
S 360,660,360,790,20,*,UP,ALU1
S 240,740,240,900,20,*,DOWN,ALU1
S 330,660,390,660,30,*,RIGHT,POLY
S 180,900,180,970,20,*,DOWN,ALU1
S 300,280,300,740,20,*,UP,ALU1
S 70,30,70,150,20,*,DOWN,ALU1
S 180,350,180,680,20,*,UP,ALU1
S 300,900,300,940,20,*,UP,ALU1
S 420,900,420,970,20,*,UP,ALU1
S 420,50,420,150,20,*,UP,ALU1
S 420,280,420,680,20,*,UP,ALU1
S 180,50,180,150,20,*,UP,ALU1
S 240,790,360,790,20,*,RIGHT,ALU1
S 300,50,300,150,20,*,UP,ALU1
S 360,100,360,400,20,*,UP,ALU1
S 240,100,240,400,20,*,UP,ALU1
S 330,820,330,860,10,*,DOWN,POLY
S 270,820,270,870,10,*,DOWN,POLY
S 210,190,210,320,10,*,DOWN,POLY
S 270,190,270,320,10,*,UP,POLY
S 390,190,390,320,10,*,UP,POLY
S 330,190,330,320,10,*,DOWN,POLY
S 270,850,330,850,30,*,RIGHT,POLY
S 360,30,360,170,30,*,UP,NDIF
S 300,30,300,170,30,*,UP,NDIF
S 300,890,300,960,30,*,UP,NDIF
S 180,30,180,170,30,*,UP,NDIF
S 420,30,420,170,30,*,UP,NDIF
S 240,30,240,170,30,*,UP,NDIF
S 240,890,240,960,30,*,UP,NDIF
S 390,10,390,190,10,*,DOWN,NTRANS
S 270,10,270,190,10,*,DOWN,NTRANS
S 210,10,210,190,10,*,UP,NTRANS
S 330,10,330,190,10,*,DOWN,NTRANS
S 270,870,270,980,10,*,UP,NTRANS
S 310,730,310,800,30,*,UP,PDIF
S 270,710,270,820,10,*,DOWN,PTRANS
S 360,730,360,800,30,*,UP,PDIF
S 180,340,180,630,30,*,UP,PDIF
S 210,320,210,650,10,*,UP,PTRANS
S 300,340,300,630,30,*,UP,PDIF
S 240,340,240,630,30,*,UP,PDIF
S 270,320,270,650,10,*,UP,PTRANS
S 420,340,420,630,30,*,DOWN,PDIF
S 240,730,240,800,30,*,UP,PDIF
S 390,320,390,650,10,*,DOWN,PTRANS
S 360,340,360,630,30,*,UP,PDIF
S 330,320,330,650,10,*,UP,PTRANS
S 330,710,330,820,10,*,DOWN,PTRANS
S 250,150,250,600,20,nenx,DOWN,CALU3
S 350,150,350,600,20,enx,DOWN,CALU3
S 300,850,300,850,10,en,LEFT,CALU1
S 350,150,360,150,20,*,RIGHT,ALU1
V 290,220,CONT_POLY,*
V 360,660,CONT_POLY,*
V 350,600,CONT_VIA2,*
V 250,600,CONT_VIA2,*
V 250,400,CONT_VIA2,*
V 350,400,CONT_VIA2,*
V 250,150,CONT_VIA2,*
V 250,400,CONT_VIA,*
V 250,600,CONT_VIA,*
V 350,600,CONT_VIA,*
V 350,400,CONT_VIA,*
V 250,150,CONT_VIA,*
V 300,850,CONT_POLY,*
V 70,90,CONT_BODY_P,*
V 70,150,CONT_BODY_P,*
V 70,30,CONT_BODY_P,*
V 420,970,CONT_BODY_P,*
V 180,970,CONT_BODY_P,*
V 420,900,CONT_BODY_P,*
V 180,900,CONT_BODY_P,*
V 300,950,CONT_DIF_N,*
V 300,900,CONT_DIF_N,*
V 360,100,CONT_DIF_N,*
V 420,50,CONT_DIF_N,*
V 420,150,CONT_DIF_N,*
V 360,150,CONT_DIF_N,*
V 180,50,CONT_DIF_N,*
V 180,150,CONT_DIF_N,*
V 180,100,CONT_DIF_N,*
V 300,100,CONT_DIF_N,*
V 420,100,CONT_DIF_N,*
V 300,150,CONT_DIF_N,*
V 240,900,CONT_DIF_N,*
V 240,150,CONT_DIF_N,*
V 240,100,CONT_DIF_N,*
V 300,50,CONT_DIF_N,*
V 240,790,CONT_DIF_P,*
V 300,740,CONT_DIF_P,*
V 240,740,CONT_DIF_P,*
V 300,290,CONT_BODY_N,*
V 180,290,CONT_BODY_N,*
V 420,290,CONT_BODY_N,*
V 180,600,CONT_DIF_P,*
V 180,350,CONT_DIF_P,*
V 180,550,CONT_DIF_P,*
V 180,500,CONT_DIF_P,*
V 180,450,CONT_DIF_P,*
V 180,400,CONT_DIF_P,*
V 300,350,CONT_DIF_P,*
V 300,450,CONT_DIF_P,*
V 300,550,CONT_DIF_P,*
V 300,400,CONT_DIF_P,*
V 300,500,CONT_DIF_P,*
V 420,400,CONT_DIF_P,*
V 420,350,CONT_DIF_P,*
V 420,450,CONT_DIF_P,*
V 420,500,CONT_DIF_P,*
V 420,550,CONT_DIF_P,*
V 420,600,CONT_DIF_P,*
V 360,400,CONT_DIF_P,*
V 360,350,CONT_DIF_P,*
V 240,350,CONT_DIF_P,*
V 240,400,CONT_DIF_P,*
V 240,600,CONT_DIF_P,*
V 360,600,CONT_DIF_P,*
V 360,790,CONT_DIF_P,*
V 360,740,CONT_DIF_P,*
V 300,680,CONT_BODY_N,*
V 420,680,CONT_BODY_N,*
V 180,680,CONT_BODY_N,*
V 350,150,CONT_VIA2,*
V 350,150,CONT_VIA,*
EOF

21
alliance/src/cells/src/dp_sxlib/dp_ts_x8_buf.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY dp_ts_x8_buf IS
PORT (
en : in BIT;
enx : out BIT;
nenx : out BIT;
vdd : in BIT;
vss : in BIT
);
END dp_ts_x8_buf;
ARCHITECTURE vbe OF dp_ts_x8_buf IS
BEGIN
ASSERT (vdd and not vss)
REPORT "power supply is missing on dp_ts_x8_buf"
SEVERITY WARNING;
enx <= en;
nenx <= not en;
END;

35
alliance/src/cells/src/padlib/CATAL Normal file
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@ -0,0 +1,35 @@
padreal G
padreal C
pck_sp C
pi_sp C
piot_sp C
piotw_sp C
pot_sp C
potw_sp C
po_sp C
pow_sp C
pvdde_sp C
pvddeck_sp C
pvddi_sp C
pvddick_sp C
pvsse_sp C
pvsseck_sp C
pvssi_sp C
pvssick_sp C
palck_sp C
pali_sp C
paliot_sp C
paliotw_sp C
palo_sp C
palot_sp C
palotw_sp C
palow_sp C
palvdde_sp C
palvddeck_sp C
palvddi_sp C
palvddick_sp C
palvsse_sp C
palvsseck_sp C
palvssi_sp C
palvssick_sp C
corner_sp C

6
alliance/src/cells/src/padlib/Makefile.am Normal file
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@ -0,0 +1,6 @@
# $Id: Makefile.am,v 1.1 2002/04/29 15:51:50 czo Exp $
padlib_DATA=CATAL corner_sp.ap corner_sp.vbe padreal.ap padreal.cif padsymb.db palck_sp.ap pali_sp.ap paliot_sp.ap paliotw_sp.ap palo_sp.ap palot_sp.ap palotw_sp.ap palow_sp.ap palvdde_sp.ap palvddeck_sp.ap palvddi_sp.ap palvddick_sp.ap palvsse_sp.ap palvsseck_sp.ap palvssi_sp.ap palvssick_sp.ap pck_sp.al pck_sp.ap pck_sp.vbe pi_sp.al pi_sp.ap pi_sp.vbe piot_sp.al piot_sp.ap piot_sp.vbe piotw_sp.al piotw_sp.ap piotw_sp.vbe po_sp.al po_sp.ap po_sp.vbe pot_sp.al pot_sp.ap pot_sp.vbe potw_sp.al potw_sp.ap potw_sp.vbe pow_sp.al pow_sp.ap pow_sp.vbe pvdde_sp.al pvdde_sp.ap pvdde_sp.vbe pvddeck_sp.al pvddeck_sp.ap pvddeck_sp.vbe pvddi_sp.al pvddi_sp.ap pvddi_sp.vbe pvddick_sp.al pvddick_sp.ap pvddick_sp.vbe pvsse_sp.al pvsse_sp.ap pvsse_sp.vbe pvsseck_sp.al pvsseck_sp.ap pvsseck_sp.vbe pvssi_sp.al pvssi_sp.ap pvssi_sp.vbe pvssick_sp.al pvssick_sp.ap pvssick_sp.vbe
EXTRA_DIST=$(dp_padlib)

24
alliance/src/cells/src/padlib/corner_sp.ap Normal file
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@ -0,0 +1,24 @@
V ALLIANCE : 6
H corner_sp,P,13/10/2000,100
A 0,0,50000,50000
C 48700,0,1200,ck,0,SOUTH,ALU2
C 45300,0,4000,vssi,0,SOUTH,ALU2
C 40900,0,4000,vddi,0,SOUTH,ALU2
C 19700,0,12000,vsse,0,SOUTH,ALU2
C 32500,0,12000,vdde,0,SOUTH,ALU2
C 50000,4700,4000,vssi,1,EAST,ALU2
C 50000,9100,4000,vddi,1,EAST,ALU2
C 50000,30300,12000,vsse,1,EAST,ALU2
C 50000,17500,12000,vdde,1,EAST,ALU2
C 50000,1300,1200,ck,1,EAST,ALU2
S 19700,0,19700,36200,12000,*,UP,ALU2
S 48200,1300,50000,1300,1200,*,RIGHT,ALU2
S 48700,100,48700,1800,1200,*,UP,ALU2
S 43400,4700,50000,4700,4000,*,LEFT,ALU2
S 45300,0,45300,6600,4000,*,UP,ALU2
S 39000,9100,50000,9100,4000,*,LEFT,ALU2
S 40900,0,40900,11000,4000,*,UP,ALU2
S 26600,17500,50000,17500,12000,*,LEFT,ALU2
S 32500,0,32500,23400,12000,*,UP,ALU2
S 13800,30300,50000,30300,12000,*,LEFT,ALU2
EOF

27
alliance/src/cells/src/padlib/corner_sp.vbe Normal file
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@ -0,0 +1,27 @@
-- VHDL data flow description generated from `corner_sp`
-- date : Thu Feb 23 17:06:23 1995
-- Entity Declaration
ENTITY corner_sp IS
PORT (
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END corner_sp;
-- Architecture Declaration
ARCHITECTURE behaviour_data_flow OF corner_sp IS
BEGIN
ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
REPORT "power supply is missing on corner_sp"
SEVERITY WARNING;
END;

7
alliance/src/cells/src/padlib/padreal.ap Normal file
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@ -0,0 +1,7 @@
V ALLIANCE : 6
H padreal,P,13/10/2000,100
A 0,7600,17200,21300
C 8600,7600,10000,in,0,SOUTH,ALU1
S 8600,7700,8600,21200,10000,*,UP,ALU1
B 8600,15200,12200,12200,CONT_VIA,*
EOF

24
alliance/src/cells/src/padlib/padreal.cif Normal file
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@ -0,0 +1,24 @@
(rds to CIF driver version 1.03
technology /users/alc/distrib/dev/alliance-3.2/etc/prol10_7.rds
Wed May 21 16:49:13 1997
padreal
distrib);
DS1 5 2;
9 padreal;
(AB : 0.00, 0.00 150.50, 118.15 in micron);
4A 0 0 6020 4726;
LCC;
B4000 4000 3010 3320;
LCM;
B3500 1320 3010 660;
B4400 4400 3010 3320;
LCM2;
B4400 4400 3010 3320;
LCG;
B4000 4000 3010 3320;
DF;
C1;
(AB : 0.00, 0.00 150.50, 118.15 in micron);
E

60
alliance/src/cells/src/padlib/padsymb.db Normal file
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@ -0,0 +1,60 @@
#cell1 padsymb any library 31744 v7r5.6
# 24-Nov-91 14:16 24-Nov-91 14:16 stacs * .
v1(50,padsymb
(33,CP
[padreal,cp]
[palck_sp,cp]
[pali_sp,cp]
[paliot_sp,cp]
[paliotw_sp,cp]
[palo_sp,cp]
[palot_sp,cp]
[palotw_sp,cp]
[palow_sp,cp]
[palvdde_sp,cp]
[palvddeck_sp,cp]
[palvddi_sp,cp]
[palvddick_sp,cp]
[palvsse_sp,cp]
[palvsseck_sp,cp]
[palvssi_sp,cp]
[palvssick_sp,cp]
[pck_sp,cp]
[pi_sp,cp]
[piot_sp,cp]
[piotw_sp,cp]
[po_sp,cp]
[pot_sp,cp]
[potw_sp,cp]
[pow_sp,cp]
[pvdde_sp,cp]
[pvddeck_sp,cp]
[pvddi_sp,cp]
[pvddick_sp,cp]
[pvsse_sp,cp]
[pvsseck_sp,cp]
[pvssi_sp,cp]
[pvssick_sp,cp]
)
(16,HNS
[pck_sp,hns]
[pi_sp,hns]
[piot_sp,hns]
[piotw_sp,hns]
[po_sp,hns]
[pot_sp,hns]
[potw_sp,hns]
[pow_sp,hns]
[pvdde_sp,hns]
[pvddeck_sp,hns]
[pvddi_sp,hns]
[pvddick_sp,hns]
[pvsse_sp,hns]
[pvsseck_sp,hns]
[pvssi_sp,hns]
[pvssick_sp,hns]
)
(1,CIF
[padreal,cif]
)
)

823
alliance/src/cells/src/padlib/palck_sp.ap Normal file
View File

@ -0,0 +1,823 @@
V ALLIANCE : 6
H palck_sp,P,13/10/2000,100
A 300,100,17500,36400
C 300,17600,12000,vdde,0,WEST,ALU2
C 300,30400,12000,vsse,0,WEST,ALU2
C 17500,30400,12000,vsse,1,EAST,ALU2
C 17500,17600,12000,vdde,1,EAST,ALU2
C 17500,9200,4000,vddi,1,EAST,ALU2
C 17500,4800,4000,vssi,1,EAST,ALU2
C 17500,1400,1200,ck,1,EAST,ALU2
C 300,1400,1200,ck,0,WEST,ALU2
C 300,9200,4000,vddi,0,WEST,ALU2
C 300,4800,4000,vssi,0,WEST,ALU2
S 15000,1000,15000,4900,200,*,UP,ALU1
S 13800,1000,13800,4900,200,*,UP,ALU1
S 12600,1000,12600,4900,200,*,UP,ALU1
S 11300,6400,12000,6400,200,*,RIGHT,ALU1
S 8400,500,15600,500,200,*,RIGHT,ALU1
S 15600,500,15600,4000,200,*,UP,ALU1
S 14400,500,14400,4000,200,*,UP,ALU1
S 13200,500,13200,4000,200,*,UP,ALU1
S 12000,500,12000,4000,200,*,UP,ALU1
S 10800,500,10800,9200,200,*,UP,ALU1
S 9600,500,9600,9200,200,*,UP,ALU1
S 8400,500,8400,5500,200,*,UP,ALU1
S 7800,4500,8400,4500,200,*,RIGHT,ALU1
S 7800,6400,8400,6400,200,*,RIGHT,ALU1
S 3700,5900,3700,12800,200,*,UP,ALU1
S 1800,12800,11400,12800,200,*,RIGHT,ALU1
S 2200,5900,2200,12800,1000,*,UP,ALU1
S 4900,5900,4900,12800,200,*,UP,ALU1
S 6100,5900,6100,12800,200,*,UP,ALU1
S 6400,14400,8200,14400,200,*,RIGHT,ALU1
S 6700,14400,6700,23400,800,*,UP,ALU1
S 11400,7300,11400,12800,200,*,UP,ALU1
S 7300,5900,7300,12800,200,*,UP,ALU1
S 9000,5900,9000,12800,200,*,UP,ALU1
S 10200,5900,10200,12800,200,*,UP,ALU1
S 12000,4400,12000,13400,200,*,UP,ALU1
S 8800,13400,12000,13400,200,*,RIGHT,ALU1
S 8800,13400,8800,15100,200,*,UP,ALU1
S 8200,14400,8200,23400,200,*,UP,ALU1
S 9300,25100,10100,25100,200,*,RIGHT,ALU1
S 9700,25100,9700,29600,1000,*,UP,ALU1
S 300,30400,17500,30400,12000,log.vsse,RIGHT,ALU2
S 8700,6400,11800,6400,300,*,RIGHT,POLY
S 11400,6800,11400,12900,300,*,UP,NTIE
S 1800,6000,11400,6000,300,*,RIGHT,NTIE
S 13200,4500,13200,5400,200,*,DOWN,ALU1
S 14400,4500,14400,5400,200,*,DOWN,ALU1
S 12000,5400,14400,5400,200,*,RIGHT,ALU1
S 1700,12800,11400,12800,300,*,RIGHT,NTIE
S 1600,9400,11600,9400,7200,*,RIGHT,NWELL
S 10200,6700,10200,9300,300,*,UP,PDIF
S 16200,1000,16200,5000,200,*,UP,ALU1
S 11400,1000,11400,5000,200,*,UP,ALU1
S 10200,1000,10200,5000,200,*,UP,ALU1
S 8700,4500,15300,4500,300,*,RIGHT,POLY
S 1800,1100,16200,1100,300,*,RIGHT,PTIE
S 1800,4900,16200,4900,300,*,RIGHT,PTIE
S 12000,1600,12000,4200,200,*,UP,NDIF
S 13800,1600,13800,4200,200,*,UP,NDIF
S 15600,1600,15600,4200,300,*,UP,NDIF
S 15600,1600,15600,4200,200,*,UP,NDIF
S 16200,1000,16200,5000,300,*,UP,PTIE
S 14700,1400,14700,4400,100,*,UP,NTRANS
S 14100,1400,14100,4400,100,*,UP,NTRANS
S 15000,1600,15000,4200,200,*,UP,NDIF
S 14400,1600,14400,4200,200,*,UP,NDIF
S 15300,1400,15300,4400,100,*,UP,NTRANS
S 12900,1400,12900,4400,100,*,UP,NTRANS
S 12600,1600,12600,4200,200,*,UP,NDIF
S 13200,1600,13200,4200,200,*,UP,NDIF
S 12300,1400,12300,4400,100,*,UP,NTRANS
S 13500,1400,13500,4400,100,*,UP,NTRANS
S 11100,1400,11100,4400,100,*,UP,NTRANS
S 11700,1400,11700,4400,100,*,UP,NTRANS
S 10500,1400,10500,4400,100,*,UP,NTRANS
S 10200,1600,10200,4200,300,*,UP,NDIF
S 11400,1600,11400,4200,200,*,UP,NDIF
S 10800,1600,10800,4200,200,*,UP,NDIF
S 10800,6700,10800,9300,300,*,UP,PDIF
S 10200,6700,10200,9300,300,*,UP,PDIF
S 10500,6500,10500,9500,100,*,UP,PTRANS
S 9600,6700,9600,9300,300,*,UP,PDIF
S 9900,6500,9900,9500,100,*,UP,PTRANS
S 9300,6500,9300,9500,100,*,UP,PTRANS
S 9900,1400,9900,4400,100,*,UP,NTRANS
S 9300,1400,9300,4400,100,*,UP,NTRANS
S 3100,1600,3100,4200,200,*,UP,NDIF
S 8400,1600,8400,4200,300,*,UP,NDIF
S 8700,1400,8700,4400,100,*,UP,NTRANS
S 9000,1600,9000,4200,200,*,UP,NDIF
S 9600,1600,9600,4200,200,*,UP,NDIF
S 3700,1600,3700,4200,200,*,UP,NDIF
S 5200,1400,5200,4400,100,*,UP,NTRANS
S 4600,1400,4600,4400,100,*,UP,NTRANS
S 2800,1400,2800,4400,100,*,UP,NTRANS
S 6700,1600,6700,4200,200,*,UP,NDIF
S 4000,1400,4000,4400,100,*,UP,NTRANS
S 3400,1400,3400,4400,100,*,UP,NTRANS
S 6100,1600,6100,4200,200,*,UP,NDIF
S 5500,1600,5500,4200,200,*,UP,NDIF
S 4900,1600,4900,4200,200,*,UP,NDIF
S 4300,1600,4300,4200,200,*,UP,NDIF
S 2500,1600,2500,4200,300,*,UP,NDIF
S 7300,1600,7300,4200,400,*,UP,NDIF
S 7000,1400,7000,4400,100,*,UP,NTRANS
S 6400,1400,6400,4400,100,*,UP,NTRANS
S 5800,1400,5800,4400,100,*,UP,NTRANS
S 2500,6700,2500,12300,400,*,UP,PDIF
S 8400,6700,8400,9300,400,*,UP,PDIF
S 8700,6500,8700,9500,100,*,UP,PTRANS
S 9000,6700,9000,9300,300,*,UP,PDIF
S 7000,6500,7000,12500,100,*,UP,PTRANS
S 3100,6700,3100,12300,200,*,UP,PDIF
S 3700,6700,3700,12300,200,*,UP,PDIF
S 4300,6700,4300,12300,200,*,UP,PDIF
S 4900,6700,4900,12300,200,*,UP,PDIF
S 5500,6700,5500,12300,200,*,UP,PDIF
S 6100,6700,6100,12300,200,*,UP,PDIF
S 6700,6700,6700,12300,200,*,UP,PDIF
S 4600,6500,4600,12500,100,*,UP,PTRANS
S 5200,6500,5200,12500,100,*,UP,PTRANS
S 5800,6500,5800,12500,100,*,UP,PTRANS
S 6400,6500,6400,12500,100,*,UP,PTRANS
S 2800,6500,2800,12500,100,*,UP,PTRANS
S 3400,6500,3400,12500,100,*,UP,PTRANS
S 4000,6500,4000,12500,100,*,UP,PTRANS
S 3700,6700,3700,12300,400,*,UP,PDIF
S 4900,6700,4900,12300,400,*,UP,PDIF
S 6100,6700,6100,12300,400,*,UP,PDIF
S 7300,6700,7300,12300,400,*,UP,PDIF
S 1800,5900,1800,12800,300,*,UP,NTIE
S 1900,1200,1900,5000,300,*,UP,PTIE
S 2800,4500,8400,4500,300,*,RIGHT,POLY
S 2800,12500,7000,12500,100,*,RIGHT,POLY
S 2800,1400,7000,1400,100,*,RIGHT,POLY
S 8700,6300,8700,6500,100,*,UP,POLY
S 2800,6400,8400,6400,300,*,RIGHT,POLY
S 8400,5300,8400,9200,200,*,UP,ALU1
S 9000,1000,9000,5000,200,*,UP,ALU1
S 2200,1000,2200,5000,900,*,UP,ALU1
S 7300,1000,7300,5000,200,*,UP,ALU1
S 6100,1000,6100,5000,200,*,UP,ALU1
S 4900,1000,4900,5000,200,*,UP,ALU1
S 3700,1000,3700,5000,200,*,UP,ALU1
S 3100,1000,3100,12300,200,*,UP,ALU1
S 4300,1000,4300,12300,200,*,UP,ALU1
S 5500,1000,5500,12300,200,*,UP,ALU1
S 6700,1000,6700,12300,200,*,UP,ALU1
S 7600,15000,7600,29900,200,*,UP,ALU1
S 8800,15000,8800,29900,200,*,UP,ALU1
S 8200,24500,8200,29600,200,*,UP,ALU1
S 9400,25600,9400,29000,300,*,UP,NDIF
S 8800,25600,8800,29000,300,*,UP,NDIF
S 8200,25600,8200,29000,300,*,UP,NDIF
S 7600,25600,7600,29000,300,*,UP,NDIF
S 7300,25400,7300,29200,100,*,UP,NTRANS
S 7900,25400,7900,29200,100,*,UP,NTRANS
S 8500,25400,8500,29200,100,*,UP,NTRANS
S 9100,25400,9100,29200,100,*,UP,NTRANS
S 7100,29500,9500,29500,300,*,RIGHT,PTIE
S 9400,14900,9400,22800,300,*,UP,PDIF
S 8800,14900,8800,22800,200,*,UP,PDIF
S 8200,14900,8200,22800,200,*,UP,PDIF
S 7600,14900,7600,22800,200,*,UP,PDIF
S 7300,14700,7300,23000,100,*,UP,PTRANS
S 7900,14700,7900,23000,100,*,UP,PTRANS
S 8500,14700,8500,23000,100,*,UP,PTRANS
S 9100,14700,9100,23000,100,*,UP,PTRANS
S 8400,14200,8400,23500,2800,*,UP,NWELL
S 8800,24500,8800,24700,200,*,UP,POLY
S 7100,25100,8500,25100,300,*,RIGHT,PTIE
S 7300,25400,9100,25400,100,*,RIGHT,POLY
S 8800,24600,8800,25400,200,*,UP,POLY
S 8800,24600,9300,24600,300,*,RIGHT,POLY
S 7100,23300,9500,23300,300,*,RIGHT,NTIE
S 6700,14200,6700,23500,1000,*,UP,NWELL
S 9900,14200,9900,23500,600,*,UP,NWELL
S 7000,25600,7000,29000,300,*,UP,NDIF
S 7000,14900,7000,22800,300,*,UP,PDIF
S 6400,14400,6400,23400,300,*,UP,NTIE
S 6400,23300,7000,23300,300,*,RIGHT,NTIE
S 10000,27100,10000,29300,300,*,UP,PTIE
S 9400,29500,10100,29500,300,*,RIGHT,PTIE
S 6300,29500,7100,29500,300,*,RIGHT,PTIE
S 6400,25000,6400,29600,300,*,UP,PTIE
S 6300,25100,7100,25100,300,*,RIGHT,PTIE
S 6700,25000,6700,29600,900,*,UP,ALU1
S 7500,30400,9400,30400,900,*,RIGHT,ALU1
S 9300,24600,9700,24600,200,*,RIGHT,ALU1
S 10000,25000,10000,27300,300,*,UP,PTIE
S 9100,25100,10000,25100,300,*,RIGHT,PTIE
S 9800,14200,9800,23500,400,*,UP,NWELL
S 6400,14400,8500,14400,300,*,RIGHT,NTIE
S 7300,14700,9100,14700,100,*,RIGHT,POLY
S 9500,23300,10000,23300,300,*,RIGHT,NTIE
S 10000,14400,10000,23400,300,*,UP,NTIE
S 9900,14200,9900,23500,600,*,UP,NWELL
S 9700,14300,9700,23400,1000,*,UP,ALU1
S 8800,13700,8800,14600,200,*,UP,POLY
S 7600,13800,8300,13800,200,*,RIGHT,ALU1
S 8200,13800,8800,13800,300,*,RIGHT,POLY
S 9100,14400,10000,14400,300,*,RIGHT,NTIE
S 8900,30900,8900,36400,1000,*,UP,ALU1
S 300,1400,17500,1400,1200,log.ck,RIGHT,ALU2
S 300,4800,17500,4800,4000,log.vssi,RIGHT,ALU2
S 300,9200,17500,9200,4000,log.vddi,RIGHT,ALU2
S 300,17600,17500,17600,12000,log.vdde,RIGHT,ALU2
B 6700,27300,800,4600,CONT_VIA,*
B 9700,18800,1000,9300,CONT_VIA,*
B 6700,18900,800,9200,CONT_VIA,*
B 2200,3900,1000,2200,CONT_VIA,*
B 2200,9200,1000,4000,CONT_VIA,*
B 14400,5400,200,200,CONT_TURN1,*
B 8400,500,200,200,CONT_TURN1,*
B 15600,500,200,200,CONT_TURN1,*
B 8800,13400,200,200,CONT_TURN1,*
B 12000,13400,200,200,CONT_TURN1,*
B 10100,25100,200,200,CONT_TURN1,*
B 9300,25100,200,200,CONT_TURN1,*
V 11800,6400,CONT_POLY,*
V 11400,6400,CONT_POLY,*
V 14400,4500,CONT_POLY,*
V 13200,4500,CONT_POLY,*
V 12000,4500,CONT_POLY,*
V 11400,11600,CONT_BODY_N,*
V 11400,12400,CONT_BODY_N,*
V 11400,12000,CONT_BODY_N,*
V 11400,12800,CONT_BODY_N,*
V 11400,10500,CONT_BODY_N,*
V 11400,10000,CONT_BODY_N,*
V 11400,8900,CONT_BODY_N,*
V 11400,8400,CONT_BODY_N,*
V 11400,7400,CONT_BODY_N,*
V 11400,7900,CONT_VIA,*
V 11400,11000,CONT_VIA,*
V 11400,9400,CONT_VIA,*
V 10200,7000,CONT_DIF_P,*
V 10200,7800,CONT_DIF_P,*
V 10200,7000,CONT_DIF_P,*
V 10200,8200,CONT_DIF_P,*
V 10200,9000,CONT_DIF_P,*
V 10200,6000,CONT_BODY_N,*
V 10200,12800,CONT_BODY_N,*
V 10200,7400,CONT_VIA,*
V 10200,8600,CONT_VIA,*
V 10200,11000,CONT_VIA,*
V 10200,9400,CONT_VIA,*
V 10200,10200,CONT_VIA,*
V 16200,2900,CONT_VIA,*
V 16200,3700,CONT_VIA,*
V 16200,4500,CONT_VIA,*
V 15000,1100,CONT_BODY_P,*
V 13800,1100,CONT_BODY_P,*
V 12600,1100,CONT_BODY_P,*
V 11400,1100,CONT_BODY_P,*
V 10200,1100,CONT_BODY_P,*
V 13800,4900,CONT_BODY_P,*
V 8400,2400,CONT_DIF_N,*
V 9600,2400,CONT_DIF_N,*
V 10800,2400,CONT_DIF_N,*
V 12000,2400,CONT_DIF_N,*
V 13200,2400,CONT_DIF_N,*
V 14400,2400,CONT_DIF_N,*
V 15600,2400,CONT_DIF_N,*
V 12600,4900,CONT_BODY_P,*
V 11400,4900,CONT_BODY_P,*
V 10200,4900,CONT_BODY_P,*
V 10800,7000,CONT_DIF_P,*
V 10800,8600,CONT_DIF_P,*
V 10800,8100,CONT_DIF_P,*
V 10800,7500,CONT_DIF_P,*
V 10800,9100,CONT_DIF_P,*
V 15000,4900,CONT_BODY_P,*
V 10800,3900,CONT_DIF_N,*
V 10800,2900,CONT_DIF_N,*
V 10800,1900,CONT_DIF_N,*
V 10800,3400,CONT_DIF_N,*
V 12000,1900,CONT_DIF_N,*
V 12000,2900,CONT_DIF_N,*
V 12000,3900,CONT_DIF_N,*
V 12000,3400,CONT_DIF_N,*
V 13200,3400,CONT_DIF_N,*
V 13200,3900,CONT_DIF_N,*
V 13200,2900,CONT_DIF_N,*
V 13200,1900,CONT_DIF_N,*
V 15000,2500,CONT_DIF_N,*
V 15000,2000,CONT_DIF_N,*
V 15000,3500,CONT_DIF_N,*
V 15000,4000,CONT_VIA,*
V 15000,3000,CONT_VIA,*
V 14400,1900,CONT_DIF_N,*
V 14400,2900,CONT_DIF_N,*
V 14400,3900,CONT_DIF_N,*
V 14400,3400,CONT_DIF_N,*
V 13800,3500,CONT_DIF_N,*
V 13800,2000,CONT_DIF_N,*
V 13800,2500,CONT_DIF_N,*
V 13800,3000,CONT_VIA,*
V 13800,4000,CONT_VIA,*
V 12600,2500,CONT_DIF_N,*
V 12600,3500,CONT_DIF_N,*
V 12600,2000,CONT_DIF_N,*
V 12600,3000,CONT_VIA,*
V 12600,4000,CONT_VIA,*
V 11400,2000,CONT_DIF_N,*
V 11400,3500,CONT_DIF_N,*
V 11400,2500,CONT_DIF_N,*
V 11400,4000,CONT_VIA,*
V 11400,3000,CONT_VIA,*
V 10200,2500,CONT_DIF_N,*
V 10200,3500,CONT_DIF_N,*
V 10200,2000,CONT_DIF_N,*
V 10200,3000,CONT_VIA,*
V 10200,4000,CONT_VIA,*
V 15600,1900,CONT_DIF_N,*
V 15600,3900,CONT_DIF_N,*
V 15600,3400,CONT_DIF_N,*
V 15600,2900,CONT_DIF_N,*
V 16200,2500,CONT_BODY_P,*
V 16200,2100,CONT_BODY_P,*
V 16200,4900,CONT_BODY_P,*
V 16200,1700,CONT_BODY_P,*
V 16200,1300,CONT_BODY_P,*
V 16200,4100,CONT_BODY_P,*
V 16200,3300,CONT_BODY_P,*
V 9600,9100,CONT_DIF_P,*
V 9600,7500,CONT_DIF_P,*
V 9600,8100,CONT_DIF_P,*
V 9600,8600,CONT_DIF_P,*
V 9600,7000,CONT_DIF_P,*
V 9600,2900,CONT_DIF_N,*
V 9000,3500,CONT_DIF_N,*
V 9000,2000,CONT_DIF_N,*
V 8400,2900,CONT_DIF_N,*
V 8400,3400,CONT_DIF_N,*
V 8400,3900,CONT_DIF_N,*
V 9600,3900,CONT_DIF_N,*
V 9600,3400,CONT_DIF_N,*
V 2500,1900,CONT_DIF_N,*
V 2500,3900,CONT_DIF_N,*
V 2500,3400,CONT_DIF_N,*
V 2500,2400,CONT_DIF_N,*
V 2500,2900,CONT_DIF_N,*
V 9000,2500,CONT_DIF_N,*
V 9600,1900,CONT_DIF_N,*
V 8400,1900,CONT_DIF_N,*
V 4900,3500,CONT_DIF_N,*
V 3700,2000,CONT_DIF_N,*
V 3700,3500,CONT_DIF_N,*
V 3700,2500,CONT_DIF_N,*
V 3100,2900,CONT_DIF_N,*
V 3100,2400,CONT_DIF_N,*
V 3100,3900,CONT_DIF_N,*
V 3100,3400,CONT_DIF_N,*
V 5500,3400,CONT_DIF_N,*
V 5500,3900,CONT_DIF_N,*
V 4300,2400,CONT_DIF_N,*
V 4300,2900,CONT_DIF_N,*
V 4300,3900,CONT_DIF_N,*
V 4300,3400,CONT_DIF_N,*
V 4900,2500,CONT_DIF_N,*
V 4900,2000,CONT_DIF_N,*
V 6700,2900,CONT_DIF_N,*
V 6700,3900,CONT_DIF_N,*
V 6700,3400,CONT_DIF_N,*
V 6100,2500,CONT_DIF_N,*
V 6100,2000,CONT_DIF_N,*
V 6100,3500,CONT_DIF_N,*
V 5500,2900,CONT_DIF_N,*
V 5500,2400,CONT_DIF_N,*
V 7300,3500,CONT_DIF_N,*
V 7300,2500,CONT_DIF_N,*
V 7300,2000,CONT_DIF_N,*
V 6700,2400,CONT_DIF_N,*
V 9000,7000,CONT_DIF_P,*
V 9000,7800,CONT_DIF_P,*
V 9000,7000,CONT_DIF_P,*
V 6700,10600,CONT_DIF_P,*
V 9000,9000,CONT_DIF_P,*
V 9000,8200,CONT_DIF_P,*
V 8400,8600,CONT_DIF_P,*
V 8400,8100,CONT_DIF_P,*
V 8400,7500,CONT_DIF_P,*
V 8400,7000,CONT_DIF_P,*
V 8400,9100,CONT_DIF_P,*
V 6700,12200,CONT_DIF_P,*
V 6700,7800,CONT_DIF_P,*
V 6700,8200,CONT_DIF_P,*
V 6700,8600,CONT_DIF_P,*
V 6700,9000,CONT_DIF_P,*
V 6700,9400,CONT_DIF_P,*
V 6700,9800,CONT_DIF_P,*
V 6700,10200,CONT_DIF_P,*
V 5500,9400,CONT_DIF_P,*
V 5500,9000,CONT_DIF_P,*
V 5500,8600,CONT_DIF_P,*
V 6700,7000,CONT_DIF_P,*
V 6700,7400,CONT_DIF_P,*
V 6700,11000,CONT_DIF_P,*
V 6700,11400,CONT_DIF_P,*
V 6700,11800,CONT_DIF_P,*
V 5500,11800,CONT_DIF_P,*
V 5500,11400,CONT_DIF_P,*
V 5500,11000,CONT_DIF_P,*
V 5500,7400,CONT_DIF_P,*
V 5500,7000,CONT_DIF_P,*
V 5500,10600,CONT_DIF_P,*
V 5500,10200,CONT_DIF_P,*
V 5500,9800,CONT_DIF_P,*
V 4300,9800,CONT_DIF_P,*
V 4300,10200,CONT_DIF_P,*
V 4300,10600,CONT_DIF_P,*
V 4300,7000,CONT_DIF_P,*
V 4300,7400,CONT_DIF_P,*
V 5500,8200,CONT_DIF_P,*
V 5500,7800,CONT_DIF_P,*
V 5500,12200,CONT_DIF_P,*
V 4300,11400,CONT_DIF_P,*
V 4300,11800,CONT_DIF_P,*
V 4300,12200,CONT_DIF_P,*
V 4300,7800,CONT_DIF_P,*
V 4300,8200,CONT_DIF_P,*
V 4300,8600,CONT_DIF_P,*
V 4300,9000,CONT_DIF_P,*
V 4300,9400,CONT_DIF_P,*
V 3100,9400,CONT_DIF_P,*
V 3100,9000,CONT_DIF_P,*
V 3100,8600,CONT_DIF_P,*
V 3100,8200,CONT_DIF_P,*
V 3100,7800,CONT_DIF_P,*
V 3100,7400,CONT_DIF_P,*
V 3100,7000,CONT_DIF_P,*
V 4300,11000,CONT_DIF_P,*
V 2500,7200,CONT_DIF_P,*
V 3100,12200,CONT_DIF_P,*
V 3100,11800,CONT_DIF_P,*
V 3100,11400,CONT_DIF_P,*
V 3100,11000,CONT_DIF_P,*
V 3100,10600,CONT_DIF_P,*
V 3100,10200,CONT_DIF_P,*
V 3100,9800,CONT_DIF_P,*
V 2500,11200,CONT_DIF_P,*
V 2500,10700,CONT_DIF_P,*
V 2500,10200,CONT_DIF_P,*
V 2500,9700,CONT_DIF_P,*
V 2500,9200,CONT_DIF_P,*
V 2500,8700,CONT_DIF_P,*
V 2500,8200,CONT_DIF_P,*
V 2500,7700,CONT_DIF_P,*
V 2500,12200,CONT_DIF_P,*
V 2500,11700,CONT_DIF_P,*
V 7300,12200,CONT_DIF_P,*
V 7300,7800,CONT_DIF_P,*
V 7300,8200,CONT_DIF_P,*
V 7300,9000,CONT_DIF_P,*
V 7300,9400,CONT_DIF_P,*
V 7300,10200,CONT_DIF_P,*
V 7300,10600,CONT_DIF_P,*
V 7300,11400,CONT_DIF_P,*
V 7300,11800,CONT_DIF_P,*
V 6100,10200,CONT_DIF_P,*
V 6100,9400,CONT_DIF_P,*
V 6100,9000,CONT_DIF_P,*
V 6100,8200,CONT_DIF_P,*
V 6100,7800,CONT_DIF_P,*
V 6100,12200,CONT_DIF_P,*
V 6100,11800,CONT_DIF_P,*
V 7300,7000,CONT_DIF_P,*
V 4900,9000,CONT_DIF_P,*
V 4900,8200,CONT_DIF_P,*
V 4900,7800,CONT_DIF_P,*
V 4900,12200,CONT_DIF_P,*
V 4900,11800,CONT_DIF_P,*
V 6100,7000,CONT_DIF_P,*
V 6100,11400,CONT_DIF_P,*
V 6100,10600,CONT_DIF_P,*
V 3700,7800,CONT_DIF_P,*
V 3700,12200,CONT_DIF_P,*
V 3700,11800,CONT_DIF_P,*
V 4900,7000,CONT_DIF_P,*
V 4900,11400,CONT_DIF_P,*
V 4900,10600,CONT_DIF_P,*
V 4900,10200,CONT_DIF_P,*
V 4900,9400,CONT_DIF_P,*
V 3700,7000,CONT_DIF_P,*
V 3700,11400,CONT_DIF_P,*
V 3700,10600,CONT_DIF_P,*
V 3700,10200,CONT_DIF_P,*
V 3700,9400,CONT_DIF_P,*
V 3700,9000,CONT_DIF_P,*
V 3700,8200,CONT_DIF_P,*
V 9000,12800,CONT_BODY_N,*
V 9000,6000,CONT_BODY_N,*
V 9600,12800,CONT_BODY_N,*
V 7300,6000,CONT_BODY_N,*
V 1800,9700,CONT_BODY_N,*
V 1800,9200,CONT_BODY_N,*
V 1800,8700,CONT_BODY_N,*
V 1800,8200,CONT_BODY_N,*
V 1800,12200,CONT_BODY_N,*
V 4900,6000,CONT_BODY_N,*
V 3700,6000,CONT_BODY_N,*
V 1800,7700,CONT_BODY_N,*
V 1800,7200,CONT_BODY_N,*
V 1800,11700,CONT_BODY_N,*
V 1800,11200,CONT_BODY_N,*
V 1800,10700,CONT_BODY_N,*
V 1800,10200,CONT_BODY_N,*
V 3700,12800,CONT_BODY_N,*
V 4900,12800,CONT_BODY_N,*
V 6100,12800,CONT_BODY_N,*
V 7300,12800,CONT_BODY_N,*
V 2300,6000,CONT_BODY_N,*
V 1800,6200,CONT_BODY_N,*
V 1800,6700,CONT_BODY_N,*
V 6100,6000,CONT_BODY_N,*
V 6700,12800,CONT_BODY_N,*
V 5500,12800,CONT_BODY_N,*
V 4300,12800,CONT_BODY_N,*
V 3100,12800,CONT_BODY_N,*
V 2500,12800,CONT_BODY_N,*
V 1800,12800,CONT_BODY_N,*
V 9000,1100,CONT_BODY_P,*
V 9000,4900,CONT_BODY_P,*
V 6100,4900,CONT_BODY_P,*
V 4900,4900,CONT_BODY_P,*
V 3700,4900,CONT_BODY_P,*
V 7300,1100,CONT_BODY_P,*
V 6100,1100,CONT_BODY_P,*
V 4900,1100,CONT_BODY_P,*
V 3700,1100,CONT_BODY_P,*
V 2400,4900,CONT_BODY_P,*
V 1900,4100,CONT_BODY_P,*
V 1900,3700,CONT_BODY_P,*
V 1900,4500,CONT_BODY_P,*
V 1900,1300,CONT_BODY_P,*
V 1900,1700,CONT_BODY_P,*
V 1900,2900,CONT_BODY_P,*
V 2400,1100,CONT_BODY_P,*
V 7300,4900,CONT_BODY_P,*
V 1900,4900,CONT_BODY_P,*
V 1900,2100,CONT_BODY_P,*
V 1900,2500,CONT_BODY_P,*
V 1900,3300,CONT_BODY_P,*
V 8300,6400,CONT_POLY,*
V 7900,4500,CONT_POLY,*
V 8300,4500,CONT_POLY,*
V 7900,6400,CONT_POLY,*
V 9000,11000,CONT_VIA,*
V 9000,8600,CONT_VIA,*
V 9000,7400,CONT_VIA,*
V 9000,4000,CONT_VIA,*
V 9000,3000,CONT_VIA,*
V 9000,10200,CONT_VIA,*
V 9000,9400,CONT_VIA,*
V 7300,11000,CONT_VIA,*
V 7300,7400,CONT_VIA,*
V 7300,8600,CONT_VIA,*
V 7300,9800,CONT_VIA,*
V 6100,7400,CONT_VIA,*
V 6100,9800,CONT_VIA,*
V 6100,8600,CONT_VIA,*
V 6100,11000,CONT_VIA,*
V 4900,11000,CONT_VIA,*
V 4900,7400,CONT_VIA,*
V 4900,9800,CONT_VIA,*
V 4900,8600,CONT_VIA,*
V 3700,9800,CONT_VIA,*
V 3700,8600,CONT_VIA,*
V 3700,11000,CONT_VIA,*
V 3700,7400,CONT_VIA,*
V 3700,4000,CONT_VIA,*
V 3700,3000,CONT_VIA,*
V 4900,3000,CONT_VIA,*
V 4900,4000,CONT_VIA,*
V 6100,4000,CONT_VIA,*
V 6100,3000,CONT_VIA,*
V 7300,4000,CONT_VIA,*
V 7300,3000,CONT_VIA,*
V 6700,1100,CONT_VIA,*
V 5500,1100,CONT_VIA,*
V 4300,1100,CONT_VIA,*
V 3100,1100,CONT_VIA,*
V 3100,1800,CONT_VIA,*
V 4300,1800,CONT_VIA,*
V 5500,1800,CONT_VIA,*
V 6700,1800,CONT_VIA,*
V 9400,28500,CONT_DIF_N,*
V 9400,26900,CONT_DIF_N,*
V 9400,26500,CONT_DIF_N,*
V 9400,28100,CONT_DIF_N,*
V 9400,27700,CONT_DIF_N,*
V 9400,26100,CONT_DIF_N,*
V 9400,27300,CONT_VIA,*
V 9400,25700,CONT_VIA,*
V 9400,28900,CONT_VIA,*
V 8200,25700,CONT_VIA,*
V 8200,26100,CONT_DIF_N,*
V 8200,27700,CONT_DIF_N,*
V 8200,28100,CONT_DIF_N,*
V 8200,27300,CONT_DIF_N,*
V 8200,28900,CONT_DIF_N,*
V 8200,26500,CONT_DIF_N,*
V 8200,28500,CONT_VIA,*
V 8200,26900,CONT_VIA,*
V 9400,29500,CONT_BODY_P,*
V 8200,29500,CONT_BODY_P,*
V 7800,14400,CONT_BODY_N,*
V 7600,25800,CONT_DIF_N,*
V 7600,28200,CONT_DIF_N,*
V 7600,28600,CONT_DIF_N,*
V 7600,26200,CONT_DIF_N,*
V 7600,26600,CONT_DIF_N,*
V 7600,27000,CONT_DIF_N,*
V 7600,27400,CONT_DIF_N,*
V 7600,27800,CONT_DIF_N,*
V 8800,26600,CONT_DIF_N,*
V 8800,27000,CONT_DIF_N,*
V 8800,26200,CONT_DIF_N,*
V 8800,25800,CONT_DIF_N,*
V 8800,28600,CONT_DIF_N,*
V 8800,27400,CONT_DIF_N,*
V 8800,27800,CONT_DIF_N,*
V 8800,28200,CONT_DIF_N,*
V 8200,15100,CONT_DIF_P,*
V 7600,15500,CONT_DIF_P,*
V 8200,15500,CONT_DIF_P,*
V 7600,15900,CONT_DIF_P,*
V 7600,15100,CONT_DIF_P,*
V 8800,15100,CONT_DIF_P,*
V 9400,15100,CONT_DIF_P,*
V 8800,15500,CONT_DIF_P,*
V 9400,15500,CONT_DIF_P,*
V 8800,15900,CONT_DIF_P,*
V 8200,16300,CONT_DIF_P,*
V 7600,16300,CONT_DIF_P,*
V 7600,20300,CONT_DIF_P,*
V 7600,18700,CONT_DIF_P,*
V 8200,18700,CONT_DIF_P,*
V 7600,19100,CONT_DIF_P,*
V 8200,19100,CONT_DIF_P,*
V 7600,19500,CONT_DIF_P,*
V 7600,19900,CONT_DIF_P,*
V 8200,19900,CONT_DIF_P,*
V 8200,20300,CONT_DIF_P,*
V 7600,17100,CONT_DIF_P,*
V 7600,16700,CONT_DIF_P,*
V 8200,16700,CONT_DIF_P,*
V 7600,18300,CONT_DIF_P,*
V 7600,17900,CONT_DIF_P,*
V 7600,17500,CONT_DIF_P,*
V 8200,17500,CONT_DIF_P,*
V 8200,17900,CONT_DIF_P,*
V 8800,16300,CONT_DIF_P,*
V 9400,16300,CONT_DIF_P,*
V 9400,20300,CONT_DIF_P,*
V 8800,19100,CONT_DIF_P,*
V 8800,19500,CONT_DIF_P,*
V 8800,19900,CONT_DIF_P,*
V 9400,19900,CONT_DIF_P,*
V 8800,20300,CONT_DIF_P,*
V 8800,18300,CONT_DIF_P,*
V 8800,17900,CONT_DIF_P,*
V 8800,18700,CONT_DIF_P,*
V 9400,18700,CONT_DIF_P,*
V 9400,19100,CONT_DIF_P,*
V 8800,17100,CONT_DIF_P,*
V 8800,16700,CONT_DIF_P,*
V 9400,16700,CONT_DIF_P,*
V 9400,17900,CONT_DIF_P,*
V 9400,17500,CONT_DIF_P,*
V 8800,17500,CONT_DIF_P,*
V 8200,15900,CONT_VIA,*
V 8200,18300,CONT_VIA,*
V 8200,19500,CONT_VIA,*
V 8200,17100,CONT_VIA,*
V 7600,20700,CONT_DIF_P,*
V 8800,20700,CONT_DIF_P,*
V 8200,20700,CONT_VIA,*
V 7600,21100,CONT_DIF_P,*
V 8800,21100,CONT_DIF_P,*
V 8200,21100,CONT_DIF_P,*
V 9400,21100,CONT_DIF_P,*
V 8200,21500,CONT_DIF_P,*
V 9400,21500,CONT_DIF_P,*
V 8800,21500,CONT_DIF_P,*
V 7600,21500,CONT_DIF_P,*
V 7600,21900,CONT_DIF_P,*
V 8800,21900,CONT_DIF_P,*
V 8200,21900,CONT_VIA,*
V 7600,22300,CONT_DIF_P,*
V 8200,22300,CONT_DIF_P,*
V 8800,22300,CONT_DIF_P,*
V 9400,22300,CONT_DIF_P,*
V 8200,25100,CONT_BODY_P,*
V 9400,25100,CONT_BODY_P,*
V 9300,24600,CONT_POLY,*
V 8200,24600,CONT_VIA,*
V 9400,23300,CONT_BODY_N,*
V 8200,23300,CONT_BODY_N,*
V 9400,22700,CONT_DIF_P,*
V 8800,22700,CONT_DIF_P,*
V 8200,22700,CONT_DIF_P,*
V 7600,22700,CONT_DIF_P,*
V 8200,14400,CONT_VIA,*
V 7300,14400,CONT_BODY_N,*
V 7000,26500,CONT_DIF_N,*
V 7000,27700,CONT_DIF_N,*
V 7000,28500,CONT_DIF_N,*
V 7000,28100,CONT_DIF_N,*
V 7000,26900,CONT_DIF_N,*
V 7000,25700,CONT_DIF_N,*
V 7000,27300,CONT_DIF_N,*
V 7000,28900,CONT_DIF_N,*
V 7000,26100,CONT_DIF_N,*
V 7000,17100,CONT_DIF_P,*
V 7000,20700,CONT_DIF_P,*
V 7000,19500,CONT_DIF_P,*
V 7000,19900,CONT_DIF_P,*
V 7000,18700,CONT_DIF_P,*
V 7000,18300,CONT_DIF_P,*
V 7000,16700,CONT_DIF_P,*
V 7000,17500,CONT_DIF_P,*
V 7000,17900,CONT_DIF_P,*
V 7000,20300,CONT_DIF_P,*
V 7000,19100,CONT_DIF_P,*
V 7000,15100,CONT_DIF_P,*
V 7000,15500,CONT_DIF_P,*
V 7000,15900,CONT_DIF_P,*
V 7000,16300,CONT_DIF_P,*
V 7000,21900,CONT_DIF_P,*
V 7000,22300,CONT_DIF_P,*
V 7000,21100,CONT_DIF_P,*
V 7000,22700,CONT_DIF_P,*
V 7000,21500,CONT_DIF_P,*
V 6400,18000,CONT_BODY_N,*
V 6400,18800,CONT_BODY_N,*
V 6400,18400,CONT_BODY_N,*
V 6400,17200,CONT_BODY_N,*
V 6400,16400,CONT_BODY_N,*
V 6400,15600,CONT_BODY_N,*
V 6400,15200,CONT_BODY_N,*
V 6400,14800,CONT_BODY_N,*
V 6400,19600,CONT_BODY_N,*
V 6400,20800,CONT_BODY_N,*
V 6400,19200,CONT_BODY_N,*
V 6400,16800,CONT_BODY_N,*
V 6400,16000,CONT_BODY_N,*
V 6900,14400,CONT_BODY_N,*
V 6400,14400,CONT_BODY_N,*
V 6400,17600,CONT_BODY_N,*
V 6400,20400,CONT_BODY_N,*
V 6400,20000,CONT_BODY_N,*
V 6400,22400,CONT_BODY_N,*
V 6400,22800,CONT_BODY_N,*
V 6400,22000,CONT_BODY_N,*
V 6400,23300,CONT_BODY_N,*
V 6400,21200,CONT_BODY_N,*
V 7000,23300,CONT_BODY_N,*
V 6400,21600,CONT_BODY_N,*
V 6400,26700,CONT_BODY_P,*
V 6400,27900,CONT_BODY_P,*
V 7000,29500,CONT_BODY_P,*
V 7000,25100,CONT_BODY_P,*
V 10000,29100,CONT_BODY_P,*
V 6400,28300,CONT_BODY_P,*
V 6400,25500,CONT_BODY_P,*
V 6400,27100,CONT_BODY_P,*
V 6400,25100,CONT_BODY_P,*
V 6400,28700,CONT_BODY_P,*
V 6400,26300,CONT_BODY_P,*
V 10000,27900,CONT_BODY_P,*
V 10000,27500,CONT_BODY_P,*
V 6400,29100,CONT_BODY_P,*
V 6400,25900,CONT_BODY_P,*
V 6400,27500,CONT_BODY_P,*
V 10000,28700,CONT_BODY_P,*
V 6400,29500,CONT_BODY_P,*
V 10000,29500,CONT_VIA,*
V 10000,28300,CONT_VIA,*
V 9700,24600,CONT_VIA,*
V 10000,25100,CONT_VIA,*
V 10000,27100,CONT_VIA,*
V 10000,26700,CONT_BODY_P,*
V 10000,26300,CONT_BODY_P,*
V 10000,25900,CONT_VIA,*
V 10000,25500,CONT_BODY_P,*
V 9400,14400,CONT_BODY_N,*
V 10000,22800,CONT_BODY_N,*
V 10000,22000,CONT_BODY_N,*
V 10000,23300,CONT_BODY_N,*
V 10000,21200,CONT_BODY_N,*
V 10000,21600,CONT_BODY_N,*
V 10000,22400,CONT_BODY_N,*
V 10000,15600,CONT_BODY_N,*
V 10000,16800,CONT_BODY_N,*
V 10000,17200,CONT_BODY_N,*
V 10000,18400,CONT_BODY_N,*
V 10000,18800,CONT_BODY_N,*
V 10000,19200,CONT_BODY_N,*
V 10000,16400,CONT_BODY_N,*
V 10000,20800,CONT_BODY_N,*
V 10000,20400,CONT_BODY_N,*
V 10000,20000,CONT_BODY_N,*
V 10000,19600,CONT_BODY_N,*
V 10000,16000,CONT_BODY_N,*
V 10000,14400,CONT_BODY_N,*
V 10000,18000,CONT_BODY_N,*
V 10000,14800,CONT_BODY_N,*
V 10000,15200,CONT_BODY_N,*
V 10000,17600,CONT_BODY_N,*
V 9400,21900,CONT_DIF_P,*
V 9400,20700,CONT_DIF_P,*
V 9400,19500,CONT_DIF_P,*
V 9400,18300,CONT_DIF_P,*
V 9400,17100,CONT_DIF_P,*
V 9400,15900,CONT_DIF_P,*
V 7700,13800,CONT_VIA,*
V 8200,13800,CONT_POLY,*
EOF

533
alliance/src/cells/src/padlib/pali_sp.ap Normal file
View File

@ -0,0 +1,533 @@
V ALLIANCE : 6
H pali_sp,P, 9/10/2000,100
A 0,-700,17200,35600
C 0,29600,12000,vsse,0,WEST,ALU2
C 17200,29600,12000,vsse,1,EAST,ALU2
C 0,8400,4000,vddi,0,WEST,ALU2
C 0,4000,4000,vssi,0,WEST,ALU2
C 17200,4000,4000,vssi,1,EAST,ALU2
C 17200,8400,4000,vddi,1,EAST,ALU2
C 0,16800,12000,vdde,0,WEST,ALU2
C 17200,16800,12000,vdde,1,EAST,ALU2
C 17200,600,1200,ck,1,EAST,ALU2
C 0,600,1200,ck,0,WEST,ALU2
C 8200,-700,200,t,1,SOUTH,ALU2
C 8200,-700,200,t,0,SOUTH,ALU1
S 8400,12550,12400,12550,300,*,RIGHT,ALU1
S 12300,4600,12300,12600,300,*,UP,ALU1
S 7300,200,7300,4200,900,*,UP,ALU1
S 8800,200,8800,4200,200,*,UP,ALU1
S 10500,200,10500,4200,200,*,UP,ALU1
S 12000,200,12000,4200,800,*,UP,ALU1
S 11700,5300,11700,12000,200,*,UP,ALU1
S 10500,5200,10500,12000,200,*,UP,ALU1
S 8800,5200,8800,12000,200,*,UP,ALU1
S 6800,12000,11800,12000,200,*,RIGHT,ALU1
S 9900,13600,9900,22600,700,*,UP,ALU1
S 9100,13600,9100,22600,200,*,UP,ALU1
S 9000,13600,10100,13600,200,*,RIGHT,ALU1
S 7900,13800,7900,22600,200,*,UP,ALU1
S 8500,23800,9200,23800,300,*,RIGHT,POLY
S 9100,23800,9500,23800,200,*,RIGHT,ALU1
S 9700,24300,9700,28800,200,*,UP,ALU1
S 9100,24300,9100,28800,200,*,UP,ALU1
S 6400,24200,6400,28800,800,*,UP,ALU1
S 7900,23700,7900,28800,200,*,UP,ALU1
S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
S 8600,30100,8600,35600,1000,*,UP,ALU1
S 8200,-700,8200,-400,300,*,UP,ALU2
S 8500,12600,8500,13000,300,*,UP,ALU1
S 7200,29600,9100,29600,900,*,RIGHT,ALU1
S 100,600,17200,600,1200,ck,RIGHT,ALU2
S 6400,13500,6400,22600,800,*,UP,ALU1
S 6000,24300,6800,24300,300,*,RIGHT,PTIE
S 6100,24200,6100,28800,300,*,UP,PTIE
S 6000,28700,6800,28700,300,*,RIGHT,PTIE
S 9100,28700,9800,28700,300,*,RIGHT,PTIE
S 6100,22500,6700,22500,300,*,RIGHT,NTIE
S 6100,13600,6700,13600,300,*,RIGHT,NTIE
S 6100,13600,6100,22600,300,*,UP,NTIE
S 6700,14100,6700,22000,300,*,UP,PDIF
S 6700,24800,6700,28200,300,*,UP,NDIF
S 9600,13400,9600,22700,600,*,UP,NWELL
S 6400,13400,6400,22700,1000,*,UP,NWELL
S 11100,3600,11100,5700,300,*,UP,ALU1
S 11000,4700,12400,4700,300,*,RIGHT,ALU1
S 9300,5600,10000,5600,300,*,RIGHT,ALU1
S 9300,3700,10000,3700,300,*,RIGHT,ALU1
S 9900,4500,9900,8400,300,*,UP,ALU1
S 7200,5100,7200,12100,1000,*,UP,ALU1
S 9800,-300,11200,-300,300,*,RIGHT,ALU1
S 8200,-700,8200,11500,300,*,UP,ALU1
S 9900,-400,9900,4700,300,*,UP,ALU1
S 11100,-400,11100,3200,300,*,UP,ALU1
S 7900,600,8500,600,100,*,RIGHT,POLY
S 10200,5600,11200,5600,300,*,RIGHT,POLY
S 10200,5500,10200,5700,100,*,UP,POLY
S 10200,3700,11400,3700,300,*,RIGHT,POLY
S 7900,5600,9900,5600,300,*,RIGHT,POLY
S 7900,11700,8500,11700,100,*,RIGHT,POLY
S 7000,4100,12400,4100,300,*,RIGHT,PTIE
S 7000,400,7000,4200,300,*,UP,PTIE
S 6900,300,12400,300,300,*,RIGHT,PTIE
S 12300,200,12300,4200,300,*,UP,PTIE
S 11700,5100,11700,12100,300,*,UP,NTIE
S 6800,5200,11800,5200,300,*,RIGHT,NTIE
S 6900,5100,6900,12000,300,*,UP,NTIE
S 6800,12000,11800,12000,300,*,RIGHT,NTIE
S 8800,5900,8800,11500,400,*,UP,PDIF
S 8500,5700,8500,11700,100,*,UP,PTRANS
S 7900,5700,7900,11700,100,*,UP,PTRANS
S 10200,5700,10200,8700,100,*,UP,PTRANS
S 9900,5900,9900,8500,400,*,UP,PDIF
S 8200,5900,8200,11500,200,*,UP,PDIF
S 10500,5900,10500,8500,300,*,UP,PDIF
S 7600,5900,7600,11500,400,*,UP,PDIF
S 7900,600,7900,3600,100,*,UP,NTRANS
S 8500,600,8500,3600,100,*,UP,NTRANS
S 8800,800,8800,3400,400,*,UP,NDIF
S 7600,800,7600,3400,300,*,UP,NDIF
S 8200,800,8200,3400,200,*,UP,NDIF
S 11100,800,11100,3400,200,*,UP,NDIF
S 10500,800,10500,3400,200,*,UP,NDIF
S 11700,800,11700,3400,300,*,UP,NDIF
S 11700,800,11700,3400,200,*,UP,NDIF
S 10200,600,10200,3600,100,*,UP,NTRANS
S 9900,800,9900,3400,300,*,UP,NDIF
S 10800,600,10800,3600,100,*,UP,NTRANS
S 11400,600,11400,3600,100,*,UP,NTRANS
S 6700,8600,11900,8600,7200,*,RIGHT,NWELL
S 7900,3700,9900,3700,300,*,RIGHT,POLY
S 9700,24200,9700,28500,300,*,UP,PTIE
S 9100,24300,9700,24300,300,*,LEFT,PTIE
S 10000,13600,10000,22600,300,*,UP,NTIE
S 9900,13400,9900,22700,600,*,UP,NWELL
S 9500,13400,9500,22700,400,*,UP,NWELL
S 9300,13600,10000,13600,300,*,RIGHT,NTIE
S 9100,13100,9500,13100,200,*,RIGHT,ALU1
S 9100,22500,10000,22500,300,*,RIGHT,NTIE
S 8500,13000,8500,14300,300,*,DOWN,ALU1
S 6800,13600,8000,13600,300,*,RIGHT,ALU1
S 8500,13100,8500,13900,200,*,UP,POLY
S 6800,22500,9200,22500,300,*,RIGHT,NTIE
S 8500,23800,8500,24600,200,*,UP,POLY
S 7000,24600,8800,24600,100,*,RIGHT,POLY
S 8800,24300,9200,24300,300,*,RIGHT,PTIE
S 6800,24300,8200,24300,300,*,RIGHT,PTIE
S 8500,23700,8500,23900,200,*,DOWN,POLY
S 7000,13900,8800,13900,100,*,RIGHT,POLY
S 8800,13600,9200,13600,300,*,RIGHT,NTIE
S 6800,13600,8200,13600,300,*,RIGHT,NTIE
S 8100,13400,8100,22700,2800,*,UP,NWELL
S 8800,13900,8800,22200,100,*,UP,PTRANS
S 8200,13900,8200,22200,100,*,UP,PTRANS
S 7600,13900,7600,22200,100,*,UP,PTRANS
S 7000,13900,7000,22200,100,*,UP,PTRANS
S 7300,14100,7300,22000,200,*,UP,PDIF
S 7900,14100,7900,22000,200,*,UP,PDIF
S 8500,14100,8500,22000,200,*,UP,PDIF
S 9100,14100,9100,22000,300,*,UP,PDIF
S 6800,28700,9200,28700,300,*,RIGHT,PTIE
S 8800,24600,8800,28400,100,*,UP,NTRANS
S 8200,24600,8200,28400,100,*,UP,NTRANS
S 7600,24600,7600,28400,100,*,UP,NTRANS
S 7000,24600,7000,28400,100,*,UP,NTRANS
S 7300,24800,7300,28200,300,*,UP,NDIF
S 7900,24800,7900,28200,300,*,UP,NDIF
S 8500,24800,8500,28200,300,*,UP,NDIF
S 9100,24800,9100,28200,300,*,UP,NDIF
S 8500,14200,8500,29100,300,*,UP,ALU1
S 7300,14200,7300,29100,300,*,UP,ALU1
S 8500,13100,9100,13100,200,*,RIGHT,POLY
S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
V 10500,9500,CONT_VIA,*
B 7200,8400,1000,4000,CONT_VIA,*
B 12000,3100,700,2100,CONT_VIA,*
B 7300,3100,800,2100,CONT_VIA,*
B 9900,18050,600,9000,CONT_VIA,*
V 9100,13600,CONT_BODY_N,*
B 6400,26500,800,4600,CONT_VIA,*
B 6400,18000,800,9100,CONT_VIA,*
V 9100,23800,CONT_POLY,*
V 9500,23800,CONT_VIA,*
B 9400,26500,800,4600,CONT_VIA,*
V 8200,-500,CONT_VIA,*
V 6100,28700,CONT_BODY_P,*
V 9700,27900,CONT_BODY_P,*
V 6100,26700,CONT_BODY_P,*
V 6100,25100,CONT_BODY_P,*
V 6100,28300,CONT_BODY_P,*
V 9700,26700,CONT_BODY_P,*
V 9700,27100,CONT_BODY_P,*
V 6100,25500,CONT_BODY_P,*
V 6100,27900,CONT_BODY_P,*
V 6100,24300,CONT_BODY_P,*
V 6100,26300,CONT_BODY_P,*
V 6100,24700,CONT_BODY_P,*
V 6100,27500,CONT_BODY_P,*
V 9700,28300,CONT_BODY_P,*
V 6700,24300,CONT_BODY_P,*
V 6700,28700,CONT_BODY_P,*
V 6100,27100,CONT_BODY_P,*
V 6100,25900,CONT_BODY_P,*
V 6100,20800,CONT_BODY_N,*
V 6700,22500,CONT_BODY_N,*
V 6100,20400,CONT_BODY_N,*
V 6100,22500,CONT_BODY_N,*
V 6100,21200,CONT_BODY_N,*
V 6100,22000,CONT_BODY_N,*
V 6100,21600,CONT_BODY_N,*
V 6100,19200,CONT_BODY_N,*
V 6100,19600,CONT_BODY_N,*
V 6100,16800,CONT_BODY_N,*
V 6100,13600,CONT_BODY_N,*
V 6600,13600,CONT_BODY_N,*
V 6100,15200,CONT_BODY_N,*
V 6100,16000,CONT_BODY_N,*
V 6100,18400,CONT_BODY_N,*
V 6100,20000,CONT_BODY_N,*
V 6100,18800,CONT_BODY_N,*
V 6100,14000,CONT_BODY_N,*
V 6100,14400,CONT_BODY_N,*
V 6100,14800,CONT_BODY_N,*
V 6100,15600,CONT_BODY_N,*
V 6100,16400,CONT_BODY_N,*
V 6100,17600,CONT_BODY_N,*
V 6100,18000,CONT_BODY_N,*
V 6100,17200,CONT_BODY_N,*
V 6700,20700,CONT_DIF_P,*
V 6700,21900,CONT_DIF_P,*
V 6700,20300,CONT_DIF_P,*
V 6700,21500,CONT_DIF_P,*
V 6700,21100,CONT_DIF_P,*
V 6700,15500,CONT_DIF_P,*
V 6700,15100,CONT_DIF_P,*
V 6700,14700,CONT_DIF_P,*
V 6700,14300,CONT_DIF_P,*
V 6700,18300,CONT_DIF_P,*
V 6700,19500,CONT_DIF_P,*
V 6700,17100,CONT_DIF_P,*
V 6700,16700,CONT_DIF_P,*
V 6700,15900,CONT_DIF_P,*
V 6700,17500,CONT_DIF_P,*
V 6700,17900,CONT_DIF_P,*
V 6700,19100,CONT_DIF_P,*
V 6700,18700,CONT_DIF_P,*
V 6700,19900,CONT_DIF_P,*
V 6700,16300,CONT_DIF_P,*
V 6700,25300,CONT_DIF_N,*
V 6700,28100,CONT_DIF_N,*
V 6700,26500,CONT_DIF_N,*
V 6700,24900,CONT_DIF_N,*
V 6700,26100,CONT_DIF_N,*
V 6700,27300,CONT_DIF_N,*
V 6700,27700,CONT_DIF_N,*
V 6700,26900,CONT_DIF_N,*
V 6700,25700,CONT_DIF_N,*
V 10500,10200,CONT_VIA,*
V 8800,2200,CONT_VIA,*
V 8800,3200,CONT_VIA,*
V 10500,7800,CONT_VIA,*
V 11700,10200,CONT_VIA,*
V 11700,8600,CONT_VIA,*
V 11700,7100,CONT_VIA,*
V 10500,2200,CONT_VIA,*
V 10500,3200,CONT_VIA,*
V 10500,6600,CONT_VIA,*
V 8800,9000,CONT_VIA,*
V 8800,7800,CONT_VIA,*
V 8800,6600,CONT_VIA,*
V 8800,10200,CONT_VIA,*
V 10500,8700,CONT_VIA,*
V 11100,5600,CONT_POLY,*
V 9800,5600,CONT_POLY,*
V 9400,5600,CONT_POLY,*
V 9800,3700,CONT_POLY,*
V 11100,3700,CONT_POLY,*
V 9400,3700,CONT_POLY,*
V 7000,3700,CONT_BODY_P,*
V 7000,500,CONT_BODY_P,*
V 7000,900,CONT_BODY_P,*
V 7000,1700,CONT_BODY_P,*
V 12300,2900,CONT_BODY_P,*
V 7000,2100,CONT_BODY_P,*
V 8800,4100,CONT_BODY_P,*
V 12300,2500,CONT_BODY_P,*
V 7000,4100,CONT_BODY_P,*
V 7000,1300,CONT_BODY_P,*
V 7500,4100,CONT_BODY_P,*
V 12300,500,CONT_BODY_P,*
V 11700,4100,CONT_BODY_P,*
V 12300,3700,CONT_BODY_P,*
V 7000,3300,CONT_BODY_P,*
V 12300,3300,CONT_BODY_P,*
V 7000,2500,CONT_BODY_P,*
V 7000,2900,CONT_BODY_P,*
V 10500,4100,CONT_BODY_P,*
V 12300,900,CONT_BODY_P,*
V 12300,2100,CONT_BODY_P,*
V 12300,4100,CONT_BODY_P,*
V 12300,1300,CONT_BODY_P,*
V 12300,1700,CONT_BODY_P,*
V 11700,300,CONT_BODY_P,*
V 10500,300,CONT_BODY_P,*
V 8800,300,CONT_BODY_P,*
V 7500,300,CONT_BODY_P,*
V 11700,9200,CONT_BODY_N,*
V 11700,9700,CONT_BODY_N,*
V 6900,6900,CONT_BODY_N,*
V 6900,7900,CONT_BODY_N,*
V 6900,6400,CONT_BODY_N,*
V 6900,10900,CONT_BODY_N,*
V 6900,7400,CONT_BODY_N,*
V 11700,6100,CONT_BODY_N,*
V 11700,5300,CONT_BODY_N,*
V 8200,12000,CONT_BODY_N,*
V 6900,11400,CONT_BODY_N,*
V 6900,5900,CONT_BODY_N,*
V 6900,5400,CONT_BODY_N,*
V 6900,12000,CONT_BODY_N,*
V 6900,10400,CONT_BODY_N,*
V 8800,12000,CONT_BODY_N,*
V 6900,9900,CONT_BODY_N,*
V 6900,9400,CONT_BODY_N,*
V 6900,8900,CONT_BODY_N,*
V 6900,8400,CONT_BODY_N,*
V 7400,5200,CONT_BODY_N,*
V 7600,12000,CONT_BODY_N,*
V 11700,6600,CONT_BODY_N,*
V 11700,7600,CONT_BODY_N,*
V 11700,8100,CONT_BODY_N,*
V 11700,10900,CONT_BODY_N,*
V 11700,11400,CONT_BODY_N,*
V 8800,5200,CONT_BODY_N,*
V 11100,12000,CONT_BODY_N,*
V 11700,12000,CONT_BODY_N,*
V 10500,5200,CONT_BODY_N,*
V 10500,12000,CONT_BODY_N,*
V 8200,7400,CONT_DIF_P,*
V 8200,6600,CONT_DIF_P,*
V 8200,6200,CONT_DIF_P,*
V 7600,6900,CONT_DIF_P,*
V 8200,8200,CONT_DIF_P,*
V 7600,11400,CONT_DIF_P,*
V 7600,6400,CONT_DIF_P,*
V 7600,10900,CONT_DIF_P,*
V 8200,7800,CONT_DIF_P,*
V 8200,7000,CONT_DIF_P,*
V 8200,11400,CONT_DIF_P,*
V 8800,11400,CONT_DIF_P,*
V 9900,6700,CONT_DIF_P,*
V 8200,11000,CONT_DIF_P,*
V 8200,10600,CONT_DIF_P,*
V 8200,10200,CONT_DIF_P,*
V 9900,7300,CONT_DIF_P,*
V 9900,7800,CONT_DIF_P,*
V 9900,6200,CONT_DIF_P,*
V 9900,8300,CONT_DIF_P,*
V 10500,6200,CONT_DIF_P,*
V 10500,7000,CONT_DIF_P,*
V 10500,6200,CONT_DIF_P,*
V 10500,7400,CONT_DIF_P,*
V 10500,8200,CONT_DIF_P,*
V 8200,9800,CONT_DIF_P,*
V 7600,9900,CONT_DIF_P,*
V 7600,9400,CONT_DIF_P,*
V 7600,8900,CONT_DIF_P,*
V 8200,8600,CONT_DIF_P,*
V 8200,9000,CONT_DIF_P,*
V 8200,9400,CONT_DIF_P,*
V 8800,6200,CONT_DIF_P,*
V 7600,7900,CONT_DIF_P,*
V 7600,7400,CONT_DIF_P,*
V 7600,8400,CONT_DIF_P,*
V 7600,10400,CONT_DIF_P,*
V 8800,11000,CONT_DIF_P,*
V 8800,10600,CONT_DIF_P,*
V 8800,9800,CONT_DIF_P,*
V 8800,9400,CONT_DIF_P,*
V 8800,8600,CONT_DIF_P,*
V 8800,8200,CONT_DIF_P,*
V 8800,7400,CONT_DIF_P,*
V 8800,7000,CONT_DIF_P,*
V 8200,3100,CONT_DIF_N,*
V 7600,2600,CONT_DIF_N,*
V 11100,2600,CONT_DIF_N,*
V 8200,2100,CONT_DIF_N,*
V 9900,2100,CONT_DIF_N,*
V 7600,1600,CONT_DIF_N,*
V 7600,2100,CONT_DIF_N,*
V 11700,2600,CONT_DIF_N,*
V 11700,3100,CONT_DIF_N,*
V 7600,1100,CONT_DIF_N,*
V 9900,1100,CONT_DIF_N,*
V 11700,2100,CONT_DIF_N,*
V 11700,1600,CONT_DIF_N,*
V 7600,3100,CONT_DIF_N,*
V 11100,2100,CONT_DIF_N,*
V 11700,1100,CONT_DIF_N,*
V 10500,1700,CONT_DIF_N,*
V 11100,1100,CONT_DIF_N,*
V 8200,1600,CONT_DIF_N,*
V 8800,1200,CONT_DIF_N,*
V 8800,1700,CONT_DIF_N,*
V 8800,2700,CONT_DIF_N,*
V 10500,2700,CONT_DIF_N,*
V 10500,1200,CONT_DIF_N,*
V 9900,2600,CONT_DIF_N,*
V 9900,3100,CONT_DIF_N,*
V 11100,3100,CONT_DIF_N,*
V 8200,2600,CONT_DIF_N,*
V 9700,25900,CONT_BODY_P,*
V 9700,24700,CONT_BODY_P,*
V 9700,25500,CONT_BODY_P,*
V 9500,13100,CONT_VIA,*
V 10000,22500,CONT_BODY_N,*
V 10000,20800,CONT_BODY_N,*
V 10000,21600,CONT_BODY_N,*
V 10000,22000,CONT_BODY_N,*
V 10000,21200,CONT_BODY_N,*
V 10000,19200,CONT_BODY_N,*
V 10000,18800,CONT_BODY_N,*
V 10000,16800,CONT_BODY_N,*
V 10000,18400,CONT_BODY_N,*
V 10000,15600,CONT_BODY_N,*
V 10000,14800,CONT_BODY_N,*
V 10000,16000,CONT_BODY_N,*
V 10000,16400,CONT_BODY_N,*
V 10000,17600,CONT_BODY_N,*
V 10000,20000,CONT_BODY_N,*
V 10000,19600,CONT_BODY_N,*
V 10000,15200,CONT_BODY_N,*
V 9600,13600,CONT_BODY_N,*
V 10000,13600,CONT_BODY_N,*
V 10000,17200,CONT_BODY_N,*
V 10000,20400,CONT_BODY_N,*
V 10000,18000,CONT_BODY_N,*
V 10000,14000,CONT_BODY_N,*
V 10000,14400,CONT_BODY_N,*
V 7000,13600,CONT_BODY_N,*
V 7900,13600,CONT_VIA,*
V 7300,21900,CONT_DIF_P,*
V 7900,21900,CONT_DIF_P,*
V 8500,21900,CONT_DIF_P,*
V 9100,21900,CONT_DIF_P,*
V 7900,22500,CONT_BODY_N,*
V 9100,22500,CONT_BODY_N,*
V 7900,23800,CONT_VIA,*
V 9100,24300,CONT_BODY_P,*
V 7900,24300,CONT_BODY_P,*
V 9100,21500,CONT_DIF_P,*
V 8500,21500,CONT_DIF_P,*
V 7900,21500,CONT_DIF_P,*
V 7300,21500,CONT_DIF_P,*
V 7900,21100,CONT_VIA,*
V 9100,21100,CONT_VIA,*
V 8500,21100,CONT_DIF_P,*
V 7300,21100,CONT_DIF_P,*
V 7300,20700,CONT_DIF_P,*
V 8500,20700,CONT_DIF_P,*
V 9100,20700,CONT_DIF_P,*
V 7900,20700,CONT_DIF_P,*
V 9100,20300,CONT_DIF_P,*
V 7900,20300,CONT_DIF_P,*
V 8500,20300,CONT_DIF_P,*
V 7300,20300,CONT_DIF_P,*
V 9100,19900,CONT_VIA,*
V 7900,19900,CONT_VIA,*
V 8500,19900,CONT_DIF_P,*
V 7300,19900,CONT_DIF_P,*
V 9100,16300,CONT_VIA,*
V 9100,17500,CONT_VIA,*
V 9100,18700,CONT_VIA,*
V 7900,16300,CONT_VIA,*
V 7900,18700,CONT_VIA,*
V 7900,17500,CONT_VIA,*
V 9100,15100,CONT_VIA,*
V 7900,15100,CONT_VIA,*
V 8500,16700,CONT_DIF_P,*
V 9100,16700,CONT_DIF_P,*
V 9100,17100,CONT_DIF_P,*
V 9100,15900,CONT_DIF_P,*
V 8500,15900,CONT_DIF_P,*
V 8500,16300,CONT_DIF_P,*
V 9100,18300,CONT_DIF_P,*
V 9100,17900,CONT_DIF_P,*
V 8500,17900,CONT_DIF_P,*
V 8500,17100,CONT_DIF_P,*
V 8500,17500,CONT_DIF_P,*
V 8500,19500,CONT_DIF_P,*
V 9100,19100,CONT_DIF_P,*
V 8500,19100,CONT_DIF_P,*
V 8500,18700,CONT_DIF_P,*
V 8500,18300,CONT_DIF_P,*
V 9100,19500,CONT_DIF_P,*
V 9100,15500,CONT_DIF_P,*
V 8500,15500,CONT_DIF_P,*
V 7900,17100,CONT_DIF_P,*
V 7900,16700,CONT_DIF_P,*
V 7300,16700,CONT_DIF_P,*
V 7300,17100,CONT_DIF_P,*
V 7300,17500,CONT_DIF_P,*
V 7900,15900,CONT_DIF_P,*
V 7300,15900,CONT_DIF_P,*
V 7300,16300,CONT_DIF_P,*
V 7900,19500,CONT_DIF_P,*
V 7900,19100,CONT_DIF_P,*
V 7300,19100,CONT_DIF_P,*
V 7300,18700,CONT_DIF_P,*
V 7900,18300,CONT_DIF_P,*
V 7300,18300,CONT_DIF_P,*
V 7900,17900,CONT_DIF_P,*
V 7300,17900,CONT_DIF_P,*
V 7300,19500,CONT_DIF_P,*
V 7300,15500,CONT_DIF_P,*
V 7900,15500,CONT_DIF_P,*
V 8500,15100,CONT_DIF_P,*
V 9100,14700,CONT_DIF_P,*
V 8500,14700,CONT_DIF_P,*
V 9100,14300,CONT_DIF_P,*
V 8500,14300,CONT_DIF_P,*
V 7300,14300,CONT_DIF_P,*
V 7300,15100,CONT_DIF_P,*
V 7900,14700,CONT_DIF_P,*
V 7300,14700,CONT_DIF_P,*
V 7900,14300,CONT_DIF_P,*
V 8500,27400,CONT_DIF_N,*
V 8500,27000,CONT_DIF_N,*
V 8500,26600,CONT_DIF_N,*
V 8500,27800,CONT_DIF_N,*
V 8500,25000,CONT_DIF_N,*
V 8500,25400,CONT_DIF_N,*
V 8500,26200,CONT_DIF_N,*
V 8500,25800,CONT_DIF_N,*
V 7300,27000,CONT_DIF_N,*
V 7300,26600,CONT_DIF_N,*
V 7300,26200,CONT_DIF_N,*
V 7300,25800,CONT_DIF_N,*
V 7300,25400,CONT_DIF_N,*
V 7300,27800,CONT_DIF_N,*
V 7300,27400,CONT_DIF_N,*
V 7300,25000,CONT_DIF_N,*
V 7500,13600,CONT_BODY_N,*
V 7900,28700,CONT_BODY_P,*
V 9100,28700,CONT_BODY_P,*
V 7900,26100,CONT_VIA,*
V 7900,27700,CONT_VIA,*
V 7900,25700,CONT_DIF_N,*
V 7900,28100,CONT_DIF_N,*
V 7900,26500,CONT_DIF_N,*
V 7900,27300,CONT_DIF_N,*
V 7900,26900,CONT_DIF_N,*
V 7900,25300,CONT_DIF_N,*
V 7900,24900,CONT_VIA,*
V 9100,25300,CONT_DIF_N,*
V 9100,26900,CONT_DIF_N,*
V 9100,27300,CONT_DIF_N,*
V 9100,25700,CONT_DIF_N,*
V 9100,26100,CONT_DIF_N,*
V 9100,27700,CONT_DIF_N,*
V 9100,13100,CONT_POLY,*
EOF

2062
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1512
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1502
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alliance/src/cells/src/padlib/palvdde_sp.ap Normal file
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@ -0,0 +1,140 @@
V ALLIANCE : 3
H palvdde_sp,P,11/ 9/95
A 0,-7,172,356
C 172,168,120,vdde,1,EAST,ALU2
C 0,168,120,vdde,0,WEST,ALU2
C 172,84,40,vddi,1,EAST,ALU2
C 0,84,40,vddi,0,WEST,ALU2
C 172,40,40,vssi,1,EAST,ALU2
C 0,40,40,vssi,0,WEST,ALU2
C 172,6,12,ck,1,EAST,ALU2
C 0,6,12,ck,0,WEST,ALU2
C 172,296,120,vsse,1,EAST,ALU2
C 0,296,120,vsse,0,WEST,ALU2
S 0,40,172,40,40,vssi,RIGHT,ALU2
S 0,84,172,84,40,vddi,RIGHT,ALU2
S 0,168,172,168,120,vdde,RIGHT,ALU2
S 0,6,172,6,12,ck,RIGHT,ALU2
S 0,296,172,296,120,vsse,RIGHT,ALU2
S 86,108,86,356,100,*,UP,ALU1
V 42,110,CONT_VIA
V 62,110,CONT_VIA
V 82,110,CONT_VIA
V 102,110,CONT_VIA
V 122,110,CONT_VIA
V 132,115,CONT_VIA
V 132,125,CONT_VIA
V 132,145,CONT_VIA
V 132,175,CONT_VIA
V 132,185,CONT_VIA
V 132,195,CONT_VIA
V 122,150,CONT_VIA
V 122,180,CONT_VIA
V 122,190,CONT_VIA
V 122,120,CONT_VIA
V 132,135,CONT_VIA
V 112,155,CONT_VIA
V 112,145,CONT_VIA
V 132,155,CONT_VIA
V 132,165,CONT_VIA
V 112,125,CONT_VIA
V 112,115,CONT_VIA
V 122,130,CONT_VIA
V 122,140,CONT_VIA
V 92,115,CONT_VIA
V 112,135,CONT_VIA
V 122,160,CONT_VIA
V 122,170,CONT_VIA
V 112,195,CONT_VIA
V 112,185,CONT_VIA
V 112,175,CONT_VIA
V 112,165,CONT_VIA
V 92,195,CONT_VIA
V 92,185,CONT_VIA
V 92,175,CONT_VIA
V 102,180,CONT_VIA
V 102,190,CONT_VIA
V 102,120,CONT_VIA
V 92,125,CONT_VIA
V 82,190,CONT_VIA
V 82,180,CONT_VIA
V 102,130,CONT_VIA
V 102,140,CONT_VIA
V 102,150,CONT_VIA
V 102,160,CONT_VIA
V 102,170,CONT_VIA
V 82,130,CONT_VIA
V 72,115,CONT_VIA
V 72,125,CONT_VIA
V 92,165,CONT_VIA
V 92,155,CONT_VIA
V 92,145,CONT_VIA
V 92,135,CONT_VIA
V 82,120,CONT_VIA
V 72,165,CONT_VIA
V 72,175,CONT_VIA
V 72,185,CONT_VIA
V 72,195,CONT_VIA
V 82,170,CONT_VIA
V 82,160,CONT_VIA
V 82,150,CONT_VIA
V 82,140,CONT_VIA
V 52,125,CONT_VIA
V 62,120,CONT_VIA
V 62,190,CONT_VIA
V 62,180,CONT_VIA
V 72,135,CONT_VIA
V 72,145,CONT_VIA
V 72,155,CONT_VIA
V 52,185,CONT_VIA
V 52,195,CONT_VIA
V 62,170,CONT_VIA
V 62,160,CONT_VIA
V 62,150,CONT_VIA
V 62,140,CONT_VIA
V 62,130,CONT_VIA
V 52,115,CONT_VIA
V 42,190,CONT_VIA
V 42,120,CONT_VIA
V 52,135,CONT_VIA
V 52,145,CONT_VIA
V 52,155,CONT_VIA
V 52,165,CONT_VIA
V 52,175,CONT_VIA
V 42,130,CONT_VIA
V 42,140,CONT_VIA
V 42,150,CONT_VIA
V 42,160,CONT_VIA
V 42,170,CONT_VIA
V 42,180,CONT_VIA
V 122,200,CONT_VIA
V 132,205,CONT_VIA
V 132,215,CONT_VIA
V 132,225,CONT_VIA
V 112,225,CONT_VIA
V 112,215,CONT_VIA
V 92,205,CONT_VIA
V 82,200,CONT_VIA
V 102,200,CONT_VIA
V 112,205,CONT_VIA
V 122,210,CONT_VIA
V 122,220,CONT_VIA
V 102,220,CONT_VIA
V 82,220,CONT_VIA
V 82,210,CONT_VIA
V 72,205,CONT_VIA
V 72,215,CONT_VIA
V 72,225,CONT_VIA
V 92,225,CONT_VIA
V 92,215,CONT_VIA
V 62,220,CONT_VIA
V 62,210,CONT_VIA
V 52,205,CONT_VIA
V 52,215,CONT_VIA
V 52,225,CONT_VIA
V 62,200,CONT_VIA
V 102,210,CONT_VIA
V 42,200,CONT_VIA
V 42,210,CONT_VIA
V 42,220,CONT_VIA
EOF

290
alliance/src/cells/src/padlib/palvddeck_sp.ap Normal file
View File

@ -0,0 +1,290 @@
V ALLIANCE : 6
H palvddeck_sp,P,13/10/2000,100
A 0,-700,17200,35600
C 0,29600,12000,vsse,0,WEST,ALU2
C 17200,29600,12000,vsse,1,EAST,ALU2
C 0,600,1200,ck,0,WEST,ALU2
C 17200,600,1200,ck,1,EAST,ALU2
C 0,4000,4000,vssi,0,WEST,ALU2
C 17200,4000,4000,vssi,1,EAST,ALU2
C 0,8400,4000,vddi,0,WEST,ALU2
C 17200,8400,4000,vddi,1,EAST,ALU2
C 0,16800,12000,vdde,0,WEST,ALU2
C 17200,16800,12000,vdde,1,EAST,ALU2
C 6700,-700,200,cko,1,SOUTH,ALU2
C 6700,-700,200,cko,0,SOUTH,ALU1
C 7900,-700,200,cko,3,SOUTH,ALU2
C 7900,-700,200,cko,2,SOUTH,ALU1
C 9100,-700,200,cko,5,SOUTH,ALU2
C 9100,-700,200,cko,4,SOUTH,ALU1
S 8600,10900,8600,35600,10000,*,UP,ALU1
S 8500,2100,8500,4900,200,*,UP,ALU1
S 7300,2200,7300,4500,200,*,UP,ALU1
S 4300,2100,6100,2100,300,*,RIGHT,ALU1
S 4300,2000,4300,5100,200,*,UP,ALU1
S 6100,10400,9700,10400,200,*,RIGHT,ALU1
S 6700,6600,9100,6600,200,*,RIGHT,ALU1
S 6200,6100,7200,6100,200,*,RIGHT,ALU1
S 6200,6100,6200,6900,200,*,UP,ALU1
S 4300,6100,4300,10400,300,*,UP,ALU1
S 6200,5000,8500,5000,200,*,RIGHT,ALU1
S 3800,100,3800,5600,200,*,UP,ALU1
S 3800,5600,5200,5600,200,*,RIGHT,ALU1
S 6200,4400,6200,5000,200,*,UP,ALU1
S 9700,6000,9700,10400,200,*,UP,ALU1
S 4200,6100,5000,6100,200,*,RIGHT,ALU1
S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
S 5700,4900,5700,6200,200,*,UP,ALU1
S 5500,2800,5500,5100,200,*,UP,ALU1
S 4100,8500,9900,8500,5200,*,RIGHT,NWELL
S 5800,5600,7600,5600,200,*,RIGHT,ALU1
S 6100,6800,6100,10400,200,*,UP,ALU1
S 7300,7100,7300,10400,200,*,UP,ALU1
S 8500,7100,8500,10400,200,*,UP,ALU1
S 6000,10400,9800,10400,300,*,RIGHT,NTIE
S 6100,10300,6100,11100,300,*,UP,NTIE
S 9700,6100,9700,10500,300,*,UP,NTIE
S 7900,6700,7900,9600,200,*,UP,ALU1
S 6700,6700,6700,9600,200,*,UP,ALU1
S 9100,6600,9100,9900,300,*,UP,PDIF
S 8500,6600,8500,9900,200,*,UP,PDIF
S 7900,6600,7900,9900,200,*,UP,PDIF
S 7300,6600,7300,9900,200,*,UP,PDIF
S 6100,6600,6100,9900,300,*,UP,PDIF
S 6700,6600,6700,9900,200,*,UP,PDIF
S 6400,6400,6400,10100,100,*,UP,PTRANS
S 7000,6400,7000,10100,100,*,UP,PTRANS
S 7600,6400,7600,10100,100,*,UP,PTRANS
S 8200,6400,8200,10100,100,*,UP,PTRANS
S 8800,6400,8800,10100,100,*,UP,PTRANS
S 4200,6100,5000,6100,300,*,RIGHT,NTIE
S 4300,6000,4300,11000,300,*,UP,NTIE
S 4900,6600,4900,10400,300,*,UP,PDIF
S 4900,6800,4900,10400,200,*,UP,ALU1
S 6100,2000,6100,4500,200,*,UP,ALU1
S 9700,2000,9700,5100,300,*,UP,PTIE
S 9700,2000,9700,5100,300,*,UP,ALU1
S 4200,5000,5000,5000,300,*,RIGHT,PTIE
S 4200,2100,9800,2100,300,*,RIGHT,PTIE
S 9700,2000,9700,5100,300,*,UP,PTIE
S 4300,2000,4300,5100,300,*,UP,PTIE
S 8500,2600,8500,4500,200,*,UP,NDIF
S 7300,2600,7300,4400,200,*,UP,NDIF
S 4900,2600,4900,4400,300,*,UP,NDIF
S 6100,2600,6100,4400,300,*,UP,NDIF
S 7900,2600,7900,4400,300,*,UP,NDIF
S 5500,2600,5500,4500,300,*,UP,NDIF
S 9100,2600,9100,4500,300,*,UP,NDIF
S 5500,6600,5500,10500,300,*,UP,PDIF
S 6700,2600,6700,4500,200,*,UP,NDIF
S 4900,2000,4900,5100,200,*,UP,ALU1
S 7600,2400,7600,4700,100,*,UP,NTRANS
S 8200,2400,8200,4700,100,*,UP,NTRANS
S 8800,2400,8800,4700,100,*,UP,NTRANS
S 5200,2400,5200,4700,100,*,UP,NTRANS
S 6400,2400,6400,4700,100,*,UP,NTRANS
S 7000,2400,7000,4700,100,*,UP,NTRANS
S 5200,6400,5200,10700,100,*,UP,PTRANS
S 5400,6100,7200,6100,300,*,RIGHT,NTIE
S 8000,6100,9800,6100,300,*,RIGHT,NTIE
S 8000,5000,9800,5000,300,*,RIGHT,PTIE
S 5400,5000,7200,5000,300,*,RIGHT,PTIE
S 6400,6400,8800,6400,100,*,RIGHT,POLY
S 5200,4700,5200,6400,100,*,UP,POLY
S 6400,4700,8800,4700,100,*,RIGHT,POLY
S 7600,4700,7600,6400,500,*,UP,POLY
S 5500,6100,5500,10400,200,*,UP,ALU1
S 0,600,17200,600,1200,ck,RIGHT,ALU2
S 6700,-700,6700,4400,200,*,UP,ALU1
S 7900,-700,7900,4400,200,*,UP,ALU1
S 9100,-700,9100,9600,200,*,UP,ALU1
S 6700,1600,9100,1600,200,*,RIGHT,ALU1
S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
B 8600,16800,10000,12000,CONT_VIA,*
B 3800,5600,200,200,CONT_TURN1,*
V 4300,10300,CONT_BODY_N,*
V 4300,9700,CONT_VIA,*
V 4300,9300,CONT_BODY_N,*
V 4300,8900,CONT_BODY_N,*
V 4300,8500,CONT_VIA,*
V 4300,8100,CONT_BODY_N,*
V 4300,7700,CONT_BODY_N,*
V 5200,5600,CONT_POLY,*
V 4300,7300,CONT_BODY_N,*
V 4300,6900,CONT_VIA,*
V 4300,6500,CONT_BODY_N,*
V 4300,6100,CONT_BODY_N,*
V 4900,6100,CONT_BODY_N,*
V 6700,6100,CONT_BODY_N,*
V 6200,6100,CONT_BODY_N,*
V 7100,6100,CONT_BODY_N,*
V 7600,5600,CONT_POLY,*
V 9700,9600,CONT_VIA,*
V 9700,7000,CONT_VIA,*
V 9700,6500,CONT_BODY_N,*
V 9700,6100,CONT_BODY_N,*
V 9700,7600,CONT_BODY_N,*
V 9700,8000,CONT_BODY_N,*
V 9700,8400,CONT_BODY_N,*
V 9700,8800,CONT_BODY_N,*
V 9700,9200,CONT_BODY_N,*
V 9700,10000,CONT_BODY_N,*
V 9700,10400,CONT_BODY_N,*
V 9300,10400,CONT_BODY_N,*
V 8900,10400,CONT_BODY_N,*
V 8500,10400,CONT_BODY_N,*
V 8100,10400,CONT_BODY_N,*
V 7700,10400,CONT_BODY_N,*
V 7300,10400,CONT_BODY_N,*
V 6900,10400,CONT_BODY_N,*
V 6500,10400,CONT_BODY_N,*
V 6100,10400,CONT_BODY_N,*
V 8500,7100,CONT_DIF_P,*
V 8500,9600,CONT_DIF_P,*
V 8500,9200,CONT_DIF_P,*
V 8500,8800,CONT_DIF_P,*
V 8500,8000,CONT_DIF_P,*
V 8500,7600,CONT_DIF_P,*
V 8500,10000,CONT_VIA,*
V 8500,8400,CONT_VIA,*
V 7300,7100,CONT_DIF_P,*
V 7300,7600,CONT_DIF_P,*
V 7300,8000,CONT_DIF_P,*
V 7300,8800,CONT_DIF_P,*
V 7300,9200,CONT_DIF_P,*
V 7300,9600,CONT_DIF_P,*
V 7300,8400,CONT_VIA,*
V 7300,10000,CONT_VIA,*
V 4900,6800,CONT_DIF_P,*
V 4900,10400,CONT_DIF_P,*
V 4900,9600,CONT_DIF_P,*
V 4900,9200,CONT_DIF_P,*
V 4900,8800,CONT_DIF_P,*
V 4900,8000,CONT_DIF_P,*
V 4900,7600,CONT_DIF_P,*
V 4900,7200,CONT_VIA,*
V 4900,10000,CONT_VIA,*
V 4900,8400,CONT_VIA,*
V 6100,7200,CONT_VIA,*
V 6100,8400,CONT_VIA,*
V 6100,10000,CONT_VIA,*
V 6100,6800,CONT_DIF_P,*
V 6100,7600,CONT_DIF_P,*
V 6100,8000,CONT_DIF_P,*
V 6100,8800,CONT_DIF_P,*
V 6100,9200,CONT_DIF_P,*
V 6100,9600,CONT_DIF_P,*
V 6200,5000,CONT_BODY_P,*
V 6600,5000,CONT_VIA,*
V 8100,5000,CONT_BODY_P,*
V 7100,5000,CONT_BODY_P,*
V 9700,2500,CONT_BODY_P,*
V 9700,3300,CONT_BODY_P,*
V 9700,3700,CONT_BODY_P,*
V 9700,4100,CONT_BODY_P,*
V 9700,5000,CONT_BODY_P,*
V 9700,2100,CONT_BODY_P,*
V 9700,4500,CONT_VIA,*
V 9700,2900,CONT_VIA,*
V 4300,5000,CONT_BODY_P,*
V 4300,4500,CONT_VIA,*
V 4300,4100,CONT_BODY_P,*
V 4300,3700,CONT_BODY_P,*
V 4300,3300,CONT_BODY_P,*
V 4300,2900,CONT_VIA,*
V 4300,2500,CONT_BODY_P,*
V 4300,2100,CONT_BODY_P,*
V 5300,2100,CONT_BODY_P,*
V 5700,2100,CONT_BODY_P,*
V 4900,5000,CONT_BODY_P,*
V 8500,5000,CONT_BODY_P,*
V 4900,2100,CONT_BODY_P,*
V 6100,2100,CONT_BODY_P,*
V 7300,2100,CONT_BODY_P,*
V 8500,2100,CONT_BODY_P,*
V 8500,2400,CONT_VIA,*
V 7300,2400,CONT_VIA,*
V 6100,2400,CONT_VIA,*
V 4900,2400,CONT_VIA,*
V 8500,2800,CONT_DIF_N,*
V 7300,2800,CONT_DIF_N,*
V 6100,2800,CONT_DIF_N,*
V 4900,2800,CONT_DIF_N,*
V 4900,3200,CONT_DIF_N,*
V 6100,3200,CONT_DIF_N,*
V 7300,3200,CONT_DIF_N,*
V 8500,3200,CONT_DIF_N,*
V 8500,3600,CONT_DIF_N,*
V 7300,3600,CONT_DIF_N,*
V 6100,3600,CONT_DIF_N,*
V 4900,3600,CONT_DIF_N,*
V 4900,4400,CONT_DIF_N,*
V 4900,4000,CONT_VIA,*
V 8500,4000,CONT_VIA,*
V 7300,4000,CONT_VIA,*
V 6100,4000,CONT_VIA,*
V 8500,4400,CONT_DIF_N,*
V 6100,4400,CONT_DIF_N,*
V 7300,4400,CONT_DIF_N,*
V 9100,3600,CONT_DIF_N,*
V 9100,4000,CONT_DIF_N,*
V 9100,4400,CONT_DIF_N,*
V 9100,2800,CONT_DIF_N,*
V 7900,3600,CONT_DIF_N,*
V 7900,3200,CONT_DIF_N,*
V 7900,4400,CONT_DIF_N,*
V 7900,4000,CONT_DIF_N,*
V 6700,4000,CONT_DIF_N,*
V 6700,4400,CONT_DIF_N,*
V 6700,2800,CONT_DIF_N,*
V 6700,3200,CONT_DIF_N,*
V 6700,3600,CONT_DIF_N,*
V 9100,3200,CONT_DIF_N,*
V 7900,2800,CONT_DIF_N,*
V 5500,4000,CONT_DIF_N,*
V 5500,4400,CONT_DIF_N,*
V 5500,2800,CONT_DIF_N,*
V 5500,3200,CONT_DIF_N,*
V 5500,3600,CONT_DIF_N,*
V 9100,9200,CONT_DIF_P,*
V 9100,9600,CONT_DIF_P,*
V 9100,6800,CONT_DIF_P,*
V 9100,7200,CONT_DIF_P,*
V 9100,7600,CONT_DIF_P,*
V 9100,8000,CONT_DIF_P,*
V 7900,8800,CONT_DIF_P,*
V 7900,8400,CONT_DIF_P,*
V 9100,8400,CONT_DIF_P,*
V 9100,8800,CONT_DIF_P,*
V 7900,7200,CONT_DIF_P,*
V 7900,6800,CONT_DIF_P,*
V 7900,9600,CONT_DIF_P,*
V 7900,9200,CONT_DIF_P,*
V 6700,6800,CONT_DIF_P,*
V 6700,7200,CONT_DIF_P,*
V 6700,7600,CONT_DIF_P,*
V 6700,8000,CONT_DIF_P,*
V 6700,8400,CONT_DIF_P,*
V 6700,8800,CONT_DIF_P,*
V 7900,8000,CONT_DIF_P,*
V 7900,7600,CONT_DIF_P,*
V 6700,9200,CONT_DIF_P,*
V 6700,9600,CONT_DIF_P,*
V 5500,10000,CONT_DIF_P,*
V 5500,10400,CONT_DIF_P,*
V 5500,6800,CONT_DIF_P,*
V 5500,7200,CONT_DIF_P,*
V 5500,7600,CONT_DIF_P,*
V 5500,8000,CONT_DIF_P,*
V 5500,8400,CONT_DIF_P,*
V 5500,8800,CONT_DIF_P,*
V 5500,9200,CONT_DIF_P,*
V 5500,9600,CONT_DIF_P,*
V 3800,200,CONT_VIA,*
V 3800,1000,CONT_VIA,*
V 6700,-700,CONT_VIA,*
V 7900,-700,CONT_VIA,*
V 9100,-700,CONT_VIA,*
EOF

44
alliance/src/cells/src/padlib/palvddi_sp.ap Normal file
View File

@ -0,0 +1,44 @@
V ALLIANCE : 6
H palvddi_sp,P,13/10/2000,100
A 0,-700,17200,35600
C 8600,-700,10000,vddi,0,SOUTH,ALU1
C 8600,-700,10000,vddi,2,SOUTH,ALU2
C 17200,16800,12000,vdde,1,EAST,ALU2
C 0,16800,12000,vdde,0,WEST,ALU2
C 17200,8400,4000,vddi,4,EAST,ALU2
C 0,8400,4000,vddi,3,WEST,ALU2
C 17200,4000,4000,vssi,1,EAST,ALU2
C 0,4000,4000,vssi,0,WEST,ALU2
C 17200,600,1200,ck,1,EAST,ALU2
C 0,600,1200,ck,0,WEST,ALU2
C 17200,29600,12000,vsse,1,EAST,ALU2
C 0,29600,12000,vsse,0,WEST,ALU2
S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
S 0,8400,17100,8400,4000,vddi,RIGHT,ALU2
S 0,600,17200,600,1200,ck,RIGHT,ALU2
S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
S 8600,-700,8600,35600,10000,*,UP,ALU1
V 5700,-400,CONT_VIA,*
V 5200,-400,CONT_VIA,*
V 4700,-400,CONT_VIA,*
V 4200,-400,CONT_VIA,*
V 3700,-400,CONT_VIA,*
V 9700,-400,CONT_VIA,*
V 10200,-400,CONT_VIA,*
V 7700,-400,CONT_VIA,*
V 8200,-400,CONT_VIA,*
V 8700,-400,CONT_VIA,*
V 9200,-400,CONT_VIA,*
V 6700,-400,CONT_VIA,*
V 7200,-400,CONT_VIA,*
V 6200,-400,CONT_VIA,*
V 10700,-400,CONT_VIA,*
V 11200,-400,CONT_VIA,*
V 11700,-400,CONT_VIA,*
V 12200,-400,CONT_VIA,*
V 13200,-400,CONT_VIA,*
V 12700,-400,CONT_VIA,*
B 8600,-500,10000,400,CONT_TURN2,*
B 8600,8400,10000,4000,CONT_VIA,*
EOF

411
alliance/src/cells/src/padlib/palvddick_sp.ap Normal file
View File

@ -0,0 +1,411 @@
V ALLIANCE : 6
H palvddick_sp,P,13/10/2000,100
A 0,-700,17200,35600
C 8600,-700,10000,vddi,0,SOUTH,ALU1
C 17200,600,1200,ck,1,EAST,ALU2
C 17200,4000,4000,vssi,1,EAST,ALU2
C 17200,8400,4000,vddi,4,EAST,ALU2
C 0,600,1200,ck,0,WEST,ALU2
C 0,4000,4000,vssi,0,WEST,ALU2
C 0,8400,4000,vddi,3,WEST,ALU2
C 0,16800,12000,vdde,0,WEST,ALU2
C 17200,16800,12000,vdde,1,EAST,ALU2
C 8600,-700,10000,vddi,1,SOUTH,ALU2
C 15500,-700,200,cko,3,SOUTH,ALU2
C 15500,-700,200,cko,2,SOUTH,ALU1
C 1700,-700,200,cko,1,SOUTH,ALU2
C 1700,-700,200,cko,0,SOUTH,ALU1
C 17200,29600,12000,vsse,1,EAST,ALU2
C 0,29600,12000,vsse,0,WEST,ALU2
S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
S 15500,-700,15500,1500,200,*,UP,ALU1
S 0,600,17200,600,1200,ck,RIGHT,ALU2
S 1700,-700,1700,1600,200,*,DOWN,ALU1
S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
S 8600,-700,8600,35600,10000,*,UP,ALU1
S 15200,5200,15800,5200,100,*,RIGHT,POLY
S 14900,7100,15500,7100,100,*,RIGHT,POLY
S 13600,5700,14100,5700,300,*,RIGHT,PTIE
S 14300,5200,14300,7100,100,*,DOWN,POLY
S 14300,5200,14600,5200,100,*,RIGHT,POLY
S 14200,2100,16800,2100,300,*,LEFT,PTIE
S 14300,2100,14300,3400,300,*,UP,PTIE
S 13300,6800,14100,6800,300,*,RIGHT,NTIE
S 14400,300,14400,3800,200,*,DOWN,ALU1
S 13600,3300,14300,3300,300,*,LEFT,PTIE
S 14300,4400,14300,6300,200,*,DOWN,ALU1
S 14600,3700,14600,3900,100,*,DOWN,POLY
S 13200,12700,16600,12700,400,*,RIGHT,NWELL
S 13200,9700,16600,9700,6200,*,RIGHT,NWELL
S 14300,7100,14300,9400,100,*,UP,PTRANS
S 14900,7100,14900,12400,100,*,UP,PTRANS
S 15500,7100,15500,12400,100,*,UP,PTRANS
S 13400,6700,13400,9800,300,*,UP,NTIE
S 13300,9700,14100,9700,300,*,RIGHT,NTIE
S 15200,7300,15200,12200,200,*,DOWN,PDIF
S 15800,7300,15800,12200,300,*,DOWN,PDIF
S 14600,7300,14600,12200,300,*,DOWN,PDIF
S 14000,7300,14000,9200,300,*,DOWN,PDIF
S 14000,9600,14000,12800,300,*,UP,NTIE
S 14000,12700,16500,12700,300,*,RIGHT,NTIE
S 16400,6700,16400,12800,300,*,UP,NTIE
S 14000,6300,14000,9100,200,*,DOWN,ALU1
S 15200,6300,15200,11900,200,*,DOWN,ALU1
S 16700,2100,16700,5800,300,*,DOWN,PTIE
S 15800,2400,15800,5200,100,*,DOWN,NTRANS
S 14600,3900,14600,5200,100,*,DOWN,NTRANS
S 15200,2400,15200,5200,100,*,DOWN,NTRANS
S 16100,2600,16100,5000,300,*,DOWN,NDIF
S 14300,4100,14300,5000,300,*,DOWN,NDIF
S 14900,2600,14900,5000,300,*,DOWN,NDIF
S 15500,2600,15500,5000,300,*,DOWN,NDIF
S 13700,3400,13700,5800,300,*,UP,PTIE
S 14900,2100,14900,5800,200,*,DOWN,ALU1
S 15500,1500,15500,6300,200,*,DOWN,ALU1
S 15400,5200,15400,7100,200,*,UP,POLY
S 14700,6300,15300,6300,300,*,LEFT,POLY
S 15700,5700,16700,5700,300,*,RIGHT,PTIE
S 14500,5700,15100,5700,300,*,RIGHT,PTIE
S 15700,6800,16400,6800,300,*,RIGHT,NTIE
S 14500,6800,15100,6800,300,*,RIGHT,NTIE
S 1400,5200,2000,5200,100,*,RIGHT,POLY
S 1700,7100,2300,7100,100,*,RIGHT,POLY
S 3100,5700,3600,5700,300,*,RIGHT,PTIE
S 2900,5200,2900,7100,100,*,UP,POLY
S 2600,5200,2900,5200,100,*,RIGHT,POLY
S 400,2100,3000,2100,300,*,LEFT,PTIE
S 2900,2100,2900,3400,300,*,DOWN,PTIE
S 3100,6800,3900,6800,300,*,RIGHT,NTIE
S 2800,300,2800,3800,200,*,UP,ALU1
S 2900,3300,3600,3300,300,*,LEFT,PTIE
S 2900,4400,2900,6300,200,*,UP,ALU1
S 2600,3700,2600,3900,100,*,UP,POLY
S 600,12700,4000,12700,400,*,RIGHT,NWELL
S 600,9700,4000,9700,6200,*,RIGHT,NWELL
S 2900,7100,2900,9400,100,*,DOWN,PTRANS
S 2300,7100,2300,12400,100,*,DOWN,PTRANS
S 1700,7100,1700,12400,100,*,DOWN,PTRANS
S 3800,6700,3800,9800,300,*,DOWN,NTIE
S 3100,9700,3900,9700,300,*,RIGHT,NTIE
S 2000,7300,2000,12200,200,*,UP,PDIF
S 1400,7300,1400,12200,300,*,UP,PDIF
S 2600,7300,2600,12200,300,*,UP,PDIF
S 3200,7300,3200,9200,300,*,UP,PDIF
S 3200,9600,3200,12800,300,*,DOWN,NTIE
S 700,12700,3200,12700,300,*,RIGHT,NTIE
S 800,6700,800,12800,300,*,DOWN,NTIE
S 3200,6300,3200,9100,200,*,UP,ALU1
S 2000,6300,2000,11900,200,*,UP,ALU1
S 500,2100,500,5800,300,*,UP,PTIE
S 1400,2400,1400,5200,100,*,UP,NTRANS
S 2600,3900,2600,5200,100,*,UP,NTRANS
S 2000,2400,2000,5200,100,*,UP,NTRANS
S 1100,2600,1100,5000,300,*,UP,NDIF
S 2900,4100,2900,5000,300,*,UP,NDIF
S 2300,2600,2300,5000,300,*,UP,NDIF
S 1700,2600,1700,5000,300,*,UP,NDIF
S 3500,3400,3500,5800,300,*,DOWN,PTIE
S 2300,2100,2300,5800,200,*,UP,ALU1
S 1700,1500,1700,6300,200,*,UP,ALU1
S 1800,5200,1800,7100,200,*,DOWN,POLY
S 1900,6300,2500,6300,300,*,LEFT,POLY
S 500,5700,1500,5700,300,*,RIGHT,PTIE
S 2100,5700,2700,5700,300,*,RIGHT,PTIE
S 800,6800,1500,6800,300,*,RIGHT,NTIE
S 2100,6800,2700,6800,300,*,RIGHT,NTIE
S 1700,1600,15700,1600,200,*,RIGHT,ALU2
S 3200,9600,3200,12800,200,*,UP,ALU1
S 14000,9600,14000,12800,200,*,DOWN,ALU1
S 14000,12600,16500,12600,500,*,LEFT,ALU1
S 700,12600,3200,12600,500,*,LEFT,ALU1
S 2500,6300,3200,6300,200,*,RIGHT,ALU1
S 14000,6300,14700,6300,200,*,RIGHT,ALU1
S 15200,6300,15500,6300,200,*,RIGHT,ALU1
S 1700,6300,2000,6300,200,*,RIGHT,ALU1
S 2600,6800,2600,12800,200,*,UP,ALU1
S 800,2100,800,5800,900,*,UP,ALU1
S 400,2100,1200,2100,200,*,LEFT,ALU1
S 14600,6800,14600,12800,200,*,DOWN,ALU1
S 15800,6800,15800,12800,200,*,DOWN,ALU1
S 16200,6800,16200,12800,700,*,UP,ALU1
S 15800,6800,16500,6800,200,*,LEFT,ALU1
S 1000,6800,1000,12800,700,*,DOWN,ALU1
S 1400,6800,1400,12800,200,*,UP,ALU1
S 700,6800,1400,6800,200,*,LEFT,ALU1
S 16400,2100,16400,5800,900,*,DOWN,ALU1
S 16000,2100,16800,2100,200,*,RIGHT,ALU1
S 1500,1600,2100,1600,200,*,LEFT,ALU1
S 15100,1600,15700,1600,200,*,LEFT,ALU1
V 5700,-400,CONT_VIA,*
V 5200,-400,CONT_VIA,*
V 4700,-400,CONT_VIA,*
V 4200,-400,CONT_VIA,*
V 3700,-400,CONT_VIA,*
V 9700,-400,CONT_VIA,*
V 10200,-400,CONT_VIA,*
V 7700,-400,CONT_VIA,*
V 8200,-400,CONT_VIA,*
V 8700,-400,CONT_VIA,*
V 9200,-400,CONT_VIA,*
V 6700,-400,CONT_VIA,*
V 7200,-400,CONT_VIA,*
V 6200,-400,CONT_VIA,*
V 10700,-400,CONT_VIA,*
V 11200,-400,CONT_VIA,*
V 11700,-400,CONT_VIA,*
V 12200,-400,CONT_VIA,*
V 13200,-400,CONT_VIA,*
V 12700,-400,CONT_VIA,*
B 8600,-500,10000,400,CONT_TURN2,*
V 1500,1600,CONT_VIA,*
V 15700,1600,CONT_VIA,*
V 15500,-700,CONT_VIA,*
V 1700,-700,CONT_VIA,*
V 16400,9900,CONT_VIA,*
V 16400,10300,CONT_BODY_N,*
V 14700,6300,CONT_POLY,*
V 16700,5700,CONT_BODY_P,*
V 16700,5300,CONT_VIA,*
V 16700,4900,CONT_BODY_P,*
V 16700,4500,CONT_BODY_P,*
V 16700,4100,CONT_BODY_P,*
V 16700,3700,CONT_VIA,*
V 16700,3300,CONT_BODY_P,*
V 16700,2900,CONT_BODY_P,*
V 16700,2500,CONT_BODY_P,*
V 16700,2100,CONT_BODY_P,*
V 14900,2100,CONT_BODY_P,*
V 16100,2100,CONT_BODY_P,*
V 14900,2500,CONT_VIA,*
V 16100,2500,CONT_VIA,*
V 16100,5300,CONT_VIA,*
V 14900,5300,CONT_VIA,*
V 14900,5700,CONT_BODY_P,*
V 16100,5700,CONT_BODY_P,*
V 16400,9100,CONT_BODY_N,*
V 16400,9500,CONT_BODY_N,*
V 14000,12300,CONT_BODY_N,*
V 14000,11900,CONT_BODY_N,*
V 14000,11500,CONT_BODY_N,*
V 14000,11100,CONT_BODY_N,*
V 14000,10700,CONT_BODY_N,*
V 16400,10700,CONT_BODY_N,*
V 16400,11100,CONT_BODY_N,*
V 16400,11500,CONT_BODY_N,*
V 16400,11900,CONT_BODY_N,*
V 16400,12300,CONT_BODY_N,*
V 16400,12700,CONT_BODY_N,*
V 16000,12700,CONT_BODY_N,*
V 15600,12700,CONT_BODY_N,*
V 15200,12700,CONT_BODY_N,*
V 14800,12700,CONT_BODY_N,*
V 14400,12700,CONT_BODY_N,*
V 14000,12700,CONT_BODY_N,*
V 14000,9700,CONT_BODY_N,*
V 16400,8300,CONT_BODY_N,*
V 16400,7900,CONT_BODY_N,*
V 16400,7500,CONT_BODY_N,*
V 16400,7100,CONT_VIA,*
V 16400,8700,CONT_VIA,*
V 14300,4400,CONT_DIF_N,*
V 14400,3800,CONT_POLY,*
V 16400,6800,CONT_BODY_N,*
V 14000,8300,CONT_DIF_P,*
V 14000,8700,CONT_DIF_P,*
V 14000,9100,CONT_DIF_P,*
V 14000,7500,CONT_DIF_P,*
V 14000,7900,CONT_DIF_P,*
V 14600,7100,CONT_VIA,*
V 14600,8700,CONT_VIA,*
V 14600,6800,CONT_BODY_N,*
V 14600,7900,CONT_DIF_P,*
V 14600,8300,CONT_DIF_P,*
V 14600,9100,CONT_DIF_P,*
V 14600,9500,CONT_DIF_P,*
V 14600,9900,CONT_DIF_P,*
V 14600,7500,CONT_DIF_P,*
V 15200,11900,CONT_DIF_P,*
V 15200,7500,CONT_DIF_P,*
V 15200,11500,CONT_DIF_P,*
V 15200,9500,CONT_DIF_P,*
V 15200,9100,CONT_DIF_P,*
V 15200,8700,CONT_DIF_P,*
V 15200,8300,CONT_DIF_P,*
V 15200,7900,CONT_DIF_P,*
V 15200,11100,CONT_DIF_P,*
V 15200,10700,CONT_DIF_P,*
V 15200,10300,CONT_DIF_P,*
V 15200,9900,CONT_DIF_P,*
V 15800,8700,CONT_VIA,*
V 15800,7100,CONT_VIA,*
V 15800,6800,CONT_BODY_N,*
V 15800,7500,CONT_DIF_P,*
V 15800,7900,CONT_DIF_P,*
V 15800,8300,CONT_DIF_P,*
V 15800,9100,CONT_DIF_P,*
V 15800,9500,CONT_DIF_P,*
V 15800,9900,CONT_DIF_P,*
V 16100,2900,CONT_DIF_N,*
V 16100,3300,CONT_DIF_N,*
V 16100,3700,CONT_DIF_N,*
V 16100,4100,CONT_DIF_N,*
V 16100,4500,CONT_DIF_N,*
V 16100,4900,CONT_DIF_N,*
V 14900,3200,CONT_DIF_N,*
V 14900,2800,CONT_DIF_N,*
V 15500,4800,CONT_DIF_N,*
V 15500,4400,CONT_DIF_N,*
V 15500,4000,CONT_DIF_N,*
V 15500,3600,CONT_DIF_N,*
V 15500,3200,CONT_DIF_N,*
V 15500,2800,CONT_DIF_N,*
V 14300,4900,CONT_DIF_N,*
V 14900,4800,CONT_DIF_N,*
V 14900,4400,CONT_DIF_N,*
V 14900,4000,CONT_DIF_N,*
V 14900,3600,CONT_DIF_N,*
V 14400,200,CONT_VIA,*
V 14400,1000,CONT_VIA,*
V 14000,10200,CONT_VIA,*
V 14600,10200,CONT_VIA,*
V 15800,10200,CONT_VIA,*
V 14600,11700,CONT_DIF_P,*
V 14600,10500,CONT_DIF_P,*
V 14600,10900,CONT_DIF_P,*
V 14600,11300,CONT_DIF_P,*
V 15800,10500,CONT_DIF_P,*
V 15800,10900,CONT_DIF_P,*
V 15800,11300,CONT_DIF_P,*
V 15800,11700,CONT_DIF_P,*
V 15800,12100,CONT_DIF_P,*
V 14600,12100,CONT_DIF_P,*
V 800,9900,CONT_VIA,*
V 800,10300,CONT_BODY_N,*
V 2500,6300,CONT_POLY,*
V 500,5700,CONT_BODY_P,*
V 500,5300,CONT_VIA,*
V 500,4900,CONT_BODY_P,*
V 500,4500,CONT_BODY_P,*
V 500,4100,CONT_BODY_P,*
V 500,3700,CONT_VIA,*
V 500,3300,CONT_BODY_P,*
V 500,2900,CONT_BODY_P,*
V 500,2500,CONT_BODY_P,*
V 500,2100,CONT_BODY_P,*
V 2300,2100,CONT_BODY_P,*
V 1100,2100,CONT_BODY_P,*
V 2300,2500,CONT_VIA,*
V 1100,2500,CONT_VIA,*
V 1100,5300,CONT_VIA,*
V 2300,5300,CONT_VIA,*
V 2300,5700,CONT_BODY_P,*
V 1100,5700,CONT_BODY_P,*
V 800,9100,CONT_BODY_N,*
V 800,9500,CONT_BODY_N,*
V 3200,12300,CONT_BODY_N,*
V 3200,11900,CONT_BODY_N,*
V 3200,11500,CONT_BODY_N,*
V 3200,11100,CONT_BODY_N,*
V 3200,10700,CONT_BODY_N,*
V 800,10700,CONT_BODY_N,*
V 800,11100,CONT_BODY_N,*
V 800,11500,CONT_BODY_N,*
V 800,11900,CONT_BODY_N,*
V 800,12300,CONT_BODY_N,*
V 800,12700,CONT_BODY_N,*
V 1200,12700,CONT_BODY_N,*
V 1600,12700,CONT_BODY_N,*
V 2000,12700,CONT_BODY_N,*
V 2400,12700,CONT_BODY_N,*
V 2800,12700,CONT_BODY_N,*
V 3200,12700,CONT_BODY_N,*
V 3200,9700,CONT_BODY_N,*
V 800,8300,CONT_BODY_N,*
V 800,7900,CONT_BODY_N,*
V 800,7500,CONT_BODY_N,*
V 800,7100,CONT_VIA,*
V 800,8700,CONT_VIA,*
V 2900,4400,CONT_DIF_N,*
V 2800,3800,CONT_POLY,*
V 800,6800,CONT_BODY_N,*
V 3200,8300,CONT_DIF_P,*
V 3200,8700,CONT_DIF_P,*
V 3200,9100,CONT_DIF_P,*
V 3200,7500,CONT_DIF_P,*
V 3200,7900,CONT_DIF_P,*
V 2600,7100,CONT_VIA,*
V 2600,8700,CONT_VIA,*
V 2600,6800,CONT_BODY_N,*
V 2600,7900,CONT_DIF_P,*
V 2600,8300,CONT_DIF_P,*
V 2600,9100,CONT_DIF_P,*
V 2600,9500,CONT_DIF_P,*
V 2600,9900,CONT_DIF_P,*
V 2600,7500,CONT_DIF_P,*
V 2000,11900,CONT_DIF_P,*
V 2000,7500,CONT_DIF_P,*
V 2000,11500,CONT_DIF_P,*
V 2000,9500,CONT_DIF_P,*
V 2000,9100,CONT_DIF_P,*
V 2000,8700,CONT_DIF_P,*
V 2000,8300,CONT_DIF_P,*
V 2000,7900,CONT_DIF_P,*
V 2000,11100,CONT_DIF_P,*
V 2000,10700,CONT_DIF_P,*
V 2000,10300,CONT_DIF_P,*
V 2000,9900,CONT_DIF_P,*
V 1400,8700,CONT_VIA,*
V 1400,7100,CONT_VIA,*
V 1400,6800,CONT_BODY_N,*
V 1400,7500,CONT_DIF_P,*
V 1400,7900,CONT_DIF_P,*
V 1400,8300,CONT_DIF_P,*
V 1400,9100,CONT_DIF_P,*
V 1400,9500,CONT_DIF_P,*
V 1400,9900,CONT_DIF_P,*
V 1100,2900,CONT_DIF_N,*
V 1100,3300,CONT_DIF_N,*
V 1100,3700,CONT_DIF_N,*
V 1100,4100,CONT_DIF_N,*
V 1100,4500,CONT_DIF_N,*
V 1100,4900,CONT_DIF_N,*
V 2300,3200,CONT_DIF_N,*
V 2300,2800,CONT_DIF_N,*
V 1700,4800,CONT_DIF_N,*
V 1700,4400,CONT_DIF_N,*
V 1700,4000,CONT_DIF_N,*
V 1700,3600,CONT_DIF_N,*
V 1700,3200,CONT_DIF_N,*
V 1700,2800,CONT_DIF_N,*
V 2900,4900,CONT_DIF_N,*
V 2300,4800,CONT_DIF_N,*
V 2300,4400,CONT_DIF_N,*
V 2300,4000,CONT_DIF_N,*
V 2300,3600,CONT_DIF_N,*
V 2800,200,CONT_VIA,*
V 2800,1000,CONT_VIA,*
V 3200,10200,CONT_VIA,*
V 2600,10200,CONT_VIA,*
V 1400,10200,CONT_VIA,*
V 2600,11700,CONT_DIF_P,*
V 2600,10500,CONT_DIF_P,*
V 2600,10900,CONT_DIF_P,*
V 2600,11300,CONT_DIF_P,*
V 1400,10500,CONT_DIF_P,*
V 1400,10900,CONT_DIF_P,*
V 1400,11300,CONT_DIF_P,*
V 1400,11700,CONT_DIF_P,*
V 1400,12100,CONT_DIF_P,*
V 2600,12100,CONT_DIF_P,*
B 8600,8400,10000,4000,CONT_VIA,*
B 3200,6300,200,200,CONT_TURN1,*
B 2000,6300,200,200,CONT_TURN1,*
B 1700,6300,200,200,CONT_TURN1,*
B 15500,6300,200,200,CONT_TURN1,*
B 15200,6300,200,200,CONT_TURN1,*
B 14000,6300,200,200,CONT_TURN1,*
V 2100,1600,CONT_VIA,*
V 15100,1600,CONT_VIA,*
EOF

21
alliance/src/cells/src/padlib/palvsse_sp.ap Normal file
View File

@ -0,0 +1,21 @@
V ALLIANCE : 6
H palvsse_sp,P,13/10/2000,100
A 0,-700,17200,35600
C 0,29600,12000,vsse,0,WEST,ALU2
C 17200,29600,12000,vsse,1,EAST,ALU2
C 0,600,1200,ck,0,WEST,ALU2
C 17200,600,1200,ck,1,EAST,ALU2
C 0,4000,4000,vssi,0,WEST,ALU2
C 17200,4000,4000,vssi,1,EAST,ALU2
C 0,8400,4000,vddi,0,WEST,ALU2
C 17200,8400,4000,vddi,1,EAST,ALU2
C 0,16800,12000,vdde,0,WEST,ALU2
C 17200,16800,12000,vdde,1,EAST,ALU2
S 8600,23600,8600,35600,10000,*,UP,ALU1
S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
S 0,600,17200,600,1200,ck,RIGHT,ALU2
S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
B 8600,29600,10000,12000,CONT_VIA,*
EOF

290
alliance/src/cells/src/padlib/palvsseck_sp.ap Normal file
View File

@ -0,0 +1,290 @@
V ALLIANCE : 6
H palvsseck_sp,P,13/10/2000,100
A 0,-700,17200,35600
C 9100,-700,200,cko,4,SOUTH,ALU1
C 9100,-700,200,cko,5,SOUTH,ALU2
C 7900,-700,200,cko,2,SOUTH,ALU1
C 7900,-700,200,cko,3,SOUTH,ALU2
C 6700,-700,200,cko,0,SOUTH,ALU1
C 6700,-700,200,cko,1,SOUTH,ALU2
C 17200,16800,12000,vdde,1,EAST,ALU2
C 0,16800,12000,vdde,0,WEST,ALU2
C 17200,8400,4000,vddi,1,EAST,ALU2
C 0,8400,4000,vddi,0,WEST,ALU2
C 17200,4000,4000,vssi,1,EAST,ALU2
C 0,4000,4000,vssi,0,WEST,ALU2
C 17200,600,1200,ck,1,EAST,ALU2
C 0,600,1200,ck,0,WEST,ALU2
C 17200,29600,12000,vsse,1,EAST,ALU2
C 0,29600,12000,vsse,0,WEST,ALU2
S 8600,23700,8600,35600,10000,*,UP,ALU1
S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
S 6700,1600,9100,1600,200,*,RIGHT,ALU1
S 9100,-700,9100,9600,200,*,UP,ALU1
S 7900,-700,7900,4400,200,*,UP,ALU1
S 6700,-700,6700,4400,200,*,UP,ALU1
S 0,600,17200,600,1200,ck,RIGHT,ALU2
S 5500,6100,5500,10400,200,*,UP,ALU1
S 7600,4700,7600,6400,500,*,UP,POLY
S 6400,4700,8800,4700,100,*,RIGHT,POLY
S 5200,4700,5200,6400,100,*,UP,POLY
S 6400,6400,8800,6400,100,*,RIGHT,POLY
S 5400,5000,7200,5000,300,*,RIGHT,PTIE
S 8000,5000,9800,5000,300,*,RIGHT,PTIE
S 8000,6100,9800,6100,300,*,RIGHT,NTIE
S 5400,6100,7200,6100,300,*,RIGHT,NTIE
S 5200,6400,5200,10700,100,*,UP,PTRANS
S 7000,2400,7000,4700,100,*,UP,NTRANS
S 6400,2400,6400,4700,100,*,UP,NTRANS
S 5200,2400,5200,4700,100,*,UP,NTRANS
S 8800,2400,8800,4700,100,*,UP,NTRANS
S 8200,2400,8200,4700,100,*,UP,NTRANS
S 7600,2400,7600,4700,100,*,UP,NTRANS
S 4900,2000,4900,5100,200,*,UP,ALU1
S 6700,2600,6700,4500,200,*,UP,NDIF
S 5500,6600,5500,10500,300,*,UP,PDIF
S 9100,2600,9100,4500,300,*,UP,NDIF
S 5500,2600,5500,4500,300,*,UP,NDIF
S 7900,2600,7900,4400,300,*,UP,NDIF
S 6100,2600,6100,4400,300,*,UP,NDIF
S 4900,2600,4900,4400,300,*,UP,NDIF
S 7300,2600,7300,4400,200,*,UP,NDIF
S 8500,2600,8500,4500,200,*,UP,NDIF
S 4300,2000,4300,5100,300,*,UP,PTIE
S 9700,2000,9700,5100,300,*,UP,PTIE
S 4200,2100,9800,2100,300,*,RIGHT,PTIE
S 4200,5000,5000,5000,300,*,RIGHT,PTIE
S 9700,2000,9700,5100,300,*,UP,ALU1
S 9700,2000,9700,5100,300,*,UP,PTIE
S 6100,2000,6100,4500,200,*,UP,ALU1
S 4900,6800,4900,10400,200,*,UP,ALU1
S 4900,6600,4900,10400,300,*,UP,PDIF
S 4300,6000,4300,11000,300,*,UP,NTIE
S 4200,6100,5000,6100,300,*,RIGHT,NTIE
S 8800,6400,8800,10100,100,*,UP,PTRANS
S 8200,6400,8200,10100,100,*,UP,PTRANS
S 7600,6400,7600,10100,100,*,UP,PTRANS
S 7000,6400,7000,10100,100,*,UP,PTRANS
S 6400,6400,6400,10100,100,*,UP,PTRANS
S 6700,6600,6700,9900,200,*,UP,PDIF
S 6100,6600,6100,9900,300,*,UP,PDIF
S 7300,6600,7300,9900,200,*,UP,PDIF
S 7900,6600,7900,9900,200,*,UP,PDIF
S 8500,6600,8500,9900,200,*,UP,PDIF
S 9100,6600,9100,9900,300,*,UP,PDIF
S 6700,6700,6700,9600,200,*,UP,ALU1
S 7900,6700,7900,9600,200,*,UP,ALU1
S 9700,6100,9700,10500,300,*,UP,NTIE
S 6100,10300,6100,11100,300,*,UP,NTIE
S 6000,10400,9800,10400,300,*,RIGHT,NTIE
S 8500,7100,8500,10400,200,*,UP,ALU1
S 7300,7100,7300,10400,200,*,UP,ALU1
S 6100,6800,6100,10400,200,*,UP,ALU1
S 5800,5600,7600,5600,200,*,RIGHT,ALU1
S 4100,8500,9900,8500,5200,*,RIGHT,NWELL
S 5500,2800,5500,5100,200,*,UP,ALU1
S 5700,4900,5700,6200,200,*,UP,ALU1
S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
S 4200,6100,5000,6100,200,*,RIGHT,ALU1
S 9700,6000,9700,10400,200,*,UP,ALU1
S 6200,4400,6200,5000,200,*,UP,ALU1
S 3800,5600,5200,5600,200,*,RIGHT,ALU1
S 3800,100,3800,5600,200,*,UP,ALU1
S 6200,5000,8500,5000,200,*,RIGHT,ALU1
S 4300,6100,4300,10400,300,*,UP,ALU1
S 6200,6100,6200,6900,200,*,UP,ALU1
S 6200,6100,7200,6100,200,*,RIGHT,ALU1
S 6700,6600,9100,6600,200,*,RIGHT,ALU1
S 6100,10400,9700,10400,200,*,RIGHT,ALU1
S 4300,2000,4300,5100,200,*,UP,ALU1
S 4300,2100,6100,2100,300,*,RIGHT,ALU1
S 7300,2200,7300,4500,200,*,UP,ALU1
S 8500,2100,8500,4900,200,*,UP,ALU1
B 8600,29600,10000,12000,CONT_VIA,*
V 9100,-700,CONT_VIA,*
V 7900,-700,CONT_VIA,*
V 6700,-700,CONT_VIA,*
V 3800,1000,CONT_VIA,*
V 3800,200,CONT_VIA,*
V 5500,9600,CONT_DIF_P,*
V 5500,9200,CONT_DIF_P,*
V 5500,8800,CONT_DIF_P,*
V 5500,8400,CONT_DIF_P,*
V 5500,8000,CONT_DIF_P,*
V 5500,7600,CONT_DIF_P,*
V 5500,7200,CONT_DIF_P,*
V 5500,6800,CONT_DIF_P,*
V 5500,10400,CONT_DIF_P,*
V 5500,10000,CONT_DIF_P,*
V 6700,9600,CONT_DIF_P,*
V 6700,9200,CONT_DIF_P,*
V 7900,7600,CONT_DIF_P,*
V 7900,8000,CONT_DIF_P,*
V 6700,8800,CONT_DIF_P,*
V 6700,8400,CONT_DIF_P,*
V 6700,8000,CONT_DIF_P,*
V 6700,7600,CONT_DIF_P,*
V 6700,7200,CONT_DIF_P,*
V 6700,6800,CONT_DIF_P,*
V 7900,9200,CONT_DIF_P,*
V 7900,9600,CONT_DIF_P,*
V 7900,6800,CONT_DIF_P,*
V 7900,7200,CONT_DIF_P,*
V 9100,8800,CONT_DIF_P,*
V 9100,8400,CONT_DIF_P,*
V 7900,8400,CONT_DIF_P,*
V 7900,8800,CONT_DIF_P,*
V 9100,8000,CONT_DIF_P,*
V 9100,7600,CONT_DIF_P,*
V 9100,7200,CONT_DIF_P,*
V 9100,6800,CONT_DIF_P,*
V 9100,9600,CONT_DIF_P,*
V 9100,9200,CONT_DIF_P,*
V 5500,3600,CONT_DIF_N,*
V 5500,3200,CONT_DIF_N,*
V 5500,2800,CONT_DIF_N,*
V 5500,4400,CONT_DIF_N,*
V 5500,4000,CONT_DIF_N,*
V 7900,2800,CONT_DIF_N,*
V 9100,3200,CONT_DIF_N,*
V 6700,3600,CONT_DIF_N,*
V 6700,3200,CONT_DIF_N,*
V 6700,2800,CONT_DIF_N,*
V 6700,4400,CONT_DIF_N,*
V 6700,4000,CONT_DIF_N,*
V 7900,4000,CONT_DIF_N,*
V 7900,4400,CONT_DIF_N,*
V 7900,3200,CONT_DIF_N,*
V 7900,3600,CONT_DIF_N,*
V 9100,2800,CONT_DIF_N,*
V 9100,4400,CONT_DIF_N,*
V 9100,4000,CONT_DIF_N,*
V 9100,3600,CONT_DIF_N,*
V 7300,4400,CONT_DIF_N,*
V 6100,4400,CONT_DIF_N,*
V 8500,4400,CONT_DIF_N,*
V 6100,4000,CONT_VIA,*
V 7300,4000,CONT_VIA,*
V 8500,4000,CONT_VIA,*
V 4900,4000,CONT_VIA,*
V 4900,4400,CONT_DIF_N,*
V 4900,3600,CONT_DIF_N,*
V 6100,3600,CONT_DIF_N,*
V 7300,3600,CONT_DIF_N,*
V 8500,3600,CONT_DIF_N,*
V 8500,3200,CONT_DIF_N,*
V 7300,3200,CONT_DIF_N,*
V 6100,3200,CONT_DIF_N,*
V 4900,3200,CONT_DIF_N,*
V 4900,2800,CONT_DIF_N,*
V 6100,2800,CONT_DIF_N,*
V 7300,2800,CONT_DIF_N,*
V 8500,2800,CONT_DIF_N,*
V 4900,2400,CONT_VIA,*
V 6100,2400,CONT_VIA,*
V 7300,2400,CONT_VIA,*
V 8500,2400,CONT_VIA,*
V 8500,2100,CONT_BODY_P,*
V 7300,2100,CONT_BODY_P,*
V 6100,2100,CONT_BODY_P,*
V 4900,2100,CONT_BODY_P,*
V 8500,5000,CONT_BODY_P,*
V 4900,5000,CONT_BODY_P,*
V 5700,2100,CONT_BODY_P,*
V 5300,2100,CONT_BODY_P,*
V 4300,2100,CONT_BODY_P,*
V 4300,2500,CONT_BODY_P,*
V 4300,2900,CONT_VIA,*
V 4300,3300,CONT_BODY_P,*
V 4300,3700,CONT_BODY_P,*
V 4300,4100,CONT_BODY_P,*
V 4300,4500,CONT_VIA,*
V 4300,5000,CONT_BODY_P,*
V 9700,2900,CONT_VIA,*
V 9700,4500,CONT_VIA,*
V 9700,2100,CONT_BODY_P,*
V 9700,5000,CONT_BODY_P,*
V 9700,4100,CONT_BODY_P,*
V 9700,3700,CONT_BODY_P,*
V 9700,3300,CONT_BODY_P,*
V 9700,2500,CONT_BODY_P,*
V 7100,5000,CONT_BODY_P,*
V 8100,5000,CONT_BODY_P,*
V 6600,5000,CONT_VIA,*
V 6200,5000,CONT_BODY_P,*
V 6100,9600,CONT_DIF_P,*
V 6100,9200,CONT_DIF_P,*
V 6100,8800,CONT_DIF_P,*
V 6100,8000,CONT_DIF_P,*
V 6100,7600,CONT_DIF_P,*
V 6100,6800,CONT_DIF_P,*
V 6100,10000,CONT_VIA,*
V 6100,8400,CONT_VIA,*
V 6100,7200,CONT_VIA,*
V 4900,8400,CONT_VIA,*
V 4900,10000,CONT_VIA,*
V 4900,7200,CONT_VIA,*
V 4900,7600,CONT_DIF_P,*
V 4900,8000,CONT_DIF_P,*
V 4900,8800,CONT_DIF_P,*
V 4900,9200,CONT_DIF_P,*
V 4900,9600,CONT_DIF_P,*
V 4900,10400,CONT_DIF_P,*
V 4900,6800,CONT_DIF_P,*
V 7300,10000,CONT_VIA,*
V 7300,8400,CONT_VIA,*
V 7300,9600,CONT_DIF_P,*
V 7300,9200,CONT_DIF_P,*
V 7300,8800,CONT_DIF_P,*
V 7300,8000,CONT_DIF_P,*
V 7300,7600,CONT_DIF_P,*
V 7300,7100,CONT_DIF_P,*
V 8500,8400,CONT_VIA,*
V 8500,10000,CONT_VIA,*
V 8500,7600,CONT_DIF_P,*
V 8500,8000,CONT_DIF_P,*
V 8500,8800,CONT_DIF_P,*
V 8500,9200,CONT_DIF_P,*
V 8500,9600,CONT_DIF_P,*
V 8500,7100,CONT_DIF_P,*
V 6100,10400,CONT_BODY_N,*
V 6500,10400,CONT_BODY_N,*
V 6900,10400,CONT_BODY_N,*
V 7300,10400,CONT_BODY_N,*
V 7700,10400,CONT_BODY_N,*
V 8100,10400,CONT_BODY_N,*
V 8500,10400,CONT_BODY_N,*
V 8900,10400,CONT_BODY_N,*
V 9300,10400,CONT_BODY_N,*
V 9700,10400,CONT_BODY_N,*
V 9700,10000,CONT_BODY_N,*
V 9700,9200,CONT_BODY_N,*
V 9700,8800,CONT_BODY_N,*
V 9700,8400,CONT_BODY_N,*
V 9700,8000,CONT_BODY_N,*
V 9700,7600,CONT_BODY_N,*
V 9700,6100,CONT_BODY_N,*
V 9700,6500,CONT_BODY_N,*
V 9700,7000,CONT_VIA,*
V 9700,9600,CONT_VIA,*
V 7600,5600,CONT_POLY,*
V 7100,6100,CONT_BODY_N,*
V 6200,6100,CONT_BODY_N,*
V 6700,6100,CONT_BODY_N,*
V 4900,6100,CONT_BODY_N,*
V 4300,6100,CONT_BODY_N,*
V 4300,6500,CONT_BODY_N,*
V 4300,6900,CONT_VIA,*
V 4300,7300,CONT_BODY_N,*
V 5200,5600,CONT_POLY,*
V 4300,7700,CONT_BODY_N,*
V 4300,8100,CONT_BODY_N,*
V 4300,8500,CONT_VIA,*
V 4300,8900,CONT_BODY_N,*
V 4300,9300,CONT_BODY_N,*
V 4300,9700,CONT_VIA,*
V 4300,10300,CONT_BODY_N,*
B 3800,5600,200,200,CONT_TURN1,*
EOF

44
alliance/src/cells/src/padlib/palvssi_sp.ap Normal file
View File

@ -0,0 +1,44 @@
V ALLIANCE : 6
H palvssi_sp,P,13/10/2000,100
A 0,0,17200,36300
C 8600,0,10000,vssi,2,SOUTH,ALU1
C 17200,17500,12000,vdde,3,EAST,ALU2
C 0,17500,12000,vdde,2,WEST,ALU2
C 17200,9100,4000,vddi,3,EAST,ALU2
C 0,9100,4000,vddi,2,WEST,ALU2
C 17200,4700,4000,vssi,9,EAST,ALU2
C 0,4700,4000,vssi,8,WEST,ALU2
C 17200,1300,1200,ck,3,EAST,ALU2
C 0,1300,1200,ck,2,WEST,ALU2
C 17200,30300,12000,vsse,3,EAST,ALU2
C 0,30300,12000,vsse,2,WEST,ALU2
C 8600,0,10000,vssi,3,SOUTH,ALU2
S 8600,0,8600,36300,10000,*,UP,ALU1
S 0,4700,17200,4700,4000,vssi,RIGHT,ALU2
S 0,9100,17200,9100,4000,vddi,RIGHT,ALU2
S 0,17500,17200,17500,12000,vdde,RIGHT,ALU2
S 0,1300,17200,1300,1200,ck,RIGHT,ALU2
S 0,30300,17200,30300,12000,vsse,RIGHT,ALU2
B 8600,200,10000,400,CONT_TURN2,*
V 10700,300,CONT_VIA,*
V 11200,300,CONT_VIA,*
V 11700,300,CONT_VIA,*
V 12200,300,CONT_VIA,*
V 13200,300,CONT_VIA,*
V 12700,300,CONT_VIA,*
V 9700,300,CONT_VIA,*
V 10200,300,CONT_VIA,*
V 7700,300,CONT_VIA,*
V 8200,300,CONT_VIA,*
V 8700,300,CONT_VIA,*
V 9200,300,CONT_VIA,*
V 6700,300,CONT_VIA,*
V 7200,300,CONT_VIA,*
V 6200,300,CONT_VIA,*
V 5700,300,CONT_VIA,*
V 5200,300,CONT_VIA,*
V 4700,300,CONT_VIA,*
V 4200,300,CONT_VIA,*
V 3700,300,CONT_VIA,*
B 8600,4700,10000,4000,CONT_VIA,*
EOF

411
alliance/src/cells/src/padlib/palvssick_sp.ap Normal file
View File

@ -0,0 +1,411 @@
V ALLIANCE : 6
H palvssick_sp,P,13/10/2000,100
A 0,0,17200,36300
C 8600,0,10000,vssi,2,SOUTH,ALU1
C 8600,0,10000,vssi,4,SOUTH,ALU2
C 17200,1300,1200,ck,3,EAST,ALU2
C 17200,4700,4000,vssi,8,EAST,ALU2
C 17200,9100,4000,vddi,3,EAST,ALU2
C 0,1300,1200,ck,2,WEST,ALU2
C 0,4700,4000,vssi,7,WEST,ALU2
C 0,9100,4000,vddi,2,WEST,ALU2
C 0,17500,12000,vdde,2,WEST,ALU2
C 17200,17500,12000,vdde,3,EAST,ALU2
C 15500,0,200,cko,7,SOUTH,ALU2
C 15500,0,200,cko,6,SOUTH,ALU1
C 1700,0,200,cko,5,SOUTH,ALU2
C 1700,0,200,cko,4,SOUTH,ALU1
C 17200,30300,12000,vsse,3,EAST,ALU2
C 0,30300,12000,vsse,2,WEST,ALU2
S 800,7500,1500,7500,300,*,RIGHT,NTIE
S 2100,7500,2700,7500,300,*,RIGHT,NTIE
S 3100,10400,3900,10400,300,*,RIGHT,NTIE
S 2000,8000,2000,12900,200,*,UP,PDIF
S 1400,8000,1400,12900,300,*,UP,PDIF
S 2600,8000,2600,12900,300,*,UP,PDIF
S 3200,8000,3200,9900,300,*,UP,PDIF
S 3200,10300,3200,13500,300,*,DOWN,NTIE
S 700,13400,3200,13400,300,*,RIGHT,NTIE
S 800,7400,800,13500,300,*,DOWN,NTIE
S 14500,7500,15100,7500,300,*,RIGHT,NTIE
S 3100,7500,3900,7500,300,*,RIGHT,NTIE
S 600,13400,4000,13400,400,*,RIGHT,NWELL
S 600,10400,4000,10400,6200,*,RIGHT,NWELL
S 2900,7800,2900,10100,100,*,DOWN,PTRANS
S 2300,7800,2300,13100,100,*,DOWN,PTRANS
S 1700,7800,1700,13100,100,*,DOWN,PTRANS
S 3800,7400,3800,10500,300,*,DOWN,NTIE
S 15200,8000,15200,12900,200,*,DOWN,PDIF
S 15800,8000,15800,12900,300,*,DOWN,PDIF
S 14600,8000,14600,12900,300,*,DOWN,PDIF
S 14000,8000,14000,9900,300,*,DOWN,PDIF
S 14000,10300,14000,13500,300,*,UP,NTIE
S 14000,13400,16500,13400,300,*,RIGHT,NTIE
S 16400,7400,16400,13500,300,*,UP,NTIE
S 15700,7500,16400,7500,300,*,RIGHT,NTIE
S 13300,7500,14100,7500,300,*,RIGHT,NTIE
S 13200,13400,16600,13400,400,*,RIGHT,NWELL
S 13200,10400,16600,10400,6200,*,RIGHT,NWELL
S 14300,7800,14300,10100,100,*,UP,PTRANS
S 14900,7800,14900,13100,100,*,UP,PTRANS
S 15500,7800,15500,13100,100,*,UP,PTRANS
S 13400,7400,13400,10500,300,*,UP,NTIE
S 13300,10400,14100,10400,300,*,RIGHT,NTIE
S 15800,3100,15800,5900,100,*,DOWN,NTRANS
S 14600,4600,14600,5900,100,*,DOWN,NTRANS
S 15200,3100,15200,5900,100,*,DOWN,NTRANS
S 1400,3100,1400,5900,100,*,UP,NTRANS
S 2600,4600,2600,5900,100,*,UP,NTRANS
S 2000,3100,2000,5900,100,*,UP,NTRANS
S 1100,3300,1100,5700,300,*,UP,NDIF
S 2900,4800,2900,5700,300,*,UP,NDIF
S 2300,3300,2300,5700,300,*,UP,NDIF
S 1700,3300,1700,5700,300,*,UP,NDIF
S 14900,3300,14900,5700,300,*,DOWN,NDIF
S 15500,3300,15500,5700,300,*,DOWN,NDIF
S 16100,3300,16100,5700,300,*,DOWN,NDIF
S 14300,4800,14300,5700,300,*,DOWN,NDIF
S 400,2800,3000,2800,300,*,LEFT,PTIE
S 500,2800,500,6500,300,*,UP,PTIE
S 500,6400,1500,6400,300,*,RIGHT,PTIE
S 3100,6400,3600,6400,300,*,RIGHT,PTIE
S 2900,2800,2900,4100,300,*,DOWN,PTIE
S 2900,4000,3600,4000,300,*,LEFT,PTIE
S 3500,4100,3500,6500,300,*,DOWN,PTIE
S 2100,6400,2700,6400,300,*,RIGHT,PTIE
S 13600,6400,14100,6400,300,*,RIGHT,PTIE
S 14200,2800,16800,2800,300,*,LEFT,PTIE
S 14300,2800,14300,4100,300,*,UP,PTIE
S 13600,4000,14300,4000,300,*,LEFT,PTIE
S 16700,2800,16700,6500,300,*,DOWN,PTIE
S 13700,4100,13700,6500,300,*,UP,PTIE
S 15700,6400,16700,6400,300,*,RIGHT,PTIE
S 14500,6400,15100,6400,300,*,RIGHT,PTIE
S 1800,5900,1800,7800,200,*,DOWN,POLY
S 1900,7000,2500,7000,300,*,LEFT,POLY
S 2600,5900,2900,5900,100,*,RIGHT,POLY
S 2600,4400,2600,4600,100,*,UP,POLY
S 15400,5900,15400,7800,200,*,UP,POLY
S 14700,7000,15300,7000,300,*,LEFT,POLY
S 1400,5900,2000,5900,100,*,RIGHT,POLY
S 1700,7800,2300,7800,100,*,RIGHT,POLY
S 2900,5900,2900,7800,100,*,UP,POLY
S 15200,5900,15800,5900,100,*,RIGHT,POLY
S 14900,7800,15500,7800,100,*,RIGHT,POLY
S 14300,5900,14300,7800,100,*,DOWN,POLY
S 14300,5900,14600,5900,100,*,RIGHT,POLY
S 14600,4400,14600,4600,100,*,DOWN,POLY
S 15500,0,15500,2200,200,*,UP,ALU1
S 1700,0,1700,2300,200,*,DOWN,ALU1
S 8600,0,8600,36300,10000,*,UP,ALU1
S 800,2800,800,6500,900,*,UP,ALU1
S 400,2800,1200,2800,200,*,LEFT,ALU1
S 700,7500,1400,7500,200,*,LEFT,ALU1
S 16400,2800,16400,6500,900,*,DOWN,ALU1
S 16000,2800,16800,2800,200,*,RIGHT,ALU1
S 1500,2300,2100,2300,200,*,LEFT,ALU1
S 15100,2300,15700,2300,200,*,LEFT,ALU1
S 14600,7500,14600,13500,200,*,DOWN,ALU1
S 15800,7500,15800,13500,200,*,DOWN,ALU1
S 16200,7500,16200,13500,700,*,UP,ALU1
S 15800,7500,16500,7500,200,*,LEFT,ALU1
S 1000,7500,1000,13500,700,*,DOWN,ALU1
S 1400,7500,1400,13500,200,*,UP,ALU1
S 14000,10300,14000,13500,200,*,DOWN,ALU1
S 14000,13300,16500,13300,500,*,LEFT,ALU1
S 700,13300,3200,13300,500,*,LEFT,ALU1
S 2500,7000,3200,7000,200,*,RIGHT,ALU1
S 14000,7000,14700,7000,200,*,RIGHT,ALU1
S 15200,7000,15500,7000,200,*,RIGHT,ALU1
S 1700,7000,2000,7000,200,*,RIGHT,ALU1
S 2600,7500,2600,13500,200,*,UP,ALU1
S 15500,2200,15500,7000,200,*,DOWN,ALU1
S 2800,1000,2800,4500,200,*,UP,ALU1
S 2900,5100,2900,7000,200,*,UP,ALU1
S 3200,7000,3200,9800,200,*,UP,ALU1
S 2000,7000,2000,12600,200,*,UP,ALU1
S 2300,2800,2300,6500,200,*,UP,ALU1
S 1700,2200,1700,7000,200,*,UP,ALU1
S 3200,10300,3200,13500,200,*,UP,ALU1
S 14400,1000,14400,4500,200,*,DOWN,ALU1
S 14300,5100,14300,7000,200,*,DOWN,ALU1
S 14000,7000,14000,9800,200,*,DOWN,ALU1
S 15200,7000,15200,12600,200,*,DOWN,ALU1
S 14900,2800,14900,6500,200,*,DOWN,ALU1
S 0,9100,17200,9100,4000,vddi,RIGHT,ALU2
S 0,4700,17200,4700,4000,vssi,RIGHT,ALU2
S 0,17500,17200,17500,12000,vdde,RIGHT,ALU2
S 0,1300,17200,1300,1200,ck,RIGHT,ALU2
S 1700,2300,15700,2300,200,*,RIGHT,ALU2
S 0,30300,17200,30300,12000,vsse,RIGHT,ALU2
V 4000,300,CONT_VIA,*
V 4500,300,CONT_VIA,*
V 8500,300,CONT_VIA,*
V 8000,300,CONT_VIA,*
V 7500,300,CONT_VIA,*
V 7000,300,CONT_VIA,*
V 6500,300,CONT_VIA,*
V 6000,300,CONT_VIA,*
V 5500,300,CONT_VIA,*
V 5000,300,CONT_VIA,*
V 9000,300,CONT_VIA,*
V 9500,300,CONT_VIA,*
V 10000,300,CONT_VIA,*
V 10500,300,CONT_VIA,*
V 11000,300,CONT_VIA,*
V 11500,300,CONT_VIA,*
V 12000,300,CONT_VIA,*
V 12500,300,CONT_VIA,*
V 13000,300,CONT_VIA,*
V 13500,300,CONT_VIA,*
B 8600,200,10000,400,CONT_TURN2,*
V 1400,11200,CONT_DIF_P,*
V 1400,11600,CONT_DIF_P,*
V 1400,12000,CONT_DIF_P,*
V 1400,12400,CONT_DIF_P,*
V 1400,12800,CONT_DIF_P,*
V 2600,12800,CONT_DIF_P,*
V 1400,9000,CONT_DIF_P,*
V 1400,9800,CONT_DIF_P,*
V 1400,10200,CONT_DIF_P,*
V 1400,10600,CONT_DIF_P,*
V 2600,12400,CONT_DIF_P,*
V 2600,11200,CONT_DIF_P,*
V 2600,11600,CONT_DIF_P,*
V 2600,12000,CONT_DIF_P,*
V 2000,8600,CONT_DIF_P,*
V 2000,11800,CONT_DIF_P,*
V 2000,11400,CONT_DIF_P,*
V 2000,11000,CONT_DIF_P,*
V 2000,10600,CONT_DIF_P,*
V 1400,7500,CONT_BODY_N,*
V 1400,8200,CONT_DIF_P,*
V 1400,8600,CONT_DIF_P,*
V 2600,8200,CONT_DIF_P,*
V 2000,12600,CONT_DIF_P,*
V 2000,8200,CONT_DIF_P,*
V 2000,12200,CONT_DIF_P,*
V 2000,10200,CONT_DIF_P,*
V 2000,9800,CONT_DIF_P,*
V 2000,9400,CONT_DIF_P,*
V 2000,9000,CONT_DIF_P,*
V 3200,8200,CONT_DIF_P,*
V 3200,8600,CONT_DIF_P,*
V 2600,7500,CONT_BODY_N,*
V 2600,8600,CONT_DIF_P,*
V 2600,9000,CONT_DIF_P,*
V 2600,9800,CONT_DIF_P,*
V 2600,10200,CONT_DIF_P,*
V 2600,10600,CONT_DIF_P,*
V 3200,10400,CONT_BODY_N,*
V 800,9000,CONT_BODY_N,*
V 800,8600,CONT_BODY_N,*
V 800,8200,CONT_BODY_N,*
V 800,7500,CONT_BODY_N,*
V 3200,9000,CONT_DIF_P,*
V 3200,9400,CONT_DIF_P,*
V 3200,9800,CONT_DIF_P,*
V 800,13000,CONT_BODY_N,*
V 800,13400,CONT_BODY_N,*
V 1200,13400,CONT_BODY_N,*
V 1600,13400,CONT_BODY_N,*
V 2000,13400,CONT_BODY_N,*
V 2400,13400,CONT_BODY_N,*
V 2800,13400,CONT_BODY_N,*
V 3200,13400,CONT_BODY_N,*
V 3200,12600,CONT_BODY_N,*
V 3200,12200,CONT_BODY_N,*
V 3200,11800,CONT_BODY_N,*
V 3200,11400,CONT_BODY_N,*
V 800,11400,CONT_BODY_N,*
V 800,11800,CONT_BODY_N,*
V 800,12200,CONT_BODY_N,*
V 800,12600,CONT_BODY_N,*
V 15800,12000,CONT_DIF_P,*
V 15800,12400,CONT_DIF_P,*
V 15800,12800,CONT_DIF_P,*
V 14600,12800,CONT_DIF_P,*
V 800,11000,CONT_BODY_N,*
V 800,9800,CONT_BODY_N,*
V 800,10200,CONT_BODY_N,*
V 3200,13000,CONT_BODY_N,*
V 15800,10200,CONT_DIF_P,*
V 15800,10600,CONT_DIF_P,*
V 14600,12400,CONT_DIF_P,*
V 14600,11200,CONT_DIF_P,*
V 14600,11600,CONT_DIF_P,*
V 14600,12000,CONT_DIF_P,*
V 15800,11200,CONT_DIF_P,*
V 15800,11600,CONT_DIF_P,*
V 15200,11400,CONT_DIF_P,*
V 15200,11000,CONT_DIF_P,*
V 15200,10600,CONT_DIF_P,*
V 15800,7500,CONT_BODY_N,*
V 15800,8200,CONT_DIF_P,*
V 15800,8600,CONT_DIF_P,*
V 15800,9000,CONT_DIF_P,*
V 15800,9800,CONT_DIF_P,*
V 15200,8200,CONT_DIF_P,*
V 15200,12200,CONT_DIF_P,*
V 15200,10200,CONT_DIF_P,*
V 15200,9800,CONT_DIF_P,*
V 15200,9400,CONT_DIF_P,*
V 15200,9000,CONT_DIF_P,*
V 15200,8600,CONT_DIF_P,*
V 15200,11800,CONT_DIF_P,*
V 14600,7500,CONT_BODY_N,*
V 14600,8600,CONT_DIF_P,*
V 14600,9000,CONT_DIF_P,*
V 14600,9800,CONT_DIF_P,*
V 14600,10200,CONT_DIF_P,*
V 14600,10600,CONT_DIF_P,*
V 14600,8200,CONT_DIF_P,*
V 15200,12600,CONT_DIF_P,*
V 16400,8600,CONT_BODY_N,*
V 16400,8200,CONT_BODY_N,*
V 16400,7500,CONT_BODY_N,*
V 14000,9000,CONT_DIF_P,*
V 14000,9400,CONT_DIF_P,*
V 14000,9800,CONT_DIF_P,*
V 14000,8200,CONT_DIF_P,*
V 14000,8600,CONT_DIF_P,*
V 16000,13400,CONT_BODY_N,*
V 15600,13400,CONT_BODY_N,*
V 15200,13400,CONT_BODY_N,*
V 14800,13400,CONT_BODY_N,*
V 14400,13400,CONT_BODY_N,*
V 14000,13400,CONT_BODY_N,*
V 14000,10400,CONT_BODY_N,*
V 16400,9000,CONT_BODY_N,*
V 14000,11800,CONT_BODY_N,*
V 14000,11400,CONT_BODY_N,*
V 16400,11400,CONT_BODY_N,*
V 16400,11800,CONT_BODY_N,*
V 16400,12200,CONT_BODY_N,*
V 16400,12600,CONT_BODY_N,*
V 16400,13000,CONT_BODY_N,*
V 16400,13400,CONT_BODY_N,*
V 16400,11000,CONT_BODY_N,*
V 16400,9800,CONT_BODY_N,*
V 16400,10200,CONT_BODY_N,*
V 14000,13000,CONT_BODY_N,*
V 14000,12600,CONT_BODY_N,*
V 14000,12200,CONT_BODY_N,*
V 2300,5500,CONT_DIF_N,*
V 2300,5100,CONT_DIF_N,*
V 2300,4700,CONT_DIF_N,*
V 2300,4300,CONT_DIF_N,*
V 2300,3500,CONT_DIF_N,*
V 1700,5500,CONT_DIF_N,*
V 1700,5100,CONT_DIF_N,*
V 1700,4700,CONT_DIF_N,*
V 1700,4300,CONT_DIF_N,*
V 1700,3900,CONT_DIF_N,*
V 1700,3500,CONT_DIF_N,*
V 2900,5600,CONT_DIF_N,*
V 2900,5100,CONT_DIF_N,*
V 1100,3600,CONT_DIF_N,*
V 1100,4000,CONT_DIF_N,*
V 1100,4400,CONT_DIF_N,*
V 1100,4800,CONT_DIF_N,*
V 1100,5200,CONT_DIF_N,*
V 1100,5600,CONT_DIF_N,*
V 2300,3900,CONT_DIF_N,*
V 15500,4300,CONT_DIF_N,*
V 15500,3900,CONT_DIF_N,*
V 15500,3500,CONT_DIF_N,*
V 14300,5600,CONT_DIF_N,*
V 14900,5500,CONT_DIF_N,*
V 14900,5100,CONT_DIF_N,*
V 14900,4700,CONT_DIF_N,*
V 14900,4300,CONT_DIF_N,*
V 16100,4800,CONT_DIF_N,*
V 16100,5200,CONT_DIF_N,*
V 16100,5600,CONT_DIF_N,*
V 14900,3900,CONT_DIF_N,*
V 14900,3500,CONT_DIF_N,*
V 15500,5500,CONT_DIF_N,*
V 15500,5100,CONT_DIF_N,*
V 15500,4700,CONT_DIF_N,*
V 14300,5100,CONT_DIF_N,*
V 16100,3600,CONT_DIF_N,*
V 16100,4000,CONT_DIF_N,*
V 16100,4400,CONT_DIF_N,*
V 500,3600,CONT_BODY_P,*
V 500,3200,CONT_BODY_P,*
V 500,2800,CONT_BODY_P,*
V 500,6400,CONT_BODY_P,*
V 500,5600,CONT_BODY_P,*
V 500,5200,CONT_BODY_P,*
V 500,4800,CONT_BODY_P,*
V 500,4000,CONT_BODY_P,*
V 2300,2800,CONT_BODY_P,*
V 1100,2800,CONT_BODY_P,*
V 2300,6400,CONT_BODY_P,*
V 1100,6400,CONT_BODY_P,*
V 14900,2800,CONT_BODY_P,*
V 16100,2800,CONT_BODY_P,*
V 14900,6400,CONT_BODY_P,*
V 16100,6400,CONT_BODY_P,*
V 16700,6400,CONT_BODY_P,*
V 16700,5600,CONT_BODY_P,*
V 16700,5200,CONT_BODY_P,*
V 16700,4800,CONT_BODY_P,*
V 16700,4000,CONT_BODY_P,*
V 16700,3600,CONT_BODY_P,*
V 16700,3200,CONT_BODY_P,*
V 16700,2800,CONT_BODY_P,*
V 14700,7000,CONT_POLY,*
V 14400,4500,CONT_POLY,*
V 2500,7000,CONT_POLY,*
V 2800,4500,CONT_POLY,*
V 15500,0,CONT_VIA,*
V 1700,0,CONT_VIA,*
V 500,6000,CONT_VIA,*
V 500,4400,CONT_VIA,*
B 15200,7000,200,200,CONT_TURN1,*
B 14000,7000,200,200,CONT_TURN1,*
V 2100,2300,CONT_VIA,*
V 15100,2300,CONT_VIA,*
B 3200,7000,200,200,CONT_TURN1,*
B 2000,7000,200,200,CONT_TURN1,*
B 1700,7000,200,200,CONT_TURN1,*
B 15500,7000,200,200,CONT_TURN1,*
V 2600,10900,CONT_VIA,*
V 1400,10900,CONT_VIA,*
V 2800,900,CONT_VIA,*
V 2800,1700,CONT_VIA,*
V 3200,10900,CONT_VIA,*
V 1400,9400,CONT_VIA,*
V 1400,7800,CONT_VIA,*
V 2600,7800,CONT_VIA,*
V 2600,9400,CONT_VIA,*
V 800,7800,CONT_VIA,*
V 800,9400,CONT_VIA,*
V 2300,6000,CONT_VIA,*
V 2300,3200,CONT_VIA,*
V 1100,3200,CONT_VIA,*
V 1100,6000,CONT_VIA,*
V 800,10600,CONT_VIA,*
V 14400,1700,CONT_VIA,*
V 14000,10900,CONT_VIA,*
V 14600,10900,CONT_VIA,*
V 15800,10900,CONT_VIA,*
V 14400,900,CONT_VIA,*
V 15800,9400,CONT_VIA,*
V 15800,7800,CONT_VIA,*
V 14600,7800,CONT_VIA,*
V 14600,9400,CONT_VIA,*
V 16400,7800,CONT_VIA,*
V 16400,9400,CONT_VIA,*
V 16100,3200,CONT_VIA,*
V 16100,6000,CONT_VIA,*
V 14900,6000,CONT_VIA,*
V 16700,4400,CONT_VIA,*
V 14900,3200,CONT_VIA,*
V 16400,10600,CONT_VIA,*
V 16700,6000,CONT_VIA,*
B 8600,4700,10000,4000,CONT_VIA,*
V 1500,2300,CONT_VIA,*
V 15700,2300,CONT_VIA,*
EOF

56
alliance/src/cells/src/padlib/pck_sp.al Normal file
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@ -0,0 +1,56 @@
V ALLIANCE : 4
H pck_sp,L,23/ 2/95
C pad,UNKNOWN,EXTERNAL,2
C ck,UNKNOWN,EXTERNAL,1
C vdde,UNKNOWN,EXTERNAL,3
C vddi,UNKNOWN,EXTERNAL,4
C vsse,UNKNOWN,EXTERNAL,5
C vssi,UNKNOWN,EXTERNAL,6
T N,1,27,6,2,7,0,0,0,0,147,29
T N,1,27,7,2,6,0,0,0,0,141,29
T N,1,27,7,2,6,0,0,0,0,153,29
T N,1,27,7,2,6,0,0,0,0,129,29
T N,1,27,6,2,7,0,0,0,0,123,29
T N,1,27,6,2,7,0,0,0,0,135,29
T N,1,27,6,2,7,0,0,0,0,111,29
T N,1,27,7,2,6,0,0,0,0,117,29
T N,1,27,7,2,6,0,0,0,0,105,29
T N,1,27,6,2,7,0,0,0,0,99,29
T N,1,27,7,2,6,0,0,0,0,93,29
T N,1,27,6,2,7,0,0,0,0,87,29
T N,1,27,1,7,6,0,0,0,0,52,29
T N,1,27,6,7,1,0,0,0,0,46,29
T N,1,27,1,7,6,0,0,0,0,28,29
T N,1,27,1,7,6,0,0,0,0,40,29
T N,1,27,6,7,1,0,0,0,0,34,29
T N,1,27,6,7,1,0,0,0,0,70,29
T N,1,27,1,7,6,0,0,0,0,64,29
T N,1,27,6,7,1,0,0,0,0,58,29
T N,1,35,2,5,5,0,0,0,0,73,273
T N,1,35,5,5,2,0,0,0,0,79,273
T N,1,35,2,5,5,0,0,0,0,85,273
T N,1,35,5,5,2,0,0,0,0,91,273
T P,1,27,7,2,4,0,0,0,0,105,80
T P,1,27,4,2,7,0,0,0,0,99,80
T P,1,27,7,2,4,0,0,0,0,93,80
T P,1,27,4,2,7,0,0,0,0,87,80
T P,1,57,4,7,1,0,0,0,0,70,95
T P,1,57,4,7,1,0,0,0,0,46,95
T P,1,57,1,7,4,0,0,0,0,52,95
T P,1,57,4,7,1,0,0,0,0,58,95
T P,1,57,1,7,4,0,0,0,0,64,95
T P,1,57,1,7,4,0,0,0,0,28,95
T P,1,57,4,7,1,0,0,0,0,34,95
T P,1,57,1,7,4,0,0,0,0,40,95
T P,1,80,2,3,3,0,0,0,0,73,188.5
T P,1,80,3,3,2,0,0,0,0,79,188.5
T P,1,80,2,3,3,0,0,0,0,85,188.5
T P,1,80,3,3,2,0,0,0,0,91,188.5
S 7,INTERNAL,0,mbk_sig3
S 6,EXTERNAL,0,vssi
S 5,EXTERNAL,0,vsse
S 4,EXTERNAL,0,vddi
S 3,EXTERNAL,0,vdde
S 2,EXTERNAL,0,pad
S 1,EXTERNAL,0,ck
EOF

17
alliance/src/cells/src/padlib/pck_sp.ap Normal file
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@ -0,0 +1,17 @@
V ALLIANCE : 3
H pck_sp,P,30/ 0/95
A 3,1,175,501
C 3,48,40,vssi,0,WEST,ALU2
C 3,92,40,vddi,0,WEST,ALU2
C 3,14,12,ck,0,WEST,ALU2
C 175,14,12,ck,1,EAST,ALU2
C 175,48,40,vssi,1,EAST,ALU2
C 175,92,40,vddi,1,EAST,ALU2
C 175,176,120,vdde,1,EAST,ALU2
C 175,304,120,vsse,1,EAST,ALU2
C 3,304,120,vsse,0,WEST,ALU2
C 3,176,120,vdde,0,WEST,ALU2
C 91,501,1,pad,0,NORTH,ALU1
I 3,1,palck_sp,log,NOSYM
I 3,364,padreal,pad,NOSYM
EOF

38
alliance/src/cells/src/padlib/pck_sp.vbe Normal file
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@ -0,0 +1,38 @@
-- VHDL data flow description generated from `pck_sp`
-- date : Thu Feb 23 17:05:59 1995
-- Entity Declaration
ENTITY pck_sp IS
GENERIC (
CONSTANT area : NATURAL := 86000; -- area
CONSTANT cin_pad : NATURAL := 1326; -- cin_pad
CONSTANT tpll_pad : NATURAL := 1443; -- tpll_pad
CONSTANT rdown_pad : NATURAL := 58; -- rdown_pad
CONSTANT tphh_pad : NATURAL := 228; -- tphh_pad
CONSTANT rup_pad : NATURAL := 68 -- rup_pad
);
PORT (
pad : in BIT; -- pad
ck : out BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END pck_sp;
-- Architecture Declaration
ARCHITECTURE behaviour_data_flow OF pck_sp IS
BEGIN
ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
REPORT "power supply is missing on pck_sp"
SEVERITY WARNING;
ck <= pad;
END;

34
alliance/src/cells/src/padlib/pi_sp.al Normal file
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@ -0,0 +1,34 @@
V ALLIANCE : 4
H pi_sp,L,23/ 2/95
C pad,UNKNOWN,EXTERNAL,2
C t,UNKNOWN,EXTERNAL,3
C ck,UNKNOWN,EXTERNAL,1
C vdde,UNKNOWN,EXTERNAL,4
C vddi,UNKNOWN,EXTERNAL,5
C vsse,UNKNOWN,EXTERNAL,6
C vssi,UNKNOWN,EXTERNAL,7
T N,1,27,3,8,7,0,0,0,0,88,29
T N,1,27,7,8,3,0,0,0,0,94,29
T N,1,27,7,2,8,0,0,0,0,111,29
T N,1,27,8,2,7,0,0,0,0,117,29
T N,1,27,7,2,8,0,0,0,0,123,29
T N,1,35,6,6,2,0,0,0,0,97,273
T N,1,35,2,6,6,0,0,0,0,91,273
T N,1,35,6,6,2,0,0,0,0,85,273
T N,1,35,2,6,6,0,0,0,0,79,273
T P,1,57,5,8,3,0,0,0,0,94,95
T P,1,57,3,8,5,0,0,0,0,88,95
T P,1,27,5,2,8,0,0,0,0,111,80
T P,1,80,4,4,2,0,0,0,0,97,188.5
T P,1,80,2,4,4,0,0,0,0,91,188.5
T P,1,80,4,4,2,0,0,0,0,85,188.5
T P,1,80,2,4,4,0,0,0,0,79,188.5
S 8,INTERNAL,0,mbk_sig4
S 7,EXTERNAL,0,vssi
S 6,EXTERNAL,0,vsse
S 5,EXTERNAL,0,vddi
S 4,EXTERNAL,0,vdde
S 3,EXTERNAL,0,t
S 2,EXTERNAL,0,pad
S 1,EXTERNAL,0,ck
EOF

19
alliance/src/cells/src/padlib/pi_sp.ap Normal file
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@ -0,0 +1,19 @@
V ALLIANCE : 3
H pi_sp,P,30/ 0/95
A 9,1,181,501
C 91,1,2,t,1,SOUTH,ALU2
C 91,1,2,t,0,SOUTH,ALU1
C 9,14,12,ck,0,WEST,ALU2
C 181,14,12,ck,1,EAST,ALU2
C 181,48,40,vssi,1,EAST,ALU2
C 181,92,40,vddi,1,EAST,ALU2
C 181,176,120,vdde,1,EAST,ALU2
C 9,304,120,vsse,0,WEST,ALU2
C 181,304,120,vsse,1,EAST,ALU2
C 9,176,120,vdde,0,WEST,ALU2
C 9,92,40,vddi,0,WEST,ALU2
C 9,48,40,vssi,0,WEST,ALU2
C 97,501,1,pad,0,NORTH,ALU1
I 9,364,padreal,pad,NOSYM
I 9,1,pali_sp,log,NOSYM
EOF

39
alliance/src/cells/src/padlib/pi_sp.vbe Normal file
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@ -0,0 +1,39 @@
-- VHDL data flow description generated from `pi_sp`
-- date : Thu Feb 23 17:06:23 1995
-- Entity Declaration
ENTITY pi_sp IS
GENERIC (
CONSTANT area : NATURAL := 86000; -- area
CONSTANT cin_pad : NATURAL := 654; -- cin_pad
CONSTANT tpll_pad : NATURAL := 1487; -- tpll_pad
CONSTANT rdown_pad : NATURAL := 234; -- rdown_pad
CONSTANT tphh_pad : NATURAL := 233; -- tphh_pad
CONSTANT rup_pad : NATURAL := 273 -- rup_pad
);
PORT (
pad : in BIT; -- pad
t : out BIT; -- t
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END pi_sp;
-- Architecture Declaration
ARCHITECTURE behaviour_data_flow OF pi_sp IS
BEGIN
ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
REPORT "power supply is missing on pi_sp"
SEVERITY WARNING;
t <= pad;
END;

118
alliance/src/cells/src/padlib/piot_sp.al Normal file
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@ -0,0 +1,118 @@
V ALLIANCE : 4
H piot_sp,L,23/ 2/95
C i,UNKNOWN,EXTERNAL,3
C b,UNKNOWN,EXTERNAL,1
C t,UNKNOWN,EXTERNAL,5
C pad,UNKNOWN,EXTERNAL,4
C ck,UNKNOWN,EXTERNAL,2
C vdde,UNKNOWN,EXTERNAL,6
C vddi,UNKNOWN,EXTERNAL,7
C vsse,UNKNOWN,EXTERNAL,8
C vssi,UNKNOWN,EXTERNAL,9
T N,1,10,9,17,16,0,0,0,0,149,30.5
T N,1,10,17,1,9,0,0,0,0,155,30.5
T N,1,29,14,16,15,0,0,0,0,119,20
T N,1,29,15,16,14,0,0,0,0,125,20
T N,1,29,14,16,15,0,0,0,0,131,20
T N,1,29,15,16,14,0,0,0,0,137,20
T N,1,30,9,13,15,0,0,0,0,83,20.5
T N,1,30,15,13,9,0,0,0,0,77,20.5
T N,1,30,9,13,15,0,0,0,0,71,20.5
T N,1,30,15,13,9,0,0,0,0,65,20.5
T N,1,30,9,12,13,0,0,0,0,59,20.5
T N,1,30,15,17,9,0,0,0,0,89,20.5
T N,1,30,9,17,15,0,0,0,0,107,20.5
T N,1,30,12,3,9,0,0,0,0,47,20.5
T N,1,30,15,17,9,0,0,0,0,101,20.5
T N,1,30,9,17,15,0,0,0,0,95,20.5
T N,1,30,9,4,11,0,0,0,0,29,20.5
T N,1,30,5,11,9,0,0,0,0,35,20.5
T N,1,30,9,11,5,0,0,0,0,41,20.5
T N,1,30,9,4,11,0,0,0,0,17,20.5
T N,1,30,11,4,9,0,0,0,0,23,20.5
T N,1,35,4,15,8,0,0,0,0,137,265
T N,1,35,8,15,4,0,0,0,0,143,265
T N,1,35,4,15,8,0,0,0,0,149,265
T N,1,35,8,15,4,0,0,0,0,155,265
T N,1,35,4,15,8,0,0,0,0,113,265
T N,1,35,8,15,4,0,0,0,0,119,265
T N,1,35,4,15,8,0,0,0,0,125,265
T N,1,35,8,15,4,0,0,0,0,131,265
T N,1,35,4,15,8,0,0,0,0,89,265
T N,1,35,8,15,4,0,0,0,0,95,265
T N,1,35,4,15,8,0,0,0,0,101,265
T N,1,35,8,15,4,0,0,0,0,107,265
T N,1,35,4,15,8,0,0,0,0,65,265
T N,1,35,8,15,4,0,0,0,0,71,265
T N,1,35,4,15,8,0,0,0,0,77,265
T N,1,35,8,15,4,0,0,0,0,83,265
T N,1,35,4,15,8,0,0,0,0,41,265
T N,1,35,8,15,4,0,0,0,0,47,265
T N,1,35,4,15,8,0,0,0,0,53,265
T N,1,35,8,15,4,0,0,0,0,59,265
T N,1,35,8,15,4,0,0,0,0,35,265
T N,1,35,4,15,8,0,0,0,0,29,265
T N,1,35,8,15,4,0,0,0,0,23,265
T N,1,35,4,15,8,0,0,0,0,17,265
T P,1,59,15,17,14,0,0,0,0,131,86
T P,1,59,14,17,15,0,0,0,0,137,86
T P,1,60,14,13,7,0,0,0,0,77,85.5
T P,1,59,15,17,14,0,0,0,0,119,86
T P,1,59,14,17,15,0,0,0,0,125,86
T P,1,60,7,13,14,0,0,0,0,83,85.5
T P,1,60,7,13,14,0,0,0,0,71,85.5
T P,1,60,14,13,7,0,0,0,0,65,85.5
T P,1,60,7,12,13,0,0,0,0,59,85.5
T P,1,60,14,16,7,0,0,0,0,101,85.5
T P,1,60,7,16,14,0,0,0,0,95,85.5
T P,1,60,14,16,7,0,0,0,0,89,85.5
T P,1,60,7,11,5,0,0,0,0,41,85.5
T P,1,60,12,3,7,0,0,0,0,47,85.5
T P,1,60,7,16,14,0,0,0,0,107,85.5
T P,40,3,7,9,4,0,0,0,0,14,91
T P,1,30,7,4,11,0,0,0,0,29,70.5
T P,1,60,5,11,7,0,0,0,0,35,85.5
T P,1,20,7,17,16,0,0,0,0,149,66.5
T P,1,20,17,1,7,0,0,0,0,155,66.5
T P,1,80,4,14,6,0,0,0,0,137,180.5
T P,1,80,6,14,4,0,0,0,0,143,180.5
T P,1,80,4,14,6,0,0,0,0,149,180.5
T P,1,80,6,14,4,0,0,0,0,155,180.5
T P,1,80,4,14,6,0,0,0,0,113,180.5
T P,1,80,6,14,4,0,0,0,0,119,180.5
T P,1,80,4,14,6,0,0,0,0,125,180.5
T P,1,80,6,14,4,0,0,0,0,131,180.5
T P,1,80,4,14,6,0,0,0,0,89,180.5
T P,1,80,6,14,4,0,0,0,0,95,180.5
T P,1,80,4,14,6,0,0,0,0,101,180.5
T P,1,80,6,14,4,0,0,0,0,107,180.5
T P,1,80,4,14,6,0,0,0,0,65,180.5
T P,1,80,6,14,4,0,0,0,0,71,180.5
T P,1,80,4,14,6,0,0,0,0,77,180.5
T P,1,80,6,14,4,0,0,0,0,83,180.5
T P,1,80,4,14,6,0,0,0,0,41,180.5
T P,1,80,6,14,4,0,0,0,0,47,180.5
T P,1,80,4,14,6,0,0,0,0,53,180.5
T P,1,80,6,14,4,0,0,0,0,59,180.5
T P,1,80,6,14,4,0,0,0,0,35,180.5
T P,1,80,4,14,6,0,0,0,0,29,180.5
T P,1,80,6,14,4,0,0,0,0,23,180.5
T P,1,80,4,14,6,0,0,0,0,17,180.5
S 17,INTERNAL,0,mbk_sig10
S 16,INTERNAL,0,mbk_sig12
S 15,INTERNAL,0,mbk_sig9
S 14,INTERNAL,0,mbk_sig11
S 13,INTERNAL,0,mbk_sig6
S 12,INTERNAL,0,mbk_sig7
S 11,INTERNAL,0,mbk_sig2
S 10,INTERNAL,0,mbk_sig15
S 9,EXTERNAL,0,vssi
S 8,EXTERNAL,0,vsse
S 7,EXTERNAL,0,vddi
S 6,EXTERNAL,0,vdde
S 5,EXTERNAL,0,t
S 4,EXTERNAL,0,pad
S 3,EXTERNAL,0,i
S 2,EXTERNAL,0,ck
S 1,EXTERNAL,0,b
EOF

23
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@ -0,0 +1,23 @@
V ALLIANCE : 3
H piot_sp,P,23/ 1/95
A 0,-7,172,493
C 157,-7,2,b,2,SOUTH,ALU1
C 157,-7,2,b,3,SOUTH,ALU2
C 49,-7,2,i,2,SOUTH,ALU1
C 38,-7,2,t,2,SOUTH,ALU1
C 49,-7,2,i,3,SOUTH,ALU2
C 38,-7,2,t,3,SOUTH,ALU2
C 88,493,1,pad,0,NORTH,ALU1
C 0,296,120,vsse,0,WEST,ALU2
C 172,296,120,vsse,1,EAST,ALU2
C 172,6,12,ck,1,EAST,ALU2
C 172,40,40,vssi,1,EAST,ALU2
C 172,84,40,vddi,1,EAST,ALU2
C 172,168,120,vdde,1,EAST,ALU2
C 0,6,12,ck,0,WEST,ALU2
C 0,40,40,vssi,0,WEST,ALU2
C 0,84,40,vddi,0,WEST,ALU2
C 0,168,120,vdde,0,WEST,ALU2
I 0,356,padreal,pad,NOSYM
I 0,-7,paliot_sp,logic,NOSYM
EOF

54
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-- VHDL data flow description generated from `piot_sp`
-- date : Thu Feb 23 17:07:10 1995
-- Entity Declaration
ENTITY piot_sp IS
GENERIC (
CONSTANT area : NATURAL := 86000; -- area
CONSTANT rup : NATURAL := 402; -- rup
CONSTANT rdown : NATURAL := 0 -- rdown
);
PORT (
i : in BIT; -- i
b : in BIT; -- b
t : out BIT; -- t
pad : inout MUX_BIT BUS; -- pad
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END piot_sp;
-- Architecture Declaration
ARCHITECTURE behaviour_data_flow OF piot_sp IS
SIGNAL b1 : BIT; -- b1
SIGNAL b2 : BIT; -- b2
SIGNAL b3 : BIT; -- b3
SIGNAL b4 : BIT; -- b4
SIGNAL b5 : BIT; -- b5
SIGNAL b6 : BIT; -- b6
BEGIN
ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
REPORT "power supply is missing on piot_sp"
SEVERITY WARNING;
b6 <= b5;
b5 <= b4;
b4 <= b3;
b3 <= b2;
b2 <= b1;
b1 <= b;
label0 : BLOCK (b6 = '1')
BEGIN
pad <= GUARDED i;
END BLOCK label0;
t <= pad;
END;

94
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V ALLIANCE : 4
H piotw_sp,L,23/ 2/95
C i,UNKNOWN,EXTERNAL,3
C b,UNKNOWN,EXTERNAL,1
C t,UNKNOWN,EXTERNAL,5
C pad,UNKNOWN,EXTERNAL,4
C ck,UNKNOWN,EXTERNAL,2
C vdde,UNKNOWN,EXTERNAL,6
C vddi,UNKNOWN,EXTERNAL,7
C vsse,UNKNOWN,EXTERNAL,8
C vssi,UNKNOWN,EXTERNAL,9
T N,1,10,9,17,16,0,0,0,0,149,30.5
T N,1,10,17,1,9,0,0,0,0,155,30.5
T N,1,29,14,16,15,0,0,0,0,119,20
T N,1,29,15,16,14,0,0,0,0,125,20
T N,1,29,14,16,15,0,0,0,0,131,20
T N,1,29,15,16,14,0,0,0,0,137,20
T N,1,30,9,13,15,0,0,0,0,83,20.5
T N,1,30,15,13,9,0,0,0,0,77,20.5
T N,1,30,9,13,15,0,0,0,0,71,20.5
T N,1,30,15,13,9,0,0,0,0,65,20.5
T N,1,30,9,12,13,0,0,0,0,59,20.5
T N,1,30,15,17,9,0,0,0,0,89,20.5
T N,1,30,9,17,15,0,0,0,0,107,20.5
T N,1,30,12,3,9,0,0,0,0,47,20.5
T N,1,30,15,17,9,0,0,0,0,101,20.5
T N,1,30,9,17,15,0,0,0,0,95,20.5
T N,1,30,9,4,11,0,0,0,0,29,20.5
T N,1,30,5,11,9,0,0,0,0,35,20.5
T N,1,30,9,11,5,0,0,0,0,41,20.5
T N,1,30,9,4,11,0,0,0,0,17,20.5
T N,1,30,11,4,9,0,0,0,0,23,20.5
T N,1,35,4,15,8,0,0,0,0,92,265
T N,1,35,8,15,4,0,0,0,0,98,265
T N,1,35,4,15,8,0,0,0,0,104,265
T N,1,35,8,15,4,0,0,0,0,110,265
T N,1,35,4,15,8,0,0,0,0,68,265
T N,1,35,8,15,4,0,0,0,0,74,265
T N,1,35,4,15,8,0,0,0,0,80,265
T N,1,35,8,15,4,0,0,0,0,86,265
T N,1,35,8,15,4,0,0,0,0,62,265
T N,1,35,4,15,8,0,0,0,0,56,265
T N,1,35,8,15,4,0,0,0,0,50,265
T N,1,35,4,15,8,0,0,0,0,44,265
T P,1,59,15,17,14,0,0,0,0,131,86
T P,1,59,14,17,15,0,0,0,0,137,86
T P,1,60,7,13,14,0,0,0,0,83,85.5
T P,1,60,14,13,7,0,0,0,0,77,85.5
T P,1,59,15,17,14,0,0,0,0,119,86
T P,1,59,14,17,15,0,0,0,0,125,86
T P,1,60,7,12,13,0,0,0,0,59,85.5
T P,1,60,7,13,14,0,0,0,0,71,85.5
T P,1,60,14,13,7,0,0,0,0,65,85.5
T P,1,60,7,16,14,0,0,0,0,107,85.5
T P,1,60,14,16,7,0,0,0,0,101,85.5
T P,1,60,7,16,14,0,0,0,0,95,85.5
T P,1,60,14,16,7,0,0,0,0,89,85.5
T P,1,60,5,11,7,0,0,0,0,35,85.5
T P,1,60,7,11,5,0,0,0,0,41,85.5
T P,1,60,12,3,7,0,0,0,0,47,85.5
T P,40,3,7,9,4,0,0,0,0,14,91
T P,1,30,7,4,11,0,0,0,0,29,70.5
T P,1,20,7,17,16,0,0,0,0,149,66.5
T P,1,20,17,1,7,0,0,0,0,155,66.5
T P,1,80,4,14,6,0,0,0,0,92,180.5
T P,1,80,6,14,4,0,0,0,0,98,180.5
T P,1,80,4,14,6,0,0,0,0,104,180.5
T P,1,80,6,14,4,0,0,0,0,110,180.5
T P,1,80,4,14,6,0,0,0,0,68,180.5
T P,1,80,6,14,4,0,0,0,0,74,180.5
T P,1,80,4,14,6,0,0,0,0,80,180.5
T P,1,80,6,14,4,0,0,0,0,86,180.5
T P,1,80,6,14,4,0,0,0,0,62,180.5
T P,1,80,4,14,6,0,0,0,0,56,180.5
T P,1,80,6,14,4,0,0,0,0,50,180.5
T P,1,80,4,14,6,0,0,0,0,44,180.5
S 17,INTERNAL,0,mbk_sig10
S 16,INTERNAL,0,mbk_sig12
S 15,INTERNAL,0,mbk_sig9
S 14,INTERNAL,0,mbk_sig11
S 13,INTERNAL,0,mbk_sig6
S 12,INTERNAL,0,mbk_sig7
S 11,INTERNAL,0,mbk_sig2
S 10,INTERNAL,0,mbk_sig15
S 9,EXTERNAL,0,vssi
S 8,EXTERNAL,0,vsse
S 7,EXTERNAL,0,vddi
S 6,EXTERNAL,0,vdde
S 5,EXTERNAL,0,t
S 4,EXTERNAL,0,pad
S 3,EXTERNAL,0,i
S 2,EXTERNAL,0,ck
S 1,EXTERNAL,0,b
EOF

23
alliance/src/cells/src/padlib/piotw_sp.ap Normal file
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@ -0,0 +1,23 @@
V ALLIANCE : 3
H piotw_sp,P,23/ 1/95
A 0,-7,172,493
C 157,-7,2,b,2,SOUTH,ALU1
C 157,-7,2,b,3,SOUTH,ALU2
C 49,-7,2,i,2,SOUTH,ALU1
C 49,-7,2,i,3,SOUTH,ALU2
C 38,-7,2,t,2,SOUTH,ALU1
C 38,-7,2,t,3,SOUTH,ALU2
C 88,493,1,pad,0,NORTH,ALU1
C 172,296,120,vsse,1,EAST,ALU2
C 0,296,120,vsse,0,WEST,ALU2
C 0,168,120,vdde,0,WEST,ALU2
C 0,84,40,vddi,0,WEST,ALU2
C 0,40,40,vssi,0,WEST,ALU2
C 0,6,12,ck,0,WEST,ALU2
C 172,168,120,vdde,1,EAST,ALU2
C 172,84,40,vddi,1,EAST,ALU2
C 172,40,40,vssi,1,EAST,ALU2
C 172,6,12,ck,1,EAST,ALU2
I 0,356,padreal,pad,NOSYM
I 0,-7,paliotw_sp,logic,NOSYM
EOF

54
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@ -0,0 +1,54 @@
-- VHDL data flow description generated from `piotw_sp`
-- date : Thu Feb 23 17:07:47 1995
-- Entity Declaration
ENTITY piotw_sp IS
GENERIC (
CONSTANT area : NATURAL := 86000; -- area
CONSTANT rup : NATURAL := 402; -- rup
CONSTANT rdown : NATURAL := 0 -- rdown
);
PORT (
i : in BIT; -- i
b : in BIT; -- b
t : out BIT; -- t
pad : inout MUX_BIT BUS; -- pad
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END piotw_sp;
-- Architecture Declaration
ARCHITECTURE behaviour_data_flow OF piotw_sp IS
SIGNAL b1 : BIT; -- b1
SIGNAL b2 : BIT; -- b2
SIGNAL b3 : BIT; -- b3
SIGNAL b4 : BIT; -- b4
SIGNAL b5 : BIT; -- b5
SIGNAL b6 : BIT; -- b6
BEGIN
ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
REPORT "power supply is missing on piotw_sp"
SEVERITY WARNING;
b6 <= b5;
b5 <= b4;
b4 <= b3;
b3 <= b2;
b2 <= b1;
b1 <= b;
label0 : BLOCK (b6 = '1')
BEGIN
pad <= GUARDED i;
END BLOCK label0;
t <= pad;
END;

80
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V ALLIANCE : 4
H po_sp,L,23/ 2/95
C i,UNKNOWN,EXTERNAL,2
C pad,UNKNOWN,EXTERNAL,3
C ck,UNKNOWN,EXTERNAL,1
C vdde,UNKNOWN,EXTERNAL,4
C vddi,UNKNOWN,EXTERNAL,5
C vsse,UNKNOWN,EXTERNAL,6
C vssi,UNKNOWN,EXTERNAL,7
T N,1,30,10,2,7,0,0,0,0,45,20.5
T N,1,30,7,10,9,0,0,0,0,57,20.5
T N,1,30,8,9,7,0,0,0,0,63,20.5
T N,1,30,7,9,8,0,0,0,0,69,20.5
T N,1,30,8,9,7,0,0,0,0,75,20.5
T N,1,30,7,9,8,0,0,0,0,81,20.5
T N,1,35,3,8,6,0,0,0,0,17,265
T N,1,35,6,8,3,0,0,0,0,23,265
T N,1,35,3,8,6,0,0,0,0,29,265
T N,1,35,6,8,3,0,0,0,0,35,265
T N,1,35,3,8,6,0,0,0,0,41,265
T N,1,35,6,8,3,0,0,0,0,47,265
T N,1,35,3,8,6,0,0,0,0,53,265
T N,1,35,6,8,3,0,0,0,0,59,265
T N,1,35,3,8,6,0,0,0,0,65,265
T N,1,35,6,8,3,0,0,0,0,71,265
T N,1,35,3,8,6,0,0,0,0,77,265
T N,1,35,6,8,3,0,0,0,0,83,265
T N,1,35,3,8,6,0,0,0,0,89,265
T N,1,35,6,8,3,0,0,0,0,95,265
T N,1,35,3,8,6,0,0,0,0,101,265
T N,1,35,6,8,3,0,0,0,0,107,265
T N,1,35,3,8,6,0,0,0,0,113,265
T N,1,35,6,8,3,0,0,0,0,119,265
T N,1,35,3,8,6,0,0,0,0,125,265
T N,1,35,6,8,3,0,0,0,0,131,265
T N,1,35,3,8,6,0,0,0,0,137,265
T N,1,35,6,8,3,0,0,0,0,143,265
T N,1,35,3,8,6,0,0,0,0,149,265
T N,1,35,6,8,3,0,0,0,0,155,265
T P,1,60,10,2,5,0,0,0,0,45,85.5
T P,1,60,5,9,8,0,0,0,0,69,85.5
T P,1,60,5,10,9,0,0,0,0,57,85.5
T P,1,60,8,9,5,0,0,0,0,63,85.5
T P,1,60,8,9,5,0,0,0,0,75,85.5
T P,1,60,5,9,8,0,0,0,0,81,85.5
T P,1,80,3,8,4,0,0,0,0,17,180.5
T P,1,80,4,8,3,0,0,0,0,23,180.5
T P,1,80,3,8,4,0,0,0,0,29,180.5
T P,1,80,4,8,3,0,0,0,0,35,180.5
T P,1,80,3,8,4,0,0,0,0,41,180.5
T P,1,80,4,8,3,0,0,0,0,47,180.5
T P,1,80,3,8,4,0,0,0,0,53,180.5
T P,1,80,4,8,3,0,0,0,0,59,180.5
T P,1,80,3,8,4,0,0,0,0,65,180.5
T P,1,80,4,8,3,0,0,0,0,71,180.5
T P,1,80,3,8,4,0,0,0,0,77,180.5
T P,1,80,4,8,3,0,0,0,0,83,180.5
T P,1,80,3,8,4,0,0,0,0,89,180.5
T P,1,80,4,8,3,0,0,0,0,95,180.5
T P,1,80,3,8,4,0,0,0,0,101,180.5
T P,1,80,4,8,3,0,0,0,0,107,180.5
T P,1,80,3,8,4,0,0,0,0,113,180.5
T P,1,80,4,8,3,0,0,0,0,119,180.5
T P,1,80,3,8,4,0,0,0,0,125,180.5
T P,1,80,4,8,3,0,0,0,0,131,180.5
T P,1,80,3,8,4,0,0,0,0,137,180.5
T P,1,80,4,8,3,0,0,0,0,143,180.5
T P,1,80,3,8,4,0,0,0,0,149,180.5
T P,1,80,4,8,3,0,0,0,0,155,180.5
S 10,INTERNAL,0,mbk_sig3
S 9,INTERNAL,0,mbk_sig4
S 8,INTERNAL,0,mbk_sig6
S 7,EXTERNAL,0,vssi
S 6,EXTERNAL,0,vsse
S 5,EXTERNAL,0,vddi
S 4,EXTERNAL,0,vdde
S 3,EXTERNAL,0,pad
S 2,EXTERNAL,0,i
S 1,EXTERNAL,0,ck
EOF

19
alliance/src/cells/src/padlib/po_sp.ap Normal file
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@ -0,0 +1,19 @@
V ALLIANCE : 3
H po_sp,P,30/ 0/95
A 0,-7,172,493
C 172,6,12,ck,1,EAST,ALU2
C 172,40,40,vssi,1,EAST,ALU2
C 172,84,40,vddi,1,EAST,ALU2
C 172,168,120,vdde,1,EAST,ALU2
C 0,168,120,vdde,0,WEST,ALU2
C 0,84,40,vddi,0,WEST,ALU2
C 0,6,12,ck,0,WEST,ALU2
C 0,40,40,vssi,0,WEST,ALU2
C 47,-7,2,i,1,SOUTH,ALU2
C 47,-7,2,i,0,SOUTH,ALU1
C 88,493,1,pad,0,NORTH,ALU1
C 172,296,120,vsse,1,EAST,ALU2
C 0,296,120,vsse,0,WEST,ALU2
I 0,-7,palo_sp,logic,NOSYM
I 0,356,padreal,pad,NOSYM
EOF

39
alliance/src/cells/src/padlib/po_sp.vbe Normal file
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@ -0,0 +1,39 @@
-- VHDL data flow description generated from `po_sp`
-- date : Thu Feb 23 17:08:20 1995
-- Entity Declaration
ENTITY po_sp IS
GENERIC (
CONSTANT area : NATURAL := 86000; -- area
CONSTANT cin_i : NATURAL := 191; -- cin_i
CONSTANT tpll_i : NATURAL := 2176; -- tpll_i
CONSTANT rdown_i : NATURAL := 15; -- rdown_i
CONSTANT tphh_i : NATURAL := 2032; -- tphh_i
CONSTANT rup_i : NATURAL := 16 -- rup_i
);
PORT (
i : in BIT; -- i
pad : out BIT; -- pad
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END po_sp;
-- Architecture Declaration
ARCHITECTURE behaviour_data_flow OF po_sp IS
BEGIN
ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
REPORT "power supply is missing on po_sp"
SEVERITY WARNING;
pad <= i;
END;

107
alliance/src/cells/src/padlib/pot_sp.al Normal file
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@ -0,0 +1,107 @@
V ALLIANCE : 4
H pot_sp,L,23/ 2/95
C i,UNKNOWN,EXTERNAL,3
C b,UNKNOWN,EXTERNAL,1
C pad,UNKNOWN,EXTERNAL,4
C ck,UNKNOWN,EXTERNAL,2
C vdde,UNKNOWN,EXTERNAL,5
C vddi,UNKNOWN,EXTERNAL,6
C vsse,UNKNOWN,EXTERNAL,7
C vssi,UNKNOWN,EXTERNAL,8
T N,1,30,15,3,8,0,0,0,0,44,20.5
T N,1,30,13,14,8,0,0,0,0,98,20.5
T N,1,30,8,14,13,0,0,0,0,92,20.5
T N,1,30,13,14,8,0,0,0,0,86,20.5
T N,1,30,8,14,13,0,0,0,0,104,20.5
T N,1,30,8,12,13,0,0,0,0,68,20.5
T N,1,30,13,12,8,0,0,0,0,62,20.5
T N,1,30,8,15,12,0,0,0,0,56,20.5
T N,1,30,8,12,13,0,0,0,0,80,20.5
T N,1,30,13,12,8,0,0,0,0,74,20.5
T N,1,29,10,11,13,0,0,0,0,116,20
T N,1,29,13,11,10,0,0,0,0,122,20
T N,1,29,10,11,13,0,0,0,0,128,20
T N,1,29,13,11,10,0,0,0,0,134,20
T N,1,10,14,1,8,0,0,0,0,152,30.5
T N,1,10,8,14,11,0,0,0,0,146,30.5
T N,1,35,4,13,7,0,0,0,0,137,265
T N,1,35,7,13,4,0,0,0,0,143,265
T N,1,35,4,13,7,0,0,0,0,149,265
T N,1,35,7,13,4,0,0,0,0,155,265
T N,1,35,4,13,7,0,0,0,0,113,265
T N,1,35,7,13,4,0,0,0,0,119,265
T N,1,35,4,13,7,0,0,0,0,125,265
T N,1,35,7,13,4,0,0,0,0,131,265
T N,1,35,4,13,7,0,0,0,0,89,265
T N,1,35,7,13,4,0,0,0,0,95,265
T N,1,35,4,13,7,0,0,0,0,101,265
T N,1,35,7,13,4,0,0,0,0,107,265
T N,1,35,4,13,7,0,0,0,0,65,265
T N,1,35,7,13,4,0,0,0,0,71,265
T N,1,35,4,13,7,0,0,0,0,77,265
T N,1,35,7,13,4,0,0,0,0,83,265
T N,1,35,4,13,7,0,0,0,0,41,265
T N,1,35,7,13,4,0,0,0,0,47,265
T N,1,35,4,13,7,0,0,0,0,53,265
T N,1,35,7,13,4,0,0,0,0,59,265
T N,1,35,7,13,4,0,0,0,0,35,265
T N,1,35,4,13,7,0,0,0,0,29,265
T N,1,35,7,13,4,0,0,0,0,23,265
T N,1,35,4,13,7,0,0,0,0,17,265
T P,40,3,6,8,4,0,0,0,0,27,91
T P,1,20,6,14,11,0,0,0,0,146,66.5
T P,1,20,14,1,6,0,0,0,0,152,66.5
T P,1,60,15,3,6,0,0,0,0,44,85.5
T P,1,60,6,11,10,0,0,0,0,104,85.5
T P,1,60,10,11,6,0,0,0,0,98,85.5
T P,1,60,6,11,10,0,0,0,0,92,85.5
T P,1,60,10,11,6,0,0,0,0,86,85.5
T P,1,60,6,12,10,0,0,0,0,68,85.5
T P,1,60,10,12,6,0,0,0,0,62,85.5
T P,1,60,6,15,12,0,0,0,0,56,85.5
T P,1,60,6,12,10,0,0,0,0,80,85.5
T P,1,60,10,12,6,0,0,0,0,74,85.5
T P,1,59,13,14,10,0,0,0,0,116,86
T P,1,59,10,14,13,0,0,0,0,122,86
T P,1,59,13,14,10,0,0,0,0,128,86
T P,1,59,10,14,13,0,0,0,0,134,86
T P,1,80,4,10,5,0,0,0,0,137,180.5
T P,1,80,5,10,4,0,0,0,0,143,180.5
T P,1,80,4,10,5,0,0,0,0,149,180.5
T P,1,80,5,10,4,0,0,0,0,155,180.5
T P,1,80,4,10,5,0,0,0,0,113,180.5
T P,1,80,5,10,4,0,0,0,0,119,180.5
T P,1,80,4,10,5,0,0,0,0,125,180.5
T P,1,80,5,10,4,0,0,0,0,131,180.5
T P,1,80,4,10,5,0,0,0,0,89,180.5
T P,1,80,5,10,4,0,0,0,0,95,180.5
T P,1,80,4,10,5,0,0,0,0,101,180.5
T P,1,80,5,10,4,0,0,0,0,107,180.5
T P,1,80,4,10,5,0,0,0,0,65,180.5
T P,1,80,5,10,4,0,0,0,0,71,180.5
T P,1,80,4,10,5,0,0,0,0,77,180.5
T P,1,80,5,10,4,0,0,0,0,83,180.5
T P,1,80,4,10,5,0,0,0,0,41,180.5
T P,1,80,5,10,4,0,0,0,0,47,180.5
T P,1,80,4,10,5,0,0,0,0,53,180.5
T P,1,80,5,10,4,0,0,0,0,59,180.5
T P,1,80,5,10,4,0,0,0,0,35,180.5
T P,1,80,4,10,5,0,0,0,0,29,180.5
T P,1,80,5,10,4,0,0,0,0,23,180.5
T P,1,80,4,10,5,0,0,0,0,17,180.5
S 15,INTERNAL,0,mbk_sig4
S 14,INTERNAL,0,mbk_sig7
S 13,INTERNAL,0,mbk_sig6
S 12,INTERNAL,0,mbk_sig3
S 11,INTERNAL,0,mbk_sig9
S 10,INTERNAL,0,mbk_sig8
S 9,INTERNAL,0,mbk_sig12
S 8,EXTERNAL,0,vssi
S 7,EXTERNAL,0,vsse
S 6,EXTERNAL,0,vddi
S 5,EXTERNAL,0,vdde
S 4,EXTERNAL,0,pad
S 3,EXTERNAL,0,i
S 2,EXTERNAL,0,ck
S 1,EXTERNAL,0,b
EOF

21
alliance/src/cells/src/padlib/pot_sp.ap Normal file
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@ -0,0 +1,21 @@
V ALLIANCE : 3
H pot_sp,P,30/ 0/95
A 0,-7,172,493
C 154,-7,2,b,0,SOUTH,ALU1
C 154,-7,2,b,1,SOUTH,ALU2
C 46,-7,2,i,0,SOUTH,ALU1
C 46,-7,2,i,1,SOUTH,ALU2
C 0,168,120,vdde,0,WEST,ALU2
C 0,84,40,vddi,0,WEST,ALU2
C 0,40,40,vssi,0,WEST,ALU2
C 0,6,12,ck,0,WEST,ALU2
C 172,168,120,vdde,1,EAST,ALU2
C 172,84,40,vddi,1,EAST,ALU2
C 172,40,40,vssi,1,EAST,ALU2
C 172,6,12,ck,1,EAST,ALU2
C 172,296,120,vsse,1,EAST,ALU2
C 0,296,120,vsse,0,WEST,ALU2
C 88,493,1,pad,0,NORTH,ALU1
I 0,-7,palot_sp,logic,NOSYM
I 0,356,padreal,pad,NOSYM
EOF

51
alliance/src/cells/src/padlib/pot_sp.vbe Normal file
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@ -0,0 +1,51 @@
-- VHDL data flow description generated from `pot_sp`
-- date : Thu Feb 23 17:09:25 1995
-- Entity Declaration
ENTITY pot_sp IS
GENERIC (
CONSTANT area : NATURAL := 86000; -- area
CONSTANT rup : NATURAL := 684404; -- rup
CONSTANT rdown : NATURAL := 24 -- rdown
);
PORT (
i : in BIT; -- i
b : in BIT; -- b
pad : out MUX_BIT BUS; -- pad
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END pot_sp;
-- Architecture Declaration
ARCHITECTURE behaviour_data_flow OF pot_sp IS
SIGNAL b1 : BIT; -- b1
SIGNAL b2 : BIT; -- b2
SIGNAL b3 : BIT; -- b3
SIGNAL b4 : BIT; -- b4
SIGNAL b5 : BIT; -- b5
SIGNAL b6 : BIT; -- b6
BEGIN
ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
REPORT "power supply is missing on pot_sp"
SEVERITY WARNING;
b6 <= b5;
b5 <= b4;
b4 <= b3;
b3 <= b2;
b2 <= b1;
b1 <= b;
label0 : BLOCK (b6 = '1')
BEGIN
pad <= GUARDED i;
END BLOCK label0;
END;

83
alliance/src/cells/src/padlib/potw_sp.al Normal file
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@ -0,0 +1,83 @@
V ALLIANCE : 4
H potw_sp,L,23/ 2/95
C i,UNKNOWN,EXTERNAL,3
C b,UNKNOWN,EXTERNAL,1
C pad,UNKNOWN,EXTERNAL,4
C ck,UNKNOWN,EXTERNAL,2
C vdde,UNKNOWN,EXTERNAL,5
C vddi,UNKNOWN,EXTERNAL,6
C vsse,UNKNOWN,EXTERNAL,7
C vssi,UNKNOWN,EXTERNAL,8
T N,1,10,8,15,14,0,0,0,0,146,30.5
T N,1,10,15,1,8,0,0,0,0,152,30.5
T N,1,29,12,14,13,0,0,0,0,134,20
T N,1,29,13,14,12,0,0,0,0,128,20
T N,1,29,12,14,13,0,0,0,0,122,20
T N,1,29,13,14,12,0,0,0,0,116,20
T N,1,30,12,11,8,0,0,0,0,74,20.5
T N,1,30,8,11,12,0,0,0,0,80,20.5
T N,1,30,8,10,11,0,0,0,0,56,20.5
T N,1,30,12,11,8,0,0,0,0,62,20.5
T N,1,30,8,11,12,0,0,0,0,68,20.5
T N,1,30,8,15,12,0,0,0,0,104,20.5
T N,1,30,12,15,8,0,0,0,0,86,20.5
T N,1,30,8,15,12,0,0,0,0,92,20.5
T N,1,30,12,15,8,0,0,0,0,98,20.5
T N,1,30,10,3,8,0,0,0,0,44,20.5
T N,1,35,7,12,4,0,0,0,0,62,265
T N,1,35,4,12,7,0,0,0,0,56,265
T N,1,35,7,12,4,0,0,0,0,50,265
T N,1,35,4,12,7,0,0,0,0,44,265
T N,1,35,4,12,7,0,0,0,0,68,265
T N,1,35,7,12,4,0,0,0,0,74,265
T N,1,35,4,12,7,0,0,0,0,80,265
T N,1,35,7,12,4,0,0,0,0,86,265
T N,1,35,4,12,7,0,0,0,0,92,265
T N,1,35,7,12,4,0,0,0,0,98,265
T N,1,35,4,12,7,0,0,0,0,104,265
T N,1,35,7,12,4,0,0,0,0,110,265
T P,1,59,13,15,12,0,0,0,0,134,86
T P,1,59,12,15,13,0,0,0,0,128,86
T P,1,59,13,15,12,0,0,0,0,122,86
T P,1,59,12,15,13,0,0,0,0,116,86
T P,1,60,13,11,6,0,0,0,0,74,85.5
T P,1,60,6,11,13,0,0,0,0,80,85.5
T P,1,60,6,10,11,0,0,0,0,56,85.5
T P,1,60,13,11,6,0,0,0,0,62,85.5
T P,1,60,6,11,13,0,0,0,0,68,85.5
T P,1,60,13,14,6,0,0,0,0,86,85.5
T P,1,60,6,14,13,0,0,0,0,92,85.5
T P,1,60,13,14,6,0,0,0,0,98,85.5
T P,1,60,6,14,13,0,0,0,0,104,85.5
T P,1,60,10,3,6,0,0,0,0,44,85.5
T P,1,20,15,1,6,0,0,0,0,152,66.5
T P,1,20,6,15,14,0,0,0,0,146,66.5
T P,40,3,6,8,4,0,0,0,0,27,91
T P,1,80,5,13,4,0,0,0,0,62,180.5
T P,1,80,4,13,5,0,0,0,0,56,180.5
T P,1,80,5,13,4,0,0,0,0,50,180.5
T P,1,80,4,13,5,0,0,0,0,44,180.5
T P,1,80,4,13,5,0,0,0,0,68,180.5
T P,1,80,5,13,4,0,0,0,0,74,180.5
T P,1,80,4,13,5,0,0,0,0,80,180.5
T P,1,80,5,13,4,0,0,0,0,86,180.5
T P,1,80,4,13,5,0,0,0,0,92,180.5
T P,1,80,5,13,4,0,0,0,0,98,180.5
T P,1,80,4,13,5,0,0,0,0,104,180.5
T P,1,80,5,13,4,0,0,0,0,110,180.5
S 15,INTERNAL,0,mbk_sig7
S 14,INTERNAL,0,mbk_sig9
S 13,INTERNAL,0,mbk_sig8
S 12,INTERNAL,0,mbk_sig6
S 11,INTERNAL,0,mbk_sig4
S 10,INTERNAL,0,mbk_sig3
S 9,INTERNAL,0,mbk_sig12
S 8,EXTERNAL,0,vssi
S 7,EXTERNAL,0,vsse
S 6,EXTERNAL,0,vddi
S 5,EXTERNAL,0,vdde
S 4,EXTERNAL,0,pad
S 3,EXTERNAL,0,i
S 2,EXTERNAL,0,ck
S 1,EXTERNAL,0,b
EOF

21
alliance/src/cells/src/padlib/potw_sp.ap Normal file
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@ -0,0 +1,21 @@
V ALLIANCE : 3
H potw_sp,P,30/ 0/95
A 0,-7,172,493
C 154,-7,2,b,0,SOUTH,ALU1
C 154,-7,2,b,1,SOUTH,ALU2
C 46,-7,2,i,1,SOUTH,ALU2
C 46,-7,2,i,0,SOUTH,ALU1
C 172,6,12,ck,1,EAST,ALU2
C 172,40,40,vssi,1,EAST,ALU2
C 172,84,40,vddi,1,EAST,ALU2
C 172,168,120,vdde,1,EAST,ALU2
C 0,6,12,ck,0,WEST,ALU2
C 0,40,40,vssi,0,WEST,ALU2
C 0,84,40,vddi,0,WEST,ALU2
C 0,168,120,vdde,0,WEST,ALU2
C 0,296,120,vsse,0,WEST,ALU2
C 172,296,120,vsse,1,EAST,ALU2
C 88,493,1,pad,0,NORTH,ALU1
I 0,-7,palotw_sp,logic,NOSYM
I 0,356,padreal,pad,NOSYM
EOF

51
alliance/src/cells/src/padlib/potw_sp.vbe Normal file
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@ -0,0 +1,51 @@
-- VHDL data flow description generated from `potw_sp`
-- date : Thu Feb 23 17:09:58 1995
-- Entity Declaration
ENTITY potw_sp IS
GENERIC (
CONSTANT area : NATURAL := 86000; -- area
CONSTANT rup : NATURAL := 684404; -- rup
CONSTANT rdown : NATURAL := 49 -- rdown
);
PORT (
i : in BIT; -- i
b : in BIT; -- b
pad : out MUX_BIT BUS; -- pad
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END potw_sp;
-- Architecture Declaration
ARCHITECTURE behaviour_data_flow OF potw_sp IS
SIGNAL b1 : BIT; -- b1
SIGNAL b2 : BIT; -- b2
SIGNAL b3 : BIT; -- b3
SIGNAL b4 : BIT; -- b4
SIGNAL b5 : BIT; -- b5
SIGNAL b6 : BIT; -- b6
BEGIN
ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
REPORT "power supply is missing on potw_sp"
SEVERITY WARNING;
b6 <= b5;
b5 <= b4;
b4 <= b3;
b3 <= b2;
b2 <= b1;
b1 <= b;
label0 : BLOCK (b6 = '1')
BEGIN
pad <= GUARDED i;
END BLOCK label0;
END;

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