diff --git a/alliance/src/cells/Makefile.am b/alliance/src/cells/Makefile.am new file mode 100644 index 00000000..536cf5da --- /dev/null +++ b/alliance/src/cells/Makefile.am @@ -0,0 +1,3 @@ +# $Id: Makefile.am,v 1.2 2002/04/30 14:57:05 czo Exp $ + +SUBDIRS = src doc diff --git a/alliance/src/cells/configure.in b/alliance/src/cells/configure.in new file mode 100644 index 00000000..47fa0408 --- /dev/null +++ b/alliance/src/cells/configure.in @@ -0,0 +1,14 @@ +dnl $Id: configure.in,v 1.1 2002/04/29 15:51:49 czo Exp $ + +AC_INIT(doc/sxlib.5) +AM_INIT_AUTOMAKE(cells, 1.1) + +AC_PROG_INSTALL + +AM_ALLIANCE + +AC_OUTPUT([ +Makefile +doc/Makefile +src/Makefile +]) diff --git a/alliance/src/cells/doc/Makefile.am b/alliance/src/cells/doc/Makefile.am new file mode 100644 index 00000000..01496542 --- /dev/null +++ b/alliance/src/cells/doc/Makefile.am @@ -0,0 +1,4 @@ +# $Id: Makefile.am,v 1.1 2002/04/29 15:51:57 czo Exp $ + +man_MANS = sxlib.5 +EXTRA_DIST = $(man_MANS) diff --git a/alliance/src/cells/doc/sxlib.5 b/alliance/src/cells/doc/sxlib.5 new file mode 100644 index 00000000..7a5104bb --- /dev/null +++ b/alliance/src/cells/doc/sxlib.5 @@ -0,0 +1,412 @@ +.\" $Id: sxlib.5,v 1.1 2002/04/29 15:51:57 czo Exp $ +.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: Franck Wajsburt +.TH SXLIB 5 "October 19, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual" +.SH NAME +.B sxlib - a portable CMOS Standard Cell Library +.so man1/alc_origin.1 + +.SH DESCRIPTION + +\fBsxlib\fP library contains standard cells that have been developed at +UPMC-ASIM/LIP6. This manual gives the list of available cells, with their +behavior, width, maximum delay and input fan-in. This manual gives also +few thumb rules to help the user to well use the cells. The given delay +are the maximum (that means worst case for a generic .35 micron process). +More precise delay can be found in ALLIANCE VHDL behavior files (.vbe file). +Cell-name is built that way _ +(see explanations below). + +.nf +Four files are attached to each cell:- +- ALLIANCE Layout ............... cell-name.ap +- ALLIANCE Transistor net-list .. cell-name.al +- ALLIANCE VHDL behavior ........ cell-name.vbe +- Compiled HILO behavior ........ 0000000xx.dat + +And few files more:- +- CATAL ......................... ALLIANCE catalog file +- sxlib.cct ..................... Cell definition for HILO CAD tools +- CIRCUIT.idx ................... HILO catalog file +- sxlib.lib ..................... Cell definition for Synopsys CAD tools +- sxlib.db ...................... Compiled cell definition for Synopsys +- sxlib.sdb ..................... Icon definition for Synopys + +.fi + +.SH PHYSICAL OUTLINE + +\fBsxlib\fP uses the symbolic layout promoted by Alliance in order to +provide process independence. All dimensions are in lambda units. The +mapping to a specific process CIF or GDS2 layout must be performed by the +\fBs2r\fP tool (symbolic to real), which uses a value for the lambda +(e.g. 1 lambda=0.3um). +.nf + + _________________ + 50 | VDD | + 45 |_________________| x : place of virtual connector. + 40 | x | + 35 | x x | they are named : name_ + 30 | x x | + 25 | x x | for example : i0_20 + 20 | x | i0_25 + 15 | x | i0_30 + 10 |_________________| + 5 | VSS | + 0 |_________________| + 0 5 10 15 20 25 30 + +.fi +All cells are 50 lambdas high and \fBN\fP times 5 lambdas wide, where +\fBN\fP is the number of pitches. That is the only physical information +given in the cell list below. Power supplies are in horizontal ALU1 and +are 6 lambdas wide. Connectors are inside the cells, placed on a 5x5 grid. +Half layout design rules are a warranty for any layer on any face, except +for the power supply and NWELL. Cells can be abutted in all directions +whenever the supply is well connected and connectors are always placed on +the 5x5 grid. + +.SH DELAY MODEL + +Cells have been extracted and simulated by using a generic 0.35um process +in order to give realistic values for the delays and capacitances. We +chose to give only the worst delay for each output signal, though it is not +very realistic (since delay depends on each input, an input can be easily +up to twice faster than another). However, we just wanted to give an idea +of the relative delay. + +Furthermore, we added 0.6ns to each output delay in order to take into +account the delay due to the signal commutation. We have supposed the +output drives the maximum capacitance. This capacitance have been computed +as follow. We considered that a good slope signal for this process was +0.8ns. Then we searched for the capacitance required to obtain the same +input and output slope (0.8ns) for the smaller inverter (inv_x1). That was +125fF. We simulated the same inverter without output capacitance. The delay +difference was about 0.6ns. This result is not exactly the same for all +cells, but 0.6ns is a good approximation. + +The given delay is then a worst case (70degree, 2.7Volt, slow process, +worst input), an idea of the typical delay can be obtain by dividing worst +delay by 1.5, and best delay by dividing by 2. More detailed data can be +found in GENERIC data included in the VHDL files (.vbe). Examples can be +found at the end of this manual. + +At last, to get a very better idea about the real delay without simulating +the spice transistor netlist, it is required to use the TAS (1) tool, which +is a timing static analyzer able to give the longer and the shorter path for +a given process. + +.SH OUTPUT DRIVE + +The output drive of a cell gives an information on the faculty for the cell +to drive a big capacitance. This faculty depends on the rising and falling +output resistance. The smaller the resistance, the bigger can be the +capacitance. Minimum drive is \fBx1\fP. This corresponds to the smallest +available inverter (inv_x1). \fBx2\fP means the cell is equivalent (from +the driving point of view) at two smaller inverters in parallel, and so +on. + +The maximum output drive is \fBx8\fP. It is limited because of the maximum +output slope and the maximum authorized instantaneous current. If it was +bigger the output slope could be very tight and the current too big. + +With the 0.35um process, an \fBx1\fP is able to drive about \fB125fF\fP, +\fBx2\fP -> \fB250fF\fP, \fBx4\fP -> \fB500fF\fP,\fBx8\fP -> \fB1000fF\fP. +This is just an indication since if a cell is overloaded, the only +consequence is to increase the propagation time. On the other hand, it is +not very good to under-load a cell because this leads to a signal overshoot. +Actually, for big gate, such as noa3ao322_x1, \fBx1\fP means maximal +driving strength reachable with a single logic layer, that can be much +less than an inv_x1. That is why is the cell list below contains more precise +drive strengh. As you can see noa3ao322_x1 as a output drive strengh of 0.6, +that means 0.6 time an inverter, so say it can drive about 0.6*125fF=75fF. + +With the 0.35um process, a \fB1\fP lambda interconnect wire is about +\fB0.15fF\fP, an average cell fan-in is 10fF. Then, if it needs about 50 +lambdas to connect 2 cells, an \fBx1\fP cell is able to drive about 7 +cells (125/(10+50*.15)=7). With 100 lambdas, 5 cells, with 750 lambdas +only 2 cells. Note that 50 lambdas means cells are very close one from +each other, nearly abutted, 100 lambdas is an average value. + +All this are indications. Only a timing analysis on the extracted +transistor net-list from layout can tell if a cell is well used or not +(see tas(1) for informations about static timing analysis). + +.SH BEHAVIOR + +For most of cells, the user can deduce the cell behavior just by reading its +name. That is very intuitive for \fBinv\fPerter and more complex for and/or +cells. For the last, the name gives the and/or tree structure. The input +order for the VHDL interface component is always the alphabetic order. + +.nf +\fBinv\fP : \fBinv\fPersor buffer +\fBbuf\fP : \fBbuf\fPfer +[\fBn\fP]\fBts\fP : [\fBn\fPot] \fBt\fPree-\fBs\fPtate +[\fBn\fP]\fBxr\fP : [\fBn\fPot] \fBx\fPo\fBr\fP inputs +[\fBn\fP]\fBmx\fP : [\fBn\fPot] \fBm\fPultiple\fBx\fPor inputs with coded command +[\fBn\fP][\fBsd\fP]\fBff\fP : [\fBn\fPot] [\fBs\fPtatic|\fBd\fPynamic] \fBf\fPlip-\fBf\fPlop inputs +[\fBn\fP]\fBoa\fP... : [\fBn\fPot] \fBa\fPnd/\fBo\fPr function (see below) + +\fBand_or cell (YACC (1) grammar):-\fP + +NAME : \fBn\fP OA_CELL -> not OA_CELL + | OA_CELL -> OA_CELL + +OA_CELL : OPERATOR INPUTS -> function with INPUTS inputs + | OPERATOR OA_CELLS INPUTS -> function with INPUTS inputs + where some inputs are OA_CELL + +OPERATOR : \fBa\fP -> and + | \fBo\fP -> or + | \fBn\fP -> not + +OA_CELLS : OA_CELLS OA_CELL -> list of OA_CELL + | OA_CELL -> last OA_CELL of the list + +INPUTS : \fBinteger\fP -> number of inputs + +The input names are implicit and formed that way \fBi\fP. +They are attributed in order beginning by \fBi0\fP. + +\fBnx\fP where x is a number means there are x inverters in parallel. For +example an23 is an \fBand\fP with 3 inputs of which two are inverted, that +is \fBand( not(i0), not(i1), i2)\fP. + +\fBExamples:-\fP (some are not in sxlib) + +na2 : not( and(i0,i1)) +on12 : or( not(i0), i1) +noa2a22 : not( or( and(i0,i1), and(i2,i3))) +noa23 : not( or( and(i0,i1), i3)) +noao22a34 : not( or( and( or(i0,i1), i2), and(i3,i4,i5), i6, i7)) + +Note that xr2 could not be expressed with an and/or formulea even if +.br +xr2 = or( and( not(i0), i1), and( not(i1), i0)) = oan12an122 +.br +but the input names are not well distributed. +.fi + +.SH CELL LIST + +All available cells are listed below. The first column is the pitch width. +The pitch value is 5 lambdas. The height is 50. Area is then *5*50. + +The second column is the output drive strenght compared with the \fBinv_x1\fP +output drive strenght (see explanation above in section OUTPUT DRIVE). + +The following column is the delay in nano-seconds. +Remember this delay corresponds to the slower +input+0.6ns (see explanation above in section DELAY MODEL). + +The last column gives the function behavior with input capacitance. +\fB/\fP means \fBnot\fP, \fB+\fP means \fBor\fP, \fB.\fP +means \fBand\fP, \fB^\fP means \fBxor\fP. +Each input is followed by fan-in capacitance in fF, +(e.g. i0<11> means i0 pin capacitance is 11fF). + +For some cells, such as +\fBfulladder\fP, it was not possible to internally connect all inputs. +That means there are several inputs that \fBmust be externally connected\fP. +In the following list, these inputs are followed by a star (*) character in +the equation. + +For example, fulladder equation is sout <= (a* . b* . cin*). +a* replaces a0, a1, a2, a3 that must be explicitly connected by the user. +Note also few cells have more than one output. In that case there are +several lines in the list, one by output. +.nf +\fB=================================================================\fP +\fBWIDTH NAME DRIVE DELAY BEHAVIOR with cin\fP +\fB-------------------------------------------------------- INVERSOR\fP + 3 inv_x1 1.0 0.7 nq <= /i<8> + 3 inv_x2 1.6 0.7 nq <= /i<12> + 4 inv_x4 3.6 0.7 nq <= /i<26> + 7 inv_x8 8.4 0.7 nq <= /i<54> +\fB---------------------------------------------------------- BUFFER\fP + 4 buf_x2 2.1 1.0 q <= i<6> + 5 buf_x4 4.3 1.0 q <= i<9> + 8 buf_x8 8.4 1.0 q <= i<15> +\fB------------------------------------------------------ THREE STATE\fP + 6 nts_x1 1.2 0.8 IF (cmd<14>) nq <= /i<14> + 8 nts_x2 2.4 0.9 IF (cmd<18>) nq <= /i<28> +10 ts_x4 4.3 1.1 IF (cmd<19>) q <= i<8> +13 ts_x8 8.4 1.2 IF (cmd<19>) q <= i<8> +\fB-------------------------------------------------------------- AND\fP + 4 na2_x1 1.0 0.9 nq <= /(i0<11>.i1<11>) + 7 na2_x4 4.3 1.2 nq <= /(i0<10>.i1<10>) + 5 na3_x1 0.9 1.0 nq <= /(i0<11>.i1<11>.i2<11>) + 8 na3_x4 4.3 1.3 nq <= /(i0<10>.i1<10>.i2<10>) + 6 na4_x1 0.7 1.0 nq <= /(i0<10>.i1<11>.i2<11>.i3<11>) +10 na4_x4 4.3 1.4 nq <= /(i0<10>.i1<11>.i2<11>.i3<11>) + 5 a2_x2 2.1 1.0 q <= (i0<9>.i1<11>) + 6 a2_x4 4.3 1.1 q <= (i0<9>.i1<11>) + 6 a3_x2 2.1 1.1 q <= (i0<10>.i1<10>.i2<10>) + 7 a3_x4 4.3 1.2 q <= (i0<10>.i1<10>.i2<10>) + 7 a4_x2 2.1 1.2 q <= (i0<10>.i1<10>.i2<10>.i3<10>) + 8 a4_x4 4.3 1.3 q <= (i0<10>.i1<10>.i2<10>.i3<10>) + 5 an12_x1 1.0 1.0 q <= (/i0<12>).i1<9> + 8 an12_x4 4.3 1.1 q <= (/i0<9>).i1<11> +\fB--------------------------------------------------------------- OR\fP + 4 no2_x1 1.0 0.9 nq <= /(i0<12>+i1<12>) + 8 no2_x4 4.3 1.2 nq <= /(i0<12>+i1<11>) + 5 no3_x1 0.8 1.0 nq <= /(i0<12>+i1<12>+i2<12>) + 8 no3_x4 4.3 1.3 nq <= /(i0<12>+i1<12>+i2<11>) + 6 no4_x1 0.6 1.1 nq <= /(i0<12>+i1<12>+i2<12>+i3<12>) +10 no4_x4 4.3 1.4 nq <= /(i0<12>+i1<12>+i2<12>+i3<12>) + 5 o2_x2 2.1 1.0 q <= (i0<10>+i1<10>) + 6 o2_x4 4.3 1.1 q <= (i0<10>+i1<10>) + 6 o3_x2 2.1 1.1 q <= (i0<10>+i1<10>+i2<9>) +10 o3_x4 4.3 1.2 q <= (i0<10>+i1<10>+i2<9>) + 7 o4_x2 2.1 1.2 q <= (i0<10>+i1<10>+i2<10>+i3<9>) + 8 o4_x4 4.3 1.3 q <= (i0<12>+i1<12>+i2<12>+i3<12>) + 5 on12_x1 1.0 0.9 q <= (/i0<11>)+i1<9> + 8 on12_x4 4.3 1.1 q <= (/i0<9>)+i1<10> +\fB--------------------------------------------------------- AND/OR 3\fP + 6 nao22_x1 1.2 0.9 nq <= /((i0<14>+i1<14>).i2<14>) +10 nao22_x4 4.3 1.3 nq <= /((i0<8> +i1<8>) .i2<9>) + 6 noa22_x1 1.2 0.9 nq <= /((i0<14>.i1<14>)+i2<14>) +10 noa22_x4 4.3 1.3 nq <= /((i0<8> .i1<8>) +i2<9>) + 6 ao22_x2 2.1 1.2 q <= ((i0<8>+i1<8>).i2<9>) + 8 ao22_x4 4.3 1.3 q <= ((i0<8>+i1<8>).i2<9>) + 6 oa22_x2 2.1 1.2 q <= ((i0<8>.i1<8>)+i2<9>) + 8 oa22_x4 4.3 1.3 q <= ((i0<8>.i1<8>)+i2<9>) +\fB--------------------------------------------------------- AND/OR 4\fP + 7 nao2o22_x1 1.2 1.0 nq <= /((i0<14>+i1<14>).(i2<14>+i3<14>)) +11 nao2o22_x4 4.3 1.4 nq <= /((i0<8> +i1<8>) .(i2<8> +i3<8>)) + 7 noa2a22_x1 1.2 1.0 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<14>)) +11 noa2a22_x4 4.3 1.4 nq <= /((i0<8> .i1<8>) +(i2<8> .i3<8>)) + 9 ao2o22_x2 2.1 1.2 q <= ((i0<8>+i1<8>).(i2<8>+i3<8>)) +10 ao2o22_x4 4.3 1.3 q <= ((i0<8>+i1<8>).(i2<8>+i3<8>)) + 9 oa2a22_x2 2.1 1.2 q <= ((i0<8>.i1<8>)+(i2<8>.i3<8>)) +10 oa2a22_x4 4.3 1.4 q <= ((i0<8>.i1<8>)+(i2<8>.i3<8>)) +\fB--------------------------------------------------------- AND/OR 5\fP + 7 noa2ao222_x1 0.7 1.1 nq <= /((i0<11>.i1<11>)+((i2<13>+i3<13>).i4<13>)) +11 noa2ao222_x4 4.3 1.4 nq <= /((i0<11>.i1<11>)+((i2<11>+i3<11>).i4<11>)) +10 oa2ao222_x2 2.1 1.2 q <= ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>)) +11 oa2ao222_x4 4.3 1.3 q <= ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>)) +\fB--------------------------------------------------------- AND/OR 6\fP +10 noa2a2a23_x1 0.8 1.2 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>) + +(i4<14>.i5<14>)) +13 noa2a2a23_x4 4.3 1.3 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>) + +(i4<14>.i5<14>)) +12 oa2a2a23_x2 2.1 1.4 q <= ((i0<13>.i1<14>) +(i2<14>.i3<14>) + +(i4<14>.i5<14>)) +13 oa2a2a23_x4 4.3 1.4 q <= ((i0<13>.i1<14>) +(i2<14>.i3<14>) + +(i4<14>.i5<14>)) +\fB--------------------------------------------------------- AND/OR 7\fP + 9 noa3ao322_x1 0.6 1.2 nq <= /((i0<13>.i1<13>.i2<12>) + +((i3<13>+i4<13>+i5<13>).i6<13>)) +11 noa3ao322_x4 4.3 1.4 nq <= /((i0<10>.i1<9>.i2<9>) + +((i3<9>+i4<9>+i5<9>).i6<9>)) +10 oa3ao322_x2 2.1 1.2 q <= /((i0<10>.i1<9>.i2<9>) + +((i3<9>+i4<9>+i5<9>).i6<9>)) +11 oa3ao322_x4 4.3 1.3 q <= /((i0<10>.i1<9>.i2<9>) + +((i3<9>+i4<9>+i5<9>).i6<9>)) +\fB--------------------------------------------------------- AND/OR 8\fP +14 noa2a2a2a24_x1 0.6 1.4 nq <= /((i0<14>.i1<14>)+(i2<13>.i3<13>) + +(i4<13>.i5<13>)+(i6<14>.i7<14>)) +17 noa2a2a2a24_x4 4.3 1.7 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<13>) + +(i4<13>.i5<13>)+(i6<14>.i7<14>)) +15 oa2a2a2a24_x2 2.1 1.5 q <= ((i0<14>.i1<14>)+(i2<14>.i3<13>) + +(i4<13>.i5<13>)+(i6<14>.i7<14>)) +16 oa2a2a2a24_x4 4.3 1.6 q <= ((i0<14>.i1<14>)+(i2<14>.i3<13>) + +(i4<13>.i5<13>)+(i6<14>.i7<14>)) +\fB------------------------------------------------------ MULTIPLEXER\fP + 7 nmx2_x1 1.2 1.0 nq <= /((i0<14>./cmd<21>)+(i1<14>.cmd)) +12 nmx2_x4 4.3 1.3 nq <= /((i0<8>./cmd<14>)+(i1<9>.cmd)) + 9 mx2_x2 2.1 1.1 q <= (i0<8>./cmd<17>)+(i1<9>.cmd) +10 mx2_x4 4.3 1.3 q <= (i0<8>./cmd<17>)+(i1<9>.cmd) +12 nmx3_x1 0.4 1.2 nq <= /((i0<9>./cmd0<15>) + +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0)) +15 nmx3_x4 4.3 1.7 nq <= /((i0<9>./cmd0<15>) + +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0)) +13 mx3_x2 2.1 1.4 q <= ((i0<9>./cmd0<15>) + +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0)) +14 mx3_x4 4.3 1.6 q <= ((i0<9>./cmd0<15>) + +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0)) +\fB-------------------------------------------------------------- XOR\fP + 9 nxr2_x1 1.2 1.1 nq <= /(i0<21>^i1<22>) +11 nxr2_x4 4.3 1.2 nq <= /(i0<20>^i1<21>) + 9 xr2_x1 1.2 1.0 q <= (i0<21>^i1<22>) +12 xr2_x4 4.3 1.2 q <= (i0<20>^i1<21>) +\fB-------------------------------------------------------- FLIP-FLOP\fP +."25 nsdff2_x4 4.3 1.0 IF RISE(ck<23>) + nq <=/((i0<11>./cmd<13>)+(i1<7>.cmd)) +18 sff1_x4 4.3 1.7 IF RISE(ck<8>) + q <= i<8> +24 sff2_x4 4.3 1.9 IF RISE(ck<8>) + q <= ((i0<8>./cmd<16>)+(i1<7>.cmd)) +28 sff3_x4 4.3 2.4 IF RISE(ck<8>) + q <= (i0<9>./cmd0<15>) + +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0) +\fB------------------------------------------------------------ ADDER\fP +16 halfadder_x2 2.1 1.2 sout <= (a<27>^b<22>) + 2.1 1.0 cout <= (a.b) +18 halfadder_x4 4.3 1.3 sout <= (a<27>^b<22>) + 4.3 1.1 cout <= (a.b) +20 fulladder_x2 2.1 1.8 sout <= (a*<28>^b*<28>^cin*<19>) + 2.1 1.4 cout <= (a*.b*+a*.cin*+b*.cin*) +21 fulladder_x4 4.3 2.2 sout <= (a*<28>^b*<28>^cin*<19>) + 4.3 1.5 cout <= (a*.b*+a*.cin*+b*.cin*) +\fB---------------------------------------------------------- SPECIAL\fP + 3 zero_x0 0 0 nq <= '0' + 3 one_x0 0 0 q <= '1' + 2 tie_x0 0 0 Body tie cell + 1 rowend_x0 0 0 Empty cell +\fB==================================================================\fP +.fi + +.SH NEW CELLS + +It is possible to add new cells in the library just by providing the 3 +files .ap, .al and .vbe in the standard cell directory. The layout view +can be created with the symbolic editor graal. The physical outline is +given above. The net-list view can be automatically generated with the +lynx extractor. The behavioral view must be written by the designer and +checked with the yagle functional abstractor. The file must contain the +generic fields in order to be used by the logic synthesis tools and the +I/Os terminals must be in the same order (alphabetic) in the .vbe and .al +files. + +If you develop new cells, please send the corresponding files +to alliance\-support@asim.lip6.fr + +.SH VHDL FILES + +You can find below the commented VHDL GENERIC for the na2_x4 cell. +.nf +ENTITY na2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; -- lamba * lambda + CONSTANT transistors : NATURAL := 10; -- number of + CONSTANT cin_i0 : NATURAL := 10; -- femto Farad for i0 + CONSTANT cin_i1 : NATURAL := 10; -- femto Farad for i1 + CONSTANT tplh_i1_nq : NATURAL := 606; -- propag. time in pico-sec + -- from i1 falling + -- to nq rizing + CONSTANT rup_i1_nq : NATURAL := 890; -- resitance in Ohms when nq + -- rizing due to i1 change + CONSTANT tphl_i1_nq : NATURAL := 349; -- propag time when nq falls + CONSTANT rdown_i1_nq : NATURAL := 800; -- resist when nq falls + CONSTANT tplh_i0_nq : NATURAL := 557; -- idem for i0 + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 408; + CONSTANT rdown_i0_nq : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +.fi + +.SH SEE ALSO + +\fBMBK_CATA_LIB (1), catal(1), scr(1), lynx(1), bop(1), glop(1), scmap(1), +c4map(1), tas(1), yagle(1), genlib(1), ap(1), al(1), vbe(1)\fP + +.so man1/alc_bug_report.1 diff --git a/alliance/src/cells/src/Makefile.am b/alliance/src/cells/src/Makefile.am new file mode 100644 index 00000000..80e7346e --- /dev/null +++ b/alliance/src/cells/src/Makefile.am @@ -0,0 +1,4 @@ +# $Id: Makefile.am,v 1.1 2002/04/29 15:51:49 czo Exp $ + +#SUBDIRS = dp_sxlib padlib rflib sxlib +SUBDIRS = sxlib diff --git a/alliance/src/cells/src/dp_sxlib/CATAL b/alliance/src/cells/src/dp_sxlib/CATAL new file mode 100644 index 00000000..b3999ee5 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/CATAL @@ -0,0 +1,24 @@ +dp_dff_scan_x4 C +dp_dff_scan_x4_buf C +dp_dff_x4 C +dp_dff_x4_buf C +dp_mux_x2 C +dp_mux_x2_buf C +dp_mux_x4 C +dp_mux_x4_buf C +dp_nmux_x1 C +dp_nmux_x1_buf C +dp_nts_x2 C +dp_nts_x2_buf C +dp_rom2_buf C +dp_rom4_buf C +dp_rom4_nxr2_x4 C +dp_rom4_xr2_x4 C +dp_sff_scan_x4 C +dp_sff_scan_x4_buf C +dp_sff_x4 C +dp_sff_x4_buf C +dp_ts_x4 C +dp_ts_x4_buf C +dp_ts_x8 C +dp_ts_x8_buf C diff --git a/alliance/src/cells/src/dp_sxlib/Makefile.am b/alliance/src/cells/src/dp_sxlib/Makefile.am new file mode 100644 index 00000000..7d1be649 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/Makefile.am @@ -0,0 +1,6 @@ +# $Id: Makefile.am,v 1.1 2002/04/29 15:51:49 czo Exp $ + +dp_sxlib_DATA= CATAL dp_dff_scan_x4.ap dp_dff_scan_x4.vbe dp_dff_scan_x4_buf.ap dp_dff_scan_x4_buf.vbe dp_dff_x4.ap dp_dff_x4.vbe dp_dff_x4_buf.ap dp_dff_x4_buf.vbe dp_mux_x2.ap dp_mux_x2.vbe dp_mux_x2_buf.ap dp_mux_x2_buf.vbe dp_mux_x4.ap dp_mux_x4.vbe dp_mux_x4_buf.ap dp_mux_x4_buf.vbe dp_nmux_x1.ap dp_nmux_x1.vbe dp_nmux_x1_buf.ap dp_nmux_x1_buf.vbe dp_nts_x2.ap dp_nts_x2.vbe dp_nts_x2_buf.ap dp_nts_x2_buf.vbe dp_rom2_buf.ap dp_rom2_buf.vbe dp_rom4_buf.ap dp_rom4_buf.vbe dp_rom4_nxr2_x4.ap dp_rom4_nxr2_x4.vbe dp_rom4_xr2_x4.ap dp_rom4_xr2_x4.vbe dp_sff_scan_x4.ap dp_sff_scan_x4.vbe dp_sff_scan_x4_buf.ap dp_sff_scan_x4_buf.vbe dp_sff_x4.ap dp_sff_x4.vbe dp_sff_x4_buf.ap dp_sff_x4_buf.vbe dp_sxlib.lef dp_ts_x4.ap dp_ts_x4.vbe dp_ts_x4_buf.ap dp_ts_x4_buf.vbe dp_ts_x8.ap dp_ts_x8.vbe dp_ts_x8_buf.ap dp_ts_x8_buf.vbe + +EXTRA_DIST=$(dp_sxlib_DATA) + diff --git a/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4.ap b/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4.ap new file mode 100644 index 00000000..27ebd1a4 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4.ap @@ -0,0 +1,234 @@ +V ALLIANCE : 6 +H dp_dff_scan_x4,P,14/11/2000,10 +A 0,0,1000,500 +R 600,200,ref_ref,nckx +R 750,200,ref_ref,ckx +R 500,200,ref_ref,scanx +R 400,200,ref_ref,nscanx +R 250,200,ref_ref,nwenx +R 150,200,ref_ref,wenx +R 100,300,ref_ref,i_30 +R 100,250,ref_ref,i_25 +R 100,200,ref_ref,i_20 +R 100,150,ref_ref,i_15 +R 100,100,ref_ref,i_10 +R 100,400,ref_ref,i_40 +R 100,350,ref_ref,i_35 +R 900,350,ref_ref,q_35 +R 900,200,ref_ref,q_20 +R 900,300,ref_ref,q_30 +R 900,400,ref_ref,q_40 +R 900,100,ref_ref,q_10 +R 900,150,ref_ref,q_15 +R 900,250,ref_ref,q_25 +S 150,200,750,200,20,*,RIGHT,TALU2 +S 600,150,640,150,20,*,RIGHT,ALU1 +S 600,300,690,300,10,*,RIGHT,ALU1 +S 600,150,600,300,10,*,DOWN,ALU1 +S 600,200,600,200,20,nckx,LEFT,CALU3 +S 740,250,740,350,10,*,DOWN,ALU1 +S 670,350,670,400,10,*,DOWN,ALU1 +S 670,350,740,350,10,*,RIGHT,ALU1 +S 570,50,570,100,20,*,UP,ALU1 +S 160,400,260,400,10,*,LEFT,ALU1 +S 260,150,260,400,10,*,UP,ALU1 +S 310,150,310,300,10,*,UP,ALU1 +S 0,400,1000,400,260,*,RIGHT,NWELL +S 220,30,220,110,30,*,DOWN,NDIF +S 210,100,210,350,10,*,UP,ALU1 +S 330,50,330,100,20,*,DOWN,ALU1 +S 300,90,300,150,10,*,DOWN,POLY +S 250,90,250,150,10,*,DOWN,POLY +S 60,90,60,140,10,*,DOWN,POLY +S 60,140,210,140,10,*,LEFT,POLY +S 60,290,60,340,10,*,DOWN,POLY +S 90,100,120,100,30,*,RIGHT,POLY +S 200,30,200,110,30,*,DOWN,NDIF +S 330,30,330,120,30,*,DOWN,NDIF +S 90,30,90,70,30,*,DOWN,NDIF +S 30,30,30,110,30,*,DOWN,NDIF +S 60,10,60,90,10,*,DOWN,NTRANS +S 250,10,250,90,10,*,DOWN,NTRANS +S 120,10,120,90,10,*,DOWN,NTRANS +S 170,10,170,90,10,*,DOWN,NTRANS +S 300,10,300,90,10,*,DOWN,NTRANS +S 30,200,360,200,10,*,LEFT,POLY +S 150,250,250,250,10,*,RIGHT,POLY +S 60,340,60,470,10,*,UP,PTRANS +S 30,360,30,450,30,*,UP,PDIF +S 90,360,90,450,30,*,UP,PDIF +S 170,340,170,470,10,*,UP,PTRANS +S 120,340,120,470,10,*,UP,PTRANS +S 960,280,960,470,30,*,DOWN,PDIF +S 930,260,930,490,10,*,DOWN,PTRANS +S 810,260,810,490,10,*,DOWN,PTRANS +S 740,280,740,470,30,*,DOWN,PDIF +S 830,280,830,470,30,*,DOWN,PDIF +S 770,260,770,490,10,*,DOWN,PTRANS +S 900,280,900,470,30,*,DOWN,PDIF +S 870,260,870,490,10,*,DOWN,PTRANS +S 330,40,330,120,30,*,DOWN,NDIF +S 740,30,740,120,30,*,DOWN,NDIF +S 930,10,930,140,10,*,UP,NTRANS +S 900,30,900,120,30,*,DOWN,NDIF +S 840,30,840,120,30,*,DOWN,NDIF +S 770,10,770,140,10,*,UP,NTRANS +S 810,10,810,140,10,*,UP,NTRANS +S 870,10,870,140,10,*,UP,NTRANS +S 960,30,960,120,30,*,DOWN,NDIF +S 360,60,360,140,10,*,DOWN,NTRANS +S 600,60,600,140,10,*,UP,NTRANS +S 570,40,570,120,30,*,DOWN,NDIF +S 640,60,640,140,10,*,UP,NTRANS +S 670,80,670,120,30,*,DOWN,NDIF +S 450,80,450,120,50,*,UP,NDIF +S 410,60,410,140,10,*,DOWN,NTRANS +S 540,60,540,140,10,*,DOWN,NTRANS +S 490,60,490,140,10,*,DOWN,NTRANS +S 60,290,210,290,10,*,RIGHT,POLY +S 90,330,120,330,30,*,RIGHT,POLY +S 250,250,250,350,10,*,UP,POLY +S 690,250,770,250,10,*,LEFT,POLY +S 730,140,770,140,10,*,LEFT,POLY +S 930,140,930,260,10,*,DOWN,POLY +S 850,200,930,200,10,*,RIGHT,POLY +S 810,140,810,260,10,*,DOWN,POLY +S 770,250,770,260,10,*,DOWN,POLY +S 870,140,870,260,10,*,DOWN,POLY +S 410,250,490,250,10,*,RIGHT,POLY +S 410,140,410,250,10,*,UP,POLY +S 450,200,600,200,10,*,RIGHT,POLY +S 30,100,30,400,10,*,DOWN,ALU1 +S 160,330,160,400,10,*,DOWN,ALU1 +S 670,100,690,100,20,*,RIGHT,ALU1 +S 740,400,790,400,10,*,RIGHT,ALU1 +S 960,300,960,450,20,*,DOWN,ALU1 +S 960,50,960,100,20,*,DOWN,ALU1 +S 450,100,450,350,10,*,UP,ALU1 +S 500,150,500,400,10,*,UP,ALU1 +S 400,400,500,400,10,*,LEFT,ALU1 +S 790,250,790,400,10,*,DOWN,ALU1 +S 690,250,740,250,10,*,RIGHT,ALU1 +S 690,100,690,250,10,*,DOWN,ALU1 +S 640,200,730,200,10,*,RIGHT,POLY +S 730,140,730,200,10,*,DOWN,POLY +S 690,250,690,300,10,*,UP,POLY +S 690,150,800,150,10,*,RIGHT,ALU1 +S 800,150,800,190,10,*,UP,ALU1 +S 850,100,850,250,10,*,DOWN,ALU1 +S 740,100,850,100,10,*,LEFT,ALU1 +S 790,250,850,250,10,*,RIGHT,ALU1 +S 840,300,840,450,20,*,DOWN,ALU1 +S 150,100,150,250,10,*,UP,ALU1 +S 410,310,410,440,10,*,UP,PTRANS +S 490,310,490,440,10,*,UP,PTRANS +S 540,310,540,440,10,*,UP,PTRANS +S 450,330,450,420,50,*,UP,PDIF +S 360,310,360,440,10,*,UP,PTRANS +S 300,310,300,440,10,*,UP,PTRANS +S 330,330,330,420,30,*,UP,PDIF +S 330,350,330,450,20,*,DOWN,ALU1 +S 330,360,330,420,30,*,UP,PDIF +S 250,310,250,440,10,*,UP,PTRANS +S 360,140,360,310,10,*,DOWN,POLY +S 490,250,490,310,10,*,DOWN,POLY +S 210,330,210,450,50,*,UP,PDIF +S 570,350,570,450,20,*,DOWN,ALU1 +S 640,360,640,490,10,*,DOWN,PTRANS +S 600,360,600,490,10,*,DOWN,PTRANS +S 570,330,570,470,30,*,UP,PDIF +S 670,380,670,470,30,*,DOWN,PDIF +S 600,90,600,360,10,*,DOWN,POLY +S 640,200,640,360,10,*,DOWN,POLY +S 400,300,400,400,10,*,DOWN,ALU1 +S 100,100,100,400,20,i,UP,CALU1 +S 900,100,900,400,20,q,DOWN,CALU1 +S 0,30,1000,30,60,vss,RIGHT,CALU1 +S 0,470,1000,470,60,vdd,RIGHT,CALU1 +S 550,150,550,300,10,scin,UP,CALU1 +S 150,200,150,200,20,wenx,LEFT,CALU3 +S 250,200,250,200,20,nwenx,LEFT,CALU3 +S 400,200,400,200,20,nscanx,LEFT,CALU3 +S 500,200,500,200,20,scanx,LEFT,CALU3 +S 750,200,750,200,20,ckx,LEFT,CALU3 +S 300,250,900,250,20,q,RIGHT,CALU2 +V 600,200,CONT_VIA,* +V 600,200,CONT_VIA2,* +V 150,200,CONT_VIA,* +V 150,200,CONT_VIA2,* +V 670,30,CONT_BODY_P,* +V 570,100,CONT_DIF_N,* +V 570,400,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 260,150,CONT_POLY,* +V 310,150,CONT_POLY,* +V 310,300,CONT_POLY,* +V 310,250,CONT_VIA,* +V 210,100,CONT_DIF_N,* +V 210,150,CONT_POLY,* +V 210,350,CONT_DIF_P,* +V 330,100,CONT_DIF_N,* +V 160,100,CONT_POLY,* +V 100,100,CONT_POLY,* +V 30,200,CONT_POLY,* +V 150,250,CONT_POLY,* +V 90,450,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 840,350,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 740,400,CONT_DIF_P,* +V 570,450,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 90,50,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 330,50,CONT_DIF_N,* +V 960,100,CONT_DIF_N,* +V 960,50,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 740,100,CONT_DIF_N,* +V 570,50,CONT_DIF_N,* +V 450,100,CONT_DIF_N,* +V 330,50,CONT_DIF_N,* +V 670,100,CONT_DIF_N,* +V 510,30,CONT_BODY_P,* +V 390,30,CONT_BODY_P,* +V 450,30,CONT_BODY_P,* +V 210,300,CONT_POLY,* +V 100,330,CONT_POLY,* +V 160,330,CONT_POLY,* +V 550,300,CONT_POLY,* +V 550,150,CONT_POLY,* +V 500,150,CONT_POLY,* +V 850,200,CONT_POLY,* +V 640,150,CONT_POLY,* +V 450,200,CONT_POLY,* +V 900,250,CONT_VIA,* +V 800,200,CONT_POLY,* +V 690,300,CONT_POLY,* +V 750,200,CONT_VIA2,* +V 750,200,CONT_VIA,* +V 740,200,CONT_POLY,* +V 840,300,CONT_DIF_P,* +V 400,200,CONT_VIA2,* +V 400,200,CONT_VIA,* +V 400,200,CONT_POLY,* +V 500,200,CONT_VIA2,* +V 500,200,CONT_VIA,* +V 250,200,CONT_VIA2,* +V 260,200,CONT_VIA,* +V 400,300,CONT_POLY,* +V 450,470,CONT_BODY_N,* +V 510,470,CONT_BODY_N,* +V 390,470,CONT_BODY_N,* +V 330,350,CONT_DIF_P,* +V 330,470,CONT_BODY_N,* +V 570,350,CONT_DIF_P,* +V 670,400,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4.vbe b/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4.vbe new file mode 100644 index 00000000..3b5ea227 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4.vbe @@ -0,0 +1,43 @@ +ENTITY dp_dff_scan_x4 IS +PORT ( + ckx : in BIT; + nckx : in BIT; + wenx : in BIT; + nwenx : in BIT; + scanx : in BIT; + nscanx : in BIT; + i : in BIT; + scin : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_dff_scan_x4; + +ARCHITECTURE vbe OF dp_dff_scan_x4 IS + SIGNAL ff : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on dp_dff_scan_x4" + SEVERITY WARNING; + + ASSERT (ckx xor nckx) + REPORT "wrong values for ckx and nckx in dp_dff_scan_x4" + SEVERITY WARNING; + + ASSERT (wenx xor nwenx) + REPORT "wrong values for wenx and nwenx in dp_dff_scan_x4" + SEVERITY WARNING; + + ASSERT (scanx xor nscanx) + REPORT "wrong values for scanx and nscanx in dp_dff_scan_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1') + BEGIN + ff <= GUARDED ((scanx and scin) or (nscanx and ((wenx and i) or (nwenx and ff)))); + END BLOCK label0; + + q <= ff; +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4_buf.ap new file mode 100644 index 00000000..096dd820 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4_buf.ap @@ -0,0 +1,392 @@ +V ALLIANCE : 6 +H dp_dff_scan_x4_buf,P,14/11/2000,10 +A 0,0,1000,1000 +R 650,400,ref_ref,nckx +R 750,400,ref_ref,ckx +R 500,400,ref_ref,scanx +R 400,400,ref_ref,nscanx +R 250,400,ref_ref,nwenx +R 150,400,ref_ref,wenx +R 950,700,ref_ref,scin +R 900,300,ref_ref,scout +R 900,250,ref_ref,scout +R 900,200,ref_ref,scout +R 900,150,ref_ref,scout +R 900,100,ref_ref,scout +R 900,350,ref_ref,scout +R 900,400,ref_ref,scout +S 150,150,750,150,20,*,RIGHT,TALU2 +S 150,400,750,400,20,*,LEFT,TALU2 +S 150,600,750,600,20,*,RIGHT,TALU2 +S 650,150,650,600,20,nckx,DOWN,CALU3 +S 500,150,500,600,20,scanx,DOWN,CALU3 +S 400,150,400,600,20,nscanx,DOWN,CALU3 +S 250,150,250,600,20,nwenx,DOWN,CALU3 +S 150,150,150,600,20,wenx,DOWN,CALU3 +S 200,850,200,850,10,wen,LEFT,CALU1 +S 450,850,450,850,10,scan,LEFT,CALU1 +S 700,850,700,850,10,ck,LEFT,CALU1 +S 900,100,900,400,20,scout,UP,CALU1 +S 0,470,1000,470,60,vdd,RIGHT,CALU1 +S 0,530,1000,530,60,vdd,RIGHT,CALU1 +S 0,30,1000,30,60,vss,RIGHT,CALU1 +S 0,970,1000,970,60,vss,RIGHT,CALU1 +S 950,700,950,700,10,scin,LEFT,CALU1 +S 140,220,210,220,20,*,RIGHT,ALU1 +S 210,220,290,220,30,*,RIGHT,POLY +S 110,220,170,220,30,*,RIGHT,POLY +S 260,740,260,790,20,*,DOWN,ALU1 +S 140,660,140,900,20,*,UP,ALU1 +S 110,660,170,660,30,*,RIGHT,POLY +S 320,900,320,970,20,*,UP,ALU1 +S 320,50,320,150,20,*,UP,ALU1 +S 80,900,80,970,20,*,DOWN,ALU1 +S 200,50,200,150,20,*,UP,ALU1 +S 80,50,80,150,20,*,UP,ALU1 +S 320,280,320,680,20,*,UP,ALU1 +S 200,900,200,940,20,*,UP,ALU1 +S 140,790,260,790,20,*,RIGHT,ALU1 +S 570,280,570,680,20,*,UP,ALU1 +S 450,50,450,150,20,*,UP,ALU1 +S 570,50,570,150,20,*,UP,ALU1 +S 820,50,820,150,20,*,UP,ALU1 +S 700,50,700,150,20,*,UP,ALU1 +S 390,790,510,790,20,*,RIGHT,ALU1 +S 450,900,450,940,20,*,UP,ALU1 +S 570,900,570,970,20,*,UP,ALU1 +S 700,900,700,940,20,*,UP,ALU1 +S 640,790,760,790,20,*,RIGHT,ALU1 +S 170,190,170,320,10,*,UP,POLY +S 290,190,290,320,10,*,UP,POLY +S 230,190,230,320,10,*,DOWN,POLY +S 170,850,230,850,30,*,RIGHT,POLY +S 230,820,230,860,10,*,DOWN,POLY +S 170,820,170,870,10,*,DOWN,POLY +S 110,190,110,320,10,*,DOWN,POLY +S 360,190,360,320,10,*,DOWN,POLY +S 480,190,480,320,10,*,DOWN,POLY +S 540,190,540,320,10,*,UP,POLY +S 420,190,420,320,10,*,UP,POLY +S 790,190,790,320,10,*,UP,POLY +S 730,190,730,320,10,*,DOWN,POLY +S 610,190,610,320,10,*,DOWN,POLY +S 670,190,670,320,10,*,UP,POLY +S 420,820,420,870,10,*,DOWN,POLY +S 480,820,480,860,10,*,DOWN,POLY +S 420,850,480,850,30,*,RIGHT,POLY +S 670,850,730,850,30,*,RIGHT,POLY +S 730,820,730,860,10,*,DOWN,POLY +S 670,820,670,870,10,*,DOWN,POLY +S 140,30,140,170,30,*,UP,NDIF +S 200,30,200,170,30,*,UP,NDIF +S 110,10,110,190,10,*,UP,NTRANS +S 170,10,170,190,10,*,DOWN,NTRANS +S 320,30,320,170,30,*,UP,NDIF +S 80,30,80,170,30,*,UP,NDIF +S 290,10,290,190,10,*,DOWN,NTRANS +S 260,30,260,170,30,*,UP,NDIF +S 230,10,230,190,10,*,DOWN,NTRANS +S 140,890,140,960,30,*,UP,NDIF +S 200,890,200,960,30,*,UP,NDIF +S 170,870,170,980,10,*,UP,NTRANS +S 570,30,570,170,30,*,UP,NDIF +S 420,10,420,190,10,*,DOWN,NTRANS +S 360,10,360,190,10,*,UP,NTRANS +S 450,30,450,170,30,*,UP,NDIF +S 390,30,390,170,30,*,UP,NDIF +S 480,10,480,190,10,*,DOWN,NTRANS +S 510,30,510,170,30,*,UP,NDIF +S 540,10,540,190,10,*,DOWN,NTRANS +S 820,30,820,170,30,*,UP,NDIF +S 640,30,640,170,30,*,UP,NDIF +S 700,30,700,170,30,*,UP,NDIF +S 610,10,610,190,10,*,UP,NTRANS +S 670,10,670,190,10,*,DOWN,NTRANS +S 790,10,790,190,10,*,DOWN,NTRANS +S 760,30,760,170,30,*,UP,NDIF +S 730,10,730,190,10,*,DOWN,NTRANS +S 450,890,450,960,30,*,UP,NDIF +S 390,890,390,960,30,*,UP,NDIF +S 640,890,640,960,30,*,UP,NDIF +S 700,890,700,960,30,*,UP,NDIF +S 420,870,420,980,10,*,UP,NTRANS +S 670,870,670,980,10,*,UP,NTRANS +S 260,730,260,800,30,*,UP,PDIF +S 80,340,80,630,30,*,UP,PDIF +S 110,320,110,650,10,*,UP,PTRANS +S 200,340,200,630,30,*,UP,PDIF +S 140,340,140,630,30,*,UP,PDIF +S 170,320,170,650,10,*,UP,PTRANS +S 320,340,320,630,30,*,DOWN,PDIF +S 290,320,290,650,10,*,DOWN,PTRANS +S 260,340,260,630,30,*,UP,PDIF +S 230,320,230,650,10,*,UP,PTRANS +S 140,730,140,800,30,*,UP,PDIF +S 170,710,170,820,10,*,DOWN,PTRANS +S 210,730,210,800,30,*,UP,PDIF +S 230,710,230,820,10,*,DOWN,PTRANS +S 570,340,570,630,30,*,DOWN,PDIF +S 420,320,420,650,10,*,UP,PTRANS +S 390,340,390,630,30,*,UP,PDIF +S 450,340,450,630,30,*,UP,PDIF +S 360,320,360,650,10,*,UP,PTRANS +S 0,500,1000,500,460,*,RIGHT,NWELL +S 480,320,480,650,10,*,UP,PTRANS +S 510,340,510,630,30,*,UP,PDIF +S 540,320,540,650,10,*,DOWN,PTRANS +S 700,340,700,630,30,*,UP,PDIF +S 640,340,640,630,30,*,UP,PDIF +S 670,320,670,650,10,*,UP,PTRANS +S 820,340,820,630,30,*,DOWN,PDIF +S 610,320,610,650,10,*,UP,PTRANS +S 790,320,790,650,10,*,DOWN,PTRANS +S 760,340,760,630,30,*,UP,PDIF +S 730,320,730,650,10,*,UP,PTRANS +S 390,730,390,800,30,*,UP,PDIF +S 510,730,510,800,30,*,UP,PDIF +S 640,730,640,800,30,*,UP,PDIF +S 480,710,480,820,10,*,DOWN,PTRANS +S 460,730,460,800,30,*,UP,PDIF +S 420,710,420,820,10,*,DOWN,PTRANS +S 710,730,710,800,30,*,UP,PDIF +S 730,710,730,820,10,*,DOWN,PTRANS +S 760,730,760,800,30,*,UP,PDIF +S 670,710,670,820,10,*,DOWN,PTRANS +S 510,660,510,790,20,*,DOWN,ALU1 +S 760,660,760,790,20,*,DOWN,ALU1 +S 640,740,640,900,20,*,UP,ALU1 +S 390,740,390,900,20,*,UP,ALU1 +S 480,660,540,660,30,*,RIGHT,POLY +S 730,660,790,660,30,*,RIGHT,POLY +S 110,770,830,770,80,*,RIGHT,NWELL +S 440,220,510,220,20,*,RIGHT,ALU1 +S 690,220,760,220,20,*,RIGHT,ALU1 +S 360,220,440,220,30,*,RIGHT,POLY +S 480,220,540,220,30,*,RIGHT,POLY +S 610,220,690,220,30,*,RIGHT,POLY +S 730,220,790,220,30,*,RIGHT,POLY +S 80,290,80,680,20,*,UP,ALU1 +S 510,100,510,400,20,*,UP,ALU1 +S 390,100,390,400,20,*,UP,ALU1 +S 140,100,140,400,20,*,UP,ALU1 +S 260,100,260,400,20,*,UP,ALU1 +S 640,100,640,400,20,*,UP,ALU1 +S 760,100,760,400,20,*,UP,ALU1 +S 700,280,700,740,20,*,DOWN,ALU1 +S 450,290,450,740,20,*,UP,ALU1 +S 200,290,200,740,20,*,DOWN,ALU1 +S 850,820,850,870,10,*,DOWN,POLY +S 820,890,820,960,30,*,UP,NDIF +S 850,710,850,820,10,*,DOWN,PTRANS +S 820,730,820,800,30,*,UP,PDIF +S 820,900,820,950,20,*,UP,ALU1 +S 820,280,820,790,20,*,UP,ALU1 +S 880,730,880,800,30,*,UP,PDIF +S 880,660,880,900,20,*,DOWN,ALU1 +S 850,710,950,710,10,*,RIGHT,POLY +S 850,870,850,940,10,*,UP,NTRANS +S 880,890,880,920,30,*,UP,NDIF +S 870,190,870,320,10,*,DOWN,POLY +S 870,320,870,650,10,*,UP,PTRANS +S 900,30,900,170,30,*,UP,NDIF +S 870,10,870,190,10,*,DOWN,NTRANS +S 900,340,900,630,30,*,UP,PDIF +S 840,30,840,170,30,*,UP,NDIF +S 840,340,840,630,30,*,DOWN,PDIF +S 750,150,750,600,20,ckx,DOWN,CALU3 +V 950,700,CONT_POLY,* +V 210,220,CONT_POLY,* +V 140,660,CONT_POLY,* +V 150,400,CONT_VIA2,* +V 150,600,CONT_VIA2,* +V 250,600,CONT_VIA2,* +V 150,150,CONT_VIA2,* +V 250,400,CONT_VIA2,* +V 500,400,CONT_VIA2,* +V 400,150,CONT_VIA2,* +V 500,600,CONT_VIA2,* +V 400,600,CONT_VIA2,* +V 400,400,CONT_VIA2,* +V 750,600,CONT_VIA2,* +V 650,150,CONT_VIA2,* +V 750,400,CONT_VIA2,* +V 650,400,CONT_VIA2,* +V 650,600,CONT_VIA2,* +V 150,150,CONT_VIA,* +V 150,400,CONT_VIA,* +V 150,600,CONT_VIA,* +V 250,600,CONT_VIA,* +V 250,400,CONT_VIA,* +V 400,150,CONT_VIA,* +V 500,400,CONT_VIA,* +V 500,600,CONT_VIA,* +V 400,600,CONT_VIA,* +V 400,400,CONT_VIA,* +V 650,150,CONT_VIA,* +V 650,600,CONT_VIA,* +V 750,600,CONT_VIA,* +V 750,400,CONT_VIA,* +V 650,400,CONT_VIA,* +V 200,850,CONT_POLY,* +V 450,850,CONT_POLY,* +V 700,850,CONT_POLY,* +V 570,970,CONT_BODY_P,* +V 320,970,CONT_BODY_P,* +V 80,970,CONT_BODY_P,* +V 320,900,CONT_BODY_P,* +V 80,900,CONT_BODY_P,* +V 570,900,CONT_BODY_P,* +V 320,100,CONT_DIF_N,* +V 260,100,CONT_DIF_N,* +V 320,50,CONT_DIF_N,* +V 320,150,CONT_DIF_N,* +V 260,150,CONT_DIF_N,* +V 80,50,CONT_DIF_N,* +V 80,150,CONT_DIF_N,* +V 80,100,CONT_DIF_N,* +V 200,100,CONT_DIF_N,* +V 200,50,CONT_DIF_N,* +V 200,150,CONT_DIF_N,* +V 140,900,CONT_DIF_N,* +V 140,150,CONT_DIF_N,* +V 140,100,CONT_DIF_N,* +V 200,900,CONT_DIF_N,* +V 200,950,CONT_DIF_N,* +V 570,50,CONT_DIF_N,* +V 510,100,CONT_DIF_N,* +V 570,100,CONT_DIF_N,* +V 390,100,CONT_DIF_N,* +V 390,150,CONT_DIF_N,* +V 450,150,CONT_DIF_N,* +V 450,50,CONT_DIF_N,* +V 450,100,CONT_DIF_N,* +V 510,150,CONT_DIF_N,* +V 570,150,CONT_DIF_N,* +V 760,100,CONT_DIF_N,* +V 820,50,CONT_DIF_N,* +V 640,150,CONT_DIF_N,* +V 640,100,CONT_DIF_N,* +V 820,100,CONT_DIF_N,* +V 820,150,CONT_DIF_N,* +V 760,150,CONT_DIF_N,* +V 700,100,CONT_DIF_N,* +V 700,50,CONT_DIF_N,* +V 700,150,CONT_DIF_N,* +V 700,900,CONT_DIF_N,* +V 700,950,CONT_DIF_N,* +V 450,950,CONT_DIF_N,* +V 450,900,CONT_DIF_N,* +V 390,900,CONT_DIF_N,* +V 640,900,CONT_DIF_N,* +V 140,790,CONT_DIF_P,* +V 200,740,CONT_DIF_P,* +V 140,740,CONT_DIF_P,* +V 200,290,CONT_BODY_N,* +V 80,290,CONT_BODY_N,* +V 320,290,CONT_BODY_N,* +V 80,600,CONT_DIF_P,* +V 80,350,CONT_DIF_P,* +V 80,550,CONT_DIF_P,* +V 80,500,CONT_DIF_P,* +V 80,450,CONT_DIF_P,* +V 80,400,CONT_DIF_P,* +V 200,350,CONT_DIF_P,* +V 200,450,CONT_DIF_P,* +V 200,550,CONT_DIF_P,* +V 200,400,CONT_DIF_P,* +V 200,500,CONT_DIF_P,* +V 320,400,CONT_DIF_P,* +V 320,350,CONT_DIF_P,* +V 320,450,CONT_DIF_P,* +V 320,500,CONT_DIF_P,* +V 320,550,CONT_DIF_P,* +V 320,600,CONT_DIF_P,* +V 260,400,CONT_DIF_P,* +V 260,350,CONT_DIF_P,* +V 140,350,CONT_DIF_P,* +V 140,400,CONT_DIF_P,* +V 140,600,CONT_DIF_P,* +V 260,600,CONT_DIF_P,* +V 260,790,CONT_DIF_P,* +V 260,740,CONT_DIF_P,* +V 200,680,CONT_BODY_N,* +V 320,680,CONT_BODY_N,* +V 80,680,CONT_BODY_N,* +V 450,550,CONT_DIF_P,* +V 450,450,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 570,290,CONT_BODY_N,* +V 450,290,CONT_BODY_N,* +V 570,600,CONT_DIF_P,* +V 570,550,CONT_DIF_P,* +V 570,500,CONT_DIF_P,* +V 570,450,CONT_DIF_P,* +V 570,350,CONT_DIF_P,* +V 570,400,CONT_DIF_P,* +V 450,500,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 570,680,CONT_BODY_N,* +V 450,680,CONT_BODY_N,* +V 510,600,CONT_DIF_P,* +V 390,600,CONT_DIF_P,* +V 390,400,CONT_DIF_P,* +V 390,350,CONT_DIF_P,* +V 510,350,CONT_DIF_P,* +V 510,400,CONT_DIF_P,* +V 700,350,CONT_DIF_P,* +V 700,450,CONT_DIF_P,* +V 700,550,CONT_DIF_P,* +V 820,500,CONT_DIF_P,* +V 820,550,CONT_DIF_P,* +V 820,600,CONT_DIF_P,* +V 700,290,CONT_BODY_N,* +V 820,290,CONT_BODY_N,* +V 760,600,CONT_DIF_P,* +V 700,680,CONT_BODY_N,* +V 820,680,CONT_BODY_N,* +V 700,400,CONT_DIF_P,* +V 700,500,CONT_DIF_P,* +V 820,400,CONT_DIF_P,* +V 820,350,CONT_DIF_P,* +V 820,450,CONT_DIF_P,* +V 390,790,CONT_DIF_P,* +V 760,400,CONT_DIF_P,* +V 760,350,CONT_DIF_P,* +V 640,350,CONT_DIF_P,* +V 640,400,CONT_DIF_P,* +V 640,600,CONT_DIF_P,* +V 510,740,CONT_DIF_P,* +V 510,790,CONT_DIF_P,* +V 390,740,CONT_DIF_P,* +V 450,740,CONT_DIF_P,* +V 700,740,CONT_DIF_P,* +V 640,740,CONT_DIF_P,* +V 760,790,CONT_DIF_P,* +V 760,740,CONT_DIF_P,* +V 640,790,CONT_DIF_P,* +V 510,660,CONT_POLY,* +V 760,660,CONT_POLY,* +V 700,600,CONT_DIF_P,* +V 450,600,CONT_DIF_P,* +V 200,600,CONT_DIF_P,* +V 440,220,CONT_POLY,* +V 690,220,CONT_POLY,* +V 750,150,CONT_VIA2,* +V 750,150,CONT_VIA,* +V 500,150,CONT_VIA2,* +V 500,150,CONT_VIA,* +V 250,150,CONT_VIA2,* +V 250,150,CONT_VIA,* +V 880,900,CONT_DIF_N,* +V 820,900,CONT_DIF_N,* +V 820,790,CONT_DIF_P,* +V 880,740,CONT_DIF_P,* +V 820,740,CONT_DIF_P,* +V 820,950,CONT_DIF_N,* +V 880,660,CONT_POLY,* +V 880,790,CONT_DIF_P,* +V 900,150,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 900,400,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4_buf.vbe new file mode 100644 index 00000000..4c54ffef --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_dff_scan_x4_buf.vbe @@ -0,0 +1,33 @@ +ENTITY dp_dff_scan_x4_buf IS +PORT ( + ck : in BIT; + wen : in BIT; + scan : in BIT; + scin : in BIT; + ckx : out BIT; + nckx : out BIT; + wenx : out BIT; + nwenx : out BIT; + scanx : out BIT; + nscanx : out BIT; + scout : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_dff_scan_x4_buf; + +ARCHITECTURE vbe OF dp_dff_scan_x4_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on dp_dff_scan_x4_buf" + SEVERITY WARNING; + + ckx <= ck; + nckx <= not ck; + wenx <= wen; + nwenx <= not wen; + scanx <= scan; + nscanx <= not scan; + scout <= scin; +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_dff_x4.ap b/alliance/src/cells/src/dp_sxlib/dp_dff_x4.ap new file mode 100644 index 00000000..bb6f7200 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_dff_x4.ap @@ -0,0 +1,170 @@ +V ALLIANCE : 6 +H dp_dff_x4,P,26/ 9/2000,100 +A 0,0,7000,5000 +R 3000,2000,ref_ref,nckx +R 500,4000,ref_ref,i_40 +R 500,1000,ref_ref,i_10 +R 500,1500,ref_ref,i_15 +R 500,2000,ref_ref,i_20 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 6000,1500,ref_ref,q_15 +R 6000,1000,ref_ref,q_10 +R 6000,4000,ref_ref,q_40 +R 6000,3000,ref_ref,q_30 +R 6000,2000,ref_ref,q_20 +R 6000,3500,ref_ref,q_35 +R 500,2500,ref_ref,i_25 +R 6000,2500,ref_ref,q_25 +R 1000,2000,ref_ref,wenx +R 2000,2000,ref_ref,nwenx +R 4500,2000,ref_ref,ckx +S 3000,1500,3400,1500,200,*,RIGHT,ALU1 +S 3000,3000,3900,3000,200,*,RIGHT,ALU1 +S 3000,1500,3000,3000,100,*,DOWN,ALU1 +S 3000,2000,3000,2000,200,nckx,LEFT,CALU3 +S 4400,2500,4400,3500,100,*,DOWN,ALU1 +S 3700,3500,3700,4000,100,*,DOWN,ALU1 +S 3700,3500,4400,3500,100,*,RIGHT,ALU1 +S 300,3300,300,4600,300,*,UP,PDIF +S 5100,2600,5100,4900,100,*,DOWN,PTRANS +S 6300,2600,6300,4900,100,*,DOWN,PTRANS +S 6600,2800,6600,4700,300,*,DOWN,PDIF +S 0,4000,7000,4000,2600,*,RIGHT,NWELL +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 1100,3100,1100,4400,100,*,UP,PTRANS +S 5700,2600,5700,4900,100,*,DOWN,PTRANS +S 6000,2800,6000,4700,300,*,DOWN,PDIF +S 4700,2600,4700,4900,100,*,DOWN,PTRANS +S 5300,2800,5300,4700,300,*,DOWN,PDIF +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 3700,3800,3700,4700,300,*,DOWN,PDIF +S 2700,3300,2700,4700,300,*,UP,PDIF +S 3000,3600,3000,4900,100,*,DOWN,PTRANS +S 3400,3600,3400,4900,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,500,*,UP,PDIF +S 4700,100,4700,1400,100,*,UP,NTRANS +S 6300,100,6300,1400,100,*,UP,NTRANS +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 1100,600,1100,1400,100,*,DOWN,NTRANS +S 3400,600,3400,1400,100,*,UP,NTRANS +S 3000,600,3000,1400,100,*,UP,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 5700,100,5700,1400,100,*,UP,NTRANS +S 5100,100,5100,1400,100,*,UP,NTRANS +S 4400,300,4400,1200,300,*,DOWN,NDIF +S 300,400,300,1200,300,*,DOWN,NDIF +S 300,300,300,1200,300,*,DOWN,NDIF +S 5400,300,5400,1200,300,*,DOWN,NDIF +S 6000,300,6000,1200,300,*,DOWN,NDIF +S 2700,400,2700,1200,300,*,DOWN,NDIF +S 6600,300,6600,1200,300,*,DOWN,NDIF +S 1500,800,1500,1200,500,*,UP,NDIF +S 3700,800,3700,1200,300,*,DOWN,NDIF +S 5700,1400,5700,2600,100,*,DOWN,POLY +S 4700,2500,4700,2600,100,*,DOWN,POLY +S 5100,1400,5100,2600,100,*,DOWN,POLY +S 5500,2000,6300,2000,100,*,RIGHT,POLY +S 6300,1400,6300,2600,100,*,DOWN,POLY +S 4300,1400,4700,1400,100,*,LEFT,POLY +S 3900,2500,4700,2500,100,*,LEFT,POLY +S 3900,2500,3900,3000,100,*,UP,POLY +S 4300,1400,4300,2000,100,*,DOWN,POLY +S 3400,2000,4300,2000,100,*,RIGHT,POLY +S 1500,2000,3000,2000,100,*,RIGHT,POLY +S 1100,1400,1100,2500,100,*,UP,POLY +S 1100,2500,1900,2500,100,*,RIGHT,POLY +S 3400,2000,3400,3600,100,*,DOWN,POLY +S 3000,900,3000,3600,100,*,DOWN,POLY +S 1900,2500,1900,3100,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2700,500,2700,1000,200,*,UP,ALU1 +S 1000,4000,2000,4000,100,*,LEFT,ALU1 +S 2000,1500,2000,4000,100,*,UP,ALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 6600,500,6600,1000,200,*,DOWN,ALU1 +S 6600,3000,6600,4500,200,*,DOWN,ALU1 +S 4400,4000,4900,4000,100,*,RIGHT,ALU1 +S 3700,1000,3900,1000,200,*,RIGHT,ALU1 +S 3900,1500,5000,1500,100,*,RIGHT,ALU1 +S 3900,1000,3900,2500,100,*,DOWN,ALU1 +S 3900,2500,4400,2500,100,*,RIGHT,ALU1 +S 4900,2500,4900,4000,100,*,DOWN,ALU1 +S 1000,3000,1000,4000,100,*,DOWN,ALU1 +S 2700,3500,2700,4500,200,*,DOWN,ALU1 +S 5400,3000,5400,4500,200,*,DOWN,ALU1 +S 4900,2500,5500,2500,100,*,RIGHT,ALU1 +S 4400,1000,5500,1000,100,*,LEFT,ALU1 +S 5500,1000,5500,2500,100,*,DOWN,ALU1 +S 5000,1500,5000,1900,100,*,UP,ALU1 +S 1000,2000,4500,2000,200,*,RIGHT,TALU2 +S 0,300,7000,300,600,vss,RIGHT,CALU1 +S 0,4700,7000,4700,600,vdd,RIGHT,CALU1 +S 500,1000,500,4000,200,i,UP,CALU1 +S 6000,1000,6000,4000,200,q,DOWN,CALU1 +S 2500,2500,6000,2500,200,q,RIGHT,CALU2 +S 1000,2000,1000,2000,200,wenx,LEFT,CALU3 +S 2000,2000,2000,2000,200,nwenx,LEFT,CALU3 +S 4500,2000,4500,2000,200,ckx,LEFT,CALU3 +V 3000,2000,CONT_VIA,* +V 3000,2000,CONT_VIA2,* +V 5400,4000,CONT_DIF_P,* +V 5400,4500,CONT_DIF_P,* +V 6600,4500,CONT_DIF_P,* +V 6600,3000,CONT_DIF_P,* +V 5400,3500,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 2100,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 5400,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 6600,3500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 6000,3000,CONT_DIF_P,* +V 6600,4000,CONT_DIF_P,* +V 2700,500,CONT_DIF_N,* +V 4400,1000,CONT_DIF_N,* +V 6000,1000,CONT_DIF_N,* +V 5400,500,CONT_DIF_N,* +V 6600,500,CONT_DIF_N,* +V 6600,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 1500,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 3700,300,CONT_BODY_P,* +V 500,3000,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 3900,3000,CONT_POLY,* +V 5000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3400,1500,CONT_POLY,* +V 5500,2000,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 4400,2000,CONT_POLY,* +V 4500,2000,CONT_VIA,* +V 6000,2500,CONT_VIA,* +V 2000,2000,CONT_VIA,* +V 1000,2000,CONT_VIA,* +V 2500,2500,CONT_VIA,* +V 2000,2000,CONT_VIA2,* +V 1000,2000,CONT_VIA2,* +V 4500,2000,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_dff_x4.vbe b/alliance/src/cells/src/dp_sxlib/dp_dff_x4.vbe new file mode 100644 index 00000000..8a10f8e4 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_dff_x4.vbe @@ -0,0 +1,36 @@ +ENTITY dp_dff_x4 IS +PORT ( + ckx : in BIT; + nckx : in BIT; + wenx : in BIT; + nwenx : in BIT; + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_dff_x4; + +ARCHITECTURE vbe OF dp_dff_x4 IS + SIGNAL ff : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on dp_dff_x4" + SEVERITY WARNING; + + ASSERT (ckx xor nckx) + REPORT "wrong values for ckx and nckx in dp_dff_x4" + SEVERITY WARNING; + + ASSERT (wenx xor nwenx) + REPORT "wrong values for wenx and nwenx in dp_dff_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1') + BEGIN + ff <= GUARDED ((wenx and i) or (nwenx and ff)); + END BLOCK label0; + + q <= ff; +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_dff_x4_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_dff_x4_buf.ap new file mode 100644 index 00000000..2636e48c --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_dff_x4_buf.ap @@ -0,0 +1,252 @@ +V ALLIANCE : 6 +H dp_dff_x4_buf,P,14/11/2000,10 +A 0,0,700,1000 +R 100,400,ref_ref,wenx +R 200,400,ref_ref,nwenx +R 350,400,ref_ref,nckx +R 450,400,ref_ref,ckx +S 100,600,450,600,20,*,RIGHT,TALU2 +S 100,400,450,400,20,*,LEFT,TALU2 +S 100,150,450,150,20,*,RIGHT,TALU2 +S 450,150,460,150,20,*,RIGHT,ALU1 +S 150,220,240,220,30,*,RIGHT,POLY +S 100,220,160,220,20,*,RIGHT,ALU1 +S 60,220,120,220,30,*,RIGHT,POLY +S 90,660,90,900,20,*,UP,ALU1 +S 210,740,210,790,20,*,DOWN,ALU1 +S 60,660,120,660,30,*,RIGHT,POLY +S 0,500,700,500,460,*,RIGHT,NWELL +S 70,770,480,770,80,*,RIGHT,NWELL +S 90,340,90,630,30,*,UP,PDIF +S 120,320,120,650,10,*,UP,PTRANS +S 270,340,270,630,30,*,DOWN,PDIF +S 30,340,30,630,30,*,UP,PDIF +S 210,730,210,800,30,*,UP,PDIF +S 60,320,60,650,10,*,UP,PTRANS +S 180,710,180,820,10,*,DOWN,PTRANS +S 160,730,160,800,30,*,UP,PDIF +S 120,710,120,820,10,*,DOWN,PTRANS +S 90,730,90,800,30,*,UP,PDIF +S 180,320,180,650,10,*,UP,PTRANS +S 210,340,210,630,30,*,UP,PDIF +S 240,320,240,650,10,*,DOWN,PTRANS +S 310,320,310,650,10,*,UP,PTRANS +S 400,340,400,630,30,*,UP,PDIF +S 340,340,340,630,30,*,UP,PDIF +S 370,320,370,650,10,*,UP,PTRANS +S 520,340,520,630,30,*,DOWN,PDIF +S 490,320,490,650,10,*,DOWN,PTRANS +S 460,340,460,630,30,*,UP,PDIF +S 430,320,430,650,10,*,UP,PTRANS +S 340,730,340,800,30,*,UP,PDIF +S 460,730,460,800,30,*,UP,PDIF +S 370,710,370,820,10,*,DOWN,PTRANS +S 410,730,410,800,30,*,UP,PDIF +S 430,710,430,820,10,*,DOWN,PTRANS +S 150,340,150,630,30,*,UP,PDIF +S 60,10,60,190,10,*,UP,NTRANS +S 120,10,120,190,10,*,DOWN,NTRANS +S 150,30,150,170,30,*,UP,NDIF +S 180,10,180,190,10,*,DOWN,NTRANS +S 210,30,210,170,30,*,UP,NDIF +S 240,10,240,190,10,*,DOWN,NTRANS +S 30,30,30,170,30,*,UP,NDIF +S 270,30,270,170,30,*,UP,NDIF +S 90,30,90,170,30,*,UP,NDIF +S 150,890,150,960,30,*,UP,NDIF +S 90,890,90,960,30,*,UP,NDIF +S 120,870,120,980,10,*,UP,NTRANS +S 310,10,310,190,10,*,UP,NTRANS +S 370,10,370,190,10,*,DOWN,NTRANS +S 520,30,520,170,30,*,UP,NDIF +S 430,10,430,190,10,*,DOWN,NTRANS +S 400,30,400,170,30,*,UP,NDIF +S 340,30,340,170,30,*,UP,NDIF +S 490,10,490,190,10,*,DOWN,NTRANS +S 460,30,460,170,30,*,UP,NDIF +S 340,890,340,960,30,*,UP,NDIF +S 400,890,400,960,30,*,UP,NDIF +S 370,870,370,980,10,*,UP,NTRANS +S 490,190,490,320,10,*,UP,POLY +S 120,820,120,870,10,*,DOWN,POLY +S 430,190,430,320,10,*,DOWN,POLY +S 60,190,60,320,10,*,DOWN,POLY +S 370,190,370,320,10,*,UP,POLY +S 120,190,120,320,10,*,UP,POLY +S 370,820,370,870,10,*,DOWN,POLY +S 370,850,430,850,30,*,RIGHT,POLY +S 430,820,430,860,10,*,DOWN,POLY +S 180,820,180,860,10,*,DOWN,POLY +S 120,850,180,850,30,*,RIGHT,POLY +S 310,190,310,320,10,*,DOWN,POLY +S 180,190,180,320,10,*,DOWN,POLY +S 240,190,240,320,10,*,UP,POLY +S 430,660,490,660,30,*,RIGHT,POLY +S 430,220,490,220,30,*,RIGHT,POLY +S 310,220,390,220,30,*,RIGHT,POLY +S 400,280,400,740,20,*,UP,ALU1 +S 30,50,30,150,20,*,UP,ALU1 +S 210,100,210,400,20,*,UP,ALU1 +S 30,350,30,680,20,*,UP,ALU1 +S 270,280,270,680,20,*,UP,ALU1 +S 270,50,270,150,20,*,UP,ALU1 +S 150,900,150,940,20,*,UP,ALU1 +S 90,790,210,790,20,*,RIGHT,ALU1 +S 340,100,340,400,20,*,UP,ALU1 +S 150,50,150,150,20,*,UP,ALU1 +S 150,280,150,740,20,*,UP,ALU1 +S 30,900,30,970,20,*,DOWN,ALU1 +S 520,50,520,150,20,*,UP,ALU1 +S 400,50,400,150,20,*,UP,ALU1 +S 520,280,520,680,20,*,UP,ALU1 +S 460,100,460,400,20,*,UP,ALU1 +S 90,100,90,400,20,*,UP,ALU1 +S 460,660,460,790,20,*,DOWN,ALU1 +S 340,740,340,900,20,*,UP,ALU1 +S 520,900,520,970,20,*,UP,ALU1 +S 400,900,400,940,20,*,UP,ALU1 +S 340,790,460,790,20,*,RIGHT,ALU1 +S 270,900,270,970,20,*,UP,ALU1 +S 390,220,460,220,20,*,RIGHT,ALU1 +S 600,50,600,150,20,*,UP,ALU1 +S 0,970,700,970,60,vss,RIGHT,CALU1 +S 0,30,700,30,60,vss,RIGHT,CALU1 +S 0,530,700,530,60,vdd,RIGHT,CALU1 +S 0,470,700,470,60,vdd,RIGHT,CALU1 +S 150,850,150,850,10,wen,LEFT,CALU1 +S 400,850,400,850,10,ck,LEFT,CALU1 +S 100,150,100,600,20,wenx,DOWN,CALU3 +S 200,150,200,600,20,nwenx,DOWN,CALU3 +S 350,150,350,600,20,nckx,DOWN,CALU3 +S 450,150,450,600,20,ckx,DOWN,CALU3 +S 200,150,210,150,20,*,RIGHT,ALU1 +V 450,150,CONT_VIA,* +V 450,150,CONT_VIA2,* +V 160,220,CONT_POLY,* +V 90,660,CONT_POLY,* +V 90,790,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 270,290,CONT_BODY_N,* +V 30,290,CONT_BODY_N,* +V 150,290,CONT_BODY_N,* +V 90,740,CONT_DIF_P,* +V 150,740,CONT_DIF_P,* +V 150,500,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,550,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,500,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 270,600,CONT_DIF_P,* +V 270,550,CONT_DIF_P,* +V 270,500,CONT_DIF_P,* +V 270,450,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 270,680,CONT_BODY_N,* +V 150,680,CONT_BODY_N,* +V 210,740,CONT_DIF_P,* +V 210,790,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 400,550,CONT_DIF_P,* +V 30,680,CONT_BODY_N,* +V 520,600,CONT_DIF_P,* +V 400,290,CONT_BODY_N,* +V 520,290,CONT_BODY_N,* +V 400,350,CONT_DIF_P,* +V 400,450,CONT_DIF_P,* +V 520,680,CONT_BODY_N,* +V 400,400,CONT_DIF_P,* +V 400,500,CONT_DIF_P,* +V 520,400,CONT_DIF_P,* +V 520,350,CONT_DIF_P,* +V 520,450,CONT_DIF_P,* +V 520,500,CONT_DIF_P,* +V 520,550,CONT_DIF_P,* +V 460,400,CONT_DIF_P,* +V 460,350,CONT_DIF_P,* +V 340,350,CONT_DIF_P,* +V 340,400,CONT_DIF_P,* +V 340,600,CONT_DIF_P,* +V 400,600,CONT_DIF_P,* +V 460,600,CONT_DIF_P,* +V 400,680,CONT_BODY_N,* +V 340,790,CONT_DIF_P,* +V 400,740,CONT_DIF_P,* +V 340,740,CONT_DIF_P,* +V 460,790,CONT_DIF_P,* +V 460,740,CONT_DIF_P,* +V 150,600,CONT_DIF_P,* +V 30,50,CONT_DIF_N,* +V 210,150,CONT_DIF_N,* +V 270,150,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 90,900,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,150,CONT_DIF_N,* +V 150,900,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 520,100,CONT_DIF_N,* +V 460,100,CONT_DIF_N,* +V 520,50,CONT_DIF_N,* +V 150,950,CONT_DIF_N,* +V 400,50,CONT_DIF_N,* +V 340,150,CONT_DIF_N,* +V 400,150,CONT_DIF_N,* +V 340,100,CONT_DIF_N,* +V 520,150,CONT_DIF_N,* +V 460,150,CONT_DIF_N,* +V 400,100,CONT_DIF_N,* +V 400,900,CONT_DIF_N,* +V 400,950,CONT_DIF_N,* +V 340,900,CONT_DIF_N,* +V 520,970,CONT_BODY_P,* +V 270,970,CONT_BODY_P,* +V 30,900,CONT_BODY_P,* +V 270,900,CONT_BODY_P,* +V 520,900,CONT_BODY_P,* +V 30,970,CONT_BODY_P,* +V 400,850,CONT_POLY,* +V 150,850,CONT_POLY,* +V 460,660,CONT_POLY,* +V 390,220,CONT_POLY,* +V 200,400,CONT_VIA,* +V 200,600,CONT_VIA,* +V 100,600,CONT_VIA,* +V 100,400,CONT_VIA,* +V 100,150,CONT_VIA,* +V 350,400,CONT_VIA,* +V 350,600,CONT_VIA,* +V 350,150,CONT_VIA,* +V 450,600,CONT_VIA,* +V 450,400,CONT_VIA,* +V 450,600,CONT_VIA2,* +V 350,150,CONT_VIA2,* +V 350,600,CONT_VIA2,* +V 100,150,CONT_VIA2,* +V 100,400,CONT_VIA2,* +V 200,400,CONT_VIA2,* +V 450,400,CONT_VIA2,* +V 350,400,CONT_VIA2,* +V 100,600,CONT_VIA2,* +V 200,600,CONT_VIA2,* +V 600,50,CONT_BODY_P,* +V 600,150,CONT_BODY_P,* +V 200,150,CONT_VIA2,* +V 200,150,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_dff_x4_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_dff_x4_buf.vbe new file mode 100644 index 00000000..150e050f --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_dff_x4_buf.vbe @@ -0,0 +1,25 @@ +ENTITY dp_dff_x4_buf IS +PORT ( + ck : in BIT; + wen : in BIT; + ckx : out BIT; + nckx : out BIT; + wenx : out BIT; + nwenx : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_dff_x4_buf; + +ARCHITECTURE vbe OF dp_dff_x4_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on dp_dff_x4_buf" + SEVERITY WARNING; + + ckx <= ck; + nckx <= not ck; + wenx <= wen; + nwenx <= not wen; +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_mux_x2.ap b/alliance/src/cells/src/dp_sxlib/dp_mux_x2.ap new file mode 100644 index 00000000..a97864eb --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_mux_x2.ap @@ -0,0 +1,109 @@ +V ALLIANCE : 6 +H dp_mux_x2,P,10/11/2000,100 +A 0,0,4000,5000 +R 500,4000,ref_ref,q_40 +R 500,3500,ref_ref,q_35 +R 500,3000,ref_ref,q_30 +R 500,2500,ref_ref,q_25 +R 500,1500,ref_ref,q_15 +R 500,1000,ref_ref,q_10 +R 500,2000,ref_ref,q_20 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 3500,1500,ref_ref,i0_15 +R 3500,2000,ref_ref,i0_20 +R 3500,3500,ref_ref,i0_35 +R 3500,3000,ref_ref,i0_30 +R 3500,1000,ref_ref,i0_10 +R 1500,1000,ref_ref,i1_10 +R 1500,4000,ref_ref,i1_40 +R 1500,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i1_30 +R 3500,2500,ref_ref,i0_25 +R 3000,2000,ref_ref,sel0 +R 2000,2000,ref_ref,sel1 +S 3300,3000,3500,3000,100,*,RIGHT,POLY +S 3300,3000,3300,3100,100,*,DOWN,POLY +S 2900,2000,2900,3100,100,*,DOWN,POLY +S 3600,3300,3600,4200,300,*,UP,PDIF +S 2900,3100,2900,4400,100,*,UP,PTRANS +S 3300,3100,3300,4400,100,*,UP,PTRANS +S 2500,3500,2600,3500,100,*,LEFT,ALU1 +S 3000,1500,3000,4000,100,*,UP,ALU1 +S 2000,4000,3000,4000,100,*,RIGHT,ALU1 +S 2500,3300,2500,4200,500,*,UP,PDIF +S 1700,2900,1700,3100,100,*,DOWN,POLY +S 1700,3100,1700,4400,100,*,UP,PTRANS +S 2100,3100,2100,4400,100,*,UP,PTRANS +S 1500,1000,1500,4000,200,i1,UP,CALU1 +S 2000,2000,2000,2000,200,sel1,LEFT,CALU3 +S 3000,2000,3000,2000,200,sel0,LEFT,CALU3 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 1000,500,1000,1700,200,*,UP,ALU1 +S 1000,3000,1000,4500,200,*,DOWN,ALU1 +S 2100,900,2100,2000,100,*,UP,POLY +S 1400,1400,1700,1400,100,*,RIGHT,POLY +S 700,1400,700,2600,100,*,UP,POLY +S 1700,900,1700,1400,100,*,UP,POLY +S 2100,2000,2900,2000,100,*,RIGHT,POLY +S 1200,300,1200,1200,700,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 400,300,400,1200,300,*,UP,NDIF +S 1700,100,1700,900,100,*,DOWN,NTRANS +S 2100,100,2100,900,100,*,DOWN,NTRANS +S 3600,300,3600,700,300,*,DOWN,NDIF +S 2900,100,2900,900,100,*,DOWN,NTRANS +S 3300,100,3300,900,100,*,DOWN,NTRANS +S 2500,300,2500,700,500,*,UP,NDIF +S 400,2800,400,4700,300,*,DOWN,PDIF +S 1000,2800,1000,3300,300,*,UP,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 2500,300,2500,1100,300,*,UP,NDIF +S 3300,900,3500,900,100,*,LEFT,POLY +S 2900,900,2900,1600,100,*,DOWN,POLY +S 2000,2000,3000,2000,200,*,RIGHT,TALU2 +S 0,4000,4000,4000,2600,*,RIGHT,NWELL +S 500,1000,500,4000,200,q,UP,CALU1 +S 700,2400,2500,2400,100,*,RIGHT,POLY +S 1500,2900,1700,2900,100,*,LEFT,POLY +S 1200,3200,1200,4700,700,*,DOWN,PDIF +S 3500,1000,3500,3500,200,i0,UP,CALU1 +S 3600,4000,3600,4700,200,*,DOWN,ALU1 +S 2500,1000,2500,2500,100,*,UP,ALU1 +S 2000,3000,2100,3000,100,*,RIGHT,ALU1 +S 2100,3000,2100,3200,100,*,DOWN,POLY +S 2000,3000,2000,4000,100,*,UP,ALU1 +S 2500,2500,2600,2500,100,*,RIGHT,ALU1 +S 2600,2500,2600,3500,100,*,UP,ALU1 +V 2000,4700,CONT_BODY_N,* +V 3500,3000,CONT_POLY,* +V 3700,4700,CONT_BODY_N,* +V 400,4000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +V 400,1000,CONT_DIF_N,* +V 3000,2000,CONT_VIA2,* +V 2000,2000,CONT_VIA2,* +V 2000,2000,CONT_VIA,* +V 3000,2000,CONT_VIA,* +V 1500,1500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 1000,1700,CONT_BODY_P,* +V 3600,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 1000,500,CONT_DIF_N,* +V 1000,4000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 1000,4500,CONT_DIF_P,* +V 2500,1000,CONT_DIF_N,* +V 3000,1500,CONT_POLY,* +V 3500,1000,CONT_POLY,* +V 2500,2400,CONT_POLY,* +V 1500,2900,CONT_POLY,* +V 3600,4000,CONT_DIF_P,* +V 2500,3500,CONT_DIF_P,* +V 2100,3000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_mux_x2.vbe b/alliance/src/cells/src/dp_sxlib/dp_mux_x2.vbe new file mode 100644 index 00000000..9e9d29c4 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_mux_x2.vbe @@ -0,0 +1,26 @@ +ENTITY dp_mux_x2 IS +PORT ( + sel0 : in BIT; + sel1 : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_mux_x2; + +ARCHITECTURE vbe OF dp_mux_x2 IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_mux_x2" + SEVERITY WARNING; + + ASSERT (sel0 xor sel1) + REPORT "wrong control signals on dp_mux_x2" + SEVERITY WARNING; + + q <= (sel0 and i0) or (sel1 and i1); + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_mux_x2_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_mux_x2_buf.ap new file mode 100644 index 00000000..8252b3ad --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_mux_x2_buf.ap @@ -0,0 +1,141 @@ +V ALLIANCE : 6 +H dp_mux_x2_buf,P,14/11/2000,10 +A 0,0,400,1000 +R 200,400,ref_ref,sel1 +R 300,400,ref_ref,sel0 +S 200,600,300,600,20,*,RIGHT,TALU2 +S 200,400,300,400,20,*,RIGHT,TALU2 +S 200,150,300,150,20,*,RIGHT,TALU2 +S 250,850,250,850,10,sel,LEFT,CALU1 +S 60,30,60,150,20,*,DOWN,ALU1 +S 370,50,370,150,20,*,UP,ALU1 +S 190,100,190,400,20,*,UP,ALU1 +S 190,660,190,900,20,*,UP,ALU1 +S 310,100,310,400,20,*,UP,ALU1 +S 190,220,260,220,20,*,RIGHT,ALU1 +S 370,900,370,970,20,*,UP,ALU1 +S 310,740,310,790,20,*,DOWN,ALU1 +S 190,790,310,790,20,*,RIGHT,ALU1 +S 250,900,250,940,20,*,UP,ALU1 +S 130,350,130,680,20,*,UP,ALU1 +S 370,280,370,680,20,*,UP,ALU1 +S 130,50,130,150,20,*,UP,ALU1 +S 250,50,250,150,20,*,UP,ALU1 +S 250,280,250,740,20,*,UP,ALU1 +S 130,900,130,970,20,*,DOWN,ALU1 +S 250,220,340,220,30,*,RIGHT,POLY +S 160,220,220,220,30,*,RIGHT,POLY +S 280,820,280,860,10,*,DOWN,POLY +S 220,850,280,850,30,*,RIGHT,POLY +S 160,660,220,660,30,*,RIGHT,POLY +S 280,190,280,320,10,*,DOWN,POLY +S 340,190,340,320,10,*,UP,POLY +S 220,190,220,320,10,*,UP,POLY +S 160,190,160,320,10,*,DOWN,POLY +S 220,820,220,870,10,*,DOWN,POLY +S 130,30,130,170,30,*,UP,NDIF +S 370,30,370,170,30,*,UP,NDIF +S 220,10,220,190,10,*,DOWN,NTRANS +S 160,10,160,190,10,*,UP,NTRANS +S 250,30,250,170,30,*,UP,NDIF +S 190,30,190,170,30,*,UP,NDIF +S 250,890,250,960,30,*,UP,NDIF +S 190,890,190,960,30,*,UP,NDIF +S 280,10,280,190,10,*,DOWN,NTRANS +S 310,30,310,170,30,*,UP,NDIF +S 340,10,340,190,10,*,DOWN,NTRANS +S 220,870,220,980,10,*,UP,NTRANS +S 340,320,340,650,10,*,DOWN,PTRANS +S 370,340,370,630,30,*,DOWN,PDIF +S 220,320,220,650,10,*,UP,PTRANS +S 190,340,190,630,30,*,UP,PDIF +S 250,340,250,630,30,*,UP,PDIF +S 160,320,160,650,10,*,UP,PTRANS +S 130,340,130,630,30,*,UP,PDIF +S 310,730,310,800,30,*,UP,PDIF +S 280,710,280,820,10,*,DOWN,PTRANS +S 260,730,260,800,30,*,UP,PDIF +S 220,710,220,820,10,*,DOWN,PTRANS +S 190,730,190,800,30,*,UP,PDIF +S 280,320,280,650,10,*,UP,PTRANS +S 310,340,310,630,30,*,UP,PDIF +S 0,500,400,500,460,*,RIGHT,NWELL +S 200,150,200,600,20,sel1,UP,CALU3 +S 300,150,300,600,20,sel0,DOWN,CALU3 +S 0,30,400,30,60,vss,RIGHT,CALU1 +S 0,970,400,970,60,vss,RIGHT,CALU1 +S 0,530,400,530,60,vdd,RIGHT,CALU1 +S 0,470,400,470,60,vdd,RIGHT,CALU1 +V 300,150,CONT_VIA,* +V 300,150,CONT_VIA2,* +V 60,150,CONT_BODY_P,* +V 60,30,CONT_BODY_P,* +V 200,150,CONT_VIA2,* +V 300,600,CONT_VIA2,* +V 200,600,CONT_VIA2,* +V 200,400,CONT_VIA2,* +V 300,400,CONT_VIA2,* +V 200,150,CONT_VIA,* +V 300,400,CONT_VIA,* +V 300,600,CONT_VIA,* +V 200,600,CONT_VIA,* +V 200,400,CONT_VIA,* +V 190,660,CONT_POLY,* +V 260,220,CONT_POLY,* +V 250,850,CONT_POLY,* +V 130,900,CONT_BODY_P,* +V 370,900,CONT_BODY_P,* +V 130,970,CONT_BODY_P,* +V 370,970,CONT_BODY_P,* +V 130,150,CONT_DIF_N,* +V 130,50,CONT_DIF_N,* +V 310,150,CONT_DIF_N,* +V 370,150,CONT_DIF_N,* +V 370,50,CONT_DIF_N,* +V 310,100,CONT_DIF_N,* +V 370,100,CONT_DIF_N,* +V 250,900,CONT_DIF_N,* +V 190,100,CONT_DIF_N,* +V 190,150,CONT_DIF_N,* +V 190,900,CONT_DIF_N,* +V 250,150,CONT_DIF_N,* +V 250,50,CONT_DIF_N,* +V 250,100,CONT_DIF_N,* +V 130,100,CONT_DIF_N,* +V 250,950,CONT_DIF_N,* +V 190,790,CONT_DIF_P,* +V 130,550,CONT_DIF_P,* +V 130,350,CONT_DIF_P,* +V 130,600,CONT_DIF_P,* +V 370,290,CONT_BODY_N,* +V 130,290,CONT_BODY_N,* +V 250,290,CONT_BODY_N,* +V 190,740,CONT_DIF_P,* +V 250,740,CONT_DIF_P,* +V 250,500,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 250,550,CONT_DIF_P,* +V 250,450,CONT_DIF_P,* +V 250,350,CONT_DIF_P,* +V 130,400,CONT_DIF_P,* +V 130,450,CONT_DIF_P,* +V 130,500,CONT_DIF_P,* +V 310,350,CONT_DIF_P,* +V 310,400,CONT_DIF_P,* +V 370,600,CONT_DIF_P,* +V 370,550,CONT_DIF_P,* +V 370,500,CONT_DIF_P,* +V 370,450,CONT_DIF_P,* +V 370,350,CONT_DIF_P,* +V 370,400,CONT_DIF_P,* +V 370,680,CONT_BODY_N,* +V 250,680,CONT_BODY_N,* +V 310,740,CONT_DIF_P,* +V 310,790,CONT_DIF_P,* +V 310,600,CONT_DIF_P,* +V 190,600,CONT_DIF_P,* +V 190,400,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 130,680,CONT_BODY_N,* +V 60,90,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_mux_x2_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_mux_x2_buf.vbe new file mode 100644 index 00000000..7e5711b7 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_mux_x2_buf.vbe @@ -0,0 +1,21 @@ +ENTITY dp_mux_x2_buf IS +PORT ( + sel : in BIT; + sel0 : out BIT; + sel1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_mux_x2_buf; + +ARCHITECTURE vbe OF dp_mux_x2_buf IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_mux_x2_buf" + SEVERITY WARNING; + + sel1 <= sel; + sel0 <= not sel; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_mux_x4.ap b/alliance/src/cells/src/dp_sxlib/dp_mux_x4.ap new file mode 100644 index 00000000..c16ab830 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_mux_x4.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H dp_mux_x4,P,10/11/2000,100 +A 0,0,4500,5000 +R 3500,2000,ref_ref,sel0 +R 2500,2000,ref_ref,sel1 +R 1000,4000,ref_ref,q_40 +R 1000,3500,ref_ref,q_35 +R 1000,3000,ref_ref,q_30 +R 1000,2500,ref_ref,q_25 +R 1000,2000,ref_ref,q_20 +R 1000,1500,ref_ref,q_15 +R 1000,1000,ref_ref,q_10 +R 4000,2500,ref_ref,i0_25 +R 4000,3000,ref_ref,i0_30 +R 4000,1000,ref_ref,i0_10 +R 2000,1000,ref_ref,i1_10 +R 4000,3500,ref_ref,i0_35 +R 4000,2000,ref_ref,i0_20 +R 4000,1500,ref_ref,i0_15 +R 2000,1500,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_20 +R 2000,2500,ref_ref,i1_25 +R 2000,3000,ref_ref,i1_30 +R 2000,3500,ref_ref,i1_35 +R 2000,4000,ref_ref,i1_40 +S 3800,3000,4000,3000,100,*,RIGHT,POLY +S 3800,3000,3800,3100,100,*,DOWN,POLY +S 3400,2000,3400,3100,100,*,DOWN,POLY +S 4100,3300,4100,4200,300,*,UP,PDIF +S 3800,3100,3800,4400,100,*,UP,PTRANS +S 3400,3100,3400,4400,100,*,UP,PTRANS +S 2000,2900,2200,2900,100,*,LEFT,POLY +S 4100,4000,4100,4700,200,*,UP,ALU1 +S 1700,3200,1700,4700,700,*,DOWN,PDIF +S 4000,1000,4000,3500,200,i0,UP,CALU1 +S 2500,4000,3500,4000,100,*,RIGHT,ALU1 +S 300,500,300,1700,200,*,UP,ALU1 +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 300,300,300,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1700,300,1700,1200,700,*,UP,NDIF +S 1500,3000,1500,4500,200,*,DOWN,ALU1 +S 1900,1400,2200,1400,100,*,RIGHT,POLY +S 3800,100,3800,900,100,*,DOWN,NTRANS +S 3400,100,3400,900,100,*,DOWN,NTRANS +S 1500,500,1500,1700,200,*,UP,ALU1 +S 4100,300,4100,700,300,*,DOWN,NDIF +S 2600,100,2600,900,100,*,DOWN,NTRANS +S 2200,100,2200,900,100,*,DOWN,NTRANS +S 2600,900,2600,2000,100,*,UP,POLY +S 2200,900,2200,1400,100,*,UP,POLY +S 3000,300,3000,700,500,*,UP,NDIF +S 600,1400,600,2600,100,*,UP,POLY +S 1200,1400,1200,2600,100,*,UP,POLY +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,2800,1500,3300,300,*,UP,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2600,2000,3400,2000,100,*,RIGHT,POLY +S 0,4000,4500,4000,2600,*,LEFT,NWELL +S 3000,300,3000,1100,300,*,UP,NDIF +S 2900,300,2900,1100,300,*,UP,NDIF +S 3800,900,4000,900,100,*,LEFT,POLY +S 3500,1500,3500,4000,100,*,UP,ALU1 +S 3400,900,3400,1600,100,*,UP,POLY +S 2500,2000,3500,2000,200,*,RIGHT,TALU2 +S 2500,2000,2500,2000,200,sel1,LEFT,CALU3 +S 3500,2000,3500,2000,200,sel0,LEFT,CALU3 +S 1000,1000,1000,4000,200,q,UP,CALU1 +S 2000,1000,2000,4000,200,i1,UP,CALU1 +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 600,2400,3000,2400,100,*,RIGHT,POLY +S 2200,3100,2200,4400,100,*,UP,PTRANS +S 2600,3100,2600,4400,100,*,UP,PTRANS +S 2200,2900,2200,3100,100,*,DOWN,POLY +S 2600,2900,2600,3200,100,*,DOWN,POLY +S 2500,3000,2500,4000,100,*,UP,ALU1 +S 2500,3000,2600,3000,100,*,RIGHT,ALU1 +S 3000,3300,3000,4200,500,*,UP,PDIF +S 3000,3500,3100,3500,100,*,LEFT,ALU1 +S 3100,2500,3100,3500,100,*,UP,ALU1 +S 3000,1000,3000,2500,100,*,UP,ALU1 +S 3000,2500,3100,2500,100,*,RIGHT,ALU1 +V 4000,3000,CONT_POLY,* +V 4200,4700,CONT_BODY_N,* +V 2500,4700,CONT_BODY_N,* +V 4100,4000,CONT_DIF_P,* +V 2000,2900,CONT_POLY,* +V 900,4000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,3000,CONT_DIF_P,* +V 900,1000,CONT_DIF_N,* +V 3000,3500,CONT_DIF_P,* +V 3500,2000,CONT_VIA,* +V 3500,2000,CONT_VIA2,* +V 2500,2000,CONT_POLY,* +V 2500,2000,CONT_VIA,* +V 2500,2000,CONT_VIA2,* +V 300,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 300,1700,CONT_BODY_P,* +V 300,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 2000,1500,CONT_POLY,* +V 4100,500,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,500,CONT_DIF_N,* +V 1500,4500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 1500,3000,CONT_DIF_P,* +V 1500,1700,CONT_BODY_P,* +V 3000,1000,CONT_DIF_N,* +V 3500,1500,CONT_POLY,* +V 4000,1000,CONT_POLY,* +V 3000,2400,CONT_POLY,* +V 2600,3000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_mux_x4.vbe b/alliance/src/cells/src/dp_sxlib/dp_mux_x4.vbe new file mode 100644 index 00000000..470bc377 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_mux_x4.vbe @@ -0,0 +1,26 @@ +ENTITY dp_mux_x4 IS +PORT ( + sel0 : in BIT; + sel1 : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_mux_x4; + +ARCHITECTURE vbe OF dp_mux_x4 IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_mux_x4" + SEVERITY WARNING; + + ASSERT (sel0 xor sel1) + REPORT "wrong control signals on dp_mux_x4" + SEVERITY WARNING; + + q <= (sel0 and i0) or (sel1 and i1); + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_mux_x4_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_mux_x4_buf.ap new file mode 100644 index 00000000..3d8636b4 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_mux_x4_buf.ap @@ -0,0 +1,141 @@ +V ALLIANCE : 6 +H dp_mux_x4_buf,P,14/11/2000,10 +A 0,0,450,1000 +R 250,400,ref_ref,sel1 +R 350,400,ref_ref,sel0 +S 250,600,350,600,20,*,RIGHT,TALU2 +S 250,400,350,400,20,*,LEFT,TALU2 +S 250,150,350,150,20,*,RIGHT,TALU2 +S 300,850,300,850,10,sel,LEFT,CALU1 +S 250,150,250,600,20,sel1,UP,CALU3 +S 350,150,350,600,20,sel0,DOWN,CALU3 +S 0,530,450,530,60,vdd,RIGHT,CALU1 +S 0,470,450,470,60,vdd,RIGHT,CALU1 +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 0,970,450,970,60,vss,RIGHT,CALU1 +S 0,500,450,500,460,*,RIGHT,NWELL +S 330,710,330,820,10,*,DOWN,PTRANS +S 310,730,310,800,30,*,UP,PDIF +S 270,710,270,820,10,*,DOWN,PTRANS +S 240,730,240,800,30,*,UP,PDIF +S 330,320,330,650,10,*,UP,PTRANS +S 360,340,360,630,30,*,UP,PDIF +S 390,320,390,650,10,*,DOWN,PTRANS +S 420,340,420,630,30,*,DOWN,PDIF +S 270,320,270,650,10,*,UP,PTRANS +S 240,340,240,630,30,*,UP,PDIF +S 300,340,300,630,30,*,UP,PDIF +S 210,320,210,650,10,*,UP,PTRANS +S 180,340,180,630,30,*,UP,PDIF +S 360,730,360,800,30,*,UP,PDIF +S 270,870,270,980,10,*,UP,NTRANS +S 300,890,300,960,30,*,UP,NDIF +S 240,890,240,960,30,*,UP,NDIF +S 330,10,330,190,10,*,DOWN,NTRANS +S 360,30,360,170,30,*,UP,NDIF +S 390,10,390,190,10,*,DOWN,NTRANS +S 180,30,180,170,30,*,UP,NDIF +S 420,30,420,170,30,*,UP,NDIF +S 270,10,270,190,10,*,DOWN,NTRANS +S 210,10,210,190,10,*,UP,NTRANS +S 300,30,300,170,30,*,UP,NDIF +S 240,30,240,170,30,*,UP,NDIF +S 210,190,210,320,10,*,DOWN,POLY +S 270,820,270,870,10,*,DOWN,POLY +S 300,220,390,220,30,*,RIGHT,POLY +S 210,220,270,220,30,*,RIGHT,POLY +S 330,820,330,860,10,*,DOWN,POLY +S 270,850,330,850,30,*,RIGHT,POLY +S 210,660,270,660,30,*,RIGHT,POLY +S 330,190,330,320,10,*,DOWN,POLY +S 390,190,390,320,10,*,UP,POLY +S 270,190,270,320,10,*,UP,POLY +S 300,900,300,940,20,*,UP,ALU1 +S 180,350,180,680,20,*,UP,ALU1 +S 420,280,420,680,20,*,UP,ALU1 +S 180,50,180,150,20,*,UP,ALU1 +S 300,50,300,150,20,*,UP,ALU1 +S 300,280,300,740,20,*,UP,ALU1 +S 180,900,180,970,20,*,DOWN,ALU1 +S 420,50,420,150,20,*,UP,ALU1 +S 240,100,240,400,20,*,UP,ALU1 +S 240,660,240,900,20,*,UP,ALU1 +S 360,100,360,400,20,*,UP,ALU1 +S 240,220,310,220,20,*,RIGHT,ALU1 +S 420,900,420,970,20,*,UP,ALU1 +S 360,740,360,790,20,*,DOWN,ALU1 +S 240,790,360,790,20,*,RIGHT,ALU1 +S 70,30,70,150,20,*,DOWN,ALU1 +V 180,680,CONT_BODY_N,* +V 420,680,CONT_BODY_N,* +V 300,680,CONT_BODY_N,* +V 360,740,CONT_DIF_P,* +V 360,790,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 240,600,CONT_DIF_P,* +V 240,400,CONT_DIF_P,* +V 240,350,CONT_DIF_P,* +V 360,350,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 420,550,CONT_DIF_P,* +V 420,500,CONT_DIF_P,* +V 420,450,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 300,500,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 300,550,CONT_DIF_P,* +V 300,450,CONT_DIF_P,* +V 300,350,CONT_DIF_P,* +V 180,400,CONT_DIF_P,* +V 180,450,CONT_DIF_P,* +V 180,500,CONT_DIF_P,* +V 180,550,CONT_DIF_P,* +V 180,350,CONT_DIF_P,* +V 180,600,CONT_DIF_P,* +V 420,290,CONT_BODY_N,* +V 180,290,CONT_BODY_N,* +V 300,290,CONT_BODY_N,* +V 240,740,CONT_DIF_P,* +V 300,740,CONT_DIF_P,* +V 240,790,CONT_DIF_P,* +V 300,950,CONT_DIF_N,* +V 300,900,CONT_DIF_N,* +V 240,100,CONT_DIF_N,* +V 240,150,CONT_DIF_N,* +V 240,900,CONT_DIF_N,* +V 300,150,CONT_DIF_N,* +V 300,50,CONT_DIF_N,* +V 300,100,CONT_DIF_N,* +V 180,100,CONT_DIF_N,* +V 180,150,CONT_DIF_N,* +V 180,50,CONT_DIF_N,* +V 360,150,CONT_DIF_N,* +V 420,150,CONT_DIF_N,* +V 420,50,CONT_DIF_N,* +V 360,100,CONT_DIF_N,* +V 420,100,CONT_DIF_N,* +V 180,900,CONT_BODY_P,* +V 420,900,CONT_BODY_P,* +V 180,970,CONT_BODY_P,* +V 420,970,CONT_BODY_P,* +V 240,660,CONT_POLY,* +V 310,220,CONT_POLY,* +V 300,850,CONT_POLY,* +V 250,400,CONT_VIA,* +V 250,150,CONT_VIA,* +V 350,400,CONT_VIA,* +V 350,600,CONT_VIA,* +V 250,600,CONT_VIA,* +V 350,400,CONT_VIA2,* +V 250,150,CONT_VIA2,* +V 350,600,CONT_VIA2,* +V 250,600,CONT_VIA2,* +V 250,400,CONT_VIA2,* +V 70,30,CONT_BODY_P,* +V 70,150,CONT_BODY_P,* +V 70,90,CONT_BODY_P,* +V 350,150,CONT_VIA2,* +V 350,150,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_mux_x4_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_mux_x4_buf.vbe new file mode 100644 index 00000000..51882792 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_mux_x4_buf.vbe @@ -0,0 +1,21 @@ +ENTITY dp_mux_x4_buf IS +PORT ( + sel : in BIT; + sel0 : out BIT; + sel1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_mux_x4_buf; + +ARCHITECTURE vbe OF dp_mux_x4_buf IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_mux_x4_buf" + SEVERITY WARNING; + + sel1 <= sel; + sel0 <= not sel; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_nmux_x1.ap b/alliance/src/cells/src/dp_sxlib/dp_nmux_x1.ap new file mode 100644 index 00000000..556c969f --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_nmux_x1.ap @@ -0,0 +1,80 @@ +V ALLIANCE : 6 +H dp_nmux_x1,P,15/11/2000,100 +A 0,0,3000,5000 +R 500,1500,ref_ref,i1_15 +R 500,1000,ref_ref,i1_10 +R 1500,1000,ref_ref,nq_10 +R 1500,1500,ref_ref,nq_15 +R 2500,1000,ref_ref,i0_10 +R 2500,1500,ref_ref,i0_15 +R 2500,2000,ref_ref,i0_20 +R 500,2000,ref_ref,i1_20 +R 500,2500,ref_ref,i1_25 +R 500,3000,ref_ref,i1_30 +R 500,3500,ref_ref,i1_35 +R 500,4000,ref_ref,i1_40 +R 2500,2500,ref_ref,i0_25 +R 2500,4000,ref_ref,i0_40 +R 2500,3500,ref_ref,i0_35 +R 2500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1000,2000,ref_ref,sel1 +R 2000,2000,ref_ref,sel0 +S 2400,2600,2400,4400,100,*,UP,PTRANS +S 1500,2800,1500,4200,500,*,UP,PDIF +S 1900,2600,1900,4400,100,*,UP,PTRANS +S 1100,2600,1100,4400,100,*,UP,PTRANS +S 600,2600,600,4400,100,*,UP,PTRANS +S 2000,2000,2000,2000,200,sel0,LEFT,CALU3 +S 1000,2000,1000,2000,200,sel1,LEFT,CALU3 +S 600,1900,600,2600,100,*,UP,POLY +S 2400,1900,2400,2600,100,*,UP,POLY +S 300,400,300,1700,300,*,DOWN,NDIF +S 2700,400,2700,1700,300,*,DOWN,NDIF +S 1900,600,1900,1900,100,*,DOWN,NTRANS +S 1500,800,1500,1700,500,*,UP,NDIF +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 2400,600,2400,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1500,2600,1900,2600,100,*,RIGHT,POLY +S 1500,2100,1500,2600,100,*,UP,POLY +S 900,2100,1500,2100,100,*,RIGHT,POLY +S 2000,2000,2000,4000,100,*,UP,ALU1 +S 1000,4000,2000,4000,100,*,LEFT,ALU1 +S 1000,2500,1000,4000,100,*,DOWN,ALU1 +S 2700,2800,2700,4500,300,*,UP,PDIF +S 300,2800,300,4500,300,*,UP,PDIF +S 0,4000,3000,4000,2600,*,RIGHT,NWELL +S 1000,2000,2000,2000,200,*,RIGHT,TALU2 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2500,1000,2500,4000,200,i0,UP,CALU1 +S 500,1000,500,4000,200,i1,UP,CALU1 +S 1500,1000,1500,3500,200,nq,UP,CALU1 +V 1500,4700,CONT_BODY_N,* +V 2100,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 1500,1500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 1500,300,CONT_BODY_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_VIA2,* +V 1000,2000,CONT_VIA,* +V 2000,2000,CONT_VIA2,* +V 2000,2000,CONT_VIA,* +V 1000,2500,CONT_POLY,* +V 2700,4500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 900,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_nmux_x1.vbe b/alliance/src/cells/src/dp_sxlib/dp_nmux_x1.vbe new file mode 100644 index 00000000..e9b7bfed --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_nmux_x1.vbe @@ -0,0 +1,26 @@ +ENTITY dp_nmux_x1 IS +PORT ( + sel0 : in BIT; + sel1 : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_nmux_x1; + +ARCHITECTURE vbe OF dp_nmux_x1 IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_nmux_x1" + SEVERITY WARNING; + + ASSERT (sel0 xor sel1) + REPORT "wrong control signals on dp_nmux_x1" + SEVERITY WARNING; + + nq <= not ((sel0 and i0) or (sel1 and i1)); + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_nmux_x1_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_nmux_x1_buf.ap new file mode 100644 index 00000000..08289ecb --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_nmux_x1_buf.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 6 +H dp_nmux_x1_buf,P,14/11/2000,10 +A 0,0,300,1000 +R 100,400,ref_ref,sel1 +R 200,400,ref_ref,sel0 +S 100,600,200,600,20,*,RIGHT,TALU2 +S 100,400,200,400,20,*,RIGHT,TALU2 +S 100,150,200,150,20,*,RIGHT,TALU2 +S 150,850,150,850,10,sel,LEFT,CALU1 +S 180,190,180,320,10,*,DOWN,POLY +S 240,190,240,320,10,*,UP,POLY +S 120,190,120,320,10,*,UP,POLY +S 60,190,60,320,10,*,DOWN,POLY +S 150,280,150,740,20,*,UP,ALU1 +S 30,900,30,970,20,*,DOWN,ALU1 +S 270,900,270,970,20,*,UP,ALU1 +S 210,740,210,790,20,*,DOWN,ALU1 +S 90,790,210,790,20,*,RIGHT,ALU1 +S 120,820,120,870,10,*,DOWN,POLY +S 180,820,180,860,10,*,DOWN,POLY +S 120,850,180,850,30,*,RIGHT,POLY +S 120,870,120,980,10,*,UP,NTRANS +S 150,890,150,960,30,*,UP,NDIF +S 90,890,90,960,30,*,UP,NDIF +S 150,900,150,940,20,*,UP,ALU1 +S 210,730,210,800,30,*,UP,PDIF +S 180,710,180,820,10,*,DOWN,PTRANS +S 160,730,160,800,30,*,UP,PDIF +S 120,710,120,820,10,*,DOWN,PTRANS +S 90,730,90,800,30,*,UP,PDIF +S 60,660,120,660,30,*,RIGHT,POLY +S 30,350,30,680,20,*,UP,ALU1 +S 270,280,270,680,20,*,UP,ALU1 +S 180,320,180,650,10,*,UP,PTRANS +S 210,340,210,630,30,*,UP,PDIF +S 240,320,240,650,10,*,DOWN,PTRANS +S 270,340,270,630,30,*,DOWN,PDIF +S 120,320,120,650,10,*,UP,PTRANS +S 90,340,90,630,30,*,UP,PDIF +S 150,340,150,630,30,*,UP,PDIF +S 60,320,60,650,10,*,UP,PTRANS +S 30,340,30,630,30,*,UP,PDIF +S 30,50,30,150,20,*,UP,ALU1 +S 150,50,150,150,20,*,UP,ALU1 +S 270,50,270,150,20,*,UP,ALU1 +S 180,10,180,190,10,*,DOWN,NTRANS +S 210,30,210,170,30,*,UP,NDIF +S 240,10,240,190,10,*,DOWN,NTRANS +S 30,30,30,170,30,*,UP,NDIF +S 270,30,270,170,30,*,UP,NDIF +S 120,10,120,190,10,*,DOWN,NTRANS +S 60,10,60,190,10,*,UP,NTRANS +S 150,30,150,170,30,*,UP,NDIF +S 90,30,90,170,30,*,UP,NDIF +S 0,500,300,500,460,*,RIGHT,NWELL +S 90,100,90,400,20,*,UP,ALU1 +S 90,660,90,900,20,*,UP,ALU1 +S 210,100,210,400,20,*,UP,ALU1 +S 90,220,160,220,20,*,RIGHT,ALU1 +S 150,220,240,220,30,*,RIGHT,POLY +S 60,220,120,220,30,*,RIGHT,POLY +S 0,970,300,970,60,vss,RIGHT,CALU1 +S 0,30,300,30,60,vss,RIGHT,CALU1 +S 0,530,300,530,60,vdd,RIGHT,CALU1 +S 0,470,300,470,60,vdd,RIGHT,CALU1 +S 100,150,100,600,20,sel1,UP,CALU3 +S 200,150,200,600,20,sel0,DOWN,CALU3 +V 200,150,CONT_VIA,* +V 200,150,CONT_VIA2,* +V 30,900,CONT_BODY_P,* +V 270,900,CONT_BODY_P,* +V 90,660,CONT_POLY,* +V 30,680,CONT_BODY_N,* +V 270,680,CONT_BODY_N,* +V 150,680,CONT_BODY_N,* +V 30,970,CONT_BODY_P,* +V 150,950,CONT_DIF_N,* +V 150,900,CONT_DIF_N,* +V 210,740,CONT_DIF_P,* +V 210,790,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 200,600,CONT_VIA,* +V 200,600,CONT_VIA2,* +V 90,600,CONT_DIF_P,* +V 100,600,CONT_VIA,* +V 100,600,CONT_VIA2,* +V 90,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 100,400,CONT_VIA,* +V 100,400,CONT_VIA2,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 200,400,CONT_VIA,* +V 200,400,CONT_VIA2,* +V 270,600,CONT_DIF_P,* +V 270,550,CONT_DIF_P,* +V 270,500,CONT_DIF_P,* +V 270,450,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 150,500,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,550,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,500,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 270,290,CONT_BODY_N,* +V 30,290,CONT_BODY_N,* +V 150,290,CONT_BODY_N,* +V 90,100,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 90,900,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,150,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 90,740,CONT_DIF_P,* +V 150,740,CONT_DIF_P,* +V 100,150,CONT_VIA2,* +V 100,150,CONT_VIA,* +V 210,150,CONT_DIF_N,* +V 270,150,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 90,790,CONT_DIF_P,* +V 270,970,CONT_BODY_P,* +V 160,220,CONT_POLY,* +V 150,850,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_nmux_x1_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_nmux_x1_buf.vbe new file mode 100644 index 00000000..ad2647df --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_nmux_x1_buf.vbe @@ -0,0 +1,21 @@ +ENTITY dp_nmux_x1_buf IS +PORT ( + sel : in BIT; + sel0 : out BIT; + sel1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_nmux_x1_buf; + +ARCHITECTURE vbe OF dp_nmux_x1_buf IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_nmux_x1_buf" + SEVERITY WARNING; + + sel1 <= sel; + sel0 <= not sel; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_nts_x2.ap b/alliance/src/cells/src/dp_sxlib/dp_nts_x2.ap new file mode 100644 index 00000000..58976d1d --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_nts_x2.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H dp_nts_x2,P,10/11/2000,100 +A 0,0,3000,5000 +R 1000,2000,ref_ref,nenx +R 2000,2000,ref_ref,enx +R 1500,2500,ref_ref,nq_25 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 500,1500,ref_ref,i_15 +R 500,1000,ref_ref,i_10 +R 500,2500,ref_ref,i_25 +R 500,2000,ref_ref,i_20 +R 500,4000,ref_ref,i_40 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 1500,4000,ref_ref,nq_40 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2000,ref_ref,nq_20 +S 2700,3000,2700,4700,200,*,UP,ALU1 +S 2700,2800,2700,4200,300,*,DOWN,PDIF +S 2400,2600,2400,4400,100,*,DOWN,PTRANS +S 2700,500,2700,1700,200,*,DOWN,ALU1 +S 1000,2000,1000,2500,200,*,DOWN,ALU1 +S 2000,1500,2000,2000,200,*,UP,ALU1 +S 1000,2500,1800,2500,300,*,RIGHT,POLY +S 500,2000,2400,2000,300,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,DOWN,PTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 2700,300,2700,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 2400,100,2400,1400,100,*,UP,NTRANS +S 1200,1500,2000,1500,300,*,RIGHT,POLY +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1800,2600,1800,4900,100,*,DOWN,PTRANS +S 1800,100,1800,1400,100,*,UP,NTRANS +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 1400,2800,1400,4700,300,*,DOWN,PDIF +S 1000,2000,2000,2000,200,*,RIGHT,TALU2 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 1500,1000,1500,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i,UP,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2000,2000,2000,2000,200,enx,LEFT,CALU3 +S 1000,2000,1000,2000,200,nenx,LEFT,CALU3 +S 2400,1400,2400,2600,100,*,DOWN,POLY +V 2700,4700,CONT_BODY_N,* +V 2700,1000,CONT_DIF_N,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,1700,CONT_BODY_P,* +V 300,4500,CONT_DIF_P,* +V 2000,2000,CONT_VIA,* +V 2000,2000,CONT_VIA2,* +V 1000,2000,CONT_VIA2,* +V 1000,2000,CONT_VIA,* +V 1000,2500,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 2700,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2000,1500,CONT_POLY,* +V 1500,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 2700,3000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_nts_x2.vbe b/alliance/src/cells/src/dp_sxlib/dp_nts_x2.vbe new file mode 100644 index 00000000..75679a4f --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_nts_x2.vbe @@ -0,0 +1,28 @@ +ENTITY dp_nts_x2 IS +PORT ( + enx : in BIT; + nenx : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END dp_nts_x2; + +ARCHITECTURE vbe OF dp_nts_x2 IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_nts_x2" + SEVERITY WARNING; + + ASSERT (enx xor nenx) + REPORT "wrong control signals on dp_nts_x2" + SEVERITY WARNING; + + label0 : BLOCK (enx = '1') + BEGIN + nq <= GUARDED not i; + END BLOCK label0; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_nts_x2_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_nts_x2_buf.ap new file mode 100644 index 00000000..49f920b9 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_nts_x2_buf.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 6 +H dp_nts_x2_buf,P,14/11/2000,10 +A 0,0,300,1000 +R 200,400,ref_ref,enx +R 100,400,ref_ref,nenx +S 100,600,200,600,20,*,RIGHT,TALU2 +S 100,400,200,400,20,*,RIGHT,TALU2 +S 100,150,200,150,20,*,RIGHT,TALU2 +S 100,150,100,600,20,nenx,UP,CALU3 +S 200,150,200,600,20,enx,DOWN,CALU3 +S 0,30,300,30,60,vss,RIGHT,CALU1 +S 0,530,300,530,60,vdd,RIGHT,CALU1 +S 0,470,300,470,60,vdd,RIGHT,CALU1 +S 0,970,300,970,60,vss,RIGHT,CALU1 +S 140,220,210,220,20,*,RIGHT,ALU1 +S 60,220,150,220,30,*,RIGHT,POLY +S 180,220,240,220,30,*,RIGHT,POLY +S 210,660,210,790,20,*,DOWN,ALU1 +S 90,740,90,900,20,*,UP,ALU1 +S 180,660,240,660,30,*,RIGHT,POLY +S 180,190,180,320,10,*,DOWN,POLY +S 240,190,240,320,10,*,UP,POLY +S 120,190,120,320,10,*,UP,POLY +S 60,190,60,320,10,*,DOWN,POLY +S 150,280,150,740,20,*,UP,ALU1 +S 30,900,30,970,20,*,DOWN,ALU1 +S 270,900,270,970,20,*,UP,ALU1 +S 90,790,210,790,20,*,RIGHT,ALU1 +S 120,820,120,870,10,*,DOWN,POLY +S 180,820,180,860,10,*,DOWN,POLY +S 120,850,180,850,30,*,RIGHT,POLY +S 120,870,120,980,10,*,UP,NTRANS +S 150,890,150,960,30,*,UP,NDIF +S 90,890,90,960,30,*,UP,NDIF +S 150,900,150,940,20,*,UP,ALU1 +S 210,730,210,800,30,*,UP,PDIF +S 180,710,180,820,10,*,DOWN,PTRANS +S 160,730,160,800,30,*,UP,PDIF +S 120,710,120,820,10,*,DOWN,PTRANS +S 90,730,90,800,30,*,UP,PDIF +S 30,350,30,680,20,*,UP,ALU1 +S 270,280,270,680,20,*,UP,ALU1 +S 180,320,180,650,10,*,UP,PTRANS +S 210,340,210,630,30,*,UP,PDIF +S 240,320,240,650,10,*,DOWN,PTRANS +S 270,340,270,630,30,*,DOWN,PDIF +S 120,320,120,650,10,*,UP,PTRANS +S 90,340,90,630,30,*,UP,PDIF +S 150,340,150,630,30,*,UP,PDIF +S 60,320,60,650,10,*,UP,PTRANS +S 30,340,30,630,30,*,UP,PDIF +S 30,50,30,150,20,*,UP,ALU1 +S 150,50,150,150,20,*,UP,ALU1 +S 270,50,270,150,20,*,UP,ALU1 +S 180,10,180,190,10,*,DOWN,NTRANS +S 210,30,210,170,30,*,UP,NDIF +S 240,10,240,190,10,*,DOWN,NTRANS +S 30,30,30,170,30,*,UP,NDIF +S 270,30,270,170,30,*,UP,NDIF +S 120,10,120,190,10,*,DOWN,NTRANS +S 60,10,60,190,10,*,UP,NTRANS +S 150,30,150,170,30,*,UP,NDIF +S 90,30,90,170,30,*,UP,NDIF +S 0,500,300,500,460,*,RIGHT,NWELL +S 90,100,90,400,20,*,UP,ALU1 +S 210,100,210,400,20,*,UP,ALU1 +S 150,850,150,850,10,en,LEFT,CALU1 +V 140,220,CONT_POLY,* +V 210,660,CONT_POLY,* +V 200,150,CONT_VIA,* +V 200,150,CONT_VIA2,* +V 30,900,CONT_BODY_P,* +V 270,900,CONT_BODY_P,* +V 30,680,CONT_BODY_N,* +V 270,680,CONT_BODY_N,* +V 150,680,CONT_BODY_N,* +V 30,970,CONT_BODY_P,* +V 150,950,CONT_DIF_N,* +V 150,900,CONT_DIF_N,* +V 210,740,CONT_DIF_P,* +V 210,790,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 200,600,CONT_VIA,* +V 200,600,CONT_VIA2,* +V 90,600,CONT_DIF_P,* +V 100,600,CONT_VIA,* +V 100,600,CONT_VIA2,* +V 90,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 100,400,CONT_VIA,* +V 100,400,CONT_VIA2,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 200,400,CONT_VIA,* +V 200,400,CONT_VIA2,* +V 270,600,CONT_DIF_P,* +V 270,550,CONT_DIF_P,* +V 270,500,CONT_DIF_P,* +V 270,450,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 150,500,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,550,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,500,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 270,290,CONT_BODY_N,* +V 30,290,CONT_BODY_N,* +V 150,290,CONT_BODY_N,* +V 90,100,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 90,900,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,150,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 90,740,CONT_DIF_P,* +V 150,740,CONT_DIF_P,* +V 100,150,CONT_VIA2,* +V 100,150,CONT_VIA,* +V 210,150,CONT_DIF_N,* +V 270,150,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 90,790,CONT_DIF_P,* +V 270,970,CONT_BODY_P,* +V 150,850,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_nts_x2_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_nts_x2_buf.vbe new file mode 100644 index 00000000..a853ddec --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_nts_x2_buf.vbe @@ -0,0 +1,21 @@ +ENTITY dp_nts_x2_buf IS +PORT ( + en : in BIT; + enx : out BIT; + nenx : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_nts_x2_buf; + +ARCHITECTURE vbe OF dp_nts_x2_buf IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_nts_x2_buf" + SEVERITY WARNING; + + enx <= en; + nenx <= not en; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_rom2_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_rom2_buf.ap new file mode 100644 index 00000000..92dbe197 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_rom2_buf.ap @@ -0,0 +1,73 @@ +V ALLIANCE : 6 +H dp_rom2_buf,P,14/11/2000,10 +A 0,0,250,1000 +R 100,400,ref_ref,wenx +S 40,600,160,600,20,*,RIGHT,TALU2 +S 40,400,160,400,20,*,RIGHT,TALU2 +S 40,150,160,150,20,*,RIGHT,TALU2 +S 160,340,160,630,30,*,UP,PDIF +S 70,320,70,650,10,*,UP,PTRANS +S 40,340,40,630,30,*,UP,PDIF +S 130,320,130,650,10,*,UP,PTRANS +S 100,340,100,630,30,*,UP,PDIF +S 130,10,130,190,10,*,DOWN,NTRANS +S 70,10,70,190,10,*,UP,NTRANS +S 100,30,100,170,30,*,UP,NDIF +S 40,30,40,170,30,*,UP,NDIF +S 160,30,160,170,30,*,UP,NDIF +S 70,650,70,710,10,*,DOWN,POLY +S 130,650,130,710,10,*,UP,POLY +S 130,190,130,320,10,*,UP,POLY +S 70,190,70,320,10,*,DOWN,POLY +S 70,220,130,220,30,*,RIGHT,POLY +S 100,100,100,400,20,*,UP,ALU1 +S 160,50,160,150,20,*,UP,ALU1 +S 40,50,40,150,20,*,UP,ALU1 +S 160,280,160,680,20,*,UP,ALU1 +S 40,290,40,680,20,*,UP,ALU1 +S 100,150,100,600,20,nix,DOWN,CALU3 +S 0,470,250,470,60,vdd,RIGHT,CALU1 +S 0,530,250,530,60,vdd,RIGHT,CALU1 +S 0,500,250,500,460,*,RIGHT,NWELL +S 0,30,250,30,60,vss,RIGHT,CALU1 +S 0,970,250,970,60,vss,RIGHT,CALU1 +S 220,50,220,150,20,*,UP,ALU1 +S 100,700,100,700,10,i,LEFT,CALU1 +S 70,700,130,700,30,*,RIGHT,POLY +V 40,550,CONT_DIF_P,* +V 160,450,CONT_DIF_P,* +V 160,550,CONT_DIF_P,* +V 160,400,CONT_DIF_P,* +V 160,500,CONT_DIF_P,* +V 160,290,CONT_BODY_N,* +V 40,290,CONT_BODY_N,* +V 40,600,CONT_DIF_P,* +V 40,350,CONT_DIF_P,* +V 100,350,CONT_DIF_P,* +V 100,400,CONT_DIF_P,* +V 100,600,CONT_DIF_P,* +V 160,680,CONT_BODY_N,* +V 40,500,CONT_DIF_P,* +V 40,450,CONT_DIF_P,* +V 40,400,CONT_DIF_P,* +V 160,350,CONT_DIF_P,* +V 160,600,CONT_DIF_P,* +V 40,680,CONT_BODY_N,* +V 100,100,CONT_DIF_N,* +V 40,150,CONT_DIF_N,* +V 40,100,CONT_DIF_N,* +V 160,50,CONT_DIF_N,* +V 160,100,CONT_DIF_N,* +V 160,150,CONT_DIF_N,* +V 40,50,CONT_DIF_N,* +V 100,150,CONT_DIF_N,* +V 100,600,CONT_VIA,* +V 100,400,CONT_VIA,* +V 100,150,CONT_VIA,* +V 100,600,CONT_VIA2,* +V 100,150,CONT_VIA2,* +V 100,400,CONT_VIA2,* +V 220,30,CONT_BODY_P,* +V 220,150,CONT_BODY_P,* +V 100,700,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_rom2_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_rom2_buf.vbe new file mode 100644 index 00000000..2ba6597a --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_rom2_buf.vbe @@ -0,0 +1,19 @@ +ENTITY dp_rom2_buf IS +PORT ( + i : in BIT; + nix : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_rom2_buf; + +ARCHITECTURE vbe OF dp_rom2_buf IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_rom2_buf" + SEVERITY WARNING; + + nix <= not i; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_rom4_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_rom4_buf.ap new file mode 100644 index 00000000..f2171b4a --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_rom4_buf.ap @@ -0,0 +1,248 @@ +V ALLIANCE : 6 +H dp_rom4_buf,P, 4/ 8/2000,10 +A 0,0,550,1000 +R 100,400,ref_ref,i0 +R 450,400,ref_ref,ni0 +R 350,400,ref_ref,i1 +R 200,400,ref_ref,ni1 +S 400,850,400,850,10,i1,LEFT,CALU1 +S 150,850,150,850,10,i0,LEFT,CALU1 +S 400,50,400,150,20,*,UP,ALU1 +S 280,50,280,150,20,*,UP,ALU1 +S 520,280,520,680,20,*,UP,ALU1 +S 400,900,400,940,20,*,UP,ALU1 +S 520,900,520,970,20,*,UP,ALU1 +S 460,100,460,400,20,*,UP,ALU1 +S 340,660,340,900,20,*,UP,ALU1 +S 340,100,340,400,20,*,UP,ALU1 +S 520,50,520,150,20,*,UP,ALU1 +S 280,900,280,970,20,*,DOWN,ALU1 +S 400,280,400,740,20,*,UP,ALU1 +S 340,790,460,790,20,*,RIGHT,ALU1 +S 460,740,460,790,20,*,DOWN,ALU1 +S 150,50,150,150,20,*,UP,ALU1 +S 30,50,30,150,20,*,UP,ALU1 +S 430,820,430,860,10,*,DOWN,POLY +S 370,820,370,870,10,*,DOWN,POLY +S 310,190,310,320,10,*,DOWN,POLY +S 370,190,370,320,10,*,UP,POLY +S 490,190,490,320,10,*,UP,POLY +S 430,190,430,320,10,*,DOWN,POLY +S 310,660,370,660,30,*,RIGHT,POLY +S 370,850,430,850,30,*,RIGHT,POLY +S 460,30,460,170,30,*,UP,NDIF +S 340,890,340,960,30,*,UP,NDIF +S 400,890,400,960,30,*,UP,NDIF +S 400,30,400,170,30,*,UP,NDIF +S 520,30,520,170,30,*,UP,NDIF +S 280,30,280,170,30,*,UP,NDIF +S 340,30,340,170,30,*,UP,NDIF +S 210,30,210,170,30,*,UP,NDIF +S 150,30,150,170,30,*,UP,NDIF +S 30,30,30,170,30,*,UP,NDIF +S 90,30,90,170,30,*,UP,NDIF +S 310,10,310,190,10,*,UP,NTRANS +S 370,10,370,190,10,*,DOWN,NTRANS +S 490,10,490,190,10,*,DOWN,NTRANS +S 430,10,430,190,10,*,DOWN,NTRANS +S 370,870,370,980,10,*,UP,NTRANS +S 120,10,120,190,10,*,DOWN,NTRANS +S 240,10,240,190,10,*,DOWN,NTRANS +S 180,10,180,190,10,*,DOWN,NTRANS +S 60,10,60,190,10,*,UP,NTRANS +S 490,320,490,650,10,*,DOWN,PTRANS +S 460,340,460,630,30,*,UP,PDIF +S 430,320,430,650,10,*,UP,PTRANS +S 340,730,340,800,30,*,UP,PDIF +S 370,710,370,820,10,*,DOWN,PTRANS +S 410,730,410,800,30,*,UP,PDIF +S 430,710,430,820,10,*,DOWN,PTRANS +S 460,730,460,800,30,*,UP,PDIF +S 280,340,280,630,30,*,UP,PDIF +S 310,320,310,650,10,*,UP,PTRANS +S 400,340,400,630,30,*,UP,PDIF +S 340,340,340,630,30,*,UP,PDIF +S 370,320,370,650,10,*,UP,PTRANS +S 520,340,520,630,30,*,DOWN,PDIF +S 0,500,550,500,460,*,RIGHT,NWELL +S 60,660,120,660,30,*,RIGHT,POLY +S 180,320,180,650,10,*,UP,PTRANS +S 210,340,210,630,30,*,UP,PDIF +S 240,320,240,650,10,*,DOWN,PTRANS +S 90,340,90,630,30,*,UP,PDIF +S 150,340,150,630,30,*,UP,PDIF +S 60,320,60,650,10,*,UP,PTRANS +S 30,340,30,630,30,*,UP,PDIF +S 270,340,270,630,30,*,DOWN,PDIF +S 120,320,120,650,10,*,UP,PTRANS +S 150,900,150,940,20,*,UP,ALU1 +S 210,740,210,790,20,*,DOWN,ALU1 +S 90,790,210,790,20,*,RIGHT,ALU1 +S 30,900,30,970,20,*,DOWN,ALU1 +S 180,820,180,860,10,*,DOWN,POLY +S 120,820,120,870,10,*,DOWN,POLY +S 120,850,180,850,30,*,RIGHT,POLY +S 150,890,150,960,30,*,UP,NDIF +S 90,890,90,960,30,*,UP,NDIF +S 120,870,120,980,10,*,UP,NTRANS +S 120,710,120,820,10,*,DOWN,PTRANS +S 90,730,90,800,30,*,UP,PDIF +S 210,730,210,800,30,*,UP,PDIF +S 180,710,180,820,10,*,DOWN,PTRANS +S 160,730,160,800,30,*,UP,PDIF +S 90,660,90,900,20,*,UP,ALU1 +S 60,190,60,320,10,*,DOWN,POLY +S 120,190,120,320,10,*,DOWN,POLY +S 180,190,180,320,10,*,DOWN,POLY +S 240,190,240,320,10,*,DOWN,POLY +S 450,150,450,600,20,ni0x,DOWN,CALU3 +S 350,150,350,600,20,i1x,UP,CALU3 +S 100,150,100,600,20,i0x,UP,CALU3 +S 200,150,200,600,20,ni1x,UP,CALU3 +S 90,100,90,400,20,*,UP,ALU1 +S 210,100,210,400,20,*,UP,ALU1 +S 30,290,30,680,20,*,UP,ALU1 +S 150,280,150,740,20,*,UP,ALU1 +S 180,250,270,250,30,*,RIGHT,POLY +S 270,250,340,250,20,*,RIGHT,ALU1 +S 400,200,490,200,30,*,RIGHT,POLY +S 100,200,400,200,20,*,RIGHT,ALU2 +S 60,250,120,250,30,*,RIGHT,POLY +S 310,200,370,200,30,*,RIGHT,POLY +S 70,580,480,580,460,*,RIGHT,NWELL +S 280,350,280,680,20,*,UP,ALU1 +S 0,970,550,970,60,vss,RIGHT,CALU1 +S 0,30,550,30,60,vss,RIGHT,CALU1 +S 0,470,550,470,60,vdd,RIGHT,CALU1 +S 0,530,550,530,60,vdd,RIGHT,CALU1 +S 100,600,450,600,20,*,RIGHT,TALU2 +S 100,400,450,400,20,*,RIGHT,TALU2 +S 100,200,400,200,20,*,RIGHT,TALU2 +S 100,150,450,150,20,*,RIGHT,TALU2 +V 450,600,CONT_VIA2,* +V 350,150,CONT_VIA2,* +V 450,400,CONT_VIA2,* +V 450,150,CONT_VIA2,* +V 350,400,CONT_VIA2,* +V 350,600,CONT_VIA2,* +V 200,150,CONT_VIA2,* +V 100,150,CONT_VIA2,* +V 450,600,CONT_VIA,* +V 450,400,CONT_VIA,* +V 350,150,CONT_VIA,* +V 350,400,CONT_VIA,* +V 450,150,CONT_VIA,* +V 350,600,CONT_VIA,* +V 200,150,CONT_VIA,* +V 100,150,CONT_VIA,* +V 400,850,CONT_POLY,* +V 340,660,CONT_POLY,* +V 520,970,CONT_BODY_P,* +V 280,970,CONT_BODY_P,* +V 520,900,CONT_BODY_P,* +V 280,900,CONT_BODY_P,* +V 400,50,CONT_DIF_N,* +V 400,150,CONT_DIF_N,* +V 340,900,CONT_DIF_N,* +V 340,150,CONT_DIF_N,* +V 340,100,CONT_DIF_N,* +V 400,900,CONT_DIF_N,* +V 400,950,CONT_DIF_N,* +V 460,100,CONT_DIF_N,* +V 520,50,CONT_DIF_N,* +V 520,150,CONT_DIF_N,* +V 460,150,CONT_DIF_N,* +V 280,50,CONT_DIF_N,* +V 280,150,CONT_DIF_N,* +V 280,100,CONT_DIF_N,* +V 400,100,CONT_DIF_N,* +V 520,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 210,150,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 30,150,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 280,680,CONT_BODY_N,* +V 340,350,CONT_DIF_P,* +V 340,400,CONT_DIF_P,* +V 340,600,CONT_DIF_P,* +V 460,600,CONT_DIF_P,* +V 460,790,CONT_DIF_P,* +V 460,740,CONT_DIF_P,* +V 400,680,CONT_BODY_N,* +V 520,680,CONT_BODY_N,* +V 520,400,CONT_DIF_P,* +V 520,350,CONT_DIF_P,* +V 520,450,CONT_DIF_P,* +V 520,500,CONT_DIF_P,* +V 520,550,CONT_DIF_P,* +V 520,600,CONT_DIF_P,* +V 460,400,CONT_DIF_P,* +V 460,350,CONT_DIF_P,* +V 280,500,CONT_DIF_P,* +V 280,450,CONT_DIF_P,* +V 280,400,CONT_DIF_P,* +V 400,350,CONT_DIF_P,* +V 400,450,CONT_DIF_P,* +V 400,550,CONT_DIF_P,* +V 400,400,CONT_DIF_P,* +V 400,500,CONT_DIF_P,* +V 400,740,CONT_DIF_P,* +V 340,740,CONT_DIF_P,* +V 400,290,CONT_BODY_N,* +V 520,290,CONT_BODY_N,* +V 280,600,CONT_DIF_P,* +V 280,350,CONT_DIF_P,* +V 280,550,CONT_DIF_P,* +V 340,790,CONT_DIF_P,* +V 200,400,CONT_VIA2,* +V 200,600,CONT_VIA2,* +V 100,600,CONT_VIA2,* +V 100,400,CONT_VIA2,* +V 200,400,CONT_VIA,* +V 200,600,CONT_VIA,* +V 100,600,CONT_VIA,* +V 100,400,CONT_VIA,* +V 90,660,CONT_POLY,* +V 30,680,CONT_BODY_N,* +V 210,600,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 150,680,CONT_BODY_N,* +V 150,550,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,500,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 30,290,CONT_BODY_N,* +V 150,290,CONT_BODY_N,* +V 150,500,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 150,850,CONT_POLY,* +V 30,900,CONT_BODY_P,* +V 30,970,CONT_BODY_P,* +V 150,950,CONT_DIF_N,* +V 150,900,CONT_DIF_N,* +V 90,900,CONT_DIF_N,* +V 210,740,CONT_DIF_P,* +V 210,790,CONT_DIF_P,* +V 90,740,CONT_DIF_P,* +V 150,740,CONT_DIF_P,* +V 90,790,CONT_DIF_P,* +V 260,250,CONT_POLY,* +V 410,200,CONT_POLY,* +V 400,200,CONT_VIA,* +V 100,200,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_rom4_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_rom4_buf.vbe new file mode 100644 index 00000000..e19f8fc2 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_rom4_buf.vbe @@ -0,0 +1,26 @@ +ENTITY dp_rom4_buf IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i0x : out BIT; + i1x : out BIT; + ni0x : out BIT; + ni1x : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_rom4_buf; + +ARCHITECTURE vbe OF dp_rom4_buf IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_rom4_buf" + SEVERITY WARNING; + + i0x <= i0; + i1x <= i1; + ni0x <= not i0; + ni1x <= not i1; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_rom4_nxr2_x4.ap b/alliance/src/cells/src/dp_sxlib/dp_rom4_nxr2_x4.ap new file mode 100644 index 00000000..3007651c --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_rom4_nxr2_x4.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H dp_rom4_nxr2_x4,P,27/10/2000,100 +A 0,0,5500,5000 +R 3500,2500,ref_ref,i1x +R 2000,2000,ref_ref,ni1x +R 4500,2000,ref_ref,ni0x +R 1000,2500,ref_ref,i0x +R 5000,3500,ref_ref,q_35 +R 5000,4000,ref_ref,q_40 +R 5000,2500,ref_ref,q_25 +R 5000,2000,ref_ref,q_20 +R 5000,1500,ref_ref,q_15 +R 5000,1000,ref_ref,q_10 +R 5000,3000,ref_ref,q_30 +S 1700,1500,2000,1500,200,*,LEFT,ALU1 +S 2000,2500,2400,2500,200,*,RIGHT,ALU1 +S 2000,1500,2000,2500,100,*,DOWN,ALU1 +S 3400,2500,3400,3000,100,*,UP,ALU1 +S 3400,2500,3500,2500,100,*,LEFT,ALU1 +S 3500,1500,3500,2500,100,*,UP,ALU1 +S 3400,1500,3500,1500,100,*,RIGHT,ALU1 +S 3400,1000,3400,1500,100,*,DOWN,ALU1 +S 2100,3000,3400,3000,100,*,RIGHT,ALU1 +S 2100,1000,3400,1000,100,*,RIGHT,ALU1 +S 3000,400,3000,1400,100,*,DOWN,NTRANS +S 2400,400,2400,1400,100,*,DOWN,NTRANS +S 1800,400,1800,1400,100,*,DOWN,NTRANS +S 1200,400,1200,1400,100,*,DOWN,NTRANS +S 2100,600,2100,1200,300,*,UP,NDIF +S 1500,600,1500,1200,300,*,UP,NDIF +S 2700,600,2700,1200,300,*,UP,NDIF +S 3900,1000,5000,1000,200,*,LEFT,ALU1 +S 3900,3000,5000,3000,200,*,RIGHT,ALU1 +S 3900,3000,3900,4000,200,*,DOWN,ALU1 +S 3000,2000,4500,2000,200,*,RIGHT,ALU2 +S 2000,2000,4500,2000,200,*,RIGHT,TALU2 +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 3600,100,3600,1400,100,*,DOWN,NTRANS +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 3900,300,3900,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 3400,1500,4200,1500,300,*,RIGHT,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 5000,1000,5000,4000,200,q,DOWN,CALU1 +S 2500,2500,3500,2500,200,*,RIGHT,ALU2 +S 1000,2500,3500,2500,200,*,RIGHT,TALU2 +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 0,3900,5500,3900,2400,*,LEFT,NWELL +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 1500,2800,1500,4200,300,*,DOWN,PDIF +S 2100,2800,2100,4200,300,*,DOWN,PDIF +S 2400,2600,2400,4400,100,*,UP,PTRANS +S 2700,2800,2700,4200,300,*,DOWN,PDIF +S 3000,2600,3000,4400,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 1800,2000,1800,2600,100,*,DOWN,POLY +S 1800,2000,2400,2000,100,*,LEFT,POLY +S 2400,1400,2400,2000,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 900,3000,900,4500,200,*,DOWN,ALU1 +S 2100,3000,2100,4000,100,*,DOWN,ALU1 +S 900,500,900,1700,200,*,DOWN,ALU1 +S 3300,3500,3300,4500,200,*,DOWN,ALU1 +S 2000,2000,2500,2000,200,*,RIGHT,ALU2 +S 4500,2000,4500,2000,200,ni0x,LEFT,CALU3 +S 2000,2000,2000,2000,200,ni1x,LEFT,CALU3 +S 1000,2500,1000,2500,200,i0x,LEFT,CALU3 +S 3500,2500,3500,2500,200,i1x,LEFT,CALU3 +V 300,300,CONT_BODY_P,* +V 5200,300,CONT_BODY_P,* +V 5200,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 4500,2000,CONT_VIA2,* +V 3500,2500,CONT_VIA2,* +V 3900,3000,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 3900,4000,CONT_DIF_P,* +V 4500,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 3400,1500,CONT_POLY,* +V 900,3000,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2700,4700,CONT_BODY_N,* +V 2100,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 2100,3500,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,1700,CONT_BODY_P,* +V 3000,2000,CONT_POLY,* +V 1100,2500,CONT_POLY,* +V 1700,1500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_VIA,* +V 2500,2000,CONT_VIA,* +V 2500,2500,CONT_VIA,* +V 1000,2500,CONT_VIA,* +V 2000,2000,CONT_VIA2,* +V 1000,2500,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_rom4_nxr2_x4.vbe b/alliance/src/cells/src/dp_sxlib/dp_rom4_nxr2_x4.vbe new file mode 100644 index 00000000..f7c6d3b2 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_rom4_nxr2_x4.vbe @@ -0,0 +1,30 @@ +ENTITY dp_rom4_nxr2_x4 IS +PORT ( + i0x : in BIT; + i1x : in BIT; + ni0x : in BIT; + ni1x : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_rom4_nxr2_x4; + +ARCHITECTURE vbe OF dp_rom4_nxr2_x4 IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_rom4_nxr2_x4" + SEVERITY WARNING; + + ASSERT (i0x xor ni0x) + REPORT "wrong control signals on dp_rom4_nxr2_x4" + SEVERITY WARNING; + + ASSERT (i1x xor ni1x) + REPORT "wrong control signals on dp_rom4_nxr2_x4" + SEVERITY WARNING; + + q <= not (i0x xor i1x); + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_rom4_xr2_x4.ap b/alliance/src/cells/src/dp_sxlib/dp_rom4_xr2_x4.ap new file mode 100644 index 00000000..e86dd575 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_rom4_xr2_x4.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H dp_rom4_xr2_x4,P,27/10/2000,100 +A 0,0,5500,5000 +R 4500,2000,ref_ref,ni0x +R 2100,2000,ref_ref,ni1x +R 3500,2500,ref_ref,i1x +R 1000,2500,ref_ref,i0x +R 5000,3000,ref_ref,q_30 +R 5000,1000,ref_ref,q_10 +R 5000,1500,ref_ref,q_15 +R 5000,2000,ref_ref,q_20 +R 5000,2500,ref_ref,q_25 +R 5000,4000,ref_ref,q_40 +R 5000,3500,ref_ref,q_35 +S 3400,2500,3400,3000,100,*,UP,ALU1 +S 3400,2500,3500,2500,100,*,RIGHT,ALU1 +S 3500,1500,3500,2500,100,*,UP,ALU1 +S 3400,1500,3500,1500,100,*,RIGHT,ALU1 +S 3400,1000,3400,1500,100,*,DOWN,ALU1 +S 2000,1500,2500,1500,200,*,LEFT,ALU1 +S 1700,2500,2000,2500,200,*,RIGHT,ALU1 +S 2000,1500,2000,2500,100,*,DOWN,ALU1 +S 2000,2000,2000,2000,200,ni1x,LEFT,CALU3 +S 4500,2000,4500,2000,200,ni0x,LEFT,CALU3 +S 2000,2000,2500,2000,200,*,RIGHT,ALU2 +S 3300,3500,3300,4500,200,*,DOWN,ALU1 +S 900,500,900,1700,200,*,DOWN,ALU1 +S 2100,3000,2100,4000,100,*,DOWN,ALU1 +S 900,3000,900,4500,200,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,2000,2400,2000,100,*,LEFT,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 900,300,900,1200,300,*,UP,NDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 3000,2600,3000,4400,100,*,UP,PTRANS +S 2700,2800,2700,4200,300,*,DOWN,PDIF +S 2400,2600,2400,4400,100,*,UP,PTRANS +S 2100,2800,2100,4200,300,*,DOWN,PDIF +S 1500,2800,1500,4200,300,*,DOWN,PDIF +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,5500,3900,2400,*,LEFT,NWELL +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 1000,2500,3500,2500,200,*,RIGHT,TALU2 +S 5000,1000,5000,4000,200,q,DOWN,CALU1 +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3400,1500,4200,1500,300,*,RIGHT,POLY +S 4500,300,4500,1200,300,*,UP,NDIF +S 3900,300,3900,1200,300,*,UP,NDIF +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 3600,100,3600,1400,100,*,DOWN,NTRANS +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 2000,2000,4500,2000,200,*,RIGHT,TALU2 +S 3000,2000,4500,2000,200,*,RIGHT,ALU2 +S 2100,1000,3400,1000,100,*,RIGHT,ALU1 +S 2100,3000,3400,3000,100,*,RIGHT,ALU1 +S 3900,3000,3900,4000,200,*,DOWN,ALU1 +S 3900,3000,5000,3000,200,*,RIGHT,ALU1 +S 3900,1000,5000,1000,200,*,LEFT,ALU1 +S 2700,600,2700,1200,300,*,UP,NDIF +S 1500,600,1500,1200,300,*,UP,NDIF +S 2100,600,2100,1200,300,*,UP,NDIF +S 1200,400,1200,1400,100,*,DOWN,NTRANS +S 1800,400,1800,1400,100,*,DOWN,NTRANS +S 2400,400,2400,1400,100,*,DOWN,NTRANS +S 3000,400,3000,1400,100,*,DOWN,NTRANS +S 2400,2000,2400,2600,100,*,DOWN,POLY +S 1800,1400,1800,2000,100,*,DOWN,POLY +S 1700,2500,3500,2500,200,*,RIGHT,ALU2 +S 3500,2500,3500,2500,200,i1x,LEFT,CALU3 +S 1000,2500,1000,2500,200,i0x,LEFT,CALU3 +V 1000,2500,CONT_VIA2,* +V 2000,2000,CONT_VIA2,* +V 1000,2500,CONT_VIA,* +V 2500,2000,CONT_VIA,* +V 3000,2000,CONT_VIA,* +V 2500,2000,CONT_POLY,* +V 1100,2500,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 900,1700,CONT_BODY_P,* +V 3300,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 2100,4700,CONT_BODY_N,* +V 2700,4700,CONT_BODY_N,* +V 2100,4000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 900,3000,CONT_DIF_P,* +V 3400,1500,CONT_POLY,* +V 3900,1000,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 3900,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 3900,3000,CONT_DIF_P,* +V 3500,2500,CONT_VIA2,* +V 4500,2000,CONT_VIA2,* +V 300,4700,CONT_BODY_N,* +V 5200,4700,CONT_BODY_N,* +V 5200,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 1700,2500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 1700,2500,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_rom4_xr2_x4.vbe b/alliance/src/cells/src/dp_sxlib/dp_rom4_xr2_x4.vbe new file mode 100644 index 00000000..ff955028 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_rom4_xr2_x4.vbe @@ -0,0 +1,30 @@ +ENTITY dp_rom4_xr2_x4 IS +PORT ( + i0x : in BIT; + i1x : in BIT; + ni0x : in BIT; + ni1x : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_rom4_xr2_x4; + +ARCHITECTURE vbe OF dp_rom4_xr2_x4 IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_rom4_xr2_x4" + SEVERITY WARNING; + + ASSERT (i0x xor ni0x) + REPORT "wrong control signals on dp_rom4_xr2_x4" + SEVERITY WARNING; + + ASSERT (i1x xor ni1x) + REPORT "wrong control signals on dp_rom4_xr2_x4" + SEVERITY WARNING; + + q <= i0x xor i1x; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4.ap b/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4.ap new file mode 100644 index 00000000..bd78b215 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4.ap @@ -0,0 +1,277 @@ +V ALLIANCE : 6 +H dp_sff_scan_x4,P,14/11/2000,10 +A 0,0,1200,500 +R 1100,200,ref_ref,q_20 +R 1100,100,ref_ref,q_10 +R 1100,400,ref_ref,q_40 +R 1100,350,ref_ref,q_35 +R 1100,300,ref_ref,q_30 +R 1100,250,ref_ref,q_25 +R 1100,150,ref_ref,q_15 +R 100,100,ref_ref,i_10 +R 100,300,ref_ref,i_30 +R 100,350,ref_ref,i_35 +R 100,200,ref_ref,i_20 +R 100,150,ref_ref,i_15 +R 100,400,ref_ref,i_40 +R 150,200,ref_ref,nwenx +R 250,200,ref_ref,wenx +R 400,250,ref_ref,nscanx +R 500,250,ref_ref,scanx +R 650,250,ref_ref,nckx +R 750,250,ref_ref,ckx +S 150,200,250,200,20,*,RIGHT,TALU2 +S 250,200,250,200,20,wenx,LEFT,CALU3 +S 150,200,150,200,20,nwenx,LEFT,CALU3 +S 400,250,400,250,20,nscanx,LEFT,CALU3 +S 500,250,500,250,20,scanx,LEFT,CALU3 +S 650,250,650,250,20,nckx,LEFT,CALU3 +S 750,250,750,250,20,ckx,LEFT,CALU3 +S 50,250,350,250,20,*,RIGHT,ALU2 +S 1170,300,1170,450,20,*,DOWN,ALU1 +S 650,300,700,300,10,*,RIGHT,ALU1 +S 700,200,700,300,10,*,UP,ALU1 +S 600,150,600,400,10,u,DOWN,ALU1 +S 690,350,750,350,10,*,RIGHT,ALU1 +S 1170,50,1170,100,20,*,DOWN,ALU1 +S 930,400,990,400,10,*,RIGHT,ALU1 +S 750,150,820,150,10,*,LEFT,ALU1 +S 930,200,930,350,10,*,DOWN,ALU1 +S 750,300,820,300,10,*,RIGHT,ALU1 +S 1050,300,1050,450,20,*,DOWN,ALU1 +S 990,100,990,400,10,z,DOWN,ALU1 +S 930,100,990,100,10,*,RIGHT,ALU1 +S 690,100,750,100,10,*,RIGHT,ALU1 +S 800,100,870,100,10,*,RIGHT,ALU1 +S 750,100,750,350,10,x,DOWN,ALU1 +S 870,100,870,400,10,y,DOWN,ALU1 +S 800,350,870,350,10,*,LEFT,ALU1 +S 1050,50,1050,100,20,*,DOWN,ALU1 +S 400,100,500,100,10,*,RIGHT,ALU1 +S 450,400,600,400,10,*,RIGHT,ALU1 +S 500,100,500,300,10,*,DOWN,ALU1 +S 450,150,450,400,10,*,DOWN,ALU1 +S 800,200,800,250,10,*,DOWN,ALU1 +S 400,100,400,150,10,*,UP,ALU1 +S 350,150,350,300,10,*,DOWN,ALU1 +S 250,300,250,400,10,*,UP,ALU1 +S 300,150,300,300,10,*,UP,ALU1 +S 150,400,250,400,10,*,RIGHT,ALU1 +S 200,100,200,350,10,*,UP,ALU1 +S 150,150,150,400,10,*,DOWN,ALU1 +S 30,100,30,350,10,*,DOWN,ALU1 +S 30,250,50,250,30,*,RIGHT,ALU1 +S 810,300,840,300,30,*,RIGHT,POLY +S 930,350,960,350,30,*,RIGHT,POLY +S 780,350,810,350,30,*,RIGHT,POLY +S 810,150,840,150,30,*,RIGHT,POLY +S 720,250,720,310,10,*,DOWN,POLY +S 1140,140,1140,260,10,*,DOWN,POLY +S 900,140,900,200,10,*,DOWN,POLY +S 840,300,840,360,10,*,DOWN,POLY +S 1020,250,1050,250,30,*,RIGHT,POLY +S 900,250,900,360,10,*,DOWN,POLY +S 720,140,720,200,10,*,DOWN,POLY +S 900,200,930,200,30,*,RIGHT,POLY +S 690,200,720,200,30,*,RIGHT,POLY +S 960,140,960,250,10,*,DOWN,POLY +S 1080,140,1080,260,10,*,DOWN,POLY +S 840,90,840,150,10,*,UP,POLY +S 780,100,810,100,30,*,RIGHT,POLY +S 1020,150,1050,150,30,*,RIGHT,POLY +S 500,140,500,250,10,*,DOWN,POLY +S 400,250,500,250,10,*,RIGHT,POLY +S 650,250,960,250,10,nckx,RIGHT,POLY +S 700,200,900,200,10,ckx,RIGHT,POLY +S 660,140,660,250,10,*,UP,POLY +S 400,250,400,310,10,*,DOWN,POLY +S 160,90,160,150,10,*,DOWN,POLY +S 90,300,120,300,30,*,RIGHT,POLY +S 260,90,260,250,10,*,DOWN,POLY +S 90,100,120,100,30,*,RIGHT,POLY +S 300,90,300,150,10,*,DOWN,POLY +S 160,250,160,310,10,*,DOWN,POLY +S 160,250,260,250,10,*,RIGHT,POLY +S 60,200,200,200,10,*,RIGHT,POLY +S 60,90,60,310,10,*,DOWN,POLY +S 1110,30,1110,120,30,*,DOWN,NDIF +S 1170,30,1170,120,30,*,DOWN,NDIF +S 990,80,990,120,30,*,DOWN,NDIF +S 930,80,930,120,30,*,DOWN,NDIF +S 690,80,690,120,30,*,DOWN,NDIF +S 750,30,750,120,30,*,DOWN,NDIF +S 630,80,630,120,30,*,DOWN,NDIF +S 570,40,570,120,30,*,DOWN,NDIF +S 450,80,450,160,30,*,DOWN,NDIF +S 570,40,570,120,30,*,UP,NDIF +S 870,30,870,70,30,*,DOWN,NDIF +S 810,30,810,70,30,*,DOWN,NDIF +S 870,30,870,120,30,*,DOWN,NDIF +S 1050,30,1050,120,30,*,DOWN,NDIF +S 330,30,330,120,30,*,UP,NDIF +S 450,80,450,120,60,*,DOWN,NDIF +S 30,30,30,110,30,*,UP,NDIF +S 200,30,200,110,30,*,DOWN,NDIF +S 90,30,90,70,30,*,DOWN,NDIF +S 220,30,220,70,50,*,DOWN,NDIF +S 720,60,720,140,10,*,UP,NTRANS +S 600,60,600,140,10,*,UP,NTRANS +S 1080,10,1080,140,10,*,UP,NTRANS +S 900,60,900,140,10,*,UP,NTRANS +S 660,60,660,140,10,*,UP,NTRANS +S 1140,10,1140,140,10,*,UP,NTRANS +S 1020,60,1020,140,10,*,UP,NTRANS +S 960,60,960,140,10,*,UP,NTRANS +S 400,60,400,140,10,*,UP,NTRANS +S 360,60,360,140,10,*,UP,NTRANS +S 500,60,500,140,10,*,UP,NTRANS +S 540,60,540,140,10,*,UP,NTRANS +S 840,10,840,90,10,*,UP,NTRANS +S 780,10,780,90,10,*,UP,NTRANS +S 260,10,260,90,10,*,UP,NTRANS +S 300,10,300,90,10,*,UP,NTRANS +S 160,10,160,90,10,*,UP,NTRANS +S 120,10,120,90,10,*,UP,NTRANS +S 60,10,60,90,10,*,UP,NTRANS +S 1140,260,1140,490,10,*,DOWN,PTRANS +S 1170,280,1170,470,30,*,DOWN,PDIF +S 660,310,660,440,10,*,DOWN,PTRANS +S 690,330,690,420,30,*,UP,PDIF +S 720,310,720,440,10,*,DOWN,PTRANS +S 750,330,750,470,30,*,UP,PDIF +S 1080,260,1080,490,10,*,DOWN,PTRANS +S 1050,280,1050,470,30,*,DOWN,PDIF +S 930,380,930,470,30,*,DOWN,PDIF +S 960,360,960,490,10,*,DOWN,PTRANS +S 800,380,800,470,30,*,DOWN,PDIF +S 990,380,990,470,30,*,UP,PDIF +S 1020,360,1020,490,10,*,DOWN,PTRANS +S 780,360,780,490,10,*,DOWN,PTRANS +S 840,360,840,490,10,*,UP,PTRANS +S 1110,280,1110,470,30,*,DOWN,PDIF +S 600,310,600,440,10,*,DOWN,PTRANS +S 630,330,630,420,30,*,UP,PDIF +S 540,310,540,440,10,*,DOWN,PTRANS +S 570,330,570,460,30,*,DOWN,PDIF +S 500,310,500,440,10,*,DOWN,PTRANS +S 860,380,860,470,30,*,DOWN,PDIF +S 900,360,900,490,10,*,DOWN,PTRANS +S 450,330,450,420,60,*,DOWN,PDIF +S 400,310,400,440,10,*,DOWN,PTRANS +S 360,310,360,440,10,*,DOWN,PTRANS +S 330,330,330,460,30,*,DOWN,PDIF +S 160,310,160,440,10,*,DOWN,PTRANS +S 120,310,120,440,10,*,DOWN,PTRANS +S 60,310,60,440,10,*,DOWN,PTRANS +S 30,330,30,420,30,*,DOWN,PDIF +S 0,390,1200,390,240,*,RIGHT,NWELL +S 260,310,260,440,10,*,DOWN,PTRANS +S 300,310,300,440,10,*,DOWN,PTRANS +S 90,330,90,460,30,*,DOWN,PDIF +S 210,330,210,420,60,*,UP,PDIF +S 750,250,800,250,20,*,RIGHT,ALU2 +S 1020,240,1020,360,10,*,DOWN,POLY +S 990,200,1040,200,10,*,RIGHT,ALU1 +S 1040,200,1140,200,30,*,RIGHT,POLY +S 0,30,1200,30,60,vss,RIGHT,CALU1 +S 0,470,1200,470,60,vdd,RIGHT,CALU1 +S 50,250,800,250,20,*,RIGHT,TALU2 +S 300,200,1100,200,20,q,RIGHT,CALU2 +S 550,150,550,300,10,scin,DOWN,CALU1 +S 100,100,100,400,20,i,DOWN,CALU1 +S 1100,100,1100,400,20,q,DOWN,CALU1 +S 1040,150,1100,150,10,*,RIGHT,ALU1 +S 1040,250,1100,250,10,*,RIGHT,ALU1 +V 650,250,CONT_VIA2,* +V 500,250,CONT_VIA2,* +V 400,250,CONT_VIA2,* +V 250,200,CONT_VIA2,* +V 150,200,CONT_VIA2,* +V 400,250,CONT_VIA,* +V 650,250,CONT_VIA,* +V 800,250,CONT_VIA,* +V 350,250,CONT_VIA,* +V 500,250,CONT_VIA,* +V 300,200,CONT_VIA,* +V 50,250,CONT_VIA,* +V 150,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 650,300,CONT_POLY,* +V 1040,250,CONT_POLY,* +V 1040,150,CONT_POLY,* +V 820,150,CONT_POLY,* +V 920,200,CONT_POLY,* +V 820,300,CONT_POLY,* +V 700,200,CONT_POLY,* +V 940,350,CONT_POLY,* +V 600,150,CONT_POLY,* +V 650,250,CONT_POLY,* +V 550,300,CONT_POLY,* +V 600,300,CONT_POLY,* +V 550,150,CONT_POLY,* +V 500,300,CONT_POLY,* +V 800,100,CONT_POLY,* +V 800,350,CONT_POLY,* +V 350,150,CONT_POLY,* +V 800,200,CONT_POLY,* +V 400,250,CONT_POLY,* +V 400,150,CONT_POLY,* +V 350,300,CONT_POLY,* +V 250,200,CONT_POLY,* +V 200,200,CONT_POLY,* +V 300,300,CONT_POLY,* +V 150,150,CONT_POLY,* +V 100,300,CONT_POLY,* +V 300,150,CONT_POLY,* +V 250,300,CONT_POLY,* +V 100,100,CONT_POLY,* +V 650,30,CONT_BODY_P,* +V 400,30,CONT_BODY_P,* +V 500,30,CONT_BODY_P,* +V 930,30,CONT_BODY_P,* +V 990,30,CONT_BODY_P,* +V 330,50,CONT_DIF_N,* +V 1050,100,CONT_DIF_N,* +V 1110,100,CONT_DIF_N,* +V 570,50,CONT_DIF_N,* +V 450,150,CONT_DIF_N,* +V 930,100,CONT_DIF_N,* +V 810,50,CONT_DIF_N,* +V 690,100,CONT_DIF_N,* +V 870,100,CONT_DIF_N,* +V 1170,50,CONT_DIF_N,* +V 1050,50,CONT_DIF_N,* +V 1170,100,CONT_DIF_N,* +V 200,100,CONT_DIF_N,* +V 90,50,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 650,470,CONT_BODY_N,* +V 1050,350,CONT_DIF_P,* +V 1050,400,CONT_DIF_P,* +V 1170,450,CONT_DIF_P,* +V 1050,450,CONT_DIF_P,* +V 1050,300,CONT_DIF_P,* +V 1170,400,CONT_DIF_P,* +V 1170,350,CONT_DIF_P,* +V 1110,400,CONT_DIF_P,* +V 930,400,CONT_DIF_P,* +V 810,450,CONT_DIF_P,* +V 1110,350,CONT_DIF_P,* +V 690,350,CONT_DIF_P,* +V 330,450,CONT_DIF_P,* +V 400,470,CONT_BODY_N,* +V 450,350,CONT_DIF_P,* +V 570,450,CONT_DIF_P,* +V 500,470,CONT_BODY_N,* +V 870,400,CONT_DIF_P,* +V 1170,300,CONT_DIF_P,* +V 1110,300,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 250,470,CONT_BODY_N,* +V 150,470,CONT_BODY_N,* +V 200,350,CONT_DIF_P,* +V 90,450,CONT_DIF_P,* +V 750,250,CONT_VIA2,* +V 1040,200,CONT_POLY,* +V 1100,200,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4.vbe b/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4.vbe new file mode 100644 index 00000000..ed25a65d --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4.vbe @@ -0,0 +1,43 @@ +ENTITY dp_sff_scan_x4 IS +PORT ( + ckx : in BIT; + nckx : in BIT; + wenx : in BIT; + nwenx : in BIT; + scanx : in BIT; + nscanx : in BIT; + i : in BIT; + scin : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_sff_scan_x4; + +ARCHITECTURE vbe OF dp_sff_scan_x4 IS + SIGNAL ff : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on dp_sff_scan_x4" + SEVERITY WARNING; + + ASSERT (ckx xor nckx) + REPORT "wrong values for ckx and nckx in dp_sff_scan_x4" + SEVERITY WARNING; + + ASSERT (wenx xor nwenx) + REPORT "wrong values for wenx and nwenx in dp_sff_scan_x4" + SEVERITY WARNING; + + ASSERT (scanx xor nscanx) + REPORT "wrong values for scanx and nscanx in dp_sff_scan_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1') + BEGIN + ff <= GUARDED ((scanx and scin) or (nscanx and ((wenx and i) or (nwenx and ff)))); + END BLOCK label0; + + q <= ff; +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4_buf.ap new file mode 100644 index 00000000..ef9bd6df --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4_buf.ap @@ -0,0 +1,403 @@ +V ALLIANCE : 6 +H dp_sff_scan_x4_buf,P,16/11/2000,100 +A 0,0,12000,10000 +R 9000,6500,ref_ref,scin +R 10500,4000,ref_ref,scout_40 +R 10500,3500,ref_ref,scout_35 +R 10500,3000,ref_ref,scout_30 +R 10500,2500,ref_ref,scout_25 +R 10500,2000,ref_ref,scout_20 +R 10500,1500,ref_ref,scout_15 +R 10500,1000,ref_ref,scout_10 +R 1500,4000,ref_ref,nwenx +R 2500,4000,ref_ref,wenx +R 4000,4000,ref_ref,nscanx +R 5000,4000,ref_ref,scanx +R 6500,4000,ref_ref,nckx +R 7500,4000,ref_ref,ckx +S 7500,1500,7500,6000,200,ckx,DOWN,CALU3 +S 9000,6500,9000,6500,100,scin,LEFT,CALU1 +S 2000,8500,2000,8500,100,wen,LEFT,CALU1 +S 4500,8500,4500,8500,100,scan,LEFT,CALU1 +S 7000,8500,7000,8500,100,ck,LEFT,CALU1 +S 9000,6500,9600,6500,100,*,RIGHT,POLY +S 9600,4300,9600,6500,100,*,DOWN,POLY +S 9300,1400,9300,1700,300,*,UP,NDIF +S 9600,1200,9600,1900,100,*,DOWN,NTRANS +S 9300,3400,9300,4100,300,*,DOWN,PDIF +S 9600,3200,9600,4300,100,*,UP,PTRANS +S 1900,2200,2600,2200,200,*,RIGHT,ALU1 +S 1100,2200,1900,2200,300,*,RIGHT,POLY +S 2300,2200,2900,2200,300,*,RIGHT,POLY +S 2600,6600,2600,7900,200,*,DOWN,ALU1 +S 1400,7400,1400,9000,200,*,UP,ALU1 +S 2300,6600,2900,6600,300,*,RIGHT,POLY +S 0,5000,12000,5000,4600,*,RIGHT,NWELL +S 3200,9000,3200,9700,200,*,UP,ALU1 +S 2600,1000,2600,4000,200,*,UP,ALU1 +S 1400,1000,1400,4000,200,*,UP,ALU1 +S 3200,500,3200,1500,200,*,UP,ALU1 +S 800,9000,800,9700,200,*,DOWN,ALU1 +S 2000,2800,2000,7400,200,*,UP,ALU1 +S 2000,500,2000,1500,200,*,UP,ALU1 +S 800,500,800,1500,200,*,UP,ALU1 +S 3200,2800,3200,6800,200,*,UP,ALU1 +S 800,3500,800,6800,200,*,UP,ALU1 +S 2000,9000,2000,9400,200,*,UP,ALU1 +S 1400,7900,2600,7900,200,*,RIGHT,ALU1 +S 5700,2800,5700,6800,200,*,UP,ALU1 +S 4500,500,4500,1500,200,*,UP,ALU1 +S 5700,500,5700,1500,200,*,UP,ALU1 +S 3900,1000,3900,4000,200,*,UP,ALU1 +S 5100,1000,5100,4000,200,*,UP,ALU1 +S 8200,2800,8200,6800,200,*,UP,ALU1 +S 7600,1000,7600,4000,200,*,UP,ALU1 +S 6400,1000,6400,4000,200,*,UP,ALU1 +S 8200,500,8200,1500,200,*,UP,ALU1 +S 7000,500,7000,1500,200,*,UP,ALU1 +S 3900,7900,5100,7900,200,*,RIGHT,ALU1 +S 4500,9000,4500,9400,200,*,UP,ALU1 +S 5700,9000,5700,9700,200,*,UP,ALU1 +S 7000,9000,7000,9400,200,*,UP,ALU1 +S 6400,7900,7600,7900,200,*,RIGHT,ALU1 +S 1700,1900,1700,3200,100,*,UP,POLY +S 2900,1900,2900,3200,100,*,UP,POLY +S 2300,1900,2300,3200,100,*,DOWN,POLY +S 1700,8500,2300,8500,300,*,RIGHT,POLY +S 2300,8200,2300,8600,100,*,DOWN,POLY +S 1700,8200,1700,8700,100,*,DOWN,POLY +S 1100,1900,1100,3200,100,*,DOWN,POLY +S 3600,1900,3600,3200,100,*,DOWN,POLY +S 4800,1900,4800,3200,100,*,DOWN,POLY +S 5400,1900,5400,3200,100,*,UP,POLY +S 4200,1900,4200,3200,100,*,UP,POLY +S 7900,1900,7900,3200,100,*,UP,POLY +S 7300,1900,7300,3200,100,*,DOWN,POLY +S 6100,1900,6100,3200,100,*,DOWN,POLY +S 6700,1900,6700,3200,100,*,UP,POLY +S 4200,8200,4200,8700,100,*,DOWN,POLY +S 4800,8200,4800,8600,100,*,DOWN,POLY +S 4200,8500,4800,8500,300,*,RIGHT,POLY +S 6700,8500,7300,8500,300,*,RIGHT,POLY +S 7300,8200,7300,8600,100,*,DOWN,POLY +S 6700,8200,6700,8700,100,*,DOWN,POLY +S 1400,300,1400,1700,300,*,UP,NDIF +S 2000,300,2000,1700,300,*,UP,NDIF +S 1100,100,1100,1900,100,*,UP,NTRANS +S 1700,100,1700,1900,100,*,DOWN,NTRANS +S 3200,300,3200,1700,300,*,UP,NDIF +S 800,300,800,1700,300,*,UP,NDIF +S 2900,100,2900,1900,100,*,DOWN,NTRANS +S 2600,300,2600,1700,300,*,UP,NDIF +S 2300,100,2300,1900,100,*,DOWN,NTRANS +S 1400,8900,1400,9600,300,*,UP,NDIF +S 2000,8900,2000,9600,300,*,UP,NDIF +S 1700,8700,1700,9800,100,*,UP,NTRANS +S 5700,300,5700,1700,300,*,UP,NDIF +S 4200,100,4200,1900,100,*,DOWN,NTRANS +S 3600,100,3600,1900,100,*,UP,NTRANS +S 4500,300,4500,1700,300,*,UP,NDIF +S 3900,300,3900,1700,300,*,UP,NDIF +S 4800,100,4800,1900,100,*,DOWN,NTRANS +S 5100,300,5100,1700,300,*,UP,NDIF +S 5400,100,5400,1900,100,*,DOWN,NTRANS +S 8200,300,8200,1700,300,*,UP,NDIF +S 6400,300,6400,1700,300,*,UP,NDIF +S 7000,300,7000,1700,300,*,UP,NDIF +S 6100,100,6100,1900,100,*,UP,NTRANS +S 6700,100,6700,1900,100,*,DOWN,NTRANS +S 7900,100,7900,1900,100,*,DOWN,NTRANS +S 7600,300,7600,1700,300,*,UP,NDIF +S 7300,100,7300,1900,100,*,DOWN,NTRANS +S 4500,8900,4500,9600,300,*,UP,NDIF +S 3900,8900,3900,9600,300,*,UP,NDIF +S 6400,8900,6400,9600,300,*,UP,NDIF +S 7000,8900,7000,9600,300,*,UP,NDIF +S 4200,8700,4200,9800,100,*,UP,NTRANS +S 6700,8700,6700,9800,100,*,UP,NTRANS +S 2600,7300,2600,8000,300,*,UP,PDIF +S 800,3400,800,6300,300,*,UP,PDIF +S 1100,3200,1100,6500,100,*,UP,PTRANS +S 2000,3400,2000,6300,300,*,UP,PDIF +S 1400,3400,1400,6300,300,*,UP,PDIF +S 1700,3200,1700,6500,100,*,UP,PTRANS +S 3200,3400,3200,6300,300,*,DOWN,PDIF +S 2900,3200,2900,6500,100,*,DOWN,PTRANS +S 2600,3400,2600,6300,300,*,UP,PDIF +S 2300,3200,2300,6500,100,*,UP,PTRANS +S 1400,7300,1400,8000,300,*,UP,PDIF +S 1700,7100,1700,8200,100,*,DOWN,PTRANS +S 2100,7300,2100,8000,300,*,UP,PDIF +S 2300,7100,2300,8200,100,*,DOWN,PTRANS +S 5700,3400,5700,6300,300,*,DOWN,PDIF +S 4200,3200,4200,6500,100,*,UP,PTRANS +S 3900,3400,3900,6300,300,*,UP,PDIF +S 4500,3400,4500,6300,300,*,UP,PDIF +S 3600,3200,3600,6500,100,*,UP,PTRANS +S 4800,3200,4800,6500,100,*,UP,PTRANS +S 5100,3400,5100,6300,300,*,UP,PDIF +S 5400,3200,5400,6500,100,*,DOWN,PTRANS +S 7000,3400,7000,6300,300,*,UP,PDIF +S 6400,3400,6400,6300,300,*,UP,PDIF +S 6700,3200,6700,6500,100,*,UP,PTRANS +S 8200,3400,8200,6300,300,*,DOWN,PDIF +S 6100,3200,6100,6500,100,*,UP,PTRANS +S 7900,3200,7900,6500,100,*,DOWN,PTRANS +S 7600,3400,7600,6300,300,*,UP,PDIF +S 7300,3200,7300,6500,100,*,UP,PTRANS +S 3900,7300,3900,8000,300,*,UP,PDIF +S 5100,7300,5100,8000,300,*,UP,PDIF +S 6400,7300,6400,8000,300,*,UP,PDIF +S 4800,7100,4800,8200,100,*,DOWN,PTRANS +S 4600,7300,4600,8000,300,*,UP,PDIF +S 4200,7100,4200,8200,100,*,DOWN,PTRANS +S 7100,7300,7100,8000,300,*,UP,PDIF +S 7300,7100,7300,8200,100,*,DOWN,PTRANS +S 7600,7300,7600,8000,300,*,UP,PDIF +S 6700,7100,6700,8200,100,*,DOWN,PTRANS +S 5100,6600,5100,7900,200,*,DOWN,ALU1 +S 7600,6600,7600,7900,200,*,DOWN,ALU1 +S 6400,7400,6400,9000,200,*,UP,ALU1 +S 3900,7400,3900,9000,200,*,UP,ALU1 +S 4800,6600,5400,6600,300,*,RIGHT,POLY +S 7300,6600,7900,6600,300,*,RIGHT,POLY +S 4500,2800,4500,7400,200,*,UP,ALU1 +S 7000,2800,7000,7400,200,*,UP,ALU1 +S 1100,7700,8300,7700,800,*,RIGHT,NWELL +S 8200,9000,8200,9700,200,*,UP,ALU1 +S 4400,2200,5100,2200,200,*,RIGHT,ALU1 +S 6900,2200,7600,2200,200,*,RIGHT,ALU1 +S 3600,2200,4400,2200,300,*,RIGHT,POLY +S 4800,2200,5400,2200,300,*,RIGHT,POLY +S 6100,2200,6900,2200,300,*,RIGHT,POLY +S 7300,2200,7900,2200,300,*,RIGHT,POLY +S 9300,1500,9300,4000,200,*,UP,ALU1 +S 9900,2800,9900,6800,200,*,UP,ALU1 +S 9900,500,9900,1500,200,*,UP,ALU1 +S 9300,2200,10000,2200,200,*,RIGHT,ALU1 +S 10200,1900,10200,3200,100,*,DOWN,POLY +S 9600,1900,9600,3200,100,*,UP,POLY +S 10500,300,10500,1700,300,*,UP,NDIF +S 9900,300,9900,1700,300,*,UP,NDIF +S 10200,100,10200,1900,100,*,DOWN,NTRANS +S 10500,3400,10500,6300,300,*,UP,PDIF +S 10200,3200,10200,6500,100,*,UP,PTRANS +S 9900,3400,9900,6300,300,*,UP,PDIF +S 0,9700,12000,9700,600,vss,RIGHT,CALU1 +S 0,300,12000,300,600,vss,RIGHT,CALU1 +S 0,4700,12000,4700,600,vdd,RIGHT,CALU1 +S 0,5300,12000,5300,600,vdd,RIGHT,CALU1 +S 1500,1500,1500,6000,200,nwenx,DOWN,CALU3 +S 2500,1500,2500,6000,200,wenx,DOWN,CALU3 +S 4000,1500,4000,6000,200,nscanx,DOWN,CALU3 +S 5000,1500,5000,6000,200,scanx,DOWN,CALU3 +S 6500,1500,6500,6000,200,nckx,DOWN,CALU3 +S 10500,1000,10500,4000,200,scout,UP,CALU1 +S 1500,1500,7500,1500,200,*,RIGHT,TALU2 +S 1500,4000,7500,4000,200,*,LEFT,TALU2 +S 1500,6000,7500,6000,200,*,RIGHT,TALU2 +V 9000,6500,CONT_POLY,* +V 7500,1500,CONT_VIA,* +V 7500,1500,CONT_VIA2,* +V 5000,1500,CONT_VIA,* +V 5000,1500,CONT_VIA2,* +V 2500,1500,CONT_VIA,* +V 2500,1500,CONT_VIA2,* +V 1900,2200,CONT_POLY,* +V 2600,6600,CONT_POLY,* +V 1500,4000,CONT_VIA2,* +V 1500,6000,CONT_VIA2,* +V 2500,6000,CONT_VIA2,* +V 1500,1500,CONT_VIA2,* +V 2500,4000,CONT_VIA2,* +V 5000,4000,CONT_VIA2,* +V 4000,1500,CONT_VIA2,* +V 5000,6000,CONT_VIA2,* +V 4000,6000,CONT_VIA2,* +V 4000,4000,CONT_VIA2,* +V 7500,6000,CONT_VIA2,* +V 6500,1500,CONT_VIA2,* +V 7500,4000,CONT_VIA2,* +V 6500,4000,CONT_VIA2,* +V 6500,6000,CONT_VIA2,* +V 1500,1500,CONT_VIA,* +V 1500,4000,CONT_VIA,* +V 1500,6000,CONT_VIA,* +V 2500,6000,CONT_VIA,* +V 2500,4000,CONT_VIA,* +V 4000,1500,CONT_VIA,* +V 5000,4000,CONT_VIA,* +V 5000,6000,CONT_VIA,* +V 4000,6000,CONT_VIA,* +V 4000,4000,CONT_VIA,* +V 6500,1500,CONT_VIA,* +V 6500,6000,CONT_VIA,* +V 7500,6000,CONT_VIA,* +V 7500,4000,CONT_VIA,* +V 6500,4000,CONT_VIA,* +V 2000,8500,CONT_POLY,* +V 4500,8500,CONT_POLY,* +V 7000,8500,CONT_POLY,* +V 5700,9700,CONT_BODY_P,* +V 3200,9700,CONT_BODY_P,* +V 800,9700,CONT_BODY_P,* +V 3200,9000,CONT_BODY_P,* +V 800,9000,CONT_BODY_P,* +V 5700,9000,CONT_BODY_P,* +V 3200,1000,CONT_DIF_N,* +V 2600,1000,CONT_DIF_N,* +V 3200,500,CONT_DIF_N,* +V 3200,1500,CONT_DIF_N,* +V 2600,1500,CONT_DIF_N,* +V 800,500,CONT_DIF_N,* +V 800,1500,CONT_DIF_N,* +V 800,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 2000,500,CONT_DIF_N,* +V 2000,1500,CONT_DIF_N,* +V 1400,9000,CONT_DIF_N,* +V 1400,1500,CONT_DIF_N,* +V 1400,1000,CONT_DIF_N,* +V 2000,9000,CONT_DIF_N,* +V 2000,9500,CONT_DIF_N,* +V 5700,500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 5700,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 3900,1500,CONT_DIF_N,* +V 4500,1500,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 4500,1000,CONT_DIF_N,* +V 5100,1500,CONT_DIF_N,* +V 5700,1500,CONT_DIF_N,* +V 7600,1000,CONT_DIF_N,* +V 8200,500,CONT_DIF_N,* +V 6400,1500,CONT_DIF_N,* +V 6400,1000,CONT_DIF_N,* +V 8200,1000,CONT_DIF_N,* +V 8200,1500,CONT_DIF_N,* +V 7600,1500,CONT_DIF_N,* +V 7000,1000,CONT_DIF_N,* +V 7000,500,CONT_DIF_N,* +V 7000,1500,CONT_DIF_N,* +V 7000,9000,CONT_DIF_N,* +V 7000,9500,CONT_DIF_N,* +V 4500,9500,CONT_DIF_N,* +V 4500,9000,CONT_DIF_N,* +V 3900,9000,CONT_DIF_N,* +V 6400,9000,CONT_DIF_N,* +V 1400,7900,CONT_DIF_P,* +V 2000,7400,CONT_DIF_P,* +V 1400,7400,CONT_DIF_P,* +V 2000,2900,CONT_BODY_N,* +V 800,2900,CONT_BODY_N,* +V 3200,2900,CONT_BODY_N,* +V 800,6000,CONT_DIF_P,* +V 800,3500,CONT_DIF_P,* +V 800,5500,CONT_DIF_P,* +V 800,5000,CONT_DIF_P,* +V 800,4500,CONT_DIF_P,* +V 800,4000,CONT_DIF_P,* +V 2000,3500,CONT_DIF_P,* +V 2000,4500,CONT_DIF_P,* +V 2000,5500,CONT_DIF_P,* +V 2000,4000,CONT_DIF_P,* +V 2000,5000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3200,4500,CONT_DIF_P,* +V 3200,5000,CONT_DIF_P,* +V 3200,5500,CONT_DIF_P,* +V 3200,6000,CONT_DIF_P,* +V 2600,4000,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 1400,3500,CONT_DIF_P,* +V 1400,4000,CONT_DIF_P,* +V 1400,6000,CONT_DIF_P,* +V 2600,6000,CONT_DIF_P,* +V 2600,7900,CONT_DIF_P,* +V 2600,7400,CONT_DIF_P,* +V 2000,6800,CONT_BODY_N,* +V 3200,6800,CONT_BODY_N,* +V 800,6800,CONT_BODY_N,* +V 4500,5500,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 5700,2900,CONT_BODY_N,* +V 4500,2900,CONT_BODY_N,* +V 5700,6000,CONT_DIF_P,* +V 5700,5500,CONT_DIF_P,* +V 5700,5000,CONT_DIF_P,* +V 5700,4500,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 4500,5000,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 5700,6800,CONT_BODY_N,* +V 4500,6800,CONT_BODY_N,* +V 5100,6000,CONT_DIF_P,* +V 3900,6000,CONT_DIF_P,* +V 3900,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 7000,3500,CONT_DIF_P,* +V 7000,4500,CONT_DIF_P,* +V 7000,5500,CONT_DIF_P,* +V 8200,5000,CONT_DIF_P,* +V 8200,5500,CONT_DIF_P,* +V 8200,6000,CONT_DIF_P,* +V 7000,2900,CONT_BODY_N,* +V 8200,2900,CONT_BODY_N,* +V 7600,6000,CONT_DIF_P,* +V 7000,6800,CONT_BODY_N,* +V 8200,6800,CONT_BODY_N,* +V 7000,4000,CONT_DIF_P,* +V 7000,5000,CONT_DIF_P,* +V 8200,4000,CONT_DIF_P,* +V 8200,3500,CONT_DIF_P,* +V 8200,4500,CONT_DIF_P,* +V 3900,7900,CONT_DIF_P,* +V 7600,4000,CONT_DIF_P,* +V 7600,3500,CONT_DIF_P,* +V 6400,3500,CONT_DIF_P,* +V 6400,4000,CONT_DIF_P,* +V 6400,6000,CONT_DIF_P,* +V 5100,7400,CONT_DIF_P,* +V 5100,7900,CONT_DIF_P,* +V 3900,7400,CONT_DIF_P,* +V 4500,7400,CONT_DIF_P,* +V 7000,7400,CONT_DIF_P,* +V 6400,7400,CONT_DIF_P,* +V 7600,7900,CONT_DIF_P,* +V 7600,7400,CONT_DIF_P,* +V 6400,7900,CONT_DIF_P,* +V 5100,6600,CONT_POLY,* +V 7600,6600,CONT_POLY,* +V 7000,6000,CONT_DIF_P,* +V 4500,6000,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 8200,9700,CONT_BODY_P,* +V 8200,9000,CONT_BODY_P,* +V 4400,2200,CONT_POLY,* +V 6900,2200,CONT_POLY,* +V 10000,2200,CONT_POLY,* +V 9300,1500,CONT_DIF_N,* +V 10500,1500,CONT_DIF_N,* +V 9900,1000,CONT_DIF_N,* +V 9900,500,CONT_DIF_N,* +V 9900,1500,CONT_DIF_N,* +V 10500,1000,CONT_DIF_N,* +V 9900,2900,CONT_BODY_N,* +V 9300,3500,CONT_DIF_P,* +V 9300,4000,CONT_DIF_P,* +V 9900,4000,CONT_DIF_P,* +V 9900,5000,CONT_DIF_P,* +V 9900,3500,CONT_DIF_P,* +V 9900,4500,CONT_DIF_P,* +V 9900,5500,CONT_DIF_P,* +V 9900,6800,CONT_BODY_N,* +V 9900,6000,CONT_DIF_P,* +V 10500,4000,CONT_DIF_P,* +V 10500,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4_buf.vbe new file mode 100644 index 00000000..42cea450 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_sff_scan_x4_buf.vbe @@ -0,0 +1,33 @@ +ENTITY dp_sff_scan_x4_buf IS +PORT ( + ck : in BIT; + wen : in BIT; + scan : in BIT; + scin : in BIT; + ckx : out BIT; + nckx : out BIT; + wenx : out BIT; + nwenx : out BIT; + scanx : out BIT; + nscanx : out BIT; + scout : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_sff_scan_x4_buf; + +ARCHITECTURE vbe OF dp_sff_scan_x4_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on dp_sff_scan_x4_buf" + SEVERITY WARNING; + + ckx <= ck; + nckx <= not ck; + wenx <= wen; + nwenx <= not wen; + scanx <= scan; + nscanx <= not scan; + scout <= scin; +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_sff_x4.ap b/alliance/src/cells/src/dp_sxlib/dp_sff_x4.ap new file mode 100644 index 00000000..986e4abc --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_sff_x4.ap @@ -0,0 +1,217 @@ +V ALLIANCE : 6 +H dp_sff_x4,P, 6/ 9/2000,10 +A 0,0,900,500 +R 450,250,ref_ref,ckx +R 350,250,ref_ref,nckx +R 200,250,ref_ref,wenx +R 100,250,ref_ref,nwenx +R 800,150,ref_ref,q_15 +R 800,250,ref_ref,q_25 +R 800,300,ref_ref,q_30 +R 800,350,ref_ref,q_35 +R 800,400,ref_ref,q_40 +R 800,100,ref_ref,q_10 +R 50,400,ref_ref,i_40 +R 50,100,ref_ref,i_10 +R 50,300,ref_ref,i_30 +R 50,350,ref_ref,i_35 +R 50,250,ref_ref,i_25 +R 50,200,ref_ref,i_20 +R 50,150,ref_ref,i_15 +S 740,150,800,150,10,*,RIGHT,ALU1 +S 740,250,800,250,10,*,RIGHT,ALU1 +S 690,200,740,200,10,*,RIGHT,ALU1 +S 740,200,840,200,30,*,RIGHT,POLY +S 250,200,800,200,20,*,RIGHT,ALU2 +S 720,240,720,360,10,*,DOWN,POLY +S 450,250,500,250,20,*,RIGHT,ALU2 +S 390,350,450,350,10,*,RIGHT,ALU1 +S 300,150,300,400,10,u,DOWN,ALU1 +S 400,200,400,300,10,*,UP,ALU1 +S 350,300,400,300,10,*,RIGHT,ALU1 +S 870,300,870,450,20,*,DOWN,ALU1 +S 750,300,750,450,20,*,DOWN,ALU1 +S 450,300,520,300,10,*,RIGHT,ALU1 +S 630,200,630,350,10,*,DOWN,ALU1 +S 450,150,520,150,10,*,LEFT,ALU1 +S 630,400,690,400,10,*,RIGHT,ALU1 +S 870,50,870,100,20,*,DOWN,ALU1 +S 750,50,750,100,20,*,DOWN,ALU1 +S 500,350,570,350,10,*,LEFT,ALU1 +S 570,100,570,400,10,y,DOWN,ALU1 +S 450,100,450,350,10,x,DOWN,ALU1 +S 500,100,570,100,10,*,RIGHT,ALU1 +S 390,100,450,100,10,*,RIGHT,ALU1 +S 630,100,690,100,10,*,RIGHT,ALU1 +S 690,100,690,400,10,z,DOWN,ALU1 +S 150,150,150,400,10,*,DOWN,ALU1 +S 200,100,200,300,10,*,DOWN,ALU1 +S 150,400,300,400,10,*,RIGHT,ALU1 +S 100,100,200,100,10,*,RIGHT,ALU1 +S 540,300,540,360,10,*,DOWN,POLY +S 600,140,600,200,10,*,DOWN,POLY +S 840,140,840,260,10,*,DOWN,POLY +S 420,250,420,310,10,*,DOWN,POLY +S 510,150,540,150,30,*,RIGHT,POLY +S 480,350,510,350,30,*,RIGHT,POLY +S 630,350,660,350,30,*,RIGHT,POLY +S 510,300,540,300,30,*,RIGHT,POLY +S 780,140,780,260,10,*,DOWN,POLY +S 660,140,660,250,10,*,DOWN,POLY +S 390,200,420,200,30,*,RIGHT,POLY +S 600,200,630,200,30,*,RIGHT,POLY +S 420,140,420,200,10,*,DOWN,POLY +S 600,250,600,360,10,*,DOWN,POLY +S 720,250,750,250,30,*,RIGHT,POLY +S 720,150,750,150,30,*,RIGHT,POLY +S 480,100,510,100,30,*,RIGHT,POLY +S 540,90,540,150,10,*,UP,POLY +S 270,40,270,120,30,*,DOWN,NDIF +S 330,80,330,120,30,*,DOWN,NDIF +S 450,30,450,120,30,*,DOWN,NDIF +S 390,80,390,120,30,*,DOWN,NDIF +S 630,80,630,120,30,*,DOWN,NDIF +S 690,80,690,120,30,*,DOWN,NDIF +S 870,30,870,120,30,*,DOWN,NDIF +S 810,30,810,120,30,*,DOWN,NDIF +S 750,30,750,120,30,*,DOWN,NDIF +S 570,30,570,120,30,*,DOWN,NDIF +S 510,30,510,70,30,*,DOWN,NDIF +S 570,30,570,70,30,*,DOWN,NDIF +S 160,80,160,160,50,*,DOWN,NDIF +S 270,40,270,120,30,*,UP,NDIF +S 140,80,140,120,30,*,UP,NDIF +S 660,60,660,140,10,*,UP,NTRANS +S 720,60,720,140,10,*,UP,NTRANS +S 840,10,840,140,10,*,UP,NTRANS +S 360,60,360,140,10,*,UP,NTRANS +S 600,60,600,140,10,*,UP,NTRANS +S 780,10,780,140,10,*,UP,NTRANS +S 300,60,300,140,10,*,UP,NTRANS +S 420,60,420,140,10,*,UP,NTRANS +S 480,10,480,90,10,*,UP,NTRANS +S 540,10,540,90,10,*,UP,NTRANS +S 240,60,240,140,10,*,UP,NTRANS +S 200,60,200,140,10,*,UP,NTRANS +S 750,280,750,470,30,*,DOWN,PDIF +S 780,260,780,490,10,*,DOWN,PTRANS +S 450,330,450,470,30,*,UP,PDIF +S 420,310,420,440,10,*,DOWN,PTRANS +S 390,330,390,420,30,*,UP,PDIF +S 360,310,360,440,10,*,DOWN,PTRANS +S 870,280,870,470,30,*,DOWN,PDIF +S 840,260,840,490,10,*,DOWN,PTRANS +S 810,280,810,470,30,*,DOWN,PDIF +S 540,360,540,490,10,*,UP,PTRANS +S 480,360,480,490,10,*,DOWN,PTRANS +S 720,360,720,490,10,*,DOWN,PTRANS +S 690,380,690,470,30,*,UP,PDIF +S 500,380,500,470,30,*,DOWN,PDIF +S 660,360,660,490,10,*,DOWN,PTRANS +S 630,380,630,470,30,*,DOWN,PDIF +S 600,360,600,490,10,*,DOWN,PTRANS +S 560,380,560,470,30,*,DOWN,PDIF +S 200,310,200,440,10,*,DOWN,PTRANS +S 270,330,270,460,30,*,DOWN,PDIF +S 240,310,240,440,10,*,DOWN,PTRANS +S 0,390,900,390,240,*,RIGHT,NWELL +S 330,330,330,420,30,*,UP,PDIF +S 300,310,300,440,10,*,DOWN,PTRANS +S 250,150,250,300,10,*,DOWN,ALU1 +S 100,100,100,150,10,*,UP,ALU1 +S 30,40,30,120,30,*,UP,NDIF +S 60,60,60,140,10,*,UP,NTRANS +S 30,330,30,460,30,*,DOWN,PDIF +S 60,310,60,440,10,*,DOWN,PTRANS +S 100,200,200,200,10,*,RIGHT,POLY +S 200,140,200,200,10,*,DOWN,POLY +S 100,310,100,440,10,*,DOWN,PTRANS +S 100,200,100,310,10,*,DOWN,POLY +S 100,60,100,140,10,*,UP,NTRANS +S 150,330,150,420,60,*,DOWN,PDIF +S 150,80,150,160,50,*,DOWN,NDIF +S 500,200,500,250,10,*,DOWN,ALU1 +S 360,140,360,250,10,*,UP,POLY +S 400,200,600,200,10,ckx,RIGHT,POLY +S 350,250,660,250,10,nckx,RIGHT,POLY +S 0,30,900,30,60,vss,RIGHT,CALU1 +S 0,470,900,470,60,vdd,RIGHT,CALU1 +S 250,200,800,200,20,*,RIGHT,TALU2 +S 100,250,500,250,20,*,RIGHT,TALU2 +S 100,250,100,250,20,nwenx,LEFT,CALU3 +S 350,250,350,250,20,nckx,LEFT,CALU3 +S 450,250,450,250,20,ckx,LEFT,CALU3 +S 200,250,200,250,20,wenx,LEFT,CALU3 +S 800,100,800,400,20,q,DOWN,CALU1 +S 50,100,50,400,20,i,DOWN,CALU1 +V 200,250,CONT_VIA,* +V 200,250,CONT_VIA2,* +V 100,250,CONT_POLY,* +V 100,250,CONT_VIA,* +V 100,250,CONT_VIA2,* +V 800,200,CONT_VIA,* +V 740,200,CONT_POLY,* +V 450,250,CONT_VIA2,* +V 740,250,CONT_POLY,* +V 350,300,CONT_POLY,* +V 350,250,CONT_POLY,* +V 300,150,CONT_POLY,* +V 640,350,CONT_POLY,* +V 400,200,CONT_POLY,* +V 520,300,CONT_POLY,* +V 620,200,CONT_POLY,* +V 520,150,CONT_POLY,* +V 740,150,CONT_POLY,* +V 500,350,CONT_POLY,* +V 500,100,CONT_POLY,* +V 200,300,CONT_POLY,* +V 50,300,CONT_POLY,* +V 50,150,CONT_POLY,* +V 300,300,CONT_POLY,* +V 690,30,CONT_BODY_P,* +V 630,30,CONT_BODY_P,* +V 200,30,CONT_BODY_P,* +V 100,30,CONT_BODY_P,* +V 270,50,CONT_DIF_N,* +V 810,100,CONT_DIF_N,* +V 750,100,CONT_DIF_N,* +V 870,100,CONT_DIF_N,* +V 750,50,CONT_DIF_N,* +V 870,50,CONT_DIF_N,* +V 570,100,CONT_DIF_N,* +V 390,100,CONT_DIF_N,* +V 510,50,CONT_DIF_N,* +V 630,100,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 750,450,CONT_DIF_P,* +V 870,450,CONT_DIF_P,* +V 750,400,CONT_DIF_P,* +V 750,350,CONT_DIF_P,* +V 390,350,CONT_DIF_P,* +V 810,350,CONT_DIF_P,* +V 510,450,CONT_DIF_P,* +V 630,400,CONT_DIF_P,* +V 810,400,CONT_DIF_P,* +V 870,350,CONT_DIF_P,* +V 870,400,CONT_DIF_P,* +V 750,300,CONT_DIF_P,* +V 810,300,CONT_DIF_P,* +V 870,300,CONT_DIF_P,* +V 570,400,CONT_DIF_P,* +V 200,470,CONT_BODY_N,* +V 270,450,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 100,470,CONT_BODY_N,* +V 250,300,CONT_POLY,* +V 250,150,CONT_POLY,* +V 250,200,CONT_VIA,* +V 100,150,CONT_POLY,* +V 30,50,CONT_DIF_N,* +V 30,450,CONT_DIF_P,* +V 500,250,CONT_VIA,* +V 500,200,CONT_POLY,* +V 350,250,CONT_VIA2,* +V 350,250,CONT_VIA,* +V 350,30,CONT_BODY_P,* +V 350,470,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_sff_x4.vbe b/alliance/src/cells/src/dp_sxlib/dp_sff_x4.vbe new file mode 100644 index 00000000..22300f6a --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_sff_x4.vbe @@ -0,0 +1,36 @@ +ENTITY dp_sff_x4 IS +PORT ( + ckx : in BIT; + nckx : in BIT; + wenx : in BIT; + nwenx : in BIT; + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_sff_x4; + +ARCHITECTURE vbe OF dp_sff_x4 IS + SIGNAL ff : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on dp_sff_x4" + SEVERITY WARNING; + + ASSERT (ckx xor nckx) + REPORT "wrong values for ckx and nckx in dp_sff_x4" + SEVERITY WARNING; + + ASSERT (wenx xor nwenx) + REPORT "wrong values for wenx and nwenx in dp_sff_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1') + BEGIN + ff <= GUARDED ((wenx and i) or (nwenx and ff)); + END BLOCK label0; + + q <= ff; +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_sff_x4_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_sff_x4_buf.ap new file mode 100644 index 00000000..c077bb72 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_sff_x4_buf.ap @@ -0,0 +1,250 @@ +V ALLIANCE : 6 +H dp_sff_x4_buf,P,14/11/2000,10 +A 0,0,900,1000 +R 100,400,ref_ref,nwenx +R 200,400,ref_ref,wenx +R 350,400,ref_ref,nckx +R 450,400,ref_ref,ckx +S 100,600,450,600,20,*,RIGHT,TALU2 +S 100,400,450,400,20,*,LEFT,TALU2 +S 100,150,450,150,20,*,RIGHT,TALU2 +S 150,850,150,850,10,wen,LEFT,CALU1 +S 400,850,400,850,10,ck,LEFT,CALU1 +S 350,150,350,600,20,nckx,DOWN,CALU3 +S 450,150,450,600,20,ckx,UP,CALU3 +S 70,770,480,770,80,*,RIGHT,NWELL +S 90,340,90,630,30,*,UP,PDIF +S 120,320,120,650,10,*,UP,PTRANS +S 270,340,270,630,30,*,DOWN,PDIF +S 30,340,30,630,30,*,UP,PDIF +S 210,730,210,800,30,*,UP,PDIF +S 60,320,60,650,10,*,UP,PTRANS +S 180,710,180,820,10,*,DOWN,PTRANS +S 160,730,160,800,30,*,UP,PDIF +S 120,710,120,820,10,*,DOWN,PTRANS +S 90,730,90,800,30,*,UP,PDIF +S 180,320,180,650,10,*,UP,PTRANS +S 210,340,210,630,30,*,UP,PDIF +S 240,320,240,650,10,*,DOWN,PTRANS +S 310,320,310,650,10,*,UP,PTRANS +S 400,340,400,630,30,*,UP,PDIF +S 340,340,340,630,30,*,UP,PDIF +S 370,320,370,650,10,*,UP,PTRANS +S 520,340,520,630,30,*,DOWN,PDIF +S 490,320,490,650,10,*,DOWN,PTRANS +S 460,340,460,630,30,*,UP,PDIF +S 430,320,430,650,10,*,UP,PTRANS +S 340,730,340,800,30,*,UP,PDIF +S 460,730,460,800,30,*,UP,PDIF +S 370,710,370,820,10,*,DOWN,PTRANS +S 410,730,410,800,30,*,UP,PDIF +S 430,710,430,820,10,*,DOWN,PTRANS +S 150,340,150,630,30,*,UP,PDIF +S 60,10,60,190,10,*,UP,NTRANS +S 120,10,120,190,10,*,DOWN,NTRANS +S 150,30,150,170,30,*,UP,NDIF +S 180,10,180,190,10,*,DOWN,NTRANS +S 210,30,210,170,30,*,UP,NDIF +S 240,10,240,190,10,*,DOWN,NTRANS +S 30,30,30,170,30,*,UP,NDIF +S 270,30,270,170,30,*,UP,NDIF +S 90,30,90,170,30,*,UP,NDIF +S 150,890,150,960,30,*,UP,NDIF +S 90,890,90,960,30,*,UP,NDIF +S 120,870,120,980,10,*,UP,NTRANS +S 310,10,310,190,10,*,UP,NTRANS +S 370,10,370,190,10,*,DOWN,NTRANS +S 520,30,520,170,30,*,UP,NDIF +S 430,10,430,190,10,*,DOWN,NTRANS +S 400,30,400,170,30,*,UP,NDIF +S 340,30,340,170,30,*,UP,NDIF +S 490,10,490,190,10,*,DOWN,NTRANS +S 460,30,460,170,30,*,UP,NDIF +S 340,890,340,960,30,*,UP,NDIF +S 400,890,400,960,30,*,UP,NDIF +S 370,870,370,980,10,*,UP,NTRANS +S 490,190,490,320,10,*,UP,POLY +S 120,820,120,870,10,*,DOWN,POLY +S 430,190,430,320,10,*,DOWN,POLY +S 60,190,60,320,10,*,DOWN,POLY +S 370,190,370,320,10,*,UP,POLY +S 120,190,120,320,10,*,UP,POLY +S 370,820,370,870,10,*,DOWN,POLY +S 370,850,430,850,30,*,RIGHT,POLY +S 430,820,430,860,10,*,DOWN,POLY +S 180,820,180,860,10,*,DOWN,POLY +S 120,850,180,850,30,*,RIGHT,POLY +S 310,190,310,320,10,*,DOWN,POLY +S 180,190,180,320,10,*,DOWN,POLY +S 240,190,240,320,10,*,UP,POLY +S 430,660,490,660,30,*,RIGHT,POLY +S 430,220,490,220,30,*,RIGHT,POLY +S 310,220,390,220,30,*,RIGHT,POLY +S 400,280,400,740,20,*,UP,ALU1 +S 30,50,30,150,20,*,UP,ALU1 +S 210,100,210,400,20,*,UP,ALU1 +S 30,350,30,680,20,*,UP,ALU1 +S 270,280,270,680,20,*,UP,ALU1 +S 270,50,270,150,20,*,UP,ALU1 +S 150,900,150,940,20,*,UP,ALU1 +S 90,790,210,790,20,*,RIGHT,ALU1 +S 340,100,340,400,20,*,UP,ALU1 +S 150,50,150,150,20,*,UP,ALU1 +S 150,280,150,740,20,*,UP,ALU1 +S 30,900,30,970,20,*,DOWN,ALU1 +S 520,50,520,150,20,*,UP,ALU1 +S 400,50,400,150,20,*,UP,ALU1 +S 520,280,520,680,20,*,UP,ALU1 +S 460,100,460,400,20,*,UP,ALU1 +S 90,100,90,400,20,*,UP,ALU1 +S 460,660,460,790,20,*,DOWN,ALU1 +S 340,740,340,900,20,*,UP,ALU1 +S 520,900,520,970,20,*,UP,ALU1 +S 400,900,400,940,20,*,UP,ALU1 +S 340,790,460,790,20,*,RIGHT,ALU1 +S 270,900,270,970,20,*,UP,ALU1 +S 390,220,460,220,20,*,RIGHT,ALU1 +S 600,50,600,150,20,*,UP,ALU1 +S 0,500,900,500,460,*,RIGHT,NWELL +S 180,660,240,660,30,*,RIGHT,POLY +S 90,740,90,900,20,*,UP,ALU1 +S 210,660,210,790,20,*,DOWN,ALU1 +S 180,220,240,220,30,*,RIGHT,POLY +S 60,220,140,220,30,*,RIGHT,POLY +S 150,220,210,220,20,*,RIGHT,ALU1 +S 100,150,100,600,20,nwenx,UP,CALU3 +S 0,30,900,30,60,vss,RIGHT,CALU1 +S 0,530,900,530,60,vdd,RIGHT,CALU1 +S 0,470,900,470,60,vdd,RIGHT,CALU1 +S 0,970,900,970,60,vss,RIGHT,CALU1 +S 200,150,200,600,20,wenx,DOWN,CALU3 +V 450,150,CONT_VIA,* +V 450,150,CONT_VIA2,* +V 200,150,CONT_VIA,* +V 200,150,CONT_VIA2,* +V 90,790,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 270,290,CONT_BODY_N,* +V 30,290,CONT_BODY_N,* +V 150,290,CONT_BODY_N,* +V 90,740,CONT_DIF_P,* +V 150,740,CONT_DIF_P,* +V 150,500,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,550,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,500,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 270,600,CONT_DIF_P,* +V 270,550,CONT_DIF_P,* +V 270,500,CONT_DIF_P,* +V 270,450,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 270,680,CONT_BODY_N,* +V 150,680,CONT_BODY_N,* +V 210,740,CONT_DIF_P,* +V 210,790,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 400,550,CONT_DIF_P,* +V 30,680,CONT_BODY_N,* +V 520,600,CONT_DIF_P,* +V 400,290,CONT_BODY_N,* +V 520,290,CONT_BODY_N,* +V 400,350,CONT_DIF_P,* +V 400,450,CONT_DIF_P,* +V 520,680,CONT_BODY_N,* +V 400,400,CONT_DIF_P,* +V 400,500,CONT_DIF_P,* +V 520,400,CONT_DIF_P,* +V 520,350,CONT_DIF_P,* +V 520,450,CONT_DIF_P,* +V 520,500,CONT_DIF_P,* +V 520,550,CONT_DIF_P,* +V 460,400,CONT_DIF_P,* +V 460,350,CONT_DIF_P,* +V 340,350,CONT_DIF_P,* +V 340,400,CONT_DIF_P,* +V 340,600,CONT_DIF_P,* +V 400,600,CONT_DIF_P,* +V 460,600,CONT_DIF_P,* +V 400,680,CONT_BODY_N,* +V 340,790,CONT_DIF_P,* +V 400,740,CONT_DIF_P,* +V 340,740,CONT_DIF_P,* +V 460,790,CONT_DIF_P,* +V 460,740,CONT_DIF_P,* +V 150,600,CONT_DIF_P,* +V 30,50,CONT_DIF_N,* +V 210,150,CONT_DIF_N,* +V 270,150,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 90,900,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,150,CONT_DIF_N,* +V 150,900,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 520,100,CONT_DIF_N,* +V 460,100,CONT_DIF_N,* +V 520,50,CONT_DIF_N,* +V 150,950,CONT_DIF_N,* +V 400,50,CONT_DIF_N,* +V 340,150,CONT_DIF_N,* +V 400,150,CONT_DIF_N,* +V 340,100,CONT_DIF_N,* +V 520,150,CONT_DIF_N,* +V 460,150,CONT_DIF_N,* +V 400,100,CONT_DIF_N,* +V 400,900,CONT_DIF_N,* +V 400,950,CONT_DIF_N,* +V 340,900,CONT_DIF_N,* +V 520,970,CONT_BODY_P,* +V 270,970,CONT_BODY_P,* +V 30,900,CONT_BODY_P,* +V 270,900,CONT_BODY_P,* +V 520,900,CONT_BODY_P,* +V 30,970,CONT_BODY_P,* +V 400,850,CONT_POLY,* +V 150,850,CONT_POLY,* +V 460,660,CONT_POLY,* +V 390,220,CONT_POLY,* +V 200,400,CONT_VIA,* +V 200,600,CONT_VIA,* +V 100,600,CONT_VIA,* +V 100,400,CONT_VIA,* +V 100,150,CONT_VIA,* +V 350,400,CONT_VIA,* +V 350,600,CONT_VIA,* +V 350,150,CONT_VIA,* +V 450,600,CONT_VIA,* +V 450,400,CONT_VIA,* +V 450,600,CONT_VIA2,* +V 350,150,CONT_VIA2,* +V 350,600,CONT_VIA2,* +V 100,150,CONT_VIA2,* +V 100,400,CONT_VIA2,* +V 200,400,CONT_VIA2,* +V 450,400,CONT_VIA2,* +V 350,400,CONT_VIA2,* +V 100,600,CONT_VIA2,* +V 200,600,CONT_VIA2,* +V 600,50,CONT_BODY_P,* +V 600,150,CONT_BODY_P,* +V 210,660,CONT_POLY,* +V 140,220,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_sff_x4_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_sff_x4_buf.vbe new file mode 100644 index 00000000..dc202748 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_sff_x4_buf.vbe @@ -0,0 +1,25 @@ +ENTITY dp_sff_x4_buf IS +PORT ( + ck : in BIT; + wen : in BIT; + ckx : out BIT; + nckx : out BIT; + wenx : out BIT; + nwenx : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_sff_x4_buf; + +ARCHITECTURE vbe OF dp_sff_x4_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on dp_sff_x4_buf" + SEVERITY WARNING; + + ckx <= ck; + nckx <= not ck; + wenx <= wen; + nwenx <= not wen; +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_sxlib.lef b/alliance/src/cells/src/dp_sxlib/dp_sxlib.lef new file mode 100644 index 00000000..e6336083 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_sxlib.lef @@ -0,0 +1,2395 @@ + +MACRO dp_dff_scan_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + LAYER L_ALU1 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END q + PIN nckx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 19.00 61.00 21.00 ; + END + END nckx + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN scin + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END scin + PIN wenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END wenx + PIN nwenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END nwenx + PIN nscanx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END nscanx + PIN scanx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 19.00 51.00 21.00 ; + END + END scanx + PIN ckx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 19.00 76.00 21.00 ; + END + END ckx + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 98.50 41.00 ; + LAYER L_ALU2 ; + RECT 14.00 19.00 76.00 21.00 ; + END +END dp_dff_scan_x4 + + +MACRO dp_dff_scan_x4_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN nckx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 59.00 66.00 61.00 ; + RECT 64.00 54.00 66.00 56.00 ; + RECT 64.00 49.00 66.00 51.00 ; + RECT 64.00 44.00 66.00 46.00 ; + RECT 64.00 39.00 66.00 41.00 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END nckx + PIN scanx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END scanx + PIN nscanx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END nscanx + PIN nwenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 24.00 54.00 26.00 56.00 ; + RECT 24.00 49.00 26.00 51.00 ; + RECT 24.00 44.00 26.00 46.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END nwenx + PIN wenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 59.00 16.00 61.00 ; + RECT 14.00 54.00 16.00 56.00 ; + RECT 14.00 49.00 16.00 51.00 ; + RECT 14.00 44.00 16.00 46.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END wenx + PIN scout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END scout + PIN ckx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 59.00 76.00 61.00 ; + RECT 74.00 54.00 76.00 56.00 ; + RECT 74.00 49.00 76.00 51.00 ; + RECT 74.00 44.00 76.00 46.00 ; + RECT 74.00 39.00 76.00 41.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 74.00 14.00 76.00 16.00 ; + END + END ckx + PIN wen + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 84.00 21.00 86.00 ; + END + END wen + PIN scan + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 84.00 46.00 86.00 ; + END + END scan + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 69.00 84.00 71.00 86.00 ; + END + END ck + PIN scin + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 94.00 69.00 96.00 71.00 ; + END + END scin + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 97.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 97.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 98.50 41.00 ; + RECT 1.50 59.00 98.50 91.00 ; + LAYER L_ALU2 ; + RECT 14.00 59.00 76.00 61.00 ; + RECT 14.00 39.00 76.00 41.00 ; + RECT 14.00 14.00 76.00 16.00 ; + END +END dp_dff_scan_x4_buf + + +MACRO dp_dff_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + LAYER L_ALU1 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END q + PIN nckx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END nckx + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN wenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END wenx + PIN nwenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END nwenx + PIN ckx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END ckx + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 68.50 41.00 ; + LAYER L_ALU2 ; + RECT 9.00 19.00 46.00 21.00 ; + END +END dp_dff_x4 + + +MACRO dp_dff_x4_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN wenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END wenx + PIN nwenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END nwenx + PIN nckx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 34.00 54.00 36.00 56.00 ; + RECT 34.00 49.00 36.00 51.00 ; + RECT 34.00 44.00 36.00 46.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END nckx + PIN ckx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 59.00 46.00 61.00 ; + RECT 44.00 54.00 46.00 56.00 ; + RECT 44.00 49.00 46.00 51.00 ; + RECT 44.00 44.00 46.00 46.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END ckx + PIN wen + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 84.00 16.00 86.00 ; + END + END wen + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 84.00 41.00 86.00 ; + END + END ck + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 67.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 67.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 68.50 41.00 ; + RECT 1.50 59.00 68.50 91.00 ; + LAYER L_ALU2 ; + RECT 9.00 14.00 46.00 16.00 ; + RECT 9.00 39.00 46.00 41.00 ; + RECT 9.00 59.00 46.00 61.00 ; + END +END dp_dff_x4_buf + + +MACRO dp_mux_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN sel1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END sel1 + PIN sel0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END sel0 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 31.00 21.00 ; + END +END dp_mux_x2 + + +MACRO dp_mux_x2_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN sel1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END sel1 + PIN sel0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END sel0 + PIN sel + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 84.00 26.00 86.00 ; + END + END sel + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 37.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 37.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + RECT 1.50 59.00 38.50 91.00 ; + LAYER L_ALU2 ; + RECT 19.00 14.00 31.00 16.00 ; + RECT 19.00 39.00 31.00 41.00 ; + RECT 19.00 59.00 31.00 61.00 ; + END +END dp_mux_x2_buf + + +MACRO dp_mux_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END i0 + PIN sel1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END sel1 + PIN sel0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END sel0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + LAYER L_ALU2 ; + RECT 24.00 19.00 36.00 21.00 ; + END +END dp_mux_x4 + + +MACRO dp_mux_x4_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN sel1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 24.00 54.00 26.00 56.00 ; + RECT 24.00 49.00 26.00 51.00 ; + RECT 24.00 44.00 26.00 46.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END sel1 + PIN sel0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 34.00 54.00 36.00 56.00 ; + RECT 34.00 49.00 36.00 51.00 ; + RECT 34.00 44.00 36.00 46.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END sel0 + PIN sel + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 84.00 31.00 86.00 ; + END + END sel + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 42.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 42.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + RECT 1.50 59.00 43.50 91.00 ; + LAYER L_ALU2 ; + RECT 24.00 14.00 36.00 16.00 ; + RECT 24.00 39.00 36.00 41.00 ; + RECT 24.00 59.00 36.00 61.00 ; + END +END dp_mux_x4_buf + + +MACRO dp_nmux_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN sel0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END sel0 + PIN sel1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END sel1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + LAYER L_ALU2 ; + RECT 9.00 19.00 21.00 21.00 ; + END +END dp_nmux_x1 + + +MACRO dp_nmux_x1_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN sel1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END sel1 + PIN sel0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END sel0 + PIN sel + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 84.00 16.00 86.00 ; + END + END sel + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 27.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 27.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + RECT 1.50 59.00 28.50 91.00 ; + LAYER L_ALU2 ; + RECT 9.00 14.00 21.00 16.00 ; + RECT 9.00 39.00 21.00 41.00 ; + RECT 9.00 59.00 21.00 61.00 ; + END +END dp_nmux_x1_buf + + +MACRO dp_nts_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN enx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END enx + PIN nenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END nenx + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + LAYER L_ALU2 ; + RECT 9.00 19.00 21.00 21.00 ; + END +END dp_nts_x2 + + +MACRO dp_nts_x2_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN nenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END nenx + PIN enx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END enx + PIN en + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 84.00 16.00 86.00 ; + END + END en + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 27.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 27.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + RECT 1.50 59.00 28.50 91.00 ; + LAYER L_ALU2 ; + RECT 9.00 14.00 21.00 16.00 ; + RECT 9.00 39.00 21.00 41.00 ; + RECT 9.00 59.00 21.00 61.00 ; + END +END dp_nts_x2_buf + + +MACRO dp_rom2_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN nix + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END nix + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 69.00 11.00 71.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 22.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 22.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + RECT 1.50 59.00 23.50 91.00 ; + LAYER L_ALU2 ; + RECT 3.00 14.00 17.00 16.00 ; + RECT 3.00 39.00 17.00 41.00 ; + RECT 3.00 59.00 17.00 61.00 ; + END +END dp_rom2_buf + + +MACRO dp_rom4_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN ni0x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 59.00 46.00 61.00 ; + RECT 44.00 54.00 46.00 56.00 ; + RECT 44.00 49.00 46.00 51.00 ; + RECT 44.00 44.00 46.00 46.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END ni0x + PIN i1x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 34.00 54.00 36.00 56.00 ; + RECT 34.00 49.00 36.00 51.00 ; + RECT 34.00 44.00 36.00 46.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1x + PIN i0x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0x + PIN ni1x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END ni1x + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 84.00 41.00 86.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 84.00 16.00 86.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 52.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 52.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + RECT 1.50 59.00 53.50 91.00 ; + LAYER L_ALU2 ; + RECT 9.00 14.00 46.00 16.00 ; + RECT 9.00 19.00 41.00 21.00 ; + RECT 9.00 39.00 46.00 41.00 ; + RECT 9.00 59.00 46.00 61.00 ; + RECT 9.00 19.00 41.00 21.00 ; + END +END dp_rom4_buf + + +MACRO dp_rom4_nxr2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END q + PIN ni0x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END ni0x + PIN ni1x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END ni1x + PIN i0x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 24.00 11.00 26.00 ; + END + END i0x + PIN i1x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 24.00 36.00 26.00 ; + END + END i1x + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 26.00 21.00 ; + RECT 9.00 24.00 36.00 26.00 ; + RECT 24.00 24.00 36.00 26.00 ; + RECT 19.00 19.00 46.00 21.00 ; + RECT 29.00 19.00 46.00 21.00 ; + END +END dp_rom4_nxr2_x4 + + +MACRO dp_rom4_xr2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END q + PIN ni1x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END ni1x + PIN ni0x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END ni0x + PIN i1x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 24.00 36.00 26.00 ; + END + END i1x + PIN i0x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 24.00 11.00 26.00 ; + END + END i0x + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + LAYER L_ALU2 ; + RECT 16.00 24.00 36.00 26.00 ; + RECT 29.00 19.00 46.00 21.00 ; + RECT 19.00 19.00 46.00 21.00 ; + RECT 9.00 24.00 36.00 26.00 ; + RECT 19.00 19.00 26.00 21.00 ; + END +END dp_rom4_xr2_x4 + + +MACRO dp_sff_scan_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + RECT 109.00 24.00 111.00 26.00 ; + RECT 109.00 19.00 111.00 21.00 ; + RECT 109.00 14.00 111.00 16.00 ; + RECT 109.00 9.00 111.00 11.00 ; + LAYER L_ALU2 ; + RECT 109.00 19.00 111.00 21.00 ; + RECT 104.00 19.00 106.00 21.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 84.00 19.00 86.00 21.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END q + PIN wenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END wenx + PIN nwenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END nwenx + PIN nscanx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 24.00 41.00 26.00 ; + END + END nscanx + PIN scanx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 24.00 51.00 26.00 ; + END + END scanx + PIN nckx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 24.00 66.00 26.00 ; + END + END nckx + PIN ckx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 24.00 76.00 26.00 ; + END + END ckx + PIN scin + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END scin + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 117.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 117.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 118.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 24.00 81.00 26.00 ; + RECT 74.00 24.00 81.00 26.00 ; + RECT 4.00 24.00 36.00 26.00 ; + RECT 14.00 19.00 26.00 21.00 ; + END +END dp_sff_scan_x4 + + +MACRO dp_sff_scan_x4_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN ckx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 59.00 76.00 61.00 ; + RECT 74.00 54.00 76.00 56.00 ; + RECT 74.00 49.00 76.00 51.00 ; + RECT 74.00 44.00 76.00 46.00 ; + RECT 74.00 39.00 76.00 41.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 74.00 14.00 76.00 16.00 ; + END + END ckx + PIN nwenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 59.00 16.00 61.00 ; + RECT 14.00 54.00 16.00 56.00 ; + RECT 14.00 49.00 16.00 51.00 ; + RECT 14.00 44.00 16.00 46.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END nwenx + PIN wenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 24.00 54.00 26.00 56.00 ; + RECT 24.00 49.00 26.00 51.00 ; + RECT 24.00 44.00 26.00 46.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END wenx + PIN nscanx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END nscanx + PIN scanx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END scanx + PIN nckx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 59.00 66.00 61.00 ; + RECT 64.00 54.00 66.00 56.00 ; + RECT 64.00 49.00 66.00 51.00 ; + RECT 64.00 44.00 66.00 46.00 ; + RECT 64.00 39.00 66.00 41.00 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END nckx + PIN scout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 104.00 39.00 106.00 41.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 104.00 29.00 106.00 31.00 ; + RECT 104.00 24.00 106.00 26.00 ; + RECT 104.00 19.00 106.00 21.00 ; + RECT 104.00 14.00 106.00 16.00 ; + RECT 104.00 9.00 106.00 11.00 ; + END + END scout + PIN scin + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 89.00 64.00 91.00 66.00 ; + END + END scin + PIN wen + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 84.00 21.00 86.00 ; + END + END wen + PIN scan + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 84.00 46.00 86.00 ; + END + END scan + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 69.00 84.00 71.00 86.00 ; + END + END ck + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 117.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 117.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 117.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 117.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 118.50 41.00 ; + RECT 1.50 59.00 118.50 91.00 ; + LAYER L_ALU2 ; + RECT 14.00 59.00 76.00 61.00 ; + RECT 14.00 39.00 76.00 41.00 ; + RECT 14.00 14.00 76.00 16.00 ; + END +END dp_sff_scan_x4_buf + + +MACRO dp_sff_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 90.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END q + PIN nwenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 24.00 11.00 26.00 ; + END + END nwenx + PIN nckx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 24.00 36.00 26.00 ; + END + END nckx + PIN ckx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 24.00 46.00 26.00 ; + END + END ckx + PIN wenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 24.00 21.00 26.00 ; + END + END wenx + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 87.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 87.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 88.50 41.00 ; + LAYER L_ALU2 ; + RECT 9.00 24.00 51.00 26.00 ; + RECT 24.00 19.00 81.00 21.00 ; + RECT 44.00 24.00 51.00 26.00 ; + RECT 24.00 19.00 81.00 21.00 ; + END +END dp_sff_x4 + + +MACRO dp_sff_x4_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 90.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN nckx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 34.00 54.00 36.00 56.00 ; + RECT 34.00 49.00 36.00 51.00 ; + RECT 34.00 44.00 36.00 46.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END nckx + PIN ckx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 59.00 46.00 61.00 ; + RECT 44.00 54.00 46.00 56.00 ; + RECT 44.00 49.00 46.00 51.00 ; + RECT 44.00 44.00 46.00 46.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END ckx + PIN nwenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END nwenx + PIN wenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END wenx + PIN wen + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 84.00 16.00 86.00 ; + END + END wen + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 84.00 41.00 86.00 ; + END + END ck + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 87.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 87.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 87.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 87.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 88.50 41.00 ; + RECT 1.50 59.00 88.50 91.00 ; + LAYER L_ALU2 ; + RECT 9.00 14.00 46.00 16.00 ; + RECT 9.00 39.00 46.00 41.00 ; + RECT 9.00 59.00 46.00 61.00 ; + END +END dp_sff_x4_buf + + +MACRO dp_ts_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN enx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END enx + PIN nenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END nenx + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + LAYER L_ALU2 ; + RECT 24.00 19.00 36.00 21.00 ; + END +END dp_ts_x4 + + +MACRO dp_ts_x4_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN enx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 34.00 54.00 36.00 56.00 ; + RECT 34.00 49.00 36.00 51.00 ; + RECT 34.00 44.00 36.00 46.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END enx + PIN nenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 24.00 54.00 26.00 56.00 ; + RECT 24.00 49.00 26.00 51.00 ; + RECT 24.00 44.00 26.00 46.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END nenx + PIN en + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 84.00 31.00 86.00 ; + END + END en + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 42.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 42.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + RECT 1.50 59.00 43.50 91.00 ; + LAYER L_ALU2 ; + RECT 24.00 59.00 36.00 61.00 ; + RECT 24.00 39.00 36.00 41.00 ; + RECT 24.00 14.00 37.00 16.00 ; + RECT 33.00 14.00 37.00 16.00 ; + END +END dp_ts_x4_buf + + +MACRO dp_ts_x8 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN enx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END enx + PIN nenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END nenx + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + LAYER L_ALU2 ; + RECT 34.00 19.00 46.00 21.00 ; + END +END dp_ts_x8 + + +MACRO dp_ts_x8_buf + CLASS CORE ; + ORIGIN 10.00 0.00 ; + SIZE 55.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN nenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 24.00 54.00 26.00 56.00 ; + RECT 24.00 49.00 26.00 51.00 ; + RECT 24.00 44.00 26.00 46.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END nenx + PIN enx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 34.00 54.00 36.00 56.00 ; + RECT 34.00 49.00 36.00 51.00 ; + RECT 34.00 44.00 36.00 46.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END enx + PIN en + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 84.00 31.00 86.00 ; + END + END en + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH -7.00 47.00 42.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH -7.00 53.00 42.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH -7.00 3.00 42.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH -7.00 97.00 42.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT -8.50 9.00 43.50 41.00 ; + RECT -8.50 59.00 43.50 91.00 ; + LAYER L_ALU2 ; + RECT 24.00 14.00 36.00 16.00 ; + RECT 24.00 39.00 36.00 41.00 ; + RECT 24.00 59.00 36.00 61.00 ; + END +END dp_ts_x8_buf + + +END LIBRARY diff --git a/alliance/src/cells/src/dp_sxlib/dp_ts_x4.ap b/alliance/src/cells/src/dp_sxlib/dp_ts_x4.ap new file mode 100644 index 00000000..53102cbe --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_ts_x4.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H dp_ts_x4,P,26/ 9/2000,100 +A 0,0,4500,5000 +R 1000,1000,ref_ref,q_10 +R 1000,1500,ref_ref,q_15 +R 1000,2000,ref_ref,q_20 +R 1000,2500,ref_ref,q_25 +R 1000,3000,ref_ref,q_30 +R 1000,3500,ref_ref,q_35 +R 1000,4000,ref_ref,q_40 +R 1500,1000,ref_ref,i_10 +R 1500,3000,ref_ref,i_30 +R 1500,3500,ref_ref,i_35 +R 1500,4000,ref_ref,i_40 +R 1500,1500,ref_ref,i_15 +R 1500,2000,ref_ref,i_20 +R 1500,2500,ref_ref,i_25 +R 2500,2000,ref_ref,nenx +R 3500,2000,ref_ref,enx +S 2000,3500,2400,3500,200,*,RIGHT,ALU1 +S 2000,1000,3600,1000,200,*,RIGHT,ALU1 +S 3500,2000,3500,2000,200,enx,LEFT,CALU3 +S 2500,2000,2500,2000,200,nenx,LEFT,CALU3 +S 2000,1000,2000,3500,100,*,DOWN,ALU1 +S 2500,1500,2500,3000,100,*,DOWN,ALU1 +S 3500,1500,3500,3000,100,*,DOWN,ALU1 +S 2000,4000,4200,4000,100,*,RIGHT,ALU1 +S 4200,1000,4200,4000,100,*,DOWN,ALU1 +S 3500,1500,3700,1500,200,*,RIGHT,ALU1 +S 3700,1500,3900,1500,300,*,RIGHT,POLY +S 3300,3000,3500,3000,300,*,RIGHT,POLY +S 2500,3000,2700,3000,300,*,RIGHT,POLY +S 2500,1500,2700,1500,300,*,RIGHT,POLY +S 3900,2000,3900,3100,100,*,UP,POLY +S 3300,1400,3300,2000,100,*,DOWN,POLY +S 1500,2000,3900,2000,100,*,RIGHT,POLY +S 600,1400,2000,1400,100,*,RIGHT,POLY +S 600,2600,1900,2600,100,*,LEFT,POLY +S 1900,2600,1900,4000,100,*,DOWN,POLY +S 0,3900,4500,3900,2400,*,LEFT,NWELL +S 2700,3100,2700,4400,100,*,UP,PTRANS +S 3600,3300,3600,4700,300,*,UP,PDIF +S 4200,3300,4200,4200,300,*,UP,PDIF +S 3900,3100,3900,4400,100,*,UP,PTRANS +S 3000,3300,3000,4200,300,*,UP,PDIF +S 3300,3100,3300,4400,100,*,UP,PTRANS +S 2400,3300,2400,4200,300,*,UP,PDIF +S 2400,800,2400,1200,300,*,UP,NDIF +S 3600,800,3600,1200,300,*,UP,NDIF +S 3000,400,3000,1200,300,*,UP,NDIF +S 3300,600,3300,1400,100,*,UP,NTRANS +S 2700,600,2700,1400,100,*,UP,NTRANS +S 4200,800,4200,1200,300,*,UP,NDIF +S 3900,600,3900,1400,100,*,UP,NTRANS +S 300,500,300,1000,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 600,100,600,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 2500,2000,3500,2000,200,*,RIGHT,TALU2 +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,4700,4500,4700,600,vdd,LEFT,CALU1 +S 1000,1000,1000,4000,200,q,UP,CALU1 +S 1500,1000,1500,4000,200,i,UP,CALU1 +V 3500,3000,CONT_POLY,* +V 3700,1500,CONT_POLY,* +V 3500,2000,CONT_VIA,* +V 3500,2000,CONT_VIA2,* +V 2500,3000,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 2500,2000,CONT_VIA,* +V 2500,2000,CONT_VIA2,* +V 1500,2000,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 2400,3500,CONT_DIF_P,* +V 3000,4000,CONT_DIF_P,* +V 3600,4500,CONT_DIF_P,* +V 4200,4000,CONT_DIF_P,* +V 3000,4700,CONT_BODY_N,* +V 2200,4700,CONT_BODY_N,* +V 4200,4700,CONT_BODY_N,* +V 4200,1000,CONT_DIF_N,* +V 2400,1000,CONT_DIF_N,* +V 3600,1000,CONT_DIF_N,* +V 3000,500,CONT_DIF_N,* +V 3600,300,CONT_BODY_P,* +V 4200,300,CONT_BODY_P,* +V 900,3000,CONT_DIF_P,* +V 2100,300,CONT_BODY_P,* +V 300,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_ts_x4.vbe b/alliance/src/cells/src/dp_sxlib/dp_ts_x4.vbe new file mode 100644 index 00000000..5793ced9 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_ts_x4.vbe @@ -0,0 +1,28 @@ +ENTITY dp_ts_x4 IS +PORT ( + enx : in BIT; + nenx : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END dp_ts_x4; + +ARCHITECTURE vbe OF dp_ts_x4 IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_ts_x4" + SEVERITY WARNING; + + ASSERT (enx xor nenx) + REPORT "wrong control signals on dp_ts_x4" + SEVERITY WARNING; + + label0 : BLOCK (enx = '1') + BEGIN + q <= GUARDED i; + END BLOCK label0; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_ts_x4_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_ts_x4_buf.ap new file mode 100644 index 00000000..f7eda45d --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_ts_x4_buf.ap @@ -0,0 +1,142 @@ +V ALLIANCE : 6 +H dp_ts_x4_buf,P,15/11/2000,100 +A 0,0,4500,10000 +R 3500,4000,ref_ref,enx +R 2500,4000,ref_ref,nenx +S 3400,1500,3600,1500,200,*,LEFT,ALU2 +S 0,9700,4500,9700,600,vss,RIGHT,CALU1 +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 0,5300,4500,5300,600,vdd,RIGHT,CALU1 +S 3500,1500,3500,6000,200,enx,DOWN,CALU3 +S 2500,1500,2500,6000,200,nenx,DOWN,CALU3 +S 0,5000,4500,5000,4600,*,RIGHT,NWELL +S 3300,7100,3300,8200,100,*,DOWN,PTRANS +S 3300,3200,3300,6500,100,*,UP,PTRANS +S 3600,3400,3600,6300,300,*,UP,PDIF +S 3900,3200,3900,6500,100,*,DOWN,PTRANS +S 2400,7300,2400,8000,300,*,UP,PDIF +S 4200,3400,4200,6300,300,*,DOWN,PDIF +S 2700,3200,2700,6500,100,*,UP,PTRANS +S 2400,3400,2400,6300,300,*,UP,PDIF +S 3000,3400,3000,6300,300,*,UP,PDIF +S 2100,3200,2100,6500,100,*,UP,PTRANS +S 1800,3400,1800,6300,300,*,UP,PDIF +S 3600,7300,3600,8000,300,*,UP,PDIF +S 2700,7100,2700,8200,100,*,DOWN,PTRANS +S 3100,7300,3100,8000,300,*,UP,PDIF +S 2700,8700,2700,9800,100,*,UP,NTRANS +S 3300,100,3300,1900,100,*,DOWN,NTRANS +S 2100,100,2100,1900,100,*,UP,NTRANS +S 2700,100,2700,1900,100,*,DOWN,NTRANS +S 3900,100,3900,1900,100,*,DOWN,NTRANS +S 2400,8900,2400,9600,300,*,UP,NDIF +S 2400,300,2400,1700,300,*,UP,NDIF +S 4200,300,4200,1700,300,*,UP,NDIF +S 1800,300,1800,1700,300,*,UP,NDIF +S 3000,8900,3000,9600,300,*,UP,NDIF +S 3000,300,3000,1700,300,*,UP,NDIF +S 3600,300,3600,1700,300,*,UP,NDIF +S 2700,8500,3300,8500,300,*,RIGHT,POLY +S 3300,1900,3300,3200,100,*,DOWN,POLY +S 3900,1900,3900,3200,100,*,UP,POLY +S 2700,1900,2700,3200,100,*,UP,POLY +S 2100,1900,2100,3200,100,*,DOWN,POLY +S 2700,8200,2700,8700,100,*,DOWN,POLY +S 3300,8200,3300,8600,100,*,DOWN,POLY +S 2400,1000,2400,4000,200,*,UP,ALU1 +S 3600,1000,3600,4000,200,*,UP,ALU1 +S 3000,500,3000,1500,200,*,UP,ALU1 +S 2400,7900,3600,7900,200,*,RIGHT,ALU1 +S 1800,500,1800,1500,200,*,UP,ALU1 +S 4200,2800,4200,6800,200,*,UP,ALU1 +S 4200,500,4200,1500,200,*,UP,ALU1 +S 4200,9000,4200,9700,200,*,UP,ALU1 +S 3000,9000,3000,9400,200,*,UP,ALU1 +S 1800,3500,1800,6800,200,*,UP,ALU1 +S 700,300,700,1500,200,*,DOWN,ALU1 +S 3000,2800,3000,7400,200,*,UP,ALU1 +S 1800,9000,1800,9700,200,*,DOWN,ALU1 +S 3300,6600,3900,6600,300,*,RIGHT,POLY +S 3600,6600,3600,7900,200,*,UP,ALU1 +S 2400,7400,2400,9000,200,*,DOWN,ALU1 +S 2100,2200,3000,2200,300,*,RIGHT,POLY +S 3300,2200,3900,2200,300,*,RIGHT,POLY +S 2900,2200,3600,2200,200,*,RIGHT,ALU1 +S 3000,8500,3000,8500,100,en,LEFT,CALU1 +S 2500,1500,3600,1500,200,*,RIGHT,TALU2 +S 2500,4000,3500,4000,200,*,LEFT,TALU2 +S 2500,6000,3500,6000,200,*,RIGHT,TALU2 +V 3500,1500,CONT_VIA2,* +V 1800,6800,CONT_BODY_N,* +V 4200,6800,CONT_BODY_N,* +V 3000,6800,CONT_BODY_N,* +V 3600,7400,CONT_DIF_P,* +V 3600,7900,CONT_DIF_P,* +V 3600,6000,CONT_DIF_P,* +V 2400,6000,CONT_DIF_P,* +V 2400,4000,CONT_DIF_P,* +V 2400,3500,CONT_DIF_P,* +V 3600,3500,CONT_DIF_P,* +V 3600,4000,CONT_DIF_P,* +V 4200,6000,CONT_DIF_P,* +V 4200,5500,CONT_DIF_P,* +V 4200,5000,CONT_DIF_P,* +V 4200,4500,CONT_DIF_P,* +V 4200,3500,CONT_DIF_P,* +V 4200,4000,CONT_DIF_P,* +V 3000,5000,CONT_DIF_P,* +V 3000,4000,CONT_DIF_P,* +V 3000,5500,CONT_DIF_P,* +V 3000,4500,CONT_DIF_P,* +V 3000,3500,CONT_DIF_P,* +V 1800,4000,CONT_DIF_P,* +V 1800,4500,CONT_DIF_P,* +V 1800,5000,CONT_DIF_P,* +V 1800,5500,CONT_DIF_P,* +V 1800,3500,CONT_DIF_P,* +V 1800,6000,CONT_DIF_P,* +V 4200,2900,CONT_BODY_N,* +V 1800,2900,CONT_BODY_N,* +V 3000,2900,CONT_BODY_N,* +V 2400,7400,CONT_DIF_P,* +V 3000,7400,CONT_DIF_P,* +V 2400,7900,CONT_DIF_P,* +V 3000,500,CONT_DIF_N,* +V 2400,1000,CONT_DIF_N,* +V 2400,1500,CONT_DIF_N,* +V 2400,9000,CONT_DIF_N,* +V 3000,1500,CONT_DIF_N,* +V 4200,1000,CONT_DIF_N,* +V 3000,1000,CONT_DIF_N,* +V 1800,1000,CONT_DIF_N,* +V 1800,1500,CONT_DIF_N,* +V 1800,500,CONT_DIF_N,* +V 3600,1500,CONT_DIF_N,* +V 4200,1500,CONT_DIF_N,* +V 4200,500,CONT_DIF_N,* +V 3600,1000,CONT_DIF_N,* +V 3000,9000,CONT_DIF_N,* +V 3000,9500,CONT_DIF_N,* +V 1800,9000,CONT_BODY_P,* +V 4200,9000,CONT_BODY_P,* +V 1800,9700,CONT_BODY_P,* +V 4200,9700,CONT_BODY_P,* +V 700,300,CONT_BODY_P,* +V 700,1500,CONT_BODY_P,* +V 700,900,CONT_BODY_P,* +V 3000,8500,CONT_POLY,* +V 2500,1500,CONT_VIA,* +V 3500,4000,CONT_VIA,* +V 3600,1500,CONT_VIA,* +V 3500,6000,CONT_VIA,* +V 2500,6000,CONT_VIA,* +V 2500,4000,CONT_VIA,* +V 2500,1500,CONT_VIA2,* +V 3500,4000,CONT_VIA2,* +V 2500,4000,CONT_VIA2,* +V 2500,6000,CONT_VIA2,* +V 3500,6000,CONT_VIA2,* +V 3600,6600,CONT_POLY,* +V 2900,2200,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_ts_x4_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_ts_x4_buf.vbe new file mode 100644 index 00000000..bc108cba --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_ts_x4_buf.vbe @@ -0,0 +1,21 @@ +ENTITY dp_ts_x4_buf IS +PORT ( + en : in BIT; + enx : out BIT; + nenx : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_ts_x4_buf; + +ARCHITECTURE vbe OF dp_ts_x4_buf IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_ts_x4_buf" + SEVERITY WARNING; + + enx <= en; + nenx <= not en; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_ts_x8.ap b/alliance/src/cells/src/dp_sxlib/dp_ts_x8.ap new file mode 100644 index 00000000..bd3be6d5 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_ts_x8.ap @@ -0,0 +1,126 @@ +V ALLIANCE : 6 +H dp_ts_x8,P,15/11/2000,100 +A 0,0,5500,5000 +R 4500,2000,ref_ref,enx +R 3500,2000,ref_ref,nenx +R 1000,1500,ref_ref,q_15 +R 1000,4000,ref_ref,q_40 +R 1000,3500,ref_ref,q_35 +R 500,1500,ref_ref,i_15 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 500,1000,ref_ref,i_10 +R 1000,1000,ref_ref,q_10 +R 1000,3000,ref_ref,q_30 +R 1000,2500,ref_ref,q_25 +R 1000,2000,ref_ref,q_20 +R 500,4000,ref_ref,i_40 +R 500,2500,ref_ref,i_25 +R 500,2000,ref_ref,i_20 +S 700,1400,3000,1400,100,*,RIGHT,POLY +S 700,2600,3000,2600,100,*,LEFT,POLY +S 500,1000,500,4000,200,i,UP,CALU1 +S 1000,1000,1000,4000,200,q,UP,CALU1 +S 0,4700,5500,4700,600,vdd,LEFT,CALU1 +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 1000,2000,2200,2000,200,*,RIGHT,ALU1 +S 700,2600,700,4900,100,*,UP,PTRANS +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 400,2800,400,4700,300,*,UP,PDIF +S 1000,2800,1000,4700,300,*,UP,PDIF +S 2500,2600,2500,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,UP,PDIF +S 1900,2600,1900,4900,100,*,UP,PTRANS +S 2200,2800,2200,4700,300,*,UP,PDIF +S 2800,2800,2800,4700,300,*,UP,PDIF +S 1300,100,1300,1400,100,*,UP,NTRANS +S 700,100,700,1400,100,*,UP,NTRANS +S 2500,100,2500,1400,100,*,UP,NTRANS +S 1900,100,1900,1400,100,*,UP,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 400,300,400,1200,300,*,UP,NDIF +S 1000,300,1000,1200,300,*,UP,NDIF +S 2800,300,2800,1200,300,*,UP,NDIF +S 2200,300,2200,1200,300,*,UP,NDIF +S 1600,500,1600,1000,200,*,DOWN,ALU1 +S 1600,3000,1600,4500,200,*,DOWN,ALU1 +S 2200,1000,2200,4000,200,*,UP,ALU1 +S 0,3900,5500,3900,2400,*,LEFT,NWELL +S 3700,3100,3700,4400,100,*,UP,PTRANS +S 4600,3300,4600,4700,300,*,UP,PDIF +S 5200,3300,5200,4200,300,*,UP,PDIF +S 4900,3100,4900,4400,100,*,UP,PTRANS +S 4000,3300,4000,4200,300,*,UP,PDIF +S 4300,3100,4300,4400,100,*,UP,PTRANS +S 3400,3300,3400,4200,300,*,UP,PDIF +S 4300,600,4300,1400,100,*,UP,NTRANS +S 3700,600,3700,1400,100,*,UP,NTRANS +S 4900,600,4900,1400,100,*,UP,NTRANS +S 3400,800,3400,1200,300,*,UP,NDIF +S 4600,800,4600,1200,300,*,UP,NDIF +S 4000,400,4000,1200,300,*,UP,NDIF +S 5200,800,5200,1200,300,*,UP,NDIF +S 500,2000,4900,2000,100,*,RIGHT,POLY +S 4700,1500,4900,1500,300,*,RIGHT,POLY +S 4300,3000,4500,3000,300,*,RIGHT,POLY +S 3500,3000,3700,3000,300,*,RIGHT,POLY +S 3500,1500,3700,1500,300,*,RIGHT,POLY +S 4900,2000,4900,3100,100,*,UP,POLY +S 4300,1400,4300,2000,100,*,DOWN,POLY +S 2900,4000,5200,4000,100,*,RIGHT,ALU1 +S 2900,1000,2900,1500,100,*,DOWN,ALU1 +S 4000,1000,4000,3500,100,*,DOWN,ALU1 +S 5200,1000,5200,4000,100,*,DOWN,ALU1 +S 3500,1500,3500,3000,200,*,DOWN,ALU1 +S 2900,2500,2900,4000,100,*,DOWN,ALU1 +S 2900,1000,4600,1000,100,*,RIGHT,ALU1 +S 3400,3500,4000,3500,100,*,RIGHT,ALU1 +S 4500,1500,4700,1500,200,*,RIGHT,ALU1 +S 3500,2000,4500,2000,200,*,RIGHT,TALU2 +S 4500,2000,4500,2000,200,enx,LEFT,CALU3 +S 3500,2000,3500,2000,200,nenx,LEFT,CALU3 +S 4500,1500,4500,3000,200,*,DOWN,ALU1 +V 3400,4700,CONT_BODY_N,* +V 3400,300,CONT_BODY_P,* +V 2200,4000,CONT_DIF_P,* +V 2200,3500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 2200,3000,CONT_DIF_P,* +V 1600,3000,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 2800,4500,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 1600,4000,CONT_DIF_P,* +V 1600,1000,CONT_DIF_N,* +V 2200,1000,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 2800,500,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 5200,4000,CONT_DIF_P,* +V 4000,4700,CONT_BODY_N,* +V 5200,4700,CONT_BODY_N,* +V 3400,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 5200,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 4000,500,CONT_DIF_N,* +V 4600,300,CONT_BODY_P,* +V 5200,300,CONT_BODY_P,* +V 2900,2500,CONT_POLY,* +V 4500,3000,CONT_POLY,* +V 4700,1500,CONT_POLY,* +V 3500,3000,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2900,1500,CONT_POLY,* +V 4500,2000,CONT_VIA,* +V 3500,2000,CONT_VIA,* +V 4500,2000,CONT_VIA2,* +V 3500,2000,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_ts_x8.vbe b/alliance/src/cells/src/dp_sxlib/dp_ts_x8.vbe new file mode 100644 index 00000000..9f939f6a --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_ts_x8.vbe @@ -0,0 +1,28 @@ +ENTITY dp_ts_x8 IS +PORT ( + enx : in BIT; + nenx : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END dp_ts_x8; + +ARCHITECTURE vbe OF dp_ts_x8 IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_ts_x8" + SEVERITY WARNING; + + ASSERT (enx xor nenx) + REPORT "wrong control signals on dp_ts_x8" + SEVERITY WARNING; + + label0 : BLOCK (enx = '1') + BEGIN + q <= GUARDED i; + END BLOCK label0; + +END; diff --git a/alliance/src/cells/src/dp_sxlib/dp_ts_x8_buf.ap b/alliance/src/cells/src/dp_sxlib/dp_ts_x8_buf.ap new file mode 100644 index 00000000..aa84ba43 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_ts_x8_buf.ap @@ -0,0 +1,142 @@ +V ALLIANCE : 6 +H dp_ts_x8_buf,P,14/11/2000,10 +A -100,0,450,1000 +R 250,400,ref_ref,nenx +R 350,400,ref_ref,enx +S 250,600,350,600,20,*,RIGHT,TALU2 +S 250,400,350,400,20,*,RIGHT,TALU2 +S 250,150,350,150,20,*,RIGHT,TALU2 +S -100,970,450,970,60,vss,RIGHT,CALU1 +S -100,30,450,30,60,vss,RIGHT,CALU1 +S -100,500,450,500,460,*,RIGHT,NWELL +S -100,470,450,470,60,vdd,RIGHT,CALU1 +S -100,530,450,530,60,vdd,RIGHT,CALU1 +S 330,220,390,220,30,*,RIGHT,POLY +S 290,220,360,220,20,*,RIGHT,ALU1 +S 210,220,300,220,30,*,RIGHT,POLY +S 360,660,360,790,20,*,UP,ALU1 +S 240,740,240,900,20,*,DOWN,ALU1 +S 330,660,390,660,30,*,RIGHT,POLY +S 180,900,180,970,20,*,DOWN,ALU1 +S 300,280,300,740,20,*,UP,ALU1 +S 70,30,70,150,20,*,DOWN,ALU1 +S 180,350,180,680,20,*,UP,ALU1 +S 300,900,300,940,20,*,UP,ALU1 +S 420,900,420,970,20,*,UP,ALU1 +S 420,50,420,150,20,*,UP,ALU1 +S 420,280,420,680,20,*,UP,ALU1 +S 180,50,180,150,20,*,UP,ALU1 +S 240,790,360,790,20,*,RIGHT,ALU1 +S 300,50,300,150,20,*,UP,ALU1 +S 360,100,360,400,20,*,UP,ALU1 +S 240,100,240,400,20,*,UP,ALU1 +S 330,820,330,860,10,*,DOWN,POLY +S 270,820,270,870,10,*,DOWN,POLY +S 210,190,210,320,10,*,DOWN,POLY +S 270,190,270,320,10,*,UP,POLY +S 390,190,390,320,10,*,UP,POLY +S 330,190,330,320,10,*,DOWN,POLY +S 270,850,330,850,30,*,RIGHT,POLY +S 360,30,360,170,30,*,UP,NDIF +S 300,30,300,170,30,*,UP,NDIF +S 300,890,300,960,30,*,UP,NDIF +S 180,30,180,170,30,*,UP,NDIF +S 420,30,420,170,30,*,UP,NDIF +S 240,30,240,170,30,*,UP,NDIF +S 240,890,240,960,30,*,UP,NDIF +S 390,10,390,190,10,*,DOWN,NTRANS +S 270,10,270,190,10,*,DOWN,NTRANS +S 210,10,210,190,10,*,UP,NTRANS +S 330,10,330,190,10,*,DOWN,NTRANS +S 270,870,270,980,10,*,UP,NTRANS +S 310,730,310,800,30,*,UP,PDIF +S 270,710,270,820,10,*,DOWN,PTRANS +S 360,730,360,800,30,*,UP,PDIF +S 180,340,180,630,30,*,UP,PDIF +S 210,320,210,650,10,*,UP,PTRANS +S 300,340,300,630,30,*,UP,PDIF +S 240,340,240,630,30,*,UP,PDIF +S 270,320,270,650,10,*,UP,PTRANS +S 420,340,420,630,30,*,DOWN,PDIF +S 240,730,240,800,30,*,UP,PDIF +S 390,320,390,650,10,*,DOWN,PTRANS +S 360,340,360,630,30,*,UP,PDIF +S 330,320,330,650,10,*,UP,PTRANS +S 330,710,330,820,10,*,DOWN,PTRANS +S 250,150,250,600,20,nenx,DOWN,CALU3 +S 350,150,350,600,20,enx,DOWN,CALU3 +S 300,850,300,850,10,en,LEFT,CALU1 +S 350,150,360,150,20,*,RIGHT,ALU1 +V 290,220,CONT_POLY,* +V 360,660,CONT_POLY,* +V 350,600,CONT_VIA2,* +V 250,600,CONT_VIA2,* +V 250,400,CONT_VIA2,* +V 350,400,CONT_VIA2,* +V 250,150,CONT_VIA2,* +V 250,400,CONT_VIA,* +V 250,600,CONT_VIA,* +V 350,600,CONT_VIA,* +V 350,400,CONT_VIA,* +V 250,150,CONT_VIA,* +V 300,850,CONT_POLY,* +V 70,90,CONT_BODY_P,* +V 70,150,CONT_BODY_P,* +V 70,30,CONT_BODY_P,* +V 420,970,CONT_BODY_P,* +V 180,970,CONT_BODY_P,* +V 420,900,CONT_BODY_P,* +V 180,900,CONT_BODY_P,* +V 300,950,CONT_DIF_N,* +V 300,900,CONT_DIF_N,* +V 360,100,CONT_DIF_N,* +V 420,50,CONT_DIF_N,* +V 420,150,CONT_DIF_N,* +V 360,150,CONT_DIF_N,* +V 180,50,CONT_DIF_N,* +V 180,150,CONT_DIF_N,* +V 180,100,CONT_DIF_N,* +V 300,100,CONT_DIF_N,* +V 420,100,CONT_DIF_N,* +V 300,150,CONT_DIF_N,* +V 240,900,CONT_DIF_N,* +V 240,150,CONT_DIF_N,* +V 240,100,CONT_DIF_N,* +V 300,50,CONT_DIF_N,* +V 240,790,CONT_DIF_P,* +V 300,740,CONT_DIF_P,* +V 240,740,CONT_DIF_P,* +V 300,290,CONT_BODY_N,* +V 180,290,CONT_BODY_N,* +V 420,290,CONT_BODY_N,* +V 180,600,CONT_DIF_P,* +V 180,350,CONT_DIF_P,* +V 180,550,CONT_DIF_P,* +V 180,500,CONT_DIF_P,* +V 180,450,CONT_DIF_P,* +V 180,400,CONT_DIF_P,* +V 300,350,CONT_DIF_P,* +V 300,450,CONT_DIF_P,* +V 300,550,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 300,500,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 420,450,CONT_DIF_P,* +V 420,500,CONT_DIF_P,* +V 420,550,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 360,350,CONT_DIF_P,* +V 240,350,CONT_DIF_P,* +V 240,400,CONT_DIF_P,* +V 240,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 360,790,CONT_DIF_P,* +V 360,740,CONT_DIF_P,* +V 300,680,CONT_BODY_N,* +V 420,680,CONT_BODY_N,* +V 180,680,CONT_BODY_N,* +V 350,150,CONT_VIA2,* +V 350,150,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/dp_sxlib/dp_ts_x8_buf.vbe b/alliance/src/cells/src/dp_sxlib/dp_ts_x8_buf.vbe new file mode 100644 index 00000000..66bbb142 --- /dev/null +++ b/alliance/src/cells/src/dp_sxlib/dp_ts_x8_buf.vbe @@ -0,0 +1,21 @@ +ENTITY dp_ts_x8_buf IS +PORT ( + en : in BIT; + enx : out BIT; + nenx : out BIT; + vdd : in BIT; + vss : in BIT +); +END dp_ts_x8_buf; + +ARCHITECTURE vbe OF dp_ts_x8_buf IS + +BEGIN + ASSERT (vdd and not vss) + REPORT "power supply is missing on dp_ts_x8_buf" + SEVERITY WARNING; + + enx <= en; + nenx <= not en; + +END; diff --git a/alliance/src/cells/src/padlib/CATAL b/alliance/src/cells/src/padlib/CATAL new file mode 100644 index 00000000..34c210f8 --- /dev/null +++ b/alliance/src/cells/src/padlib/CATAL @@ -0,0 +1,35 @@ +padreal G +padreal C +pck_sp C +pi_sp C +piot_sp C +piotw_sp C +pot_sp C +potw_sp C +po_sp C +pow_sp C +pvdde_sp C +pvddeck_sp C +pvddi_sp C +pvddick_sp C +pvsse_sp C +pvsseck_sp C +pvssi_sp C +pvssick_sp C +palck_sp C +pali_sp C +paliot_sp C +paliotw_sp C +palo_sp C +palot_sp C +palotw_sp C +palow_sp C +palvdde_sp C +palvddeck_sp C +palvddi_sp C +palvddick_sp C +palvsse_sp C +palvsseck_sp C +palvssi_sp C +palvssick_sp C +corner_sp C diff --git a/alliance/src/cells/src/padlib/Makefile.am b/alliance/src/cells/src/padlib/Makefile.am new file mode 100644 index 00000000..06361eba --- /dev/null +++ b/alliance/src/cells/src/padlib/Makefile.am @@ -0,0 +1,6 @@ +# $Id: Makefile.am,v 1.1 2002/04/29 15:51:50 czo Exp $ + +padlib_DATA=CATAL corner_sp.ap corner_sp.vbe padreal.ap padreal.cif padsymb.db palck_sp.ap pali_sp.ap paliot_sp.ap paliotw_sp.ap palo_sp.ap palot_sp.ap palotw_sp.ap palow_sp.ap palvdde_sp.ap palvddeck_sp.ap palvddi_sp.ap palvddick_sp.ap palvsse_sp.ap palvsseck_sp.ap palvssi_sp.ap palvssick_sp.ap pck_sp.al pck_sp.ap pck_sp.vbe pi_sp.al pi_sp.ap pi_sp.vbe piot_sp.al piot_sp.ap piot_sp.vbe piotw_sp.al piotw_sp.ap piotw_sp.vbe po_sp.al po_sp.ap po_sp.vbe pot_sp.al pot_sp.ap pot_sp.vbe potw_sp.al potw_sp.ap potw_sp.vbe pow_sp.al pow_sp.ap pow_sp.vbe pvdde_sp.al pvdde_sp.ap pvdde_sp.vbe pvddeck_sp.al pvddeck_sp.ap pvddeck_sp.vbe pvddi_sp.al pvddi_sp.ap pvddi_sp.vbe pvddick_sp.al pvddick_sp.ap pvddick_sp.vbe pvsse_sp.al pvsse_sp.ap pvsse_sp.vbe pvsseck_sp.al pvsseck_sp.ap pvsseck_sp.vbe pvssi_sp.al pvssi_sp.ap pvssi_sp.vbe pvssick_sp.al pvssick_sp.ap pvssick_sp.vbe + +EXTRA_DIST=$(dp_padlib) + diff --git a/alliance/src/cells/src/padlib/corner_sp.ap b/alliance/src/cells/src/padlib/corner_sp.ap new file mode 100644 index 00000000..d71aabe0 --- /dev/null +++ b/alliance/src/cells/src/padlib/corner_sp.ap @@ -0,0 +1,24 @@ +V ALLIANCE : 6 +H corner_sp,P,13/10/2000,100 +A 0,0,50000,50000 +C 48700,0,1200,ck,0,SOUTH,ALU2 +C 45300,0,4000,vssi,0,SOUTH,ALU2 +C 40900,0,4000,vddi,0,SOUTH,ALU2 +C 19700,0,12000,vsse,0,SOUTH,ALU2 +C 32500,0,12000,vdde,0,SOUTH,ALU2 +C 50000,4700,4000,vssi,1,EAST,ALU2 +C 50000,9100,4000,vddi,1,EAST,ALU2 +C 50000,30300,12000,vsse,1,EAST,ALU2 +C 50000,17500,12000,vdde,1,EAST,ALU2 +C 50000,1300,1200,ck,1,EAST,ALU2 +S 19700,0,19700,36200,12000,*,UP,ALU2 +S 48200,1300,50000,1300,1200,*,RIGHT,ALU2 +S 48700,100,48700,1800,1200,*,UP,ALU2 +S 43400,4700,50000,4700,4000,*,LEFT,ALU2 +S 45300,0,45300,6600,4000,*,UP,ALU2 +S 39000,9100,50000,9100,4000,*,LEFT,ALU2 +S 40900,0,40900,11000,4000,*,UP,ALU2 +S 26600,17500,50000,17500,12000,*,LEFT,ALU2 +S 32500,0,32500,23400,12000,*,UP,ALU2 +S 13800,30300,50000,30300,12000,*,LEFT,ALU2 +EOF diff --git a/alliance/src/cells/src/padlib/corner_sp.vbe b/alliance/src/cells/src/padlib/corner_sp.vbe new file mode 100644 index 00000000..bd9d7ca6 --- /dev/null +++ b/alliance/src/cells/src/padlib/corner_sp.vbe @@ -0,0 +1,27 @@ +-- VHDL data flow description generated from `corner_sp` +-- date : Thu Feb 23 17:06:23 1995 + + +-- Entity Declaration + +ENTITY corner_sp IS + PORT ( + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END corner_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF corner_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on corner_sp" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/padlib/padreal.ap b/alliance/src/cells/src/padlib/padreal.ap new file mode 100644 index 00000000..d5822782 --- /dev/null +++ b/alliance/src/cells/src/padlib/padreal.ap @@ -0,0 +1,7 @@ +V ALLIANCE : 6 +H padreal,P,13/10/2000,100 +A 0,7600,17200,21300 +C 8600,7600,10000,in,0,SOUTH,ALU1 +S 8600,7700,8600,21200,10000,*,UP,ALU1 +B 8600,15200,12200,12200,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/padlib/padreal.cif b/alliance/src/cells/src/padlib/padreal.cif new file mode 100644 index 00000000..8ce61cd4 --- /dev/null +++ b/alliance/src/cells/src/padlib/padreal.cif @@ -0,0 +1,24 @@ +(rds to CIF driver version 1.03 +technology /users/alc/distrib/dev/alliance-3.2/etc/prol10_7.rds +Wed May 21 16:49:13 1997 +padreal +distrib); + +DS1 5 2; +9 padreal; +(AB : 0.00, 0.00 150.50, 118.15 in micron); +4A 0 0 6020 4726; +LCC; +B4000 4000 3010 3320; +LCM; +B3500 1320 3010 660; +B4400 4400 3010 3320; +LCM2; +B4400 4400 3010 3320; +LCG; +B4000 4000 3010 3320; +DF; + +C1; +(AB : 0.00, 0.00 150.50, 118.15 in micron); +E diff --git a/alliance/src/cells/src/padlib/padsymb.db b/alliance/src/cells/src/padlib/padsymb.db new file mode 100644 index 00000000..7ef08ac8 --- /dev/null +++ b/alliance/src/cells/src/padlib/padsymb.db @@ -0,0 +1,60 @@ +#cell1 padsymb any library 31744 v7r5.6 +# 24-Nov-91 14:16 24-Nov-91 14:16 stacs * . +v1(50,padsymb +(33,CP +[padreal,cp] +[palck_sp,cp] +[pali_sp,cp] +[paliot_sp,cp] +[paliotw_sp,cp] +[palo_sp,cp] +[palot_sp,cp] +[palotw_sp,cp] +[palow_sp,cp] +[palvdde_sp,cp] +[palvddeck_sp,cp] +[palvddi_sp,cp] +[palvddick_sp,cp] +[palvsse_sp,cp] +[palvsseck_sp,cp] +[palvssi_sp,cp] +[palvssick_sp,cp] +[pck_sp,cp] +[pi_sp,cp] +[piot_sp,cp] +[piotw_sp,cp] +[po_sp,cp] +[pot_sp,cp] +[potw_sp,cp] +[pow_sp,cp] +[pvdde_sp,cp] +[pvddeck_sp,cp] +[pvddi_sp,cp] +[pvddick_sp,cp] +[pvsse_sp,cp] +[pvsseck_sp,cp] +[pvssi_sp,cp] +[pvssick_sp,cp] +) +(16,HNS +[pck_sp,hns] +[pi_sp,hns] +[piot_sp,hns] +[piotw_sp,hns] +[po_sp,hns] +[pot_sp,hns] +[potw_sp,hns] +[pow_sp,hns] +[pvdde_sp,hns] +[pvddeck_sp,hns] +[pvddi_sp,hns] +[pvddick_sp,hns] +[pvsse_sp,hns] +[pvsseck_sp,hns] +[pvssi_sp,hns] +[pvssick_sp,hns] +) +(1,CIF +[padreal,cif] +) +) diff --git a/alliance/src/cells/src/padlib/palck_sp.ap b/alliance/src/cells/src/padlib/palck_sp.ap new file mode 100644 index 00000000..ac3f5a7c --- /dev/null +++ b/alliance/src/cells/src/padlib/palck_sp.ap @@ -0,0 +1,823 @@ +V ALLIANCE : 6 +H palck_sp,P,13/10/2000,100 +A 300,100,17500,36400 +C 300,17600,12000,vdde,0,WEST,ALU2 +C 300,30400,12000,vsse,0,WEST,ALU2 +C 17500,30400,12000,vsse,1,EAST,ALU2 +C 17500,17600,12000,vdde,1,EAST,ALU2 +C 17500,9200,4000,vddi,1,EAST,ALU2 +C 17500,4800,4000,vssi,1,EAST,ALU2 +C 17500,1400,1200,ck,1,EAST,ALU2 +C 300,1400,1200,ck,0,WEST,ALU2 +C 300,9200,4000,vddi,0,WEST,ALU2 +C 300,4800,4000,vssi,0,WEST,ALU2 +S 15000,1000,15000,4900,200,*,UP,ALU1 +S 13800,1000,13800,4900,200,*,UP,ALU1 +S 12600,1000,12600,4900,200,*,UP,ALU1 +S 11300,6400,12000,6400,200,*,RIGHT,ALU1 +S 8400,500,15600,500,200,*,RIGHT,ALU1 +S 15600,500,15600,4000,200,*,UP,ALU1 +S 14400,500,14400,4000,200,*,UP,ALU1 +S 13200,500,13200,4000,200,*,UP,ALU1 +S 12000,500,12000,4000,200,*,UP,ALU1 +S 10800,500,10800,9200,200,*,UP,ALU1 +S 9600,500,9600,9200,200,*,UP,ALU1 +S 8400,500,8400,5500,200,*,UP,ALU1 +S 7800,4500,8400,4500,200,*,RIGHT,ALU1 +S 7800,6400,8400,6400,200,*,RIGHT,ALU1 +S 3700,5900,3700,12800,200,*,UP,ALU1 +S 1800,12800,11400,12800,200,*,RIGHT,ALU1 +S 2200,5900,2200,12800,1000,*,UP,ALU1 +S 4900,5900,4900,12800,200,*,UP,ALU1 +S 6100,5900,6100,12800,200,*,UP,ALU1 +S 6400,14400,8200,14400,200,*,RIGHT,ALU1 +S 6700,14400,6700,23400,800,*,UP,ALU1 +S 11400,7300,11400,12800,200,*,UP,ALU1 +S 7300,5900,7300,12800,200,*,UP,ALU1 +S 9000,5900,9000,12800,200,*,UP,ALU1 +S 10200,5900,10200,12800,200,*,UP,ALU1 +S 12000,4400,12000,13400,200,*,UP,ALU1 +S 8800,13400,12000,13400,200,*,RIGHT,ALU1 +S 8800,13400,8800,15100,200,*,UP,ALU1 +S 8200,14400,8200,23400,200,*,UP,ALU1 +S 9300,25100,10100,25100,200,*,RIGHT,ALU1 +S 9700,25100,9700,29600,1000,*,UP,ALU1 +S 300,30400,17500,30400,12000,log.vsse,RIGHT,ALU2 +S 8700,6400,11800,6400,300,*,RIGHT,POLY +S 11400,6800,11400,12900,300,*,UP,NTIE +S 1800,6000,11400,6000,300,*,RIGHT,NTIE +S 13200,4500,13200,5400,200,*,DOWN,ALU1 +S 14400,4500,14400,5400,200,*,DOWN,ALU1 +S 12000,5400,14400,5400,200,*,RIGHT,ALU1 +S 1700,12800,11400,12800,300,*,RIGHT,NTIE +S 1600,9400,11600,9400,7200,*,RIGHT,NWELL +S 10200,6700,10200,9300,300,*,UP,PDIF +S 16200,1000,16200,5000,200,*,UP,ALU1 +S 11400,1000,11400,5000,200,*,UP,ALU1 +S 10200,1000,10200,5000,200,*,UP,ALU1 +S 8700,4500,15300,4500,300,*,RIGHT,POLY +S 1800,1100,16200,1100,300,*,RIGHT,PTIE +S 1800,4900,16200,4900,300,*,RIGHT,PTIE +S 12000,1600,12000,4200,200,*,UP,NDIF +S 13800,1600,13800,4200,200,*,UP,NDIF +S 15600,1600,15600,4200,300,*,UP,NDIF +S 15600,1600,15600,4200,200,*,UP,NDIF +S 16200,1000,16200,5000,300,*,UP,PTIE +S 14700,1400,14700,4400,100,*,UP,NTRANS +S 14100,1400,14100,4400,100,*,UP,NTRANS +S 15000,1600,15000,4200,200,*,UP,NDIF +S 14400,1600,14400,4200,200,*,UP,NDIF +S 15300,1400,15300,4400,100,*,UP,NTRANS +S 12900,1400,12900,4400,100,*,UP,NTRANS +S 12600,1600,12600,4200,200,*,UP,NDIF +S 13200,1600,13200,4200,200,*,UP,NDIF +S 12300,1400,12300,4400,100,*,UP,NTRANS +S 13500,1400,13500,4400,100,*,UP,NTRANS +S 11100,1400,11100,4400,100,*,UP,NTRANS +S 11700,1400,11700,4400,100,*,UP,NTRANS +S 10500,1400,10500,4400,100,*,UP,NTRANS +S 10200,1600,10200,4200,300,*,UP,NDIF +S 11400,1600,11400,4200,200,*,UP,NDIF +S 10800,1600,10800,4200,200,*,UP,NDIF +S 10800,6700,10800,9300,300,*,UP,PDIF +S 10200,6700,10200,9300,300,*,UP,PDIF +S 10500,6500,10500,9500,100,*,UP,PTRANS +S 9600,6700,9600,9300,300,*,UP,PDIF +S 9900,6500,9900,9500,100,*,UP,PTRANS +S 9300,6500,9300,9500,100,*,UP,PTRANS +S 9900,1400,9900,4400,100,*,UP,NTRANS +S 9300,1400,9300,4400,100,*,UP,NTRANS +S 3100,1600,3100,4200,200,*,UP,NDIF +S 8400,1600,8400,4200,300,*,UP,NDIF +S 8700,1400,8700,4400,100,*,UP,NTRANS +S 9000,1600,9000,4200,200,*,UP,NDIF +S 9600,1600,9600,4200,200,*,UP,NDIF +S 3700,1600,3700,4200,200,*,UP,NDIF +S 5200,1400,5200,4400,100,*,UP,NTRANS +S 4600,1400,4600,4400,100,*,UP,NTRANS +S 2800,1400,2800,4400,100,*,UP,NTRANS +S 6700,1600,6700,4200,200,*,UP,NDIF +S 4000,1400,4000,4400,100,*,UP,NTRANS +S 3400,1400,3400,4400,100,*,UP,NTRANS +S 6100,1600,6100,4200,200,*,UP,NDIF +S 5500,1600,5500,4200,200,*,UP,NDIF +S 4900,1600,4900,4200,200,*,UP,NDIF +S 4300,1600,4300,4200,200,*,UP,NDIF +S 2500,1600,2500,4200,300,*,UP,NDIF +S 7300,1600,7300,4200,400,*,UP,NDIF +S 7000,1400,7000,4400,100,*,UP,NTRANS +S 6400,1400,6400,4400,100,*,UP,NTRANS +S 5800,1400,5800,4400,100,*,UP,NTRANS +S 2500,6700,2500,12300,400,*,UP,PDIF +S 8400,6700,8400,9300,400,*,UP,PDIF +S 8700,6500,8700,9500,100,*,UP,PTRANS +S 9000,6700,9000,9300,300,*,UP,PDIF +S 7000,6500,7000,12500,100,*,UP,PTRANS +S 3100,6700,3100,12300,200,*,UP,PDIF +S 3700,6700,3700,12300,200,*,UP,PDIF +S 4300,6700,4300,12300,200,*,UP,PDIF +S 4900,6700,4900,12300,200,*,UP,PDIF +S 5500,6700,5500,12300,200,*,UP,PDIF +S 6100,6700,6100,12300,200,*,UP,PDIF +S 6700,6700,6700,12300,200,*,UP,PDIF +S 4600,6500,4600,12500,100,*,UP,PTRANS +S 5200,6500,5200,12500,100,*,UP,PTRANS +S 5800,6500,5800,12500,100,*,UP,PTRANS +S 6400,6500,6400,12500,100,*,UP,PTRANS +S 2800,6500,2800,12500,100,*,UP,PTRANS +S 3400,6500,3400,12500,100,*,UP,PTRANS +S 4000,6500,4000,12500,100,*,UP,PTRANS +S 3700,6700,3700,12300,400,*,UP,PDIF +S 4900,6700,4900,12300,400,*,UP,PDIF +S 6100,6700,6100,12300,400,*,UP,PDIF +S 7300,6700,7300,12300,400,*,UP,PDIF +S 1800,5900,1800,12800,300,*,UP,NTIE +S 1900,1200,1900,5000,300,*,UP,PTIE +S 2800,4500,8400,4500,300,*,RIGHT,POLY +S 2800,12500,7000,12500,100,*,RIGHT,POLY +S 2800,1400,7000,1400,100,*,RIGHT,POLY +S 8700,6300,8700,6500,100,*,UP,POLY +S 2800,6400,8400,6400,300,*,RIGHT,POLY +S 8400,5300,8400,9200,200,*,UP,ALU1 +S 9000,1000,9000,5000,200,*,UP,ALU1 +S 2200,1000,2200,5000,900,*,UP,ALU1 +S 7300,1000,7300,5000,200,*,UP,ALU1 +S 6100,1000,6100,5000,200,*,UP,ALU1 +S 4900,1000,4900,5000,200,*,UP,ALU1 +S 3700,1000,3700,5000,200,*,UP,ALU1 +S 3100,1000,3100,12300,200,*,UP,ALU1 +S 4300,1000,4300,12300,200,*,UP,ALU1 +S 5500,1000,5500,12300,200,*,UP,ALU1 +S 6700,1000,6700,12300,200,*,UP,ALU1 +S 7600,15000,7600,29900,200,*,UP,ALU1 +S 8800,15000,8800,29900,200,*,UP,ALU1 +S 8200,24500,8200,29600,200,*,UP,ALU1 +S 9400,25600,9400,29000,300,*,UP,NDIF +S 8800,25600,8800,29000,300,*,UP,NDIF +S 8200,25600,8200,29000,300,*,UP,NDIF +S 7600,25600,7600,29000,300,*,UP,NDIF +S 7300,25400,7300,29200,100,*,UP,NTRANS +S 7900,25400,7900,29200,100,*,UP,NTRANS +S 8500,25400,8500,29200,100,*,UP,NTRANS +S 9100,25400,9100,29200,100,*,UP,NTRANS +S 7100,29500,9500,29500,300,*,RIGHT,PTIE +S 9400,14900,9400,22800,300,*,UP,PDIF +S 8800,14900,8800,22800,200,*,UP,PDIF +S 8200,14900,8200,22800,200,*,UP,PDIF +S 7600,14900,7600,22800,200,*,UP,PDIF +S 7300,14700,7300,23000,100,*,UP,PTRANS +S 7900,14700,7900,23000,100,*,UP,PTRANS +S 8500,14700,8500,23000,100,*,UP,PTRANS +S 9100,14700,9100,23000,100,*,UP,PTRANS +S 8400,14200,8400,23500,2800,*,UP,NWELL +S 8800,24500,8800,24700,200,*,UP,POLY +S 7100,25100,8500,25100,300,*,RIGHT,PTIE +S 7300,25400,9100,25400,100,*,RIGHT,POLY +S 8800,24600,8800,25400,200,*,UP,POLY +S 8800,24600,9300,24600,300,*,RIGHT,POLY +S 7100,23300,9500,23300,300,*,RIGHT,NTIE +S 6700,14200,6700,23500,1000,*,UP,NWELL +S 9900,14200,9900,23500,600,*,UP,NWELL +S 7000,25600,7000,29000,300,*,UP,NDIF +S 7000,14900,7000,22800,300,*,UP,PDIF +S 6400,14400,6400,23400,300,*,UP,NTIE +S 6400,23300,7000,23300,300,*,RIGHT,NTIE +S 10000,27100,10000,29300,300,*,UP,PTIE +S 9400,29500,10100,29500,300,*,RIGHT,PTIE +S 6300,29500,7100,29500,300,*,RIGHT,PTIE +S 6400,25000,6400,29600,300,*,UP,PTIE +S 6300,25100,7100,25100,300,*,RIGHT,PTIE +S 6700,25000,6700,29600,900,*,UP,ALU1 +S 7500,30400,9400,30400,900,*,RIGHT,ALU1 +S 9300,24600,9700,24600,200,*,RIGHT,ALU1 +S 10000,25000,10000,27300,300,*,UP,PTIE +S 9100,25100,10000,25100,300,*,RIGHT,PTIE +S 9800,14200,9800,23500,400,*,UP,NWELL +S 6400,14400,8500,14400,300,*,RIGHT,NTIE +S 7300,14700,9100,14700,100,*,RIGHT,POLY +S 9500,23300,10000,23300,300,*,RIGHT,NTIE +S 10000,14400,10000,23400,300,*,UP,NTIE +S 9900,14200,9900,23500,600,*,UP,NWELL +S 9700,14300,9700,23400,1000,*,UP,ALU1 +S 8800,13700,8800,14600,200,*,UP,POLY +S 7600,13800,8300,13800,200,*,RIGHT,ALU1 +S 8200,13800,8800,13800,300,*,RIGHT,POLY +S 9100,14400,10000,14400,300,*,RIGHT,NTIE +S 8900,30900,8900,36400,1000,*,UP,ALU1 +S 300,1400,17500,1400,1200,log.ck,RIGHT,ALU2 +S 300,4800,17500,4800,4000,log.vssi,RIGHT,ALU2 +S 300,9200,17500,9200,4000,log.vddi,RIGHT,ALU2 +S 300,17600,17500,17600,12000,log.vdde,RIGHT,ALU2 +B 6700,27300,800,4600,CONT_VIA,* +B 9700,18800,1000,9300,CONT_VIA,* +B 6700,18900,800,9200,CONT_VIA,* +B 2200,3900,1000,2200,CONT_VIA,* +B 2200,9200,1000,4000,CONT_VIA,* +B 14400,5400,200,200,CONT_TURN1,* +B 8400,500,200,200,CONT_TURN1,* +B 15600,500,200,200,CONT_TURN1,* +B 8800,13400,200,200,CONT_TURN1,* +B 12000,13400,200,200,CONT_TURN1,* +B 10100,25100,200,200,CONT_TURN1,* +B 9300,25100,200,200,CONT_TURN1,* +V 11800,6400,CONT_POLY,* +V 11400,6400,CONT_POLY,* +V 14400,4500,CONT_POLY,* +V 13200,4500,CONT_POLY,* +V 12000,4500,CONT_POLY,* +V 11400,11600,CONT_BODY_N,* +V 11400,12400,CONT_BODY_N,* +V 11400,12000,CONT_BODY_N,* +V 11400,12800,CONT_BODY_N,* +V 11400,10500,CONT_BODY_N,* +V 11400,10000,CONT_BODY_N,* +V 11400,8900,CONT_BODY_N,* +V 11400,8400,CONT_BODY_N,* +V 11400,7400,CONT_BODY_N,* +V 11400,7900,CONT_VIA,* +V 11400,11000,CONT_VIA,* +V 11400,9400,CONT_VIA,* +V 10200,7000,CONT_DIF_P,* +V 10200,7800,CONT_DIF_P,* +V 10200,7000,CONT_DIF_P,* +V 10200,8200,CONT_DIF_P,* +V 10200,9000,CONT_DIF_P,* +V 10200,6000,CONT_BODY_N,* +V 10200,12800,CONT_BODY_N,* +V 10200,7400,CONT_VIA,* +V 10200,8600,CONT_VIA,* +V 10200,11000,CONT_VIA,* +V 10200,9400,CONT_VIA,* +V 10200,10200,CONT_VIA,* +V 16200,2900,CONT_VIA,* +V 16200,3700,CONT_VIA,* +V 16200,4500,CONT_VIA,* +V 15000,1100,CONT_BODY_P,* +V 13800,1100,CONT_BODY_P,* +V 12600,1100,CONT_BODY_P,* +V 11400,1100,CONT_BODY_P,* +V 10200,1100,CONT_BODY_P,* +V 13800,4900,CONT_BODY_P,* +V 8400,2400,CONT_DIF_N,* +V 9600,2400,CONT_DIF_N,* +V 10800,2400,CONT_DIF_N,* +V 12000,2400,CONT_DIF_N,* +V 13200,2400,CONT_DIF_N,* +V 14400,2400,CONT_DIF_N,* +V 15600,2400,CONT_DIF_N,* +V 12600,4900,CONT_BODY_P,* +V 11400,4900,CONT_BODY_P,* +V 10200,4900,CONT_BODY_P,* +V 10800,7000,CONT_DIF_P,* +V 10800,8600,CONT_DIF_P,* +V 10800,8100,CONT_DIF_P,* +V 10800,7500,CONT_DIF_P,* +V 10800,9100,CONT_DIF_P,* +V 15000,4900,CONT_BODY_P,* +V 10800,3900,CONT_DIF_N,* +V 10800,2900,CONT_DIF_N,* +V 10800,1900,CONT_DIF_N,* +V 10800,3400,CONT_DIF_N,* +V 12000,1900,CONT_DIF_N,* +V 12000,2900,CONT_DIF_N,* +V 12000,3900,CONT_DIF_N,* +V 12000,3400,CONT_DIF_N,* +V 13200,3400,CONT_DIF_N,* +V 13200,3900,CONT_DIF_N,* +V 13200,2900,CONT_DIF_N,* +V 13200,1900,CONT_DIF_N,* +V 15000,2500,CONT_DIF_N,* +V 15000,2000,CONT_DIF_N,* +V 15000,3500,CONT_DIF_N,* +V 15000,4000,CONT_VIA,* +V 15000,3000,CONT_VIA,* +V 14400,1900,CONT_DIF_N,* +V 14400,2900,CONT_DIF_N,* +V 14400,3900,CONT_DIF_N,* +V 14400,3400,CONT_DIF_N,* +V 13800,3500,CONT_DIF_N,* +V 13800,2000,CONT_DIF_N,* +V 13800,2500,CONT_DIF_N,* +V 13800,3000,CONT_VIA,* +V 13800,4000,CONT_VIA,* +V 12600,2500,CONT_DIF_N,* +V 12600,3500,CONT_DIF_N,* +V 12600,2000,CONT_DIF_N,* +V 12600,3000,CONT_VIA,* +V 12600,4000,CONT_VIA,* +V 11400,2000,CONT_DIF_N,* +V 11400,3500,CONT_DIF_N,* +V 11400,2500,CONT_DIF_N,* +V 11400,4000,CONT_VIA,* +V 11400,3000,CONT_VIA,* +V 10200,2500,CONT_DIF_N,* +V 10200,3500,CONT_DIF_N,* +V 10200,2000,CONT_DIF_N,* +V 10200,3000,CONT_VIA,* +V 10200,4000,CONT_VIA,* +V 15600,1900,CONT_DIF_N,* +V 15600,3900,CONT_DIF_N,* +V 15600,3400,CONT_DIF_N,* +V 15600,2900,CONT_DIF_N,* +V 16200,2500,CONT_BODY_P,* +V 16200,2100,CONT_BODY_P,* +V 16200,4900,CONT_BODY_P,* +V 16200,1700,CONT_BODY_P,* +V 16200,1300,CONT_BODY_P,* +V 16200,4100,CONT_BODY_P,* +V 16200,3300,CONT_BODY_P,* +V 9600,9100,CONT_DIF_P,* +V 9600,7500,CONT_DIF_P,* +V 9600,8100,CONT_DIF_P,* +V 9600,8600,CONT_DIF_P,* +V 9600,7000,CONT_DIF_P,* +V 9600,2900,CONT_DIF_N,* +V 9000,3500,CONT_DIF_N,* +V 9000,2000,CONT_DIF_N,* +V 8400,2900,CONT_DIF_N,* +V 8400,3400,CONT_DIF_N,* +V 8400,3900,CONT_DIF_N,* +V 9600,3900,CONT_DIF_N,* +V 9600,3400,CONT_DIF_N,* +V 2500,1900,CONT_DIF_N,* +V 2500,3900,CONT_DIF_N,* +V 2500,3400,CONT_DIF_N,* +V 2500,2400,CONT_DIF_N,* +V 2500,2900,CONT_DIF_N,* +V 9000,2500,CONT_DIF_N,* +V 9600,1900,CONT_DIF_N,* +V 8400,1900,CONT_DIF_N,* +V 4900,3500,CONT_DIF_N,* +V 3700,2000,CONT_DIF_N,* +V 3700,3500,CONT_DIF_N,* +V 3700,2500,CONT_DIF_N,* +V 3100,2900,CONT_DIF_N,* +V 3100,2400,CONT_DIF_N,* +V 3100,3900,CONT_DIF_N,* +V 3100,3400,CONT_DIF_N,* +V 5500,3400,CONT_DIF_N,* +V 5500,3900,CONT_DIF_N,* +V 4300,2400,CONT_DIF_N,* +V 4300,2900,CONT_DIF_N,* +V 4300,3900,CONT_DIF_N,* +V 4300,3400,CONT_DIF_N,* +V 4900,2500,CONT_DIF_N,* +V 4900,2000,CONT_DIF_N,* +V 6700,2900,CONT_DIF_N,* +V 6700,3900,CONT_DIF_N,* +V 6700,3400,CONT_DIF_N,* +V 6100,2500,CONT_DIF_N,* +V 6100,2000,CONT_DIF_N,* +V 6100,3500,CONT_DIF_N,* +V 5500,2900,CONT_DIF_N,* +V 5500,2400,CONT_DIF_N,* +V 7300,3500,CONT_DIF_N,* +V 7300,2500,CONT_DIF_N,* +V 7300,2000,CONT_DIF_N,* +V 6700,2400,CONT_DIF_N,* +V 9000,7000,CONT_DIF_P,* +V 9000,7800,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 6700,10600,CONT_DIF_P,* +V 9000,9000,CONT_DIF_P,* +V 9000,8200,CONT_DIF_P,* +V 8400,8600,CONT_DIF_P,* +V 8400,8100,CONT_DIF_P,* +V 8400,7500,CONT_DIF_P,* +V 8400,7000,CONT_DIF_P,* +V 8400,9100,CONT_DIF_P,* +V 6700,12200,CONT_DIF_P,* +V 6700,7800,CONT_DIF_P,* +V 6700,8200,CONT_DIF_P,* +V 6700,8600,CONT_DIF_P,* +V 6700,9000,CONT_DIF_P,* +V 6700,9400,CONT_DIF_P,* +V 6700,9800,CONT_DIF_P,* +V 6700,10200,CONT_DIF_P,* +V 5500,9400,CONT_DIF_P,* +V 5500,9000,CONT_DIF_P,* +V 5500,8600,CONT_DIF_P,* +V 6700,7000,CONT_DIF_P,* +V 6700,7400,CONT_DIF_P,* +V 6700,11000,CONT_DIF_P,* +V 6700,11400,CONT_DIF_P,* +V 6700,11800,CONT_DIF_P,* +V 5500,11800,CONT_DIF_P,* +V 5500,11400,CONT_DIF_P,* +V 5500,11000,CONT_DIF_P,* +V 5500,7400,CONT_DIF_P,* +V 5500,7000,CONT_DIF_P,* +V 5500,10600,CONT_DIF_P,* +V 5500,10200,CONT_DIF_P,* +V 5500,9800,CONT_DIF_P,* +V 4300,9800,CONT_DIF_P,* +V 4300,10200,CONT_DIF_P,* +V 4300,10600,CONT_DIF_P,* +V 4300,7000,CONT_DIF_P,* +V 4300,7400,CONT_DIF_P,* +V 5500,8200,CONT_DIF_P,* +V 5500,7800,CONT_DIF_P,* +V 5500,12200,CONT_DIF_P,* +V 4300,11400,CONT_DIF_P,* +V 4300,11800,CONT_DIF_P,* +V 4300,12200,CONT_DIF_P,* +V 4300,7800,CONT_DIF_P,* +V 4300,8200,CONT_DIF_P,* +V 4300,8600,CONT_DIF_P,* +V 4300,9000,CONT_DIF_P,* +V 4300,9400,CONT_DIF_P,* +V 3100,9400,CONT_DIF_P,* +V 3100,9000,CONT_DIF_P,* +V 3100,8600,CONT_DIF_P,* +V 3100,8200,CONT_DIF_P,* +V 3100,7800,CONT_DIF_P,* +V 3100,7400,CONT_DIF_P,* +V 3100,7000,CONT_DIF_P,* +V 4300,11000,CONT_DIF_P,* +V 2500,7200,CONT_DIF_P,* +V 3100,12200,CONT_DIF_P,* +V 3100,11800,CONT_DIF_P,* +V 3100,11400,CONT_DIF_P,* +V 3100,11000,CONT_DIF_P,* +V 3100,10600,CONT_DIF_P,* +V 3100,10200,CONT_DIF_P,* +V 3100,9800,CONT_DIF_P,* +V 2500,11200,CONT_DIF_P,* +V 2500,10700,CONT_DIF_P,* +V 2500,10200,CONT_DIF_P,* +V 2500,9700,CONT_DIF_P,* +V 2500,9200,CONT_DIF_P,* +V 2500,8700,CONT_DIF_P,* +V 2500,8200,CONT_DIF_P,* +V 2500,7700,CONT_DIF_P,* +V 2500,12200,CONT_DIF_P,* +V 2500,11700,CONT_DIF_P,* +V 7300,12200,CONT_DIF_P,* +V 7300,7800,CONT_DIF_P,* +V 7300,8200,CONT_DIF_P,* +V 7300,9000,CONT_DIF_P,* +V 7300,9400,CONT_DIF_P,* +V 7300,10200,CONT_DIF_P,* +V 7300,10600,CONT_DIF_P,* +V 7300,11400,CONT_DIF_P,* +V 7300,11800,CONT_DIF_P,* +V 6100,10200,CONT_DIF_P,* +V 6100,9400,CONT_DIF_P,* +V 6100,9000,CONT_DIF_P,* +V 6100,8200,CONT_DIF_P,* +V 6100,7800,CONT_DIF_P,* +V 6100,12200,CONT_DIF_P,* +V 6100,11800,CONT_DIF_P,* +V 7300,7000,CONT_DIF_P,* +V 4900,9000,CONT_DIF_P,* +V 4900,8200,CONT_DIF_P,* +V 4900,7800,CONT_DIF_P,* +V 4900,12200,CONT_DIF_P,* +V 4900,11800,CONT_DIF_P,* +V 6100,7000,CONT_DIF_P,* +V 6100,11400,CONT_DIF_P,* +V 6100,10600,CONT_DIF_P,* +V 3700,7800,CONT_DIF_P,* +V 3700,12200,CONT_DIF_P,* +V 3700,11800,CONT_DIF_P,* +V 4900,7000,CONT_DIF_P,* +V 4900,11400,CONT_DIF_P,* +V 4900,10600,CONT_DIF_P,* +V 4900,10200,CONT_DIF_P,* +V 4900,9400,CONT_DIF_P,* +V 3700,7000,CONT_DIF_P,* +V 3700,11400,CONT_DIF_P,* +V 3700,10600,CONT_DIF_P,* +V 3700,10200,CONT_DIF_P,* +V 3700,9400,CONT_DIF_P,* +V 3700,9000,CONT_DIF_P,* +V 3700,8200,CONT_DIF_P,* +V 9000,12800,CONT_BODY_N,* +V 9000,6000,CONT_BODY_N,* +V 9600,12800,CONT_BODY_N,* +V 7300,6000,CONT_BODY_N,* +V 1800,9700,CONT_BODY_N,* +V 1800,9200,CONT_BODY_N,* +V 1800,8700,CONT_BODY_N,* +V 1800,8200,CONT_BODY_N,* +V 1800,12200,CONT_BODY_N,* +V 4900,6000,CONT_BODY_N,* +V 3700,6000,CONT_BODY_N,* +V 1800,7700,CONT_BODY_N,* +V 1800,7200,CONT_BODY_N,* +V 1800,11700,CONT_BODY_N,* +V 1800,11200,CONT_BODY_N,* +V 1800,10700,CONT_BODY_N,* +V 1800,10200,CONT_BODY_N,* +V 3700,12800,CONT_BODY_N,* +V 4900,12800,CONT_BODY_N,* +V 6100,12800,CONT_BODY_N,* +V 7300,12800,CONT_BODY_N,* +V 2300,6000,CONT_BODY_N,* +V 1800,6200,CONT_BODY_N,* +V 1800,6700,CONT_BODY_N,* +V 6100,6000,CONT_BODY_N,* +V 6700,12800,CONT_BODY_N,* +V 5500,12800,CONT_BODY_N,* +V 4300,12800,CONT_BODY_N,* +V 3100,12800,CONT_BODY_N,* +V 2500,12800,CONT_BODY_N,* +V 1800,12800,CONT_BODY_N,* +V 9000,1100,CONT_BODY_P,* +V 9000,4900,CONT_BODY_P,* +V 6100,4900,CONT_BODY_P,* +V 4900,4900,CONT_BODY_P,* +V 3700,4900,CONT_BODY_P,* +V 7300,1100,CONT_BODY_P,* +V 6100,1100,CONT_BODY_P,* +V 4900,1100,CONT_BODY_P,* +V 3700,1100,CONT_BODY_P,* +V 2400,4900,CONT_BODY_P,* +V 1900,4100,CONT_BODY_P,* +V 1900,3700,CONT_BODY_P,* +V 1900,4500,CONT_BODY_P,* +V 1900,1300,CONT_BODY_P,* +V 1900,1700,CONT_BODY_P,* +V 1900,2900,CONT_BODY_P,* +V 2400,1100,CONT_BODY_P,* +V 7300,4900,CONT_BODY_P,* +V 1900,4900,CONT_BODY_P,* +V 1900,2100,CONT_BODY_P,* +V 1900,2500,CONT_BODY_P,* +V 1900,3300,CONT_BODY_P,* +V 8300,6400,CONT_POLY,* +V 7900,4500,CONT_POLY,* +V 8300,4500,CONT_POLY,* +V 7900,6400,CONT_POLY,* +V 9000,11000,CONT_VIA,* +V 9000,8600,CONT_VIA,* +V 9000,7400,CONT_VIA,* +V 9000,4000,CONT_VIA,* +V 9000,3000,CONT_VIA,* +V 9000,10200,CONT_VIA,* +V 9000,9400,CONT_VIA,* +V 7300,11000,CONT_VIA,* +V 7300,7400,CONT_VIA,* +V 7300,8600,CONT_VIA,* +V 7300,9800,CONT_VIA,* +V 6100,7400,CONT_VIA,* +V 6100,9800,CONT_VIA,* +V 6100,8600,CONT_VIA,* +V 6100,11000,CONT_VIA,* +V 4900,11000,CONT_VIA,* +V 4900,7400,CONT_VIA,* +V 4900,9800,CONT_VIA,* +V 4900,8600,CONT_VIA,* +V 3700,9800,CONT_VIA,* +V 3700,8600,CONT_VIA,* +V 3700,11000,CONT_VIA,* +V 3700,7400,CONT_VIA,* +V 3700,4000,CONT_VIA,* +V 3700,3000,CONT_VIA,* +V 4900,3000,CONT_VIA,* +V 4900,4000,CONT_VIA,* +V 6100,4000,CONT_VIA,* +V 6100,3000,CONT_VIA,* +V 7300,4000,CONT_VIA,* +V 7300,3000,CONT_VIA,* +V 6700,1100,CONT_VIA,* +V 5500,1100,CONT_VIA,* +V 4300,1100,CONT_VIA,* +V 3100,1100,CONT_VIA,* +V 3100,1800,CONT_VIA,* +V 4300,1800,CONT_VIA,* +V 5500,1800,CONT_VIA,* +V 6700,1800,CONT_VIA,* +V 9400,28500,CONT_DIF_N,* +V 9400,26900,CONT_DIF_N,* +V 9400,26500,CONT_DIF_N,* +V 9400,28100,CONT_DIF_N,* +V 9400,27700,CONT_DIF_N,* +V 9400,26100,CONT_DIF_N,* +V 9400,27300,CONT_VIA,* +V 9400,25700,CONT_VIA,* +V 9400,28900,CONT_VIA,* +V 8200,25700,CONT_VIA,* +V 8200,26100,CONT_DIF_N,* +V 8200,27700,CONT_DIF_N,* +V 8200,28100,CONT_DIF_N,* +V 8200,27300,CONT_DIF_N,* +V 8200,28900,CONT_DIF_N,* +V 8200,26500,CONT_DIF_N,* +V 8200,28500,CONT_VIA,* +V 8200,26900,CONT_VIA,* +V 9400,29500,CONT_BODY_P,* +V 8200,29500,CONT_BODY_P,* +V 7800,14400,CONT_BODY_N,* +V 7600,25800,CONT_DIF_N,* +V 7600,28200,CONT_DIF_N,* +V 7600,28600,CONT_DIF_N,* +V 7600,26200,CONT_DIF_N,* +V 7600,26600,CONT_DIF_N,* +V 7600,27000,CONT_DIF_N,* +V 7600,27400,CONT_DIF_N,* +V 7600,27800,CONT_DIF_N,* +V 8800,26600,CONT_DIF_N,* +V 8800,27000,CONT_DIF_N,* +V 8800,26200,CONT_DIF_N,* +V 8800,25800,CONT_DIF_N,* +V 8800,28600,CONT_DIF_N,* +V 8800,27400,CONT_DIF_N,* +V 8800,27800,CONT_DIF_N,* +V 8800,28200,CONT_DIF_N,* +V 8200,15100,CONT_DIF_P,* +V 7600,15500,CONT_DIF_P,* +V 8200,15500,CONT_DIF_P,* +V 7600,15900,CONT_DIF_P,* +V 7600,15100,CONT_DIF_P,* +V 8800,15100,CONT_DIF_P,* +V 9400,15100,CONT_DIF_P,* +V 8800,15500,CONT_DIF_P,* +V 9400,15500,CONT_DIF_P,* +V 8800,15900,CONT_DIF_P,* +V 8200,16300,CONT_DIF_P,* +V 7600,16300,CONT_DIF_P,* +V 7600,20300,CONT_DIF_P,* +V 7600,18700,CONT_DIF_P,* +V 8200,18700,CONT_DIF_P,* +V 7600,19100,CONT_DIF_P,* +V 8200,19100,CONT_DIF_P,* +V 7600,19500,CONT_DIF_P,* +V 7600,19900,CONT_DIF_P,* +V 8200,19900,CONT_DIF_P,* +V 8200,20300,CONT_DIF_P,* +V 7600,17100,CONT_DIF_P,* +V 7600,16700,CONT_DIF_P,* +V 8200,16700,CONT_DIF_P,* +V 7600,18300,CONT_DIF_P,* +V 7600,17900,CONT_DIF_P,* +V 7600,17500,CONT_DIF_P,* +V 8200,17500,CONT_DIF_P,* +V 8200,17900,CONT_DIF_P,* +V 8800,16300,CONT_DIF_P,* +V 9400,16300,CONT_DIF_P,* +V 9400,20300,CONT_DIF_P,* +V 8800,19100,CONT_DIF_P,* +V 8800,19500,CONT_DIF_P,* +V 8800,19900,CONT_DIF_P,* +V 9400,19900,CONT_DIF_P,* +V 8800,20300,CONT_DIF_P,* +V 8800,18300,CONT_DIF_P,* +V 8800,17900,CONT_DIF_P,* +V 8800,18700,CONT_DIF_P,* +V 9400,18700,CONT_DIF_P,* +V 9400,19100,CONT_DIF_P,* +V 8800,17100,CONT_DIF_P,* +V 8800,16700,CONT_DIF_P,* +V 9400,16700,CONT_DIF_P,* +V 9400,17900,CONT_DIF_P,* +V 9400,17500,CONT_DIF_P,* +V 8800,17500,CONT_DIF_P,* +V 8200,15900,CONT_VIA,* +V 8200,18300,CONT_VIA,* +V 8200,19500,CONT_VIA,* +V 8200,17100,CONT_VIA,* +V 7600,20700,CONT_DIF_P,* +V 8800,20700,CONT_DIF_P,* +V 8200,20700,CONT_VIA,* +V 7600,21100,CONT_DIF_P,* +V 8800,21100,CONT_DIF_P,* +V 8200,21100,CONT_DIF_P,* +V 9400,21100,CONT_DIF_P,* +V 8200,21500,CONT_DIF_P,* +V 9400,21500,CONT_DIF_P,* +V 8800,21500,CONT_DIF_P,* +V 7600,21500,CONT_DIF_P,* +V 7600,21900,CONT_DIF_P,* +V 8800,21900,CONT_DIF_P,* +V 8200,21900,CONT_VIA,* +V 7600,22300,CONT_DIF_P,* +V 8200,22300,CONT_DIF_P,* +V 8800,22300,CONT_DIF_P,* +V 9400,22300,CONT_DIF_P,* +V 8200,25100,CONT_BODY_P,* +V 9400,25100,CONT_BODY_P,* +V 9300,24600,CONT_POLY,* +V 8200,24600,CONT_VIA,* +V 9400,23300,CONT_BODY_N,* +V 8200,23300,CONT_BODY_N,* +V 9400,22700,CONT_DIF_P,* +V 8800,22700,CONT_DIF_P,* +V 8200,22700,CONT_DIF_P,* +V 7600,22700,CONT_DIF_P,* +V 8200,14400,CONT_VIA,* +V 7300,14400,CONT_BODY_N,* +V 7000,26500,CONT_DIF_N,* +V 7000,27700,CONT_DIF_N,* +V 7000,28500,CONT_DIF_N,* +V 7000,28100,CONT_DIF_N,* +V 7000,26900,CONT_DIF_N,* +V 7000,25700,CONT_DIF_N,* +V 7000,27300,CONT_DIF_N,* +V 7000,28900,CONT_DIF_N,* +V 7000,26100,CONT_DIF_N,* +V 7000,17100,CONT_DIF_P,* +V 7000,20700,CONT_DIF_P,* +V 7000,19500,CONT_DIF_P,* +V 7000,19900,CONT_DIF_P,* +V 7000,18700,CONT_DIF_P,* +V 7000,18300,CONT_DIF_P,* +V 7000,16700,CONT_DIF_P,* +V 7000,17500,CONT_DIF_P,* +V 7000,17900,CONT_DIF_P,* +V 7000,20300,CONT_DIF_P,* +V 7000,19100,CONT_DIF_P,* +V 7000,15100,CONT_DIF_P,* +V 7000,15500,CONT_DIF_P,* +V 7000,15900,CONT_DIF_P,* +V 7000,16300,CONT_DIF_P,* +V 7000,21900,CONT_DIF_P,* +V 7000,22300,CONT_DIF_P,* +V 7000,21100,CONT_DIF_P,* +V 7000,22700,CONT_DIF_P,* +V 7000,21500,CONT_DIF_P,* +V 6400,18000,CONT_BODY_N,* +V 6400,18800,CONT_BODY_N,* +V 6400,18400,CONT_BODY_N,* +V 6400,17200,CONT_BODY_N,* +V 6400,16400,CONT_BODY_N,* +V 6400,15600,CONT_BODY_N,* +V 6400,15200,CONT_BODY_N,* +V 6400,14800,CONT_BODY_N,* +V 6400,19600,CONT_BODY_N,* +V 6400,20800,CONT_BODY_N,* +V 6400,19200,CONT_BODY_N,* +V 6400,16800,CONT_BODY_N,* +V 6400,16000,CONT_BODY_N,* +V 6900,14400,CONT_BODY_N,* +V 6400,14400,CONT_BODY_N,* +V 6400,17600,CONT_BODY_N,* +V 6400,20400,CONT_BODY_N,* +V 6400,20000,CONT_BODY_N,* +V 6400,22400,CONT_BODY_N,* +V 6400,22800,CONT_BODY_N,* +V 6400,22000,CONT_BODY_N,* +V 6400,23300,CONT_BODY_N,* +V 6400,21200,CONT_BODY_N,* +V 7000,23300,CONT_BODY_N,* +V 6400,21600,CONT_BODY_N,* +V 6400,26700,CONT_BODY_P,* +V 6400,27900,CONT_BODY_P,* +V 7000,29500,CONT_BODY_P,* +V 7000,25100,CONT_BODY_P,* +V 10000,29100,CONT_BODY_P,* +V 6400,28300,CONT_BODY_P,* +V 6400,25500,CONT_BODY_P,* +V 6400,27100,CONT_BODY_P,* +V 6400,25100,CONT_BODY_P,* +V 6400,28700,CONT_BODY_P,* +V 6400,26300,CONT_BODY_P,* +V 10000,27900,CONT_BODY_P,* +V 10000,27500,CONT_BODY_P,* +V 6400,29100,CONT_BODY_P,* +V 6400,25900,CONT_BODY_P,* +V 6400,27500,CONT_BODY_P,* +V 10000,28700,CONT_BODY_P,* +V 6400,29500,CONT_BODY_P,* +V 10000,29500,CONT_VIA,* +V 10000,28300,CONT_VIA,* +V 9700,24600,CONT_VIA,* +V 10000,25100,CONT_VIA,* +V 10000,27100,CONT_VIA,* +V 10000,26700,CONT_BODY_P,* +V 10000,26300,CONT_BODY_P,* +V 10000,25900,CONT_VIA,* +V 10000,25500,CONT_BODY_P,* +V 9400,14400,CONT_BODY_N,* +V 10000,22800,CONT_BODY_N,* +V 10000,22000,CONT_BODY_N,* +V 10000,23300,CONT_BODY_N,* +V 10000,21200,CONT_BODY_N,* +V 10000,21600,CONT_BODY_N,* +V 10000,22400,CONT_BODY_N,* +V 10000,15600,CONT_BODY_N,* +V 10000,16800,CONT_BODY_N,* +V 10000,17200,CONT_BODY_N,* +V 10000,18400,CONT_BODY_N,* +V 10000,18800,CONT_BODY_N,* +V 10000,19200,CONT_BODY_N,* +V 10000,16400,CONT_BODY_N,* +V 10000,20800,CONT_BODY_N,* +V 10000,20400,CONT_BODY_N,* +V 10000,20000,CONT_BODY_N,* +V 10000,19600,CONT_BODY_N,* +V 10000,16000,CONT_BODY_N,* +V 10000,14400,CONT_BODY_N,* +V 10000,18000,CONT_BODY_N,* +V 10000,14800,CONT_BODY_N,* +V 10000,15200,CONT_BODY_N,* +V 10000,17600,CONT_BODY_N,* +V 9400,21900,CONT_DIF_P,* +V 9400,20700,CONT_DIF_P,* +V 9400,19500,CONT_DIF_P,* +V 9400,18300,CONT_DIF_P,* +V 9400,17100,CONT_DIF_P,* +V 9400,15900,CONT_DIF_P,* +V 7700,13800,CONT_VIA,* +V 8200,13800,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/padlib/pali_sp.ap b/alliance/src/cells/src/padlib/pali_sp.ap new file mode 100644 index 00000000..8acf28a9 --- /dev/null +++ b/alliance/src/cells/src/padlib/pali_sp.ap @@ -0,0 +1,533 @@ +V ALLIANCE : 6 +H pali_sp,P, 9/10/2000,100 +A 0,-700,17200,35600 +C 0,29600,12000,vsse,0,WEST,ALU2 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 0,8400,4000,vddi,0,WEST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 17200,8400,4000,vddi,1,EAST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,16800,12000,vdde,1,EAST,ALU2 +C 17200,600,1200,ck,1,EAST,ALU2 +C 0,600,1200,ck,0,WEST,ALU2 +C 8200,-700,200,t,1,SOUTH,ALU2 +C 8200,-700,200,t,0,SOUTH,ALU1 +S 8400,12550,12400,12550,300,*,RIGHT,ALU1 +S 12300,4600,12300,12600,300,*,UP,ALU1 +S 7300,200,7300,4200,900,*,UP,ALU1 +S 8800,200,8800,4200,200,*,UP,ALU1 +S 10500,200,10500,4200,200,*,UP,ALU1 +S 12000,200,12000,4200,800,*,UP,ALU1 +S 11700,5300,11700,12000,200,*,UP,ALU1 +S 10500,5200,10500,12000,200,*,UP,ALU1 +S 8800,5200,8800,12000,200,*,UP,ALU1 +S 6800,12000,11800,12000,200,*,RIGHT,ALU1 +S 9900,13600,9900,22600,700,*,UP,ALU1 +S 9100,13600,9100,22600,200,*,UP,ALU1 +S 9000,13600,10100,13600,200,*,RIGHT,ALU1 +S 7900,13800,7900,22600,200,*,UP,ALU1 +S 8500,23800,9200,23800,300,*,RIGHT,POLY +S 9100,23800,9500,23800,200,*,RIGHT,ALU1 +S 9700,24300,9700,28800,200,*,UP,ALU1 +S 9100,24300,9100,28800,200,*,UP,ALU1 +S 6400,24200,6400,28800,800,*,UP,ALU1 +S 7900,23700,7900,28800,200,*,UP,ALU1 +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 8600,30100,8600,35600,1000,*,UP,ALU1 +S 8200,-700,8200,-400,300,*,UP,ALU2 +S 8500,12600,8500,13000,300,*,UP,ALU1 +S 7200,29600,9100,29600,900,*,RIGHT,ALU1 +S 100,600,17200,600,1200,ck,RIGHT,ALU2 +S 6400,13500,6400,22600,800,*,UP,ALU1 +S 6000,24300,6800,24300,300,*,RIGHT,PTIE +S 6100,24200,6100,28800,300,*,UP,PTIE +S 6000,28700,6800,28700,300,*,RIGHT,PTIE +S 9100,28700,9800,28700,300,*,RIGHT,PTIE +S 6100,22500,6700,22500,300,*,RIGHT,NTIE +S 6100,13600,6700,13600,300,*,RIGHT,NTIE +S 6100,13600,6100,22600,300,*,UP,NTIE +S 6700,14100,6700,22000,300,*,UP,PDIF +S 6700,24800,6700,28200,300,*,UP,NDIF +S 9600,13400,9600,22700,600,*,UP,NWELL +S 6400,13400,6400,22700,1000,*,UP,NWELL +S 11100,3600,11100,5700,300,*,UP,ALU1 +S 11000,4700,12400,4700,300,*,RIGHT,ALU1 +S 9300,5600,10000,5600,300,*,RIGHT,ALU1 +S 9300,3700,10000,3700,300,*,RIGHT,ALU1 +S 9900,4500,9900,8400,300,*,UP,ALU1 +S 7200,5100,7200,12100,1000,*,UP,ALU1 +S 9800,-300,11200,-300,300,*,RIGHT,ALU1 +S 8200,-700,8200,11500,300,*,UP,ALU1 +S 9900,-400,9900,4700,300,*,UP,ALU1 +S 11100,-400,11100,3200,300,*,UP,ALU1 +S 7900,600,8500,600,100,*,RIGHT,POLY +S 10200,5600,11200,5600,300,*,RIGHT,POLY +S 10200,5500,10200,5700,100,*,UP,POLY +S 10200,3700,11400,3700,300,*,RIGHT,POLY +S 7900,5600,9900,5600,300,*,RIGHT,POLY +S 7900,11700,8500,11700,100,*,RIGHT,POLY +S 7000,4100,12400,4100,300,*,RIGHT,PTIE +S 7000,400,7000,4200,300,*,UP,PTIE +S 6900,300,12400,300,300,*,RIGHT,PTIE +S 12300,200,12300,4200,300,*,UP,PTIE +S 11700,5100,11700,12100,300,*,UP,NTIE +S 6800,5200,11800,5200,300,*,RIGHT,NTIE +S 6900,5100,6900,12000,300,*,UP,NTIE +S 6800,12000,11800,12000,300,*,RIGHT,NTIE +S 8800,5900,8800,11500,400,*,UP,PDIF +S 8500,5700,8500,11700,100,*,UP,PTRANS +S 7900,5700,7900,11700,100,*,UP,PTRANS +S 10200,5700,10200,8700,100,*,UP,PTRANS +S 9900,5900,9900,8500,400,*,UP,PDIF +S 8200,5900,8200,11500,200,*,UP,PDIF +S 10500,5900,10500,8500,300,*,UP,PDIF +S 7600,5900,7600,11500,400,*,UP,PDIF +S 7900,600,7900,3600,100,*,UP,NTRANS +S 8500,600,8500,3600,100,*,UP,NTRANS +S 8800,800,8800,3400,400,*,UP,NDIF +S 7600,800,7600,3400,300,*,UP,NDIF +S 8200,800,8200,3400,200,*,UP,NDIF +S 11100,800,11100,3400,200,*,UP,NDIF +S 10500,800,10500,3400,200,*,UP,NDIF +S 11700,800,11700,3400,300,*,UP,NDIF +S 11700,800,11700,3400,200,*,UP,NDIF +S 10200,600,10200,3600,100,*,UP,NTRANS +S 9900,800,9900,3400,300,*,UP,NDIF +S 10800,600,10800,3600,100,*,UP,NTRANS +S 11400,600,11400,3600,100,*,UP,NTRANS +S 6700,8600,11900,8600,7200,*,RIGHT,NWELL +S 7900,3700,9900,3700,300,*,RIGHT,POLY +S 9700,24200,9700,28500,300,*,UP,PTIE +S 9100,24300,9700,24300,300,*,LEFT,PTIE +S 10000,13600,10000,22600,300,*,UP,NTIE +S 9900,13400,9900,22700,600,*,UP,NWELL +S 9500,13400,9500,22700,400,*,UP,NWELL +S 9300,13600,10000,13600,300,*,RIGHT,NTIE +S 9100,13100,9500,13100,200,*,RIGHT,ALU1 +S 9100,22500,10000,22500,300,*,RIGHT,NTIE +S 8500,13000,8500,14300,300,*,DOWN,ALU1 +S 6800,13600,8000,13600,300,*,RIGHT,ALU1 +S 8500,13100,8500,13900,200,*,UP,POLY +S 6800,22500,9200,22500,300,*,RIGHT,NTIE +S 8500,23800,8500,24600,200,*,UP,POLY +S 7000,24600,8800,24600,100,*,RIGHT,POLY +S 8800,24300,9200,24300,300,*,RIGHT,PTIE +S 6800,24300,8200,24300,300,*,RIGHT,PTIE +S 8500,23700,8500,23900,200,*,DOWN,POLY +S 7000,13900,8800,13900,100,*,RIGHT,POLY +S 8800,13600,9200,13600,300,*,RIGHT,NTIE +S 6800,13600,8200,13600,300,*,RIGHT,NTIE +S 8100,13400,8100,22700,2800,*,UP,NWELL +S 8800,13900,8800,22200,100,*,UP,PTRANS +S 8200,13900,8200,22200,100,*,UP,PTRANS +S 7600,13900,7600,22200,100,*,UP,PTRANS +S 7000,13900,7000,22200,100,*,UP,PTRANS +S 7300,14100,7300,22000,200,*,UP,PDIF +S 7900,14100,7900,22000,200,*,UP,PDIF +S 8500,14100,8500,22000,200,*,UP,PDIF +S 9100,14100,9100,22000,300,*,UP,PDIF +S 6800,28700,9200,28700,300,*,RIGHT,PTIE +S 8800,24600,8800,28400,100,*,UP,NTRANS +S 8200,24600,8200,28400,100,*,UP,NTRANS +S 7600,24600,7600,28400,100,*,UP,NTRANS +S 7000,24600,7000,28400,100,*,UP,NTRANS +S 7300,24800,7300,28200,300,*,UP,NDIF +S 7900,24800,7900,28200,300,*,UP,NDIF +S 8500,24800,8500,28200,300,*,UP,NDIF +S 9100,24800,9100,28200,300,*,UP,NDIF +S 8500,14200,8500,29100,300,*,UP,ALU1 +S 7300,14200,7300,29100,300,*,UP,ALU1 +S 8500,13100,9100,13100,200,*,RIGHT,POLY +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +V 10500,9500,CONT_VIA,* +B 7200,8400,1000,4000,CONT_VIA,* +B 12000,3100,700,2100,CONT_VIA,* +B 7300,3100,800,2100,CONT_VIA,* +B 9900,18050,600,9000,CONT_VIA,* +V 9100,13600,CONT_BODY_N,* +B 6400,26500,800,4600,CONT_VIA,* +B 6400,18000,800,9100,CONT_VIA,* +V 9100,23800,CONT_POLY,* +V 9500,23800,CONT_VIA,* +B 9400,26500,800,4600,CONT_VIA,* +V 8200,-500,CONT_VIA,* +V 6100,28700,CONT_BODY_P,* +V 9700,27900,CONT_BODY_P,* +V 6100,26700,CONT_BODY_P,* +V 6100,25100,CONT_BODY_P,* +V 6100,28300,CONT_BODY_P,* +V 9700,26700,CONT_BODY_P,* +V 9700,27100,CONT_BODY_P,* +V 6100,25500,CONT_BODY_P,* +V 6100,27900,CONT_BODY_P,* +V 6100,24300,CONT_BODY_P,* +V 6100,26300,CONT_BODY_P,* +V 6100,24700,CONT_BODY_P,* +V 6100,27500,CONT_BODY_P,* +V 9700,28300,CONT_BODY_P,* +V 6700,24300,CONT_BODY_P,* +V 6700,28700,CONT_BODY_P,* +V 6100,27100,CONT_BODY_P,* +V 6100,25900,CONT_BODY_P,* +V 6100,20800,CONT_BODY_N,* +V 6700,22500,CONT_BODY_N,* +V 6100,20400,CONT_BODY_N,* +V 6100,22500,CONT_BODY_N,* +V 6100,21200,CONT_BODY_N,* +V 6100,22000,CONT_BODY_N,* +V 6100,21600,CONT_BODY_N,* +V 6100,19200,CONT_BODY_N,* +V 6100,19600,CONT_BODY_N,* +V 6100,16800,CONT_BODY_N,* +V 6100,13600,CONT_BODY_N,* +V 6600,13600,CONT_BODY_N,* +V 6100,15200,CONT_BODY_N,* +V 6100,16000,CONT_BODY_N,* +V 6100,18400,CONT_BODY_N,* +V 6100,20000,CONT_BODY_N,* +V 6100,18800,CONT_BODY_N,* +V 6100,14000,CONT_BODY_N,* +V 6100,14400,CONT_BODY_N,* +V 6100,14800,CONT_BODY_N,* +V 6100,15600,CONT_BODY_N,* +V 6100,16400,CONT_BODY_N,* +V 6100,17600,CONT_BODY_N,* +V 6100,18000,CONT_BODY_N,* +V 6100,17200,CONT_BODY_N,* +V 6700,20700,CONT_DIF_P,* +V 6700,21900,CONT_DIF_P,* +V 6700,20300,CONT_DIF_P,* +V 6700,21500,CONT_DIF_P,* +V 6700,21100,CONT_DIF_P,* +V 6700,15500,CONT_DIF_P,* +V 6700,15100,CONT_DIF_P,* +V 6700,14700,CONT_DIF_P,* +V 6700,14300,CONT_DIF_P,* +V 6700,18300,CONT_DIF_P,* +V 6700,19500,CONT_DIF_P,* +V 6700,17100,CONT_DIF_P,* +V 6700,16700,CONT_DIF_P,* +V 6700,15900,CONT_DIF_P,* +V 6700,17500,CONT_DIF_P,* +V 6700,17900,CONT_DIF_P,* +V 6700,19100,CONT_DIF_P,* +V 6700,18700,CONT_DIF_P,* +V 6700,19900,CONT_DIF_P,* +V 6700,16300,CONT_DIF_P,* +V 6700,25300,CONT_DIF_N,* +V 6700,28100,CONT_DIF_N,* +V 6700,26500,CONT_DIF_N,* +V 6700,24900,CONT_DIF_N,* +V 6700,26100,CONT_DIF_N,* +V 6700,27300,CONT_DIF_N,* +V 6700,27700,CONT_DIF_N,* +V 6700,26900,CONT_DIF_N,* +V 6700,25700,CONT_DIF_N,* +V 10500,10200,CONT_VIA,* +V 8800,2200,CONT_VIA,* +V 8800,3200,CONT_VIA,* +V 10500,7800,CONT_VIA,* +V 11700,10200,CONT_VIA,* +V 11700,8600,CONT_VIA,* +V 11700,7100,CONT_VIA,* +V 10500,2200,CONT_VIA,* +V 10500,3200,CONT_VIA,* +V 10500,6600,CONT_VIA,* +V 8800,9000,CONT_VIA,* +V 8800,7800,CONT_VIA,* +V 8800,6600,CONT_VIA,* +V 8800,10200,CONT_VIA,* +V 10500,8700,CONT_VIA,* +V 11100,5600,CONT_POLY,* +V 9800,5600,CONT_POLY,* +V 9400,5600,CONT_POLY,* +V 9800,3700,CONT_POLY,* +V 11100,3700,CONT_POLY,* +V 9400,3700,CONT_POLY,* +V 7000,3700,CONT_BODY_P,* +V 7000,500,CONT_BODY_P,* +V 7000,900,CONT_BODY_P,* +V 7000,1700,CONT_BODY_P,* +V 12300,2900,CONT_BODY_P,* +V 7000,2100,CONT_BODY_P,* +V 8800,4100,CONT_BODY_P,* +V 12300,2500,CONT_BODY_P,* +V 7000,4100,CONT_BODY_P,* +V 7000,1300,CONT_BODY_P,* +V 7500,4100,CONT_BODY_P,* +V 12300,500,CONT_BODY_P,* +V 11700,4100,CONT_BODY_P,* +V 12300,3700,CONT_BODY_P,* +V 7000,3300,CONT_BODY_P,* +V 12300,3300,CONT_BODY_P,* +V 7000,2500,CONT_BODY_P,* +V 7000,2900,CONT_BODY_P,* +V 10500,4100,CONT_BODY_P,* +V 12300,900,CONT_BODY_P,* +V 12300,2100,CONT_BODY_P,* +V 12300,4100,CONT_BODY_P,* +V 12300,1300,CONT_BODY_P,* +V 12300,1700,CONT_BODY_P,* +V 11700,300,CONT_BODY_P,* +V 10500,300,CONT_BODY_P,* +V 8800,300,CONT_BODY_P,* +V 7500,300,CONT_BODY_P,* +V 11700,9200,CONT_BODY_N,* +V 11700,9700,CONT_BODY_N,* +V 6900,6900,CONT_BODY_N,* +V 6900,7900,CONT_BODY_N,* +V 6900,6400,CONT_BODY_N,* +V 6900,10900,CONT_BODY_N,* +V 6900,7400,CONT_BODY_N,* +V 11700,6100,CONT_BODY_N,* +V 11700,5300,CONT_BODY_N,* +V 8200,12000,CONT_BODY_N,* +V 6900,11400,CONT_BODY_N,* +V 6900,5900,CONT_BODY_N,* +V 6900,5400,CONT_BODY_N,* +V 6900,12000,CONT_BODY_N,* +V 6900,10400,CONT_BODY_N,* +V 8800,12000,CONT_BODY_N,* +V 6900,9900,CONT_BODY_N,* +V 6900,9400,CONT_BODY_N,* +V 6900,8900,CONT_BODY_N,* +V 6900,8400,CONT_BODY_N,* +V 7400,5200,CONT_BODY_N,* +V 7600,12000,CONT_BODY_N,* +V 11700,6600,CONT_BODY_N,* +V 11700,7600,CONT_BODY_N,* +V 11700,8100,CONT_BODY_N,* +V 11700,10900,CONT_BODY_N,* +V 11700,11400,CONT_BODY_N,* +V 8800,5200,CONT_BODY_N,* +V 11100,12000,CONT_BODY_N,* +V 11700,12000,CONT_BODY_N,* +V 10500,5200,CONT_BODY_N,* +V 10500,12000,CONT_BODY_N,* +V 8200,7400,CONT_DIF_P,* +V 8200,6600,CONT_DIF_P,* +V 8200,6200,CONT_DIF_P,* +V 7600,6900,CONT_DIF_P,* +V 8200,8200,CONT_DIF_P,* +V 7600,11400,CONT_DIF_P,* +V 7600,6400,CONT_DIF_P,* +V 7600,10900,CONT_DIF_P,* +V 8200,7800,CONT_DIF_P,* +V 8200,7000,CONT_DIF_P,* +V 8200,11400,CONT_DIF_P,* +V 8800,11400,CONT_DIF_P,* +V 9900,6700,CONT_DIF_P,* +V 8200,11000,CONT_DIF_P,* +V 8200,10600,CONT_DIF_P,* +V 8200,10200,CONT_DIF_P,* +V 9900,7300,CONT_DIF_P,* +V 9900,7800,CONT_DIF_P,* +V 9900,6200,CONT_DIF_P,* +V 9900,8300,CONT_DIF_P,* +V 10500,6200,CONT_DIF_P,* +V 10500,7000,CONT_DIF_P,* +V 10500,6200,CONT_DIF_P,* +V 10500,7400,CONT_DIF_P,* +V 10500,8200,CONT_DIF_P,* +V 8200,9800,CONT_DIF_P,* +V 7600,9900,CONT_DIF_P,* +V 7600,9400,CONT_DIF_P,* +V 7600,8900,CONT_DIF_P,* +V 8200,8600,CONT_DIF_P,* +V 8200,9000,CONT_DIF_P,* +V 8200,9400,CONT_DIF_P,* +V 8800,6200,CONT_DIF_P,* +V 7600,7900,CONT_DIF_P,* +V 7600,7400,CONT_DIF_P,* +V 7600,8400,CONT_DIF_P,* +V 7600,10400,CONT_DIF_P,* +V 8800,11000,CONT_DIF_P,* +V 8800,10600,CONT_DIF_P,* +V 8800,9800,CONT_DIF_P,* +V 8800,9400,CONT_DIF_P,* +V 8800,8600,CONT_DIF_P,* +V 8800,8200,CONT_DIF_P,* +V 8800,7400,CONT_DIF_P,* +V 8800,7000,CONT_DIF_P,* +V 8200,3100,CONT_DIF_N,* +V 7600,2600,CONT_DIF_N,* +V 11100,2600,CONT_DIF_N,* +V 8200,2100,CONT_DIF_N,* +V 9900,2100,CONT_DIF_N,* +V 7600,1600,CONT_DIF_N,* +V 7600,2100,CONT_DIF_N,* +V 11700,2600,CONT_DIF_N,* +V 11700,3100,CONT_DIF_N,* +V 7600,1100,CONT_DIF_N,* +V 9900,1100,CONT_DIF_N,* +V 11700,2100,CONT_DIF_N,* +V 11700,1600,CONT_DIF_N,* +V 7600,3100,CONT_DIF_N,* +V 11100,2100,CONT_DIF_N,* +V 11700,1100,CONT_DIF_N,* +V 10500,1700,CONT_DIF_N,* +V 11100,1100,CONT_DIF_N,* +V 8200,1600,CONT_DIF_N,* +V 8800,1200,CONT_DIF_N,* +V 8800,1700,CONT_DIF_N,* +V 8800,2700,CONT_DIF_N,* +V 10500,2700,CONT_DIF_N,* +V 10500,1200,CONT_DIF_N,* +V 9900,2600,CONT_DIF_N,* +V 9900,3100,CONT_DIF_N,* +V 11100,3100,CONT_DIF_N,* +V 8200,2600,CONT_DIF_N,* +V 9700,25900,CONT_BODY_P,* +V 9700,24700,CONT_BODY_P,* +V 9700,25500,CONT_BODY_P,* +V 9500,13100,CONT_VIA,* +V 10000,22500,CONT_BODY_N,* +V 10000,20800,CONT_BODY_N,* +V 10000,21600,CONT_BODY_N,* +V 10000,22000,CONT_BODY_N,* +V 10000,21200,CONT_BODY_N,* +V 10000,19200,CONT_BODY_N,* +V 10000,18800,CONT_BODY_N,* +V 10000,16800,CONT_BODY_N,* +V 10000,18400,CONT_BODY_N,* +V 10000,15600,CONT_BODY_N,* +V 10000,14800,CONT_BODY_N,* +V 10000,16000,CONT_BODY_N,* +V 10000,16400,CONT_BODY_N,* +V 10000,17600,CONT_BODY_N,* +V 10000,20000,CONT_BODY_N,* +V 10000,19600,CONT_BODY_N,* +V 10000,15200,CONT_BODY_N,* +V 9600,13600,CONT_BODY_N,* +V 10000,13600,CONT_BODY_N,* +V 10000,17200,CONT_BODY_N,* +V 10000,20400,CONT_BODY_N,* +V 10000,18000,CONT_BODY_N,* +V 10000,14000,CONT_BODY_N,* +V 10000,14400,CONT_BODY_N,* +V 7000,13600,CONT_BODY_N,* +V 7900,13600,CONT_VIA,* +V 7300,21900,CONT_DIF_P,* +V 7900,21900,CONT_DIF_P,* +V 8500,21900,CONT_DIF_P,* +V 9100,21900,CONT_DIF_P,* +V 7900,22500,CONT_BODY_N,* +V 9100,22500,CONT_BODY_N,* +V 7900,23800,CONT_VIA,* +V 9100,24300,CONT_BODY_P,* +V 7900,24300,CONT_BODY_P,* +V 9100,21500,CONT_DIF_P,* +V 8500,21500,CONT_DIF_P,* +V 7900,21500,CONT_DIF_P,* +V 7300,21500,CONT_DIF_P,* +V 7900,21100,CONT_VIA,* +V 9100,21100,CONT_VIA,* +V 8500,21100,CONT_DIF_P,* +V 7300,21100,CONT_DIF_P,* +V 7300,20700,CONT_DIF_P,* +V 8500,20700,CONT_DIF_P,* +V 9100,20700,CONT_DIF_P,* +V 7900,20700,CONT_DIF_P,* +V 9100,20300,CONT_DIF_P,* +V 7900,20300,CONT_DIF_P,* +V 8500,20300,CONT_DIF_P,* +V 7300,20300,CONT_DIF_P,* +V 9100,19900,CONT_VIA,* +V 7900,19900,CONT_VIA,* +V 8500,19900,CONT_DIF_P,* +V 7300,19900,CONT_DIF_P,* +V 9100,16300,CONT_VIA,* +V 9100,17500,CONT_VIA,* +V 9100,18700,CONT_VIA,* +V 7900,16300,CONT_VIA,* +V 7900,18700,CONT_VIA,* +V 7900,17500,CONT_VIA,* +V 9100,15100,CONT_VIA,* +V 7900,15100,CONT_VIA,* +V 8500,16700,CONT_DIF_P,* +V 9100,16700,CONT_DIF_P,* +V 9100,17100,CONT_DIF_P,* +V 9100,15900,CONT_DIF_P,* +V 8500,15900,CONT_DIF_P,* +V 8500,16300,CONT_DIF_P,* +V 9100,18300,CONT_DIF_P,* +V 9100,17900,CONT_DIF_P,* +V 8500,17900,CONT_DIF_P,* +V 8500,17100,CONT_DIF_P,* +V 8500,17500,CONT_DIF_P,* +V 8500,19500,CONT_DIF_P,* +V 9100,19100,CONT_DIF_P,* +V 8500,19100,CONT_DIF_P,* +V 8500,18700,CONT_DIF_P,* +V 8500,18300,CONT_DIF_P,* +V 9100,19500,CONT_DIF_P,* +V 9100,15500,CONT_DIF_P,* +V 8500,15500,CONT_DIF_P,* +V 7900,17100,CONT_DIF_P,* +V 7900,16700,CONT_DIF_P,* +V 7300,16700,CONT_DIF_P,* +V 7300,17100,CONT_DIF_P,* +V 7300,17500,CONT_DIF_P,* +V 7900,15900,CONT_DIF_P,* +V 7300,15900,CONT_DIF_P,* +V 7300,16300,CONT_DIF_P,* +V 7900,19500,CONT_DIF_P,* +V 7900,19100,CONT_DIF_P,* +V 7300,19100,CONT_DIF_P,* +V 7300,18700,CONT_DIF_P,* +V 7900,18300,CONT_DIF_P,* +V 7300,18300,CONT_DIF_P,* +V 7900,17900,CONT_DIF_P,* +V 7300,17900,CONT_DIF_P,* +V 7300,19500,CONT_DIF_P,* +V 7300,15500,CONT_DIF_P,* +V 7900,15500,CONT_DIF_P,* +V 8500,15100,CONT_DIF_P,* +V 9100,14700,CONT_DIF_P,* +V 8500,14700,CONT_DIF_P,* +V 9100,14300,CONT_DIF_P,* +V 8500,14300,CONT_DIF_P,* +V 7300,14300,CONT_DIF_P,* +V 7300,15100,CONT_DIF_P,* +V 7900,14700,CONT_DIF_P,* +V 7300,14700,CONT_DIF_P,* +V 7900,14300,CONT_DIF_P,* +V 8500,27400,CONT_DIF_N,* +V 8500,27000,CONT_DIF_N,* +V 8500,26600,CONT_DIF_N,* +V 8500,27800,CONT_DIF_N,* +V 8500,25000,CONT_DIF_N,* +V 8500,25400,CONT_DIF_N,* +V 8500,26200,CONT_DIF_N,* +V 8500,25800,CONT_DIF_N,* +V 7300,27000,CONT_DIF_N,* +V 7300,26600,CONT_DIF_N,* +V 7300,26200,CONT_DIF_N,* +V 7300,25800,CONT_DIF_N,* +V 7300,25400,CONT_DIF_N,* +V 7300,27800,CONT_DIF_N,* +V 7300,27400,CONT_DIF_N,* +V 7300,25000,CONT_DIF_N,* +V 7500,13600,CONT_BODY_N,* +V 7900,28700,CONT_BODY_P,* +V 9100,28700,CONT_BODY_P,* +V 7900,26100,CONT_VIA,* +V 7900,27700,CONT_VIA,* +V 7900,25700,CONT_DIF_N,* +V 7900,28100,CONT_DIF_N,* +V 7900,26500,CONT_DIF_N,* +V 7900,27300,CONT_DIF_N,* +V 7900,26900,CONT_DIF_N,* +V 7900,25300,CONT_DIF_N,* +V 7900,24900,CONT_VIA,* +V 9100,25300,CONT_DIF_N,* +V 9100,26900,CONT_DIF_N,* +V 9100,27300,CONT_DIF_N,* +V 9100,25700,CONT_DIF_N,* +V 9100,26100,CONT_DIF_N,* +V 9100,27700,CONT_DIF_N,* +V 9100,13100,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/padlib/paliot_sp.ap b/alliance/src/cells/src/padlib/paliot_sp.ap new file mode 100644 index 00000000..b827f3a3 --- /dev/null +++ b/alliance/src/cells/src/padlib/paliot_sp.ap @@ -0,0 +1,2062 @@ +V ALLIANCE : 6 +H paliot_sp,P, 9/10/2000,100 +A 0,-700,17200,35600 +C 0,29600,12000,vsse,0,WEST,ALU2 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 17200,16800,12000,vdde,1,EAST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,8400,4000,vddi,1,EAST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 0,8400,4000,vddi,0,WEST,ALU2 +C 17200,600,1200,ck,1,EAST,ALU2 +C 0,600,1200,ck,0,WEST,ALU2 +C 3800,-700,200,t,1,SOUTH,ALU2 +C 4900,-700,200,i,1,SOUTH,ALU2 +C 15700,-700,200,b,1,SOUTH,ALU2 +C 15700,-700,200,b,0,SOUTH,ALU1 +C 3800,-700,200,t,0,SOUTH,ALU1 +C 4900,-700,200,i,0,SOUTH,ALU1 +S 15800,24300,16400,24300,200,*,RIGHT,ALU1 +S 15800,24300,15800,28800,200,*,UP,ALU1 +S 16200,24300,16200,29300,600,*,UP,ALU1 +S 2600,23900,2600,28800,200,*,UP,ALU1 +S 3800,24300,3800,28800,200,*,UP,ALU1 +S 5000,23800,5000,28800,200,*,UP,ALU1 +S 6200,24300,6200,28800,200,*,UP,ALU1 +S 8600,24300,8600,28800,200,*,UP,ALU1 +S 11000,24300,11000,28800,200,*,UP,ALU1 +S 13400,24300,13400,28800,200,*,UP,ALU1 +S 16400,1600,16900,1600,200,*,LEFT,ALU1 +S 3700,23200,16900,23200,200,*,RIGHT,ALU2 +S 6800,1600,16900,1600,200,*,RIGHT,ALU2 +S 3700,13600,5300,13600,200,*,RIGHT,ALU1 +S 3800,13600,3800,22600,200,*,UP,ALU1 +S 16900,1600,16900,23300,200,*,UP,ALU1 +S 800,-200,3200,-200,200,*,RIGHT,ALU1 +S 5400,-200,15100,-200,200,*,RIGHT,ALU1 +S 15200,-200,15200,4000,200,*,UP,ALU1 +S 800,5000,800,12000,200,*,DOWN,ALU1 +S 800,12000,2200,12000,200,*,RIGHT,ALU1 +S 1800,9200,2000,9200,100,*,RIGHT,ALU1 +S 800,10300,2100,10300,1000,*,LEFT,ALU1 +S 1100,8800,1100,9900,500,*,DOWN,ALU1 +S 3200,12000,6200,12000,200,*,RIGHT,ALU1 +S 800,-100,800,4100,200,*,UP,ALU1 +S 2000,-200,2000,3900,200,*,UP,ALU1 +S 3200,-200,3200,3900,200,*,UP,ALU1 +S 11000,-200,11000,3200,200,*,UP,ALU1 +S 9800,-200,9800,4100,200,*,UP,ALU1 +S 8600,-200,8600,4100,200,*,UP,ALU1 +S 7400,-200,7400,3200,200,*,UP,ALU1 +S 6200,-200,6200,4100,200,*,UP,ALU1 +S 6200,5200,6200,12000,200,*,UP,ALU1 +S 3200,5000,3200,12000,200,*,UP,ALU1 +S 4400,5000,4400,12000,200,*,UP,ALU1 +S 4400,-300,4400,4000,200,*,UP,ALU1 +S 15100,4500,15800,4500,200,*,LEFT,ALU1 +S 7700,5100,11700,5100,200,*,RIGHT,ALU1 +S 6200,4000,10400,4000,200,*,RIGHT,ALU1 +S 11000,5100,11000,12100,200,*,UP,ALU1 +S 16200,13500,16200,22600,600,*,UP,ALU1 +S 15800,13600,15800,22600,200,*,UP,ALU1 +S 14600,13600,14600,22600,200,*,UP,ALU1 +S 13400,13600,13400,22600,200,*,UP,ALU1 +S 12200,13600,12200,22600,200,*,UP,ALU1 +S 11000,13600,11000,22600,200,*,UP,ALU1 +S 9800,13600,9800,22600,200,*,UP,ALU1 +S 8600,13600,8600,22600,200,*,UP,ALU1 +S 7400,13600,7400,22600,200,*,UP,ALU1 +S 6200,13600,6200,22600,200,*,UP,ALU1 +S 5000,13600,5000,22600,200,*,UP,ALU1 +S 2600,13700,2600,22600,200,*,UP,ALU1 +S 2600,12600,3300,12600,200,*,RIGHT,ALU1 +S 2700,9000,2700,12600,200,*,UP,ALU1 +S 3200,12600,3200,13000,200,*,UP,ALU1 +S 14000,3900,14000,13100,200,*,UP,ALU1 +S 12800,5800,12800,13000,200,*,UP,ALU1 +S 11600,5800,11600,13100,200,*,UP,ALU1 +S 10400,5800,10400,13100,200,*,UP,ALU1 +S 9200,5800,9200,13100,200,*,UP,ALU1 +S 8000,5800,8000,13100,200,*,UP,ALU1 +S 6800,5800,6800,13100,200,*,UP,ALU1 +S 3700,13100,15300,13100,200,*,RIGHT,ALU1 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2 +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +S 0,600,17200,600,1200,ck,RIGHT,ALU2 +S 3200,13100,3800,13100,200,*,RIGHT,POLY +S 2000,14200,2000,29100,200,*,UP,ALU1 +S 3200,14200,3200,29100,200,*,UP,ALU1 +S 3800,24800,3800,28200,300,*,UP,NDIF +S 3200,24800,3200,28200,300,*,UP,NDIF +S 2600,24800,2600,28200,300,*,UP,NDIF +S 2000,24800,2000,28200,300,*,UP,NDIF +S 1700,24600,1700,28400,100,*,UP,NTRANS +S 2300,24600,2300,28400,100,*,UP,NTRANS +S 2900,24600,2900,28400,100,*,UP,NTRANS +S 3500,24600,3500,28400,100,*,UP,NTRANS +S 1500,28700,3900,28700,300,*,RIGHT,PTIE +S 3800,14100,3800,22000,300,*,UP,PDIF +S 3200,14100,3200,22000,200,*,UP,PDIF +S 2600,14100,2600,22000,200,*,UP,PDIF +S 2000,14100,2000,22000,200,*,UP,PDIF +S 1700,13900,1700,22200,100,*,UP,PTRANS +S 2300,13900,2300,22200,100,*,UP,PTRANS +S 2900,13900,2900,22200,100,*,UP,PTRANS +S 3500,13900,3500,22200,100,*,UP,PTRANS +S 2800,13400,2800,22700,2800,*,UP,NWELL +S 1500,13600,2900,13600,300,*,RIGHT,NTIE +S 3500,13600,3900,13600,300,*,RIGHT,NTIE +S 1700,13900,3500,13900,100,*,RIGHT,POLY +S 3200,23700,3200,23900,200,*,DOWN,POLY +S 1500,24300,2900,24300,300,*,RIGHT,PTIE +S 3500,24300,3900,24300,300,*,RIGHT,PTIE +S 1700,24600,3500,24600,100,*,RIGHT,POLY +S 3200,23800,3200,24600,200,*,UP,POLY +S 3200,23800,3700,23800,300,*,RIGHT,POLY +S 1500,22500,3900,22500,300,*,RIGHT,NTIE +S 3200,13100,3200,13900,200,*,UP,POLY +S 1500,13600,2700,13600,200,*,RIGHT,ALU1 +S 3200,13000,3200,14300,200,*,DOWN,ALU1 +S 3900,22500,6300,22500,300,*,RIGHT,NTIE +S 6100,23200,6100,23800,200,*,UP,ALU1 +S 5600,23800,6100,23800,300,*,RIGHT,POLY +S 5600,23800,5600,24600,200,*,UP,POLY +S 4100,24600,5900,24600,100,*,RIGHT,POLY +S 5900,24300,6300,24300,300,*,RIGHT,PTIE +S 3900,24300,5300,24300,300,*,RIGHT,PTIE +S 5600,23700,5600,23900,200,*,DOWN,POLY +S 5900,13600,6300,13600,200,*,RIGHT,ALU1 +S 4100,13900,5900,13900,100,*,RIGHT,POLY +S 5600,13300,5600,13900,200,*,UP,POLY +S 5900,13600,6300,13600,300,*,RIGHT,NTIE +S 3900,13600,5300,13600,300,*,RIGHT,NTIE +S 5200,13400,5200,22700,2800,*,UP,NWELL +S 5900,13900,5900,22200,100,*,UP,PTRANS +S 5300,13900,5300,22200,100,*,UP,PTRANS +S 4700,13900,4700,22200,100,*,UP,PTRANS +S 4100,13900,4100,22200,100,*,UP,PTRANS +S 4400,14100,4400,22000,200,*,UP,PDIF +S 5000,14100,5000,22000,200,*,UP,PDIF +S 5600,14100,5600,22000,200,*,UP,PDIF +S 6200,14100,6200,22000,300,*,UP,PDIF +S 3900,28700,6300,28700,300,*,RIGHT,PTIE +S 5900,24600,5900,28400,100,*,UP,NTRANS +S 5300,24600,5300,28400,100,*,UP,NTRANS +S 4700,24600,4700,28400,100,*,UP,NTRANS +S 4100,24600,4100,28400,100,*,UP,NTRANS +S 4400,24800,4400,28200,300,*,UP,NDIF +S 5000,24800,5000,28200,300,*,UP,NDIF +S 5600,24800,5600,28200,300,*,UP,NDIF +S 6200,24800,6200,28200,300,*,UP,NDIF +S 5600,14200,5600,29100,200,*,UP,ALU1 +S 4400,14200,4400,29100,200,*,UP,ALU1 +S 6300,22500,8700,22500,300,*,RIGHT,NTIE +S 8500,23200,8500,23800,200,*,UP,ALU1 +S 8000,23800,8500,23800,300,*,RIGHT,POLY +S 8000,23800,8000,24600,200,*,UP,POLY +S 6500,24600,8300,24600,100,*,RIGHT,POLY +S 8300,24300,8700,24300,300,*,RIGHT,PTIE +S 6300,24300,7700,24300,300,*,RIGHT,PTIE +S 8000,23700,8000,23900,200,*,DOWN,POLY +S 8300,13600,8700,13600,200,*,RIGHT,ALU1 +S 6300,13600,7700,13600,200,*,RIGHT,ALU1 +S 6500,13900,8300,13900,100,*,RIGHT,POLY +S 8000,13300,8000,13900,200,*,UP,POLY +S 8300,13600,8700,13600,300,*,RIGHT,NTIE +S 6300,13600,7700,13600,300,*,RIGHT,NTIE +S 7600,13400,7600,22700,2800,*,UP,NWELL +S 8300,13900,8300,22200,100,*,UP,PTRANS +S 7700,13900,7700,22200,100,*,UP,PTRANS +S 7100,13900,7100,22200,100,*,UP,PTRANS +S 6500,13900,6500,22200,100,*,UP,PTRANS +S 6800,14100,6800,22000,200,*,UP,PDIF +S 7400,14100,7400,22000,200,*,UP,PDIF +S 8000,14100,8000,22000,200,*,UP,PDIF +S 8600,14100,8600,22000,300,*,UP,PDIF +S 6300,28700,8700,28700,300,*,RIGHT,PTIE +S 8300,24600,8300,28400,100,*,UP,NTRANS +S 7700,24600,7700,28400,100,*,UP,NTRANS +S 7100,24600,7100,28400,100,*,UP,NTRANS +S 6500,24600,6500,28400,100,*,UP,NTRANS +S 6800,24800,6800,28200,300,*,UP,NDIF +S 7400,24800,7400,28200,300,*,UP,NDIF +S 8000,24800,8000,28200,300,*,UP,NDIF +S 8600,24800,8600,28200,300,*,UP,NDIF +S 7400,23700,7400,28800,200,*,UP,ALU1 +S 8000,14200,8000,29100,200,*,UP,ALU1 +S 6800,14200,6800,29100,200,*,UP,ALU1 +S 8700,22500,11100,22500,300,*,RIGHT,NTIE +S 10900,23200,10900,23800,200,*,UP,ALU1 +S 10400,23800,10900,23800,300,*,RIGHT,POLY +S 10400,23800,10400,24600,200,*,UP,POLY +S 8900,24600,10700,24600,100,*,RIGHT,POLY +S 10700,24300,11100,24300,300,*,RIGHT,PTIE +S 8700,24300,10100,24300,300,*,RIGHT,PTIE +S 10400,23700,10400,23900,200,*,DOWN,POLY +S 10700,13600,11100,13600,200,*,RIGHT,ALU1 +S 8700,13600,10100,13600,200,*,RIGHT,ALU1 +S 8900,13900,10700,13900,100,*,RIGHT,POLY +S 10400,13300,10400,13900,200,*,UP,POLY +S 10700,13600,11100,13600,300,*,RIGHT,NTIE +S 8700,13600,10100,13600,300,*,RIGHT,NTIE +S 10000,13400,10000,22700,2800,*,UP,NWELL +S 10700,13900,10700,22200,100,*,UP,PTRANS +S 10100,13900,10100,22200,100,*,UP,PTRANS +S 9500,13900,9500,22200,100,*,UP,PTRANS +S 8900,13900,8900,22200,100,*,UP,PTRANS +S 9200,14100,9200,22000,200,*,UP,PDIF +S 9800,14100,9800,22000,200,*,UP,PDIF +S 10400,14100,10400,22000,200,*,UP,PDIF +S 11000,14100,11000,22000,300,*,UP,PDIF +S 8700,28700,11100,28700,300,*,RIGHT,PTIE +S 10700,24600,10700,28400,100,*,UP,NTRANS +S 10100,24600,10100,28400,100,*,UP,NTRANS +S 9500,24600,9500,28400,100,*,UP,NTRANS +S 8900,24600,8900,28400,100,*,UP,NTRANS +S 9200,24800,9200,28200,300,*,UP,NDIF +S 9800,24800,9800,28200,300,*,UP,NDIF +S 10400,24800,10400,28200,300,*,UP,NDIF +S 11000,24800,11000,28200,300,*,UP,NDIF +S 9800,23700,9800,28800,200,*,UP,ALU1 +S 10400,14200,10400,29100,200,*,UP,ALU1 +S 9200,14200,9200,29100,200,*,UP,ALU1 +S 11100,22500,13500,22500,300,*,RIGHT,NTIE +S 13300,23200,13300,23800,200,*,UP,ALU1 +S 12800,23800,13300,23800,300,*,RIGHT,POLY +S 12800,23800,12800,24600,200,*,UP,POLY +S 11300,24600,13100,24600,100,*,RIGHT,POLY +S 13100,24300,13500,24300,300,*,RIGHT,PTIE +S 11100,24300,12500,24300,300,*,RIGHT,PTIE +S 12800,23700,12800,23900,200,*,DOWN,POLY +S 13100,13600,13500,13600,200,*,RIGHT,ALU1 +S 11100,13600,12500,13600,200,*,RIGHT,ALU1 +S 11300,13900,13100,13900,100,*,RIGHT,POLY +S 12800,13300,12800,13900,200,*,UP,POLY +S 13100,13600,13500,13600,300,*,RIGHT,NTIE +S 11100,13600,12500,13600,300,*,RIGHT,NTIE +S 12400,13400,12400,22700,2800,*,UP,NWELL +S 13100,13900,13100,22200,100,*,UP,PTRANS +S 12500,13900,12500,22200,100,*,UP,PTRANS +S 11900,13900,11900,22200,100,*,UP,PTRANS +S 11300,13900,11300,22200,100,*,UP,PTRANS +S 11600,14100,11600,22000,200,*,UP,PDIF +S 12200,14100,12200,22000,200,*,UP,PDIF +S 12800,14100,12800,22000,200,*,UP,PDIF +S 13400,14100,13400,22000,300,*,UP,PDIF +S 11100,28700,13500,28700,300,*,RIGHT,PTIE +S 13100,24600,13100,28400,100,*,UP,NTRANS +S 12500,24600,12500,28400,100,*,UP,NTRANS +S 11900,24600,11900,28400,100,*,UP,NTRANS +S 11300,24600,11300,28400,100,*,UP,NTRANS +S 11600,24800,11600,28200,300,*,UP,NDIF +S 12200,24800,12200,28200,300,*,UP,NDIF +S 12800,24800,12800,28200,300,*,UP,NDIF +S 13400,24800,13400,28200,300,*,UP,NDIF +S 12200,23700,12200,28800,200,*,UP,ALU1 +S 12800,14200,12800,29100,200,*,UP,ALU1 +S 11600,14200,11600,29100,200,*,UP,ALU1 +S 13500,22500,15900,22500,300,*,RIGHT,NTIE +S 15700,23200,15700,23800,200,*,UP,ALU1 +S 15200,23800,15700,23800,300,*,RIGHT,POLY +S 15200,23800,15200,24600,200,*,UP,POLY +S 13700,24600,15500,24600,100,*,RIGHT,POLY +S 15500,24300,15900,24300,300,*,RIGHT,PTIE +S 13500,24300,14900,24300,300,*,RIGHT,PTIE +S 15200,23700,15200,23900,200,*,DOWN,POLY +S 15500,13600,15900,13600,200,*,RIGHT,ALU1 +S 13500,13600,14900,13600,200,*,RIGHT,ALU1 +S 13700,13900,15500,13900,100,*,RIGHT,POLY +S 15200,13300,15200,13900,200,*,UP,POLY +S 15500,13600,15900,13600,300,*,RIGHT,NTIE +S 13500,13600,14900,13600,300,*,RIGHT,NTIE +S 14800,13400,14800,22700,2800,*,UP,NWELL +S 15500,13900,15500,22200,100,*,UP,PTRANS +S 14900,13900,14900,22200,100,*,UP,PTRANS +S 14300,13900,14300,22200,100,*,UP,PTRANS +S 13700,13900,13700,22200,100,*,UP,PTRANS +S 14000,14100,14000,22000,200,*,UP,PDIF +S 14600,14100,14600,22000,200,*,UP,PDIF +S 15200,14100,15200,22000,200,*,UP,PDIF +S 15800,14100,15800,22000,300,*,UP,PDIF +S 13500,28700,15900,28700,300,*,RIGHT,PTIE +S 15500,24600,15500,28400,100,*,UP,NTRANS +S 14900,24600,14900,28400,100,*,UP,NTRANS +S 14300,24600,14300,28400,100,*,UP,NTRANS +S 13700,24600,13700,28400,100,*,UP,NTRANS +S 14000,24800,14000,28200,300,*,UP,NDIF +S 14600,24800,14600,28200,300,*,UP,NDIF +S 15200,24800,15200,28200,300,*,UP,NDIF +S 15800,24800,15800,28200,300,*,UP,NDIF +S 14600,23700,14600,28800,200,*,UP,ALU1 +S 15200,14200,15200,29100,200,*,UP,ALU1 +S 14000,14200,14000,29100,200,*,UP,ALU1 +S 3700,23100,3700,23800,200,*,UP,ALU1 +S 15800,28900,15800,29300,200,*,UP,ALU1 +S 8600,29200,8600,35600,13500,*,UP,ALU1 +S 700,28000,700,28800,100,*,UP,ALU1 +S 1100,24200,1100,29300,800,*,UP,ALU1 +S 2000,5700,2000,9300,200,*,DOWN,ALU1 +S 1800,9200,1800,9400,200,*,DOWN,ALU1 +S 15500,8100,15500,12100,2000,*,DOWN,ALU1 +S 15800,2800,15800,7500,200,*,UP,ALU1 +S 14600,2700,14600,7500,200,*,UP,ALU1 +S 15200,5000,15200,12100,200,*,UP,ALU1 +S 9700,4600,11100,4600,200,*,LEFT,ALU1 +S 11100,3900,11100,4600,200,*,UP,ALU1 +S 14000,600,14000,3300,200,*,UP,ALU1 +S 12800,600,12800,3300,200,*,UP,ALU1 +S 12200,700,12200,3900,200,*,UP,ALU1 +S 12200,4600,12200,11400,200,*,UP,ALU1 +S 11600,4600,13500,4600,200,*,RIGHT,ALU1 +S 13400,4600,13400,11400,200,*,UP,ALU1 +S 3700,13100,15300,13100,200,*,RIGHT,ALU1 +S 13400,700,13400,3900,200,*,UP,ALU1 +S 11600,600,11600,4600,200,*,UP,ALU1 +S 12200,3900,14000,3900,200,*,RIGHT,ALU1 +S 8600,5000,8600,12000,200,*,UP,ALU1 +S 6800,600,6800,3300,200,*,UP,ALU1 +S 1400,4500,3300,4500,200,*,RIGHT,ALU1 +S 6200,5100,7100,5100,200,*,RIGHT,ALU1 +S 2600,900,2600,8200,200,*,UP,ALU1 +S 1400,900,1400,4500,200,*,UP,ALU1 +S 5600,900,5600,11400,200,*,UP,ALU1 +S 5600,4600,7300,4600,200,*,RIGHT,ALU1 +S 9800,5700,9800,12000,200,*,UP,ALU1 +S 7400,5700,7400,12000,200,*,UP,ALU1 +S 10400,600,10400,3300,200,*,UP,ALU1 +S 9200,600,9200,3300,200,*,UP,ALU1 +S 8000,600,8000,3300,200,*,UP,ALU1 +S 5000,900,5000,11400,200,*,UP,ALU1 +S 14900,-100,14900,1900,800,*,DOWN,ALU1 +S 1400,11300,2700,11300,200,*,RIGHT,ALU1 +S 1100,13500,1100,22600,800,*,UP,ALU1 +S 700,5100,2100,5100,200,*,LEFT,ALU1 +S 1100,5000,1100,8700,900,*,UP,ALU1 +S 4900,-700,4900,300,200,*,UP,ALU1 +S 15700,-700,15700,2300,200,*,DOWN,ALU1 +S 3800,-700,3800,11400,200,*,UP,ALU1 +S 2900,3700,2900,5400,100,*,UP,POLY +S 8900,5400,10700,5400,100,*,RIGHT,POLY +S 8900,3700,10700,3700,100,*,RIGHT,POLY +S 9800,4600,9800,5400,300,*,DOWN,POLY +S 10800,4500,11300,4500,100,*,LEFT,POLY +S 11300,4500,11300,5400,100,*,DOWN,POLY +S 11300,5400,14900,5400,100,*,RIGHT,POLY +S 10700,3700,10700,4500,100,*,DOWN,POLY +S 7400,3700,7400,5400,200,*,UP,POLY +S 3600,4500,4000,4500,300,*,RIGHT,POLY +S 2900,8700,2900,9000,100,*,UP,POLY +S 4700,3700,4700,5400,100,*,UP,POLY +S 4100,3700,4100,5400,100,*,UP,POLY +S 3500,3700,3500,5400,100,*,UP,POLY +S 4700,200,4700,400,100,*,UP,POLY +S 1700,3700,2900,3700,100,*,RIGHT,POLY +S 11300,3600,11300,4100,100,*,DOWN,POLY +S 11400,3800,11400,4100,100,*,DOWN,POLY +S 11400,3700,14300,3700,100,*,RIGHT,POLY +S 11400,3600,14300,3600,100,*,RIGHT,POLY +S 5900,3700,5900,5400,100,*,UP,POLY +S 5200,5300,5900,5300,300,*,RIGHT,POLY +S 6500,3700,8300,3700,100,*,RIGHT,POLY +S 6500,5400,8300,5400,100,*,RIGHT,POLY +S 14300,3700,14300,3900,100,*,DOWN,POLY +S 14200,4700,14200,5300,100,*,DOWN,POLY +S 14300,4700,14300,5300,100,*,DOWN,POLY +S 14200,4500,14900,4500,300,*,RIGHT,POLY +S 14900,3700,14900,4300,100,*,UP,POLY +S 10600,3800,10600,4500,100,*,DOWN,POLY +S 10600,4600,11200,4600,100,*,LEFT,POLY +S 11400,4500,11400,5300,100,*,DOWN,POLY +S 11300,5500,14900,5500,100,*,RIGHT,POLY +S 15500,3700,15500,5500,100,*,UP,POLY +S 15500,2200,15500,2400,100,*,DOWN,POLY +S 14200,3700,14200,3900,100,*,DOWN,POLY +S 15900,24300,16500,24300,300,*,RIGHT,PTIE +S 16000,28700,16500,28700,300,*,RIGHT,PTIE +S 16400,24200,16400,28800,300,*,UP,PTIE +S 700,24300,1500,24300,300,*,RIGHT,PTIE +S 800,24200,800,28800,300,*,UP,PTIE +S 700,28700,1500,28700,300,*,RIGHT,PTIE +S 16400,1700,16400,4100,300,*,UP,PTIE +S 7700,4000,10400,4000,300,*,RIGHT,PTIE +S 11600,4000,14000,4000,300,*,RIGHT,PTIE +S 6100,4000,7100,4000,300,*,RIGHT,PTIE +S 15700,4000,16500,4000,300,*,LEFT,PTIE +S 14600,0,14600,1900,300,*,DOWN,PTIE +S 14900,0,14900,1900,300,*,DOWN,PTIE +S 15200,1800,16500,1800,300,*,LEFT,PTIE +S 700,4000,2700,4000,300,*,RIGHT,PTIE +S 15200,-300,15200,1900,300,*,DOWN,PTIE +S 700,-200,15300,-200,300,*,RIGHT,PTIE +S 800,-300,800,4100,300,*,UP,PTIE +S 16000,22500,16500,22500,300,*,RIGHT,NTIE +S 800,22500,1400,22500,300,*,RIGHT,NTIE +S 7700,5100,9500,5100,300,*,RIGHT,NTIE +S 10100,5100,11000,5100,300,*,RIGHT,NTIE +S 15700,5100,16500,5100,300,*,RIGHT,NTIE +S 1400,5100,1400,6400,1100,*,DOWN,NTIE +S 2000,9700,2000,12000,300,*,UP,NTIE +S 2000,5000,2000,9100,300,*,UP,NTIE +S 2200,8900,2200,9900,300,*,UP,NTIE +S 15500,8100,15500,12000,2000,*,DOWN,NTIE +S 16400,13600,16400,22600,300,*,UP,NTIE +S 6100,5100,7100,5100,300,*,RIGHT,NTIE +S 16400,5000,16400,12100,300,*,UP,NTIE +S 14500,5100,15300,5100,300,*,RIGHT,NTIE +S 11600,5100,14000,5100,300,*,RIGHT,NTIE +S 16000,13600,16500,13600,300,*,RIGHT,NTIE +S 800,13600,800,22600,300,*,UP,NTIE +S 800,13600,1400,13600,300,*,RIGHT,NTIE +S 700,5100,2700,5100,300,*,RIGHT,NTIE +S 800,5000,800,12100,300,*,UP,NTIE +S 700,12000,16500,12000,300,*,RIGHT,NTIE +S 15500,5500,15500,7800,100,*,UP,PTRANS +S 14900,5500,14900,7800,100,*,UP,PTRANS +S 15200,5700,15200,7600,300,*,UP,PDIF +S 15800,5700,15800,7600,300,*,UP,PDIF +S 14600,5700,14600,7600,300,*,UP,PDIF +S 3500,5400,3500,11700,100,*,UP,PTRANS +S 3800,5600,3800,11500,300,*,UP,PDIF +S 3200,5600,3200,11500,300,*,UP,PDIF +S 2600,5600,2600,8500,300,*,UP,PDIF +S 2900,5400,2900,8700,100,*,UP,PTRANS +S 10700,5400,10700,11700,100,*,UP,PTRANS +S 4700,5400,4700,11700,100,*,UP,PTRANS +S 5000,5600,5000,11500,300,*,UP,PDIF +S 4400,5600,4400,11500,300,*,UP,PDIF +S 4100,5400,4100,11700,100,*,UP,PTRANS +S 11000,5600,11000,11500,300,*,UP,PDIF +S 9200,5600,9200,11500,300,*,UP,PDIF +S 8900,5400,8900,11700,100,*,UP,PTRANS +S 9500,5400,9500,11700,100,*,UP,PTRANS +S 10100,5400,10100,11700,100,*,UP,PTRANS +S 5900,5400,5900,11700,100,*,UP,PTRANS +S 6200,5600,6200,11500,300,*,UP,PDIF +S 6500,5400,6500,11700,100,*,UP,PTRANS +S 7100,5400,7100,11700,100,*,UP,PTRANS +S 9800,5600,9800,11500,300,*,UP,PDIF +S 8300,5400,8300,11700,100,*,UP,PTRANS +S 7400,5600,7400,11500,300,*,UP,PDIF +S 8600,5600,8600,11500,300,*,UP,PDIF +S 6800,5600,6800,11500,300,*,UP,PDIF +S 10400,5600,10400,11500,300,*,UP,PDIF +S 8000,5600,8000,11500,300,*,UP,PDIF +S 5600,5600,5600,11500,300,*,UP,PDIF +S 12500,5500,12500,11700,100,*,UP,PTRANS +S 11600,5700,11600,11500,300,*,UP,PDIF +S 11900,5500,11900,11700,100,*,UP,PTRANS +S 1400,14100,1400,22000,300,*,UP,PDIF +S 7700,5400,7700,11700,100,*,UP,PTRANS +S 14000,5700,14000,11500,300,*,UP,PDIF +S 13700,5500,13700,11700,100,*,UP,PTRANS +S 13400,5700,13400,11500,300,*,UP,PDIF +S 13100,5500,13100,11700,100,*,UP,PTRANS +S 12800,5700,12800,11500,300,*,UP,PDIF +S 12200,5700,12200,11500,300,*,UP,PDIF +S 1400,24900,1400,28200,300,*,UP,NDIF +S 2300,400,2300,3700,100,*,UP,NTRANS +S 1700,400,1700,3700,100,*,UP,NTRANS +S 2000,600,2000,3500,200,*,UP,NDIF +S 2600,600,2600,3500,300,*,UP,NDIF +S 1400,600,1400,3500,300,*,UP,NDIF +S 11000,600,11000,3500,300,*,UP,NDIF +S 4100,400,4100,3700,100,*,UP,NTRANS +S 3500,400,3500,3700,100,*,UP,NTRANS +S 3800,600,3800,3500,300,*,UP,NDIF +S 3200,600,3200,3500,200,*,UP,NDIF +S 2900,400,2900,3700,100,*,UP,NTRANS +S 9500,400,9500,3700,100,*,UP,NTRANS +S 10100,400,10100,3700,100,*,UP,NTRANS +S 4400,600,4400,3500,200,*,UP,NDIF +S 4700,400,4700,3700,100,*,UP,NTRANS +S 5000,600,5000,3500,300,*,UP,NDIF +S 10700,400,10700,3700,100,*,UP,NTRANS +S 9800,600,9800,3500,200,*,UP,NDIF +S 9200,600,9200,3500,300,*,UP,NDIF +S 8900,400,8900,3700,100,*,UP,NTRANS +S 10400,600,10400,3500,300,*,UP,NDIF +S 8000,600,8000,3500,300,*,UP,NDIF +S 5600,600,5600,3500,300,*,UP,NDIF +S 5900,400,5900,3700,100,*,UP,NTRANS +S 6200,600,6200,3500,200,*,UP,NDIF +S 6500,400,6500,3700,100,*,UP,NTRANS +S 7100,400,7100,3700,100,*,UP,NTRANS +S 7700,400,7700,3700,100,*,UP,NTRANS +S 8300,400,8300,3700,100,*,UP,NTRANS +S 7400,600,7400,3500,200,*,UP,NDIF +S 8600,600,8600,3500,200,*,UP,NDIF +S 6800,600,6800,3500,300,*,UP,NDIF +S 11600,600,11600,3400,300,*,UP,NDIF +S 13700,400,13700,3600,100,*,UP,NTRANS +S 13100,400,13100,3600,100,*,UP,NTRANS +S 12500,400,12500,3600,100,*,UP,NTRANS +S 11900,400,11900,3600,100,*,UP,NTRANS +S 15500,2400,15500,3700,100,*,UP,NTRANS +S 15800,2600,15800,3500,300,*,UP,NDIF +S 14000,600,14000,3400,300,*,UP,NDIF +S 13400,600,13400,3400,200,*,UP,NDIF +S 12800,600,12800,3400,300,*,UP,NDIF +S 12200,600,12200,3400,200,*,UP,NDIF +S 15200,2600,15200,3500,300,*,DOWN,NDIF +S 14600,2600,14600,3500,300,*,UP,NDIF +S 14900,2400,14900,3700,100,*,UP,NTRANS +S 16300,13400,16300,22700,600,*,UP,NWELL +S 1000,13400,1000,22700,800,*,UP,NWELL +S 600,8600,16600,8600,7200,*,RIGHT,NWELL +S 600,5100,16600,5100,400,*,RIGHT,NWELL +S 16200,23200,17000,23200,200,*,RIGHT,ALU1 +S 16400,5000,16400,12100,200,*,UP,ALU1 +S 16400,2300,16400,4100,200,*,UP,ALU1 +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 1100,9100,1700,9100,3900,*,RIGHT,PTRANS +V 16400,1600,CONT_VIA,* +B 15500,9200,1800,2100,CONT_VIA,* +B 16100,18000,800,9100,CONT_VIA,* +B 1000,18000,700,9100,CONT_VIA,* +B 1100,26700,800,5200,CONT_VIA,* +V 3700,13600,CONT_BODY_N,* +V 3800,13100,CONT_POLY,* +V 3800,27700,CONT_DIF_N,* +V 3800,26100,CONT_DIF_N,* +V 3800,25700,CONT_DIF_N,* +V 3800,27300,CONT_DIF_N,* +V 3800,26900,CONT_DIF_N,* +V 3800,25300,CONT_DIF_N,* +V 3800,26500,CONT_VIA,* +V 3800,24900,CONT_VIA,* +V 3800,28100,CONT_VIA,* +V 2600,24900,CONT_VIA,* +V 2600,25300,CONT_DIF_N,* +V 2600,26900,CONT_DIF_N,* +V 2600,27300,CONT_DIF_N,* +V 2600,26500,CONT_DIF_N,* +V 2600,28100,CONT_DIF_N,* +V 2600,25700,CONT_DIF_N,* +V 2600,27700,CONT_VIA,* +V 2600,26100,CONT_VIA,* +V 3800,28700,CONT_BODY_P,* +V 2600,28700,CONT_BODY_P,* +V 2200,13600,CONT_BODY_N,* +V 2000,25000,CONT_DIF_N,* +V 2000,27400,CONT_DIF_N,* +V 2000,27800,CONT_DIF_N,* +V 2000,25400,CONT_DIF_N,* +V 2000,25800,CONT_DIF_N,* +V 2000,26200,CONT_DIF_N,* +V 2000,26600,CONT_DIF_N,* +V 2000,27000,CONT_DIF_N,* +V 3200,25800,CONT_DIF_N,* +V 3200,26200,CONT_DIF_N,* +V 3200,25400,CONT_DIF_N,* +V 3200,25000,CONT_DIF_N,* +V 3200,27800,CONT_DIF_N,* +V 3200,26600,CONT_DIF_N,* +V 3200,27000,CONT_DIF_N,* +V 3200,27400,CONT_DIF_N,* +V 2600,14300,CONT_DIF_P,* +V 2000,14700,CONT_DIF_P,* +V 2600,14700,CONT_DIF_P,* +V 2000,15100,CONT_DIF_P,* +V 2000,14300,CONT_DIF_P,* +V 3200,14300,CONT_DIF_P,* +V 3800,14300,CONT_DIF_P,* +V 3200,14700,CONT_DIF_P,* +V 3800,14700,CONT_DIF_P,* +V 3200,15100,CONT_DIF_P,* +V 2600,15500,CONT_DIF_P,* +V 2000,15500,CONT_DIF_P,* +V 2000,19500,CONT_DIF_P,* +V 2000,17900,CONT_DIF_P,* +V 2600,17900,CONT_DIF_P,* +V 2000,18300,CONT_DIF_P,* +V 2600,18300,CONT_DIF_P,* +V 2000,18700,CONT_DIF_P,* +V 2000,19100,CONT_DIF_P,* +V 2600,19100,CONT_DIF_P,* +V 2600,19500,CONT_DIF_P,* +V 2000,16300,CONT_DIF_P,* +V 2000,15900,CONT_DIF_P,* +V 2600,15900,CONT_DIF_P,* +V 2000,17500,CONT_DIF_P,* +V 2000,17100,CONT_DIF_P,* +V 2000,16700,CONT_DIF_P,* +V 2600,16700,CONT_DIF_P,* +V 2600,17100,CONT_DIF_P,* +V 3200,15500,CONT_DIF_P,* +V 3800,15500,CONT_DIF_P,* +V 3800,19500,CONT_DIF_P,* +V 3200,18300,CONT_DIF_P,* +V 3200,18700,CONT_DIF_P,* +V 3200,19100,CONT_DIF_P,* +V 3800,19100,CONT_DIF_P,* +V 3200,19500,CONT_DIF_P,* +V 3200,17500,CONT_DIF_P,* +V 3200,17100,CONT_DIF_P,* +V 3200,17900,CONT_DIF_P,* +V 3800,17900,CONT_DIF_P,* +V 3800,18300,CONT_DIF_P,* +V 3200,16300,CONT_DIF_P,* +V 3200,15900,CONT_DIF_P,* +V 3800,15900,CONT_DIF_P,* +V 3800,17100,CONT_DIF_P,* +V 3800,16700,CONT_DIF_P,* +V 3200,16700,CONT_DIF_P,* +V 2600,15100,CONT_VIA,* +V 3800,15100,CONT_VIA,* +V 2600,17500,CONT_VIA,* +V 2600,18700,CONT_VIA,* +V 2600,16300,CONT_VIA,* +V 3800,18700,CONT_VIA,* +V 3800,17500,CONT_VIA,* +V 3800,16300,CONT_VIA,* +V 2000,19900,CONT_DIF_P,* +V 3200,19900,CONT_DIF_P,* +V 2600,19900,CONT_VIA,* +V 3800,19900,CONT_VIA,* +V 2000,20300,CONT_DIF_P,* +V 3200,20300,CONT_DIF_P,* +V 2600,20300,CONT_DIF_P,* +V 3800,20300,CONT_DIF_P,* +V 2600,20700,CONT_DIF_P,* +V 3800,20700,CONT_DIF_P,* +V 3200,20700,CONT_DIF_P,* +V 2000,20700,CONT_DIF_P,* +V 2000,21100,CONT_DIF_P,* +V 3200,21100,CONT_DIF_P,* +V 3800,21100,CONT_VIA,* +V 2600,21100,CONT_VIA,* +V 2000,21500,CONT_DIF_P,* +V 2600,21500,CONT_DIF_P,* +V 3200,21500,CONT_DIF_P,* +V 3800,21500,CONT_DIF_P,* +V 2600,24300,CONT_BODY_P,* +V 3800,24300,CONT_BODY_P,* +V 3700,23800,CONT_POLY,* +V 2600,23800,CONT_VIA,* +V 3800,22500,CONT_BODY_N,* +V 2600,22500,CONT_BODY_N,* +V 3800,21900,CONT_DIF_P,* +V 3200,21900,CONT_DIF_P,* +V 2600,21900,CONT_DIF_P,* +V 2000,21900,CONT_DIF_P,* +V 2600,13600,CONT_VIA,* +V 1700,13600,CONT_BODY_N,* +V 4400,21900,CONT_DIF_P,* +V 5000,21900,CONT_DIF_P,* +V 5600,21900,CONT_DIF_P,* +V 6200,21900,CONT_DIF_P,* +V 5000,22500,CONT_BODY_N,* +V 6200,22500,CONT_BODY_N,* +V 6100,23200,CONT_VIA,* +V 5000,23800,CONT_VIA,* +V 6100,23800,CONT_POLY,* +V 6200,24300,CONT_BODY_P,* +V 5000,24300,CONT_BODY_P,* +V 6200,21500,CONT_DIF_P,* +V 5600,21500,CONT_DIF_P,* +V 5000,21500,CONT_DIF_P,* +V 4400,21500,CONT_DIF_P,* +V 5000,21100,CONT_VIA,* +V 6200,21100,CONT_VIA,* +V 5600,21100,CONT_DIF_P,* +V 4400,21100,CONT_DIF_P,* +V 4400,20700,CONT_DIF_P,* +V 5600,20700,CONT_DIF_P,* +V 6200,20700,CONT_DIF_P,* +V 5000,20700,CONT_DIF_P,* +V 6200,20300,CONT_DIF_P,* +V 5000,20300,CONT_DIF_P,* +V 5600,20300,CONT_DIF_P,* +V 4400,20300,CONT_DIF_P,* +V 6200,19900,CONT_VIA,* +V 5000,19900,CONT_VIA,* +V 5600,19900,CONT_DIF_P,* +V 4400,19900,CONT_DIF_P,* +V 6200,16300,CONT_VIA,* +V 6200,17500,CONT_VIA,* +V 6200,18700,CONT_VIA,* +V 5000,16300,CONT_VIA,* +V 5000,18700,CONT_VIA,* +V 5000,17500,CONT_VIA,* +V 6200,15100,CONT_VIA,* +V 5000,15100,CONT_VIA,* +V 5600,16700,CONT_DIF_P,* +V 6200,16700,CONT_DIF_P,* +V 6200,17100,CONT_DIF_P,* +V 6200,15900,CONT_DIF_P,* +V 5600,15900,CONT_DIF_P,* +V 5600,16300,CONT_DIF_P,* +V 6200,18300,CONT_DIF_P,* +V 6200,17900,CONT_DIF_P,* +V 5600,17900,CONT_DIF_P,* +V 5600,17100,CONT_DIF_P,* +V 5600,17500,CONT_DIF_P,* +V 5600,19500,CONT_DIF_P,* +V 6200,19100,CONT_DIF_P,* +V 5600,19100,CONT_DIF_P,* +V 5600,18700,CONT_DIF_P,* +V 5600,18300,CONT_DIF_P,* +V 6200,19500,CONT_DIF_P,* +V 6200,15500,CONT_DIF_P,* +V 5600,15500,CONT_DIF_P,* +V 5000,17100,CONT_DIF_P,* +V 5000,16700,CONT_DIF_P,* +V 4400,16700,CONT_DIF_P,* +V 4400,17100,CONT_DIF_P,* +V 4400,17500,CONT_DIF_P,* +V 5000,15900,CONT_DIF_P,* +V 4400,15900,CONT_DIF_P,* +V 4400,16300,CONT_DIF_P,* +V 5000,19500,CONT_DIF_P,* +V 5000,19100,CONT_DIF_P,* +V 4400,19100,CONT_DIF_P,* +V 4400,18700,CONT_DIF_P,* +V 5000,18300,CONT_DIF_P,* +V 4400,18300,CONT_DIF_P,* +V 5000,17900,CONT_DIF_P,* +V 4400,17900,CONT_DIF_P,* +V 4400,19500,CONT_DIF_P,* +V 4400,15500,CONT_DIF_P,* +V 5000,15500,CONT_DIF_P,* +V 5600,15100,CONT_DIF_P,* +V 6200,14700,CONT_DIF_P,* +V 5600,14700,CONT_DIF_P,* +V 6200,14300,CONT_DIF_P,* +V 5600,14300,CONT_DIF_P,* +V 4400,14300,CONT_DIF_P,* +V 4400,15100,CONT_DIF_P,* +V 5000,14700,CONT_DIF_P,* +V 4400,14700,CONT_DIF_P,* +V 5000,14300,CONT_DIF_P,* +V 5600,27400,CONT_DIF_N,* +V 5600,27000,CONT_DIF_N,* +V 5600,26600,CONT_DIF_N,* +V 5600,27800,CONT_DIF_N,* +V 5600,25000,CONT_DIF_N,* +V 5600,25400,CONT_DIF_N,* +V 5600,26200,CONT_DIF_N,* +V 5600,25800,CONT_DIF_N,* +V 4400,27000,CONT_DIF_N,* +V 4400,26600,CONT_DIF_N,* +V 4400,26200,CONT_DIF_N,* +V 4400,25800,CONT_DIF_N,* +V 4400,25400,CONT_DIF_N,* +V 4400,27800,CONT_DIF_N,* +V 4400,27400,CONT_DIF_N,* +V 4400,25000,CONT_DIF_N,* +V 4900,13600,CONT_VIA,* +V 5600,13100,CONT_POLY,* +V 6000,13600,CONT_BODY_N,* +V 4600,13600,CONT_BODY_N,* +V 5200,13600,CONT_BODY_N,* +V 4100,13600,CONT_BODY_N,* +V 5000,28700,CONT_BODY_P,* +V 6200,28700,CONT_BODY_P,* +V 5000,26100,CONT_VIA,* +V 5000,27700,CONT_VIA,* +V 5000,25700,CONT_DIF_N,* +V 5000,28100,CONT_DIF_N,* +V 5000,26500,CONT_DIF_N,* +V 5000,27300,CONT_DIF_N,* +V 5000,26900,CONT_DIF_N,* +V 5000,25300,CONT_DIF_N,* +V 5000,24900,CONT_VIA,* +V 6200,28100,CONT_VIA,* +V 6200,24900,CONT_VIA,* +V 6200,26500,CONT_VIA,* +V 6200,25300,CONT_DIF_N,* +V 6200,26900,CONT_DIF_N,* +V 6200,27300,CONT_DIF_N,* +V 6200,25700,CONT_DIF_N,* +V 6200,26100,CONT_DIF_N,* +V 6200,27700,CONT_DIF_N,* +V 6800,21900,CONT_DIF_P,* +V 7400,21900,CONT_DIF_P,* +V 8000,21900,CONT_DIF_P,* +V 8600,21900,CONT_DIF_P,* +V 7400,22500,CONT_BODY_N,* +V 8600,22500,CONT_BODY_N,* +V 8500,23200,CONT_VIA,* +V 7400,23800,CONT_VIA,* +V 8500,23800,CONT_POLY,* +V 8600,24300,CONT_BODY_P,* +V 7400,24300,CONT_BODY_P,* +V 8600,21500,CONT_DIF_P,* +V 8000,21500,CONT_DIF_P,* +V 7400,21500,CONT_DIF_P,* +V 6800,21500,CONT_DIF_P,* +V 7400,21100,CONT_VIA,* +V 8600,21100,CONT_VIA,* +V 8000,21100,CONT_DIF_P,* +V 6800,21100,CONT_DIF_P,* +V 6800,20700,CONT_DIF_P,* +V 8000,20700,CONT_DIF_P,* +V 8600,20700,CONT_DIF_P,* +V 7400,20700,CONT_DIF_P,* +V 8600,20300,CONT_DIF_P,* +V 7400,20300,CONT_DIF_P,* +V 8000,20300,CONT_DIF_P,* +V 6800,20300,CONT_DIF_P,* +V 8600,19900,CONT_VIA,* +V 7400,19900,CONT_VIA,* +V 8000,19900,CONT_DIF_P,* +V 6800,19900,CONT_DIF_P,* +V 8600,16300,CONT_VIA,* +V 8600,17500,CONT_VIA,* +V 8600,18700,CONT_VIA,* +V 7400,16300,CONT_VIA,* +V 7400,18700,CONT_VIA,* +V 7400,17500,CONT_VIA,* +V 8600,15100,CONT_VIA,* +V 7400,15100,CONT_VIA,* +V 8000,16700,CONT_DIF_P,* +V 8600,16700,CONT_DIF_P,* +V 8600,17100,CONT_DIF_P,* +V 8600,15900,CONT_DIF_P,* +V 8000,15900,CONT_DIF_P,* +V 8000,16300,CONT_DIF_P,* +V 8600,18300,CONT_DIF_P,* +V 8600,17900,CONT_DIF_P,* +V 8000,17900,CONT_DIF_P,* +V 8000,17100,CONT_DIF_P,* +V 8000,17500,CONT_DIF_P,* +V 8000,19500,CONT_DIF_P,* +V 8600,19100,CONT_DIF_P,* +V 8000,19100,CONT_DIF_P,* +V 8000,18700,CONT_DIF_P,* +V 8000,18300,CONT_DIF_P,* +V 8600,19500,CONT_DIF_P,* +V 8600,15500,CONT_DIF_P,* +V 8000,15500,CONT_DIF_P,* +V 7400,17100,CONT_DIF_P,* +V 7400,16700,CONT_DIF_P,* +V 6800,16700,CONT_DIF_P,* +V 6800,17100,CONT_DIF_P,* +V 6800,17500,CONT_DIF_P,* +V 7400,15900,CONT_DIF_P,* +V 6800,15900,CONT_DIF_P,* +V 6800,16300,CONT_DIF_P,* +V 7400,19500,CONT_DIF_P,* +V 7400,19100,CONT_DIF_P,* +V 6800,19100,CONT_DIF_P,* +V 6800,18700,CONT_DIF_P,* +V 7400,18300,CONT_DIF_P,* +V 6800,18300,CONT_DIF_P,* +V 7400,17900,CONT_DIF_P,* +V 6800,17900,CONT_DIF_P,* +V 6800,19500,CONT_DIF_P,* +V 6800,15500,CONT_DIF_P,* +V 7400,15500,CONT_DIF_P,* +V 8000,15100,CONT_DIF_P,* +V 8600,14700,CONT_DIF_P,* +V 8000,14700,CONT_DIF_P,* +V 8600,14300,CONT_DIF_P,* +V 8000,14300,CONT_DIF_P,* +V 6800,14300,CONT_DIF_P,* +V 6800,15100,CONT_DIF_P,* +V 7400,14700,CONT_DIF_P,* +V 6800,14700,CONT_DIF_P,* +V 7400,14300,CONT_DIF_P,* +V 8000,27400,CONT_DIF_N,* +V 8000,27000,CONT_DIF_N,* +V 8000,26600,CONT_DIF_N,* +V 8000,27800,CONT_DIF_N,* +V 8000,25000,CONT_DIF_N,* +V 8000,25400,CONT_DIF_N,* +V 8000,26200,CONT_DIF_N,* +V 8000,25800,CONT_DIF_N,* +V 6800,27000,CONT_DIF_N,* +V 6800,26600,CONT_DIF_N,* +V 6800,26200,CONT_DIF_N,* +V 6800,25800,CONT_DIF_N,* +V 6800,25400,CONT_DIF_N,* +V 6800,27800,CONT_DIF_N,* +V 6800,27400,CONT_DIF_N,* +V 6800,25000,CONT_DIF_N,* +V 7300,13600,CONT_VIA,* +V 8000,13100,CONT_POLY,* +V 8400,13600,CONT_BODY_N,* +V 7000,13600,CONT_BODY_N,* +V 7600,13600,CONT_BODY_N,* +V 6500,13600,CONT_BODY_N,* +V 7400,28700,CONT_BODY_P,* +V 8600,28700,CONT_BODY_P,* +V 7400,26100,CONT_VIA,* +V 7400,27700,CONT_VIA,* +V 7400,25700,CONT_DIF_N,* +V 7400,28100,CONT_DIF_N,* +V 7400,26500,CONT_DIF_N,* +V 7400,27300,CONT_DIF_N,* +V 7400,26900,CONT_DIF_N,* +V 7400,25300,CONT_DIF_N,* +V 7400,24900,CONT_VIA,* +V 8600,28100,CONT_VIA,* +V 8600,24900,CONT_VIA,* +V 8600,26500,CONT_VIA,* +V 8600,25300,CONT_DIF_N,* +V 8600,26900,CONT_DIF_N,* +V 8600,27300,CONT_DIF_N,* +V 8600,25700,CONT_DIF_N,* +V 8600,26100,CONT_DIF_N,* +V 8600,27700,CONT_DIF_N,* +V 9200,21900,CONT_DIF_P,* +V 9800,21900,CONT_DIF_P,* +V 10400,21900,CONT_DIF_P,* +V 11000,21900,CONT_DIF_P,* +V 9800,22500,CONT_BODY_N,* +V 11000,22500,CONT_BODY_N,* +V 10900,23200,CONT_VIA,* +V 9800,23800,CONT_VIA,* +V 10900,23800,CONT_POLY,* +V 11000,24300,CONT_BODY_P,* +V 9800,24300,CONT_BODY_P,* +V 11000,21500,CONT_DIF_P,* +V 10400,21500,CONT_DIF_P,* +V 9800,21500,CONT_DIF_P,* +V 9200,21500,CONT_DIF_P,* +V 9800,21100,CONT_VIA,* +V 11000,21100,CONT_VIA,* +V 10400,21100,CONT_DIF_P,* +V 9200,21100,CONT_DIF_P,* +V 9200,20700,CONT_DIF_P,* +V 10400,20700,CONT_DIF_P,* +V 11000,20700,CONT_DIF_P,* +V 9800,20700,CONT_DIF_P,* +V 11000,20300,CONT_DIF_P,* +V 9800,20300,CONT_DIF_P,* +V 10400,20300,CONT_DIF_P,* +V 9200,20300,CONT_DIF_P,* +V 11000,19900,CONT_VIA,* +V 9800,19900,CONT_VIA,* +V 10400,19900,CONT_DIF_P,* +V 9200,19900,CONT_DIF_P,* +V 11000,16300,CONT_VIA,* +V 11000,17500,CONT_VIA,* +V 11000,18700,CONT_VIA,* +V 9800,16300,CONT_VIA,* +V 9800,18700,CONT_VIA,* +V 9800,17500,CONT_VIA,* +V 11000,15100,CONT_VIA,* +V 9800,15100,CONT_VIA,* +V 10400,16700,CONT_DIF_P,* +V 11000,16700,CONT_DIF_P,* +V 11000,17100,CONT_DIF_P,* +V 11000,15900,CONT_DIF_P,* +V 10400,15900,CONT_DIF_P,* +V 10400,16300,CONT_DIF_P,* +V 11000,18300,CONT_DIF_P,* +V 11000,17900,CONT_DIF_P,* +V 10400,17900,CONT_DIF_P,* +V 10400,17100,CONT_DIF_P,* +V 10400,17500,CONT_DIF_P,* +V 10400,19500,CONT_DIF_P,* +V 11000,19100,CONT_DIF_P,* +V 10400,19100,CONT_DIF_P,* +V 10400,18700,CONT_DIF_P,* +V 10400,18300,CONT_DIF_P,* +V 11000,19500,CONT_DIF_P,* +V 11000,15500,CONT_DIF_P,* +V 10400,15500,CONT_DIF_P,* +V 9800,17100,CONT_DIF_P,* +V 9800,16700,CONT_DIF_P,* +V 9200,16700,CONT_DIF_P,* +V 9200,17100,CONT_DIF_P,* +V 9200,17500,CONT_DIF_P,* +V 9800,15900,CONT_DIF_P,* +V 9200,15900,CONT_DIF_P,* +V 9200,16300,CONT_DIF_P,* +V 9800,19500,CONT_DIF_P,* +V 9800,19100,CONT_DIF_P,* +V 9200,19100,CONT_DIF_P,* +V 9200,18700,CONT_DIF_P,* +V 9800,18300,CONT_DIF_P,* +V 9200,18300,CONT_DIF_P,* +V 9800,17900,CONT_DIF_P,* +V 9200,17900,CONT_DIF_P,* +V 9200,19500,CONT_DIF_P,* +V 9200,15500,CONT_DIF_P,* +V 9800,15500,CONT_DIF_P,* +V 10400,15100,CONT_DIF_P,* +V 11000,14700,CONT_DIF_P,* +V 10400,14700,CONT_DIF_P,* +V 11000,14300,CONT_DIF_P,* +V 10400,14300,CONT_DIF_P,* +V 9200,14300,CONT_DIF_P,* +V 9200,15100,CONT_DIF_P,* +V 9800,14700,CONT_DIF_P,* +V 9200,14700,CONT_DIF_P,* +V 9800,14300,CONT_DIF_P,* +V 10400,27400,CONT_DIF_N,* +V 10400,27000,CONT_DIF_N,* +V 10400,26600,CONT_DIF_N,* +V 10400,27800,CONT_DIF_N,* +V 10400,25000,CONT_DIF_N,* +V 10400,25400,CONT_DIF_N,* +V 10400,26200,CONT_DIF_N,* +V 10400,25800,CONT_DIF_N,* +V 9200,27000,CONT_DIF_N,* +V 9200,26600,CONT_DIF_N,* +V 9200,26200,CONT_DIF_N,* +V 9200,25800,CONT_DIF_N,* +V 9200,25400,CONT_DIF_N,* +V 9200,27800,CONT_DIF_N,* +V 9200,27400,CONT_DIF_N,* +V 9200,25000,CONT_DIF_N,* +V 9700,13600,CONT_VIA,* +V 10400,13100,CONT_POLY,* +V 10800,13600,CONT_BODY_N,* +V 9400,13600,CONT_BODY_N,* +V 10000,13600,CONT_BODY_N,* +V 8900,13600,CONT_BODY_N,* +V 9800,28700,CONT_BODY_P,* +V 11000,28700,CONT_BODY_P,* +V 9800,26100,CONT_VIA,* +V 9800,27700,CONT_VIA,* +V 9800,25700,CONT_DIF_N,* +V 9800,28100,CONT_DIF_N,* +V 9800,26500,CONT_DIF_N,* +V 9800,27300,CONT_DIF_N,* +V 9800,26900,CONT_DIF_N,* +V 9800,25300,CONT_DIF_N,* +V 9800,24900,CONT_VIA,* +V 11000,28100,CONT_VIA,* +V 11000,24900,CONT_VIA,* +V 11000,26500,CONT_VIA,* +V 11000,25300,CONT_DIF_N,* +V 11000,26900,CONT_DIF_N,* +V 11000,27300,CONT_DIF_N,* +V 11000,25700,CONT_DIF_N,* +V 11000,26100,CONT_DIF_N,* +V 11000,27700,CONT_DIF_N,* +V 11600,21900,CONT_DIF_P,* +V 12200,21900,CONT_DIF_P,* +V 12800,21900,CONT_DIF_P,* +V 13400,21900,CONT_DIF_P,* +V 12200,22500,CONT_BODY_N,* +V 13400,22500,CONT_BODY_N,* +V 13300,23200,CONT_VIA,* +V 12200,23800,CONT_VIA,* +V 13300,23800,CONT_POLY,* +V 13400,24300,CONT_BODY_P,* +V 12200,24300,CONT_BODY_P,* +V 13400,21500,CONT_DIF_P,* +V 12800,21500,CONT_DIF_P,* +V 12200,21500,CONT_DIF_P,* +V 11600,21500,CONT_DIF_P,* +V 12200,21100,CONT_VIA,* +V 13400,21100,CONT_VIA,* +V 12800,21100,CONT_DIF_P,* +V 11600,21100,CONT_DIF_P,* +V 11600,20700,CONT_DIF_P,* +V 12800,20700,CONT_DIF_P,* +V 13400,20700,CONT_DIF_P,* +V 12200,20700,CONT_DIF_P,* +V 13400,20300,CONT_DIF_P,* +V 12200,20300,CONT_DIF_P,* +V 12800,20300,CONT_DIF_P,* +V 11600,20300,CONT_DIF_P,* +V 13400,19900,CONT_VIA,* +V 12200,19900,CONT_VIA,* +V 12800,19900,CONT_DIF_P,* +V 11600,19900,CONT_DIF_P,* +V 13400,16300,CONT_VIA,* +V 13400,17500,CONT_VIA,* +V 13400,18700,CONT_VIA,* +V 12200,16300,CONT_VIA,* +V 12200,18700,CONT_VIA,* +V 12200,17500,CONT_VIA,* +V 13400,15100,CONT_VIA,* +V 12200,15100,CONT_VIA,* +V 12800,16700,CONT_DIF_P,* +V 13400,16700,CONT_DIF_P,* +V 13400,17100,CONT_DIF_P,* +V 13400,15900,CONT_DIF_P,* +V 12800,15900,CONT_DIF_P,* +V 12800,16300,CONT_DIF_P,* +V 13400,18300,CONT_DIF_P,* +V 13400,17900,CONT_DIF_P,* +V 12800,17900,CONT_DIF_P,* +V 12800,17100,CONT_DIF_P,* +V 12800,17500,CONT_DIF_P,* +V 12800,19500,CONT_DIF_P,* +V 13400,19100,CONT_DIF_P,* +V 12800,19100,CONT_DIF_P,* +V 12800,18700,CONT_DIF_P,* +V 12800,18300,CONT_DIF_P,* +V 13400,19500,CONT_DIF_P,* +V 13400,15500,CONT_DIF_P,* +V 12800,15500,CONT_DIF_P,* +V 12200,17100,CONT_DIF_P,* +V 12200,16700,CONT_DIF_P,* +V 11600,16700,CONT_DIF_P,* +V 11600,17100,CONT_DIF_P,* +V 11600,17500,CONT_DIF_P,* +V 12200,15900,CONT_DIF_P,* +V 11600,15900,CONT_DIF_P,* +V 11600,16300,CONT_DIF_P,* +V 12200,19500,CONT_DIF_P,* +V 12200,19100,CONT_DIF_P,* +V 11600,19100,CONT_DIF_P,* +V 11600,18700,CONT_DIF_P,* +V 12200,18300,CONT_DIF_P,* +V 11600,18300,CONT_DIF_P,* +V 12200,17900,CONT_DIF_P,* +V 11600,17900,CONT_DIF_P,* +V 11600,19500,CONT_DIF_P,* +V 11600,15500,CONT_DIF_P,* +V 12200,15500,CONT_DIF_P,* +V 12800,15100,CONT_DIF_P,* +V 13400,14700,CONT_DIF_P,* +V 12800,14700,CONT_DIF_P,* +V 13400,14300,CONT_DIF_P,* +V 12800,14300,CONT_DIF_P,* +V 11600,14300,CONT_DIF_P,* +V 11600,15100,CONT_DIF_P,* +V 12200,14700,CONT_DIF_P,* +V 11600,14700,CONT_DIF_P,* +V 12200,14300,CONT_DIF_P,* +V 12800,27400,CONT_DIF_N,* +V 12800,27000,CONT_DIF_N,* +V 12800,26600,CONT_DIF_N,* +V 12800,27800,CONT_DIF_N,* +V 12800,25000,CONT_DIF_N,* +V 12800,25400,CONT_DIF_N,* +V 12800,26200,CONT_DIF_N,* +V 12800,25800,CONT_DIF_N,* +V 11600,27000,CONT_DIF_N,* +V 11600,26600,CONT_DIF_N,* +V 11600,26200,CONT_DIF_N,* +V 11600,25800,CONT_DIF_N,* +V 11600,25400,CONT_DIF_N,* +V 11600,27800,CONT_DIF_N,* +V 11600,27400,CONT_DIF_N,* +V 11600,25000,CONT_DIF_N,* +V 12100,13600,CONT_VIA,* +V 12800,13100,CONT_POLY,* +V 13200,13600,CONT_BODY_N,* +V 11800,13600,CONT_BODY_N,* +V 12400,13600,CONT_BODY_N,* +V 11300,13600,CONT_BODY_N,* +V 12200,28700,CONT_BODY_P,* +V 13400,28700,CONT_BODY_P,* +V 12200,26100,CONT_VIA,* +V 12200,27700,CONT_VIA,* +V 12200,25700,CONT_DIF_N,* +V 12200,28100,CONT_DIF_N,* +V 12200,26500,CONT_DIF_N,* +V 12200,27300,CONT_DIF_N,* +V 12200,26900,CONT_DIF_N,* +V 12200,25300,CONT_DIF_N,* +V 12200,24900,CONT_VIA,* +V 13400,28100,CONT_VIA,* +V 13400,24900,CONT_VIA,* +V 13400,26500,CONT_VIA,* +V 13400,25300,CONT_DIF_N,* +V 13400,26900,CONT_DIF_N,* +V 13400,27300,CONT_DIF_N,* +V 13400,25700,CONT_DIF_N,* +V 13400,26100,CONT_DIF_N,* +V 13400,27700,CONT_DIF_N,* +V 14000,21900,CONT_DIF_P,* +V 14600,21900,CONT_DIF_P,* +V 15200,21900,CONT_DIF_P,* +V 15800,21900,CONT_DIF_P,* +V 14600,22500,CONT_BODY_N,* +V 15800,22500,CONT_BODY_N,* +V 15700,23200,CONT_VIA,* +V 14600,23800,CONT_VIA,* +V 15700,23800,CONT_POLY,* +V 15800,24300,CONT_BODY_P,* +V 14600,24300,CONT_BODY_P,* +V 15800,21500,CONT_DIF_P,* +V 15200,21500,CONT_DIF_P,* +V 14600,21500,CONT_DIF_P,* +V 14000,21500,CONT_DIF_P,* +V 14600,21100,CONT_VIA,* +V 15200,21100,CONT_DIF_P,* +V 14000,21100,CONT_DIF_P,* +V 14000,20700,CONT_DIF_P,* +V 15200,20700,CONT_DIF_P,* +V 15800,20700,CONT_DIF_P,* +V 14600,20700,CONT_DIF_P,* +V 15800,20300,CONT_DIF_P,* +V 14600,20300,CONT_DIF_P,* +V 15200,20300,CONT_DIF_P,* +V 14000,20300,CONT_DIF_P,* +V 14600,19900,CONT_VIA,* +V 15200,19900,CONT_DIF_P,* +V 14000,19900,CONT_DIF_P,* +V 14600,16300,CONT_VIA,* +V 14600,18700,CONT_VIA,* +V 14600,17500,CONT_VIA,* +V 14600,15100,CONT_VIA,* +V 15200,16700,CONT_DIF_P,* +V 15800,16700,CONT_DIF_P,* +V 15800,17100,CONT_DIF_P,* +V 15800,15900,CONT_DIF_P,* +V 15200,15900,CONT_DIF_P,* +V 15200,16300,CONT_DIF_P,* +V 15800,18300,CONT_DIF_P,* +V 15800,17900,CONT_DIF_P,* +V 15200,17900,CONT_DIF_P,* +V 15200,17100,CONT_DIF_P,* +V 15200,17500,CONT_DIF_P,* +V 15200,19500,CONT_DIF_P,* +V 15800,19100,CONT_DIF_P,* +V 15200,19100,CONT_DIF_P,* +V 15200,18700,CONT_DIF_P,* +V 15200,18300,CONT_DIF_P,* +V 15800,19500,CONT_DIF_P,* +V 15800,15500,CONT_DIF_P,* +V 15200,15500,CONT_DIF_P,* +V 14600,17100,CONT_DIF_P,* +V 14600,16700,CONT_DIF_P,* +V 14000,16700,CONT_DIF_P,* +V 14000,17100,CONT_DIF_P,* +V 14000,17500,CONT_DIF_P,* +V 14600,15900,CONT_DIF_P,* +V 14000,15900,CONT_DIF_P,* +V 14000,16300,CONT_DIF_P,* +V 14600,19500,CONT_DIF_P,* +V 14600,19100,CONT_DIF_P,* +V 14000,19100,CONT_DIF_P,* +V 14000,18700,CONT_DIF_P,* +V 14600,18300,CONT_DIF_P,* +V 14000,18300,CONT_DIF_P,* +V 14600,17900,CONT_DIF_P,* +V 14000,17900,CONT_DIF_P,* +V 14000,19500,CONT_DIF_P,* +V 14000,15500,CONT_DIF_P,* +V 14600,15500,CONT_DIF_P,* +V 15200,15100,CONT_DIF_P,* +V 15800,14700,CONT_DIF_P,* +V 15200,14700,CONT_DIF_P,* +V 15800,14300,CONT_DIF_P,* +V 15200,14300,CONT_DIF_P,* +V 14000,14300,CONT_DIF_P,* +V 14000,15100,CONT_DIF_P,* +V 14600,14700,CONT_DIF_P,* +V 14000,14700,CONT_DIF_P,* +V 14600,14300,CONT_DIF_P,* +V 15200,27400,CONT_DIF_N,* +V 15200,27000,CONT_DIF_N,* +V 15200,26600,CONT_DIF_N,* +V 15200,27800,CONT_DIF_N,* +V 15200,25000,CONT_DIF_N,* +V 15200,25400,CONT_DIF_N,* +V 15200,26200,CONT_DIF_N,* +V 15200,25800,CONT_DIF_N,* +V 14000,27000,CONT_DIF_N,* +V 14000,26600,CONT_DIF_N,* +V 14000,26200,CONT_DIF_N,* +V 14000,25800,CONT_DIF_N,* +V 14000,25400,CONT_DIF_N,* +V 14000,27800,CONT_DIF_N,* +V 14000,27400,CONT_DIF_N,* +V 14000,25000,CONT_DIF_N,* +V 14500,13600,CONT_VIA,* +V 15200,13100,CONT_POLY,* +V 15600,13600,CONT_BODY_N,* +V 14200,13600,CONT_BODY_N,* +V 14800,13600,CONT_BODY_N,* +V 13700,13600,CONT_BODY_N,* +V 14600,28700,CONT_BODY_P,* +V 15800,28700,CONT_BODY_P,* +V 14600,26100,CONT_VIA,* +V 14600,27700,CONT_VIA,* +V 14600,25700,CONT_DIF_N,* +V 14600,28100,CONT_DIF_N,* +V 14600,26500,CONT_DIF_N,* +V 14600,27300,CONT_DIF_N,* +V 14600,26900,CONT_DIF_N,* +V 14600,25300,CONT_DIF_N,* +V 14600,24900,CONT_VIA,* +V 15800,28100,CONT_VIA,* +V 15800,24900,CONT_VIA,* +V 15800,26500,CONT_VIA,* +V 15800,25300,CONT_DIF_N,* +V 15800,26900,CONT_DIF_N,* +V 15800,27300,CONT_DIF_N,* +V 15800,25700,CONT_DIF_N,* +V 15800,26100,CONT_DIF_N,* +V 15800,27700,CONT_DIF_N,* +V 16400,29200,CONT_VIA,* +V 15800,29200,CONT_VIA,* +V 16400,25900,CONT_VIA,* +V 16100,24300,CONT_VIA,* +V 16400,27900,CONT_VIA,* +V 3700,23200,CONT_VIA,* +V 2000,5800,CONT_VIA,* +V 16400,3600,CONT_VIA,* +V 16400,2400,CONT_VIA,* +V 15200,3500,CONT_VIA,* +V 14000,1600,CONT_VIA,* +V 12800,1600,CONT_VIA,* +V 11600,1600,CONT_VIA,* +V 16400,7500,CONT_VIA,* +V 16400,6700,CONT_VIA,* +V 2000,3200,CONT_VIA,* +V 2000,2300,CONT_VIA,* +V 3200,9000,CONT_VIA,* +V 3200,7400,CONT_VIA,* +V 3200,6600,CONT_VIA,* +V 3200,2300,CONT_VIA,* +V 3200,3500,CONT_VIA,* +V 3200,10200,CONT_VIA,* +V 6800,1600,CONT_VIA,* +V 4400,2300,CONT_VIA,* +V 4400,6600,CONT_VIA,* +V 4400,7400,CONT_VIA,* +V 4400,9000,CONT_VIA,* +V 4400,10200,CONT_VIA,* +V 4400,3500,CONT_VIA,* +V 9800,6600,CONT_VIA,* +V 9800,10200,CONT_VIA,* +V 6200,9000,CONT_VIA,* +V 8000,1600,CONT_VIA,* +V 9800,9000,CONT_VIA,* +V 9800,7400,CONT_VIA,* +V 9800,2300,CONT_VIA,* +V 11000,7400,CONT_VIA,* +V 11000,9000,CONT_VIA,* +V 11000,10200,CONT_VIA,* +V 7400,6600,CONT_VIA,* +V 11000,6600,CONT_VIA,* +V 11000,2300,CONT_VIA,* +V 7400,7400,CONT_VIA,* +V 7400,2300,CONT_VIA,* +V 6200,2300,CONT_VIA,* +V 6200,3500,CONT_VIA,* +V 6200,10200,CONT_VIA,* +V 8600,3500,CONT_VIA,* +V 6200,7400,CONT_VIA,* +V 6200,6600,CONT_VIA,* +V 8600,7400,CONT_VIA,* +V 8600,9000,CONT_VIA,* +V 8600,10200,CONT_VIA,* +V 8600,6600,CONT_VIA,* +V 8600,2300,CONT_VIA,* +V 7400,10200,CONT_VIA,* +V 7400,9000,CONT_VIA,* +V 9200,1600,CONT_VIA,* +V 10400,1600,CONT_VIA,* +V 2000,9900,CONT_VIA,* +V 800,9800,CONT_VIA,* +V 800,6600,CONT_VIA,* +V 800,2300,CONT_VIA,* +V 800,3500,CONT_VIA,* +V 15700,-700,CONT_VIA,* +V 3800,-700,CONT_VIA,* +V 4900,-700,CONT_VIA,* +V 9800,4600,CONT_POLY,* +V 15100,4500,CONT_POLY,* +V 11100,4000,CONT_POLY,* +V 1800,9400,CONT_POLY,* +V 15700,2300,CONT_POLY,* +V 14500,3800,CONT_POLY,* +V 5100,5300,CONT_POLY,* +V 2700,8900,CONT_POLY,* +V 3300,4500,CONT_POLY,* +V 4900,300,CONT_POLY,* +V 7400,4600,CONT_POLY,* +V 16400,28300,CONT_BODY_P,* +V 16400,28700,CONT_BODY_P,* +V 16400,24300,CONT_BODY_P,* +V 16400,25500,CONT_BODY_P,* +V 16400,25100,CONT_BODY_P,* +V 16400,24700,CONT_BODY_P,* +V 16400,26300,CONT_BODY_P,* +V 16400,26700,CONT_BODY_P,* +V 16400,27100,CONT_BODY_P,* +V 16400,27500,CONT_BODY_P,* +V 1200,28700,CONT_BODY_P,* +V 1200,24300,CONT_BODY_P,* +V 800,28300,CONT_BODY_P,* +V 800,24300,CONT_BODY_P,* +V 800,25500,CONT_BODY_P,* +V 800,25100,CONT_BODY_P,* +V 800,24700,CONT_BODY_P,* +V 800,28700,CONT_BODY_P,* +V 800,25900,CONT_BODY_P,* +V 800,26300,CONT_BODY_P,* +V 800,26700,CONT_BODY_P,* +V 800,27100,CONT_BODY_P,* +V 800,27500,CONT_BODY_P,* +V 800,27900,CONT_BODY_P,* +V 16400,2800,CONT_BODY_P,* +V 16400,3200,CONT_BODY_P,* +V 15200,4000,CONT_BODY_P,* +V 16400,4000,CONT_BODY_P,* +V 16400,4000,CONT_BODY_P,* +V 2000,4000,CONT_BODY_P,* +V 7800,4000,CONT_BODY_P,* +V 9000,4000,CONT_BODY_P,* +V 8200,4000,CONT_BODY_P,* +V 7000,4000,CONT_BODY_P,* +V 6600,4000,CONT_BODY_P,* +V 4400,4000,CONT_BODY_P,* +V 3200,4000,CONT_BODY_P,* +V 15200,1800,CONT_BODY_P,* +V 9400,4000,CONT_BODY_P,* +V 9900,4000,CONT_BODY_P,* +V 10300,4000,CONT_BODY_P,* +V 6200,4000,CONT_BODY_P,* +V 8600,4000,CONT_BODY_P,* +V 14700,200,CONT_BODY_P,* +V 15200,600,CONT_BODY_P,* +V 14700,600,CONT_BODY_P,* +V 15200,1000,CONT_BODY_P,* +V 14700,1000,CONT_BODY_P,* +V 15200,1400,CONT_BODY_P,* +V 14700,1400,CONT_BODY_P,* +V 14700,1800,CONT_BODY_P,* +V 15200,200,CONT_BODY_P,* +V 800,700,CONT_BODY_P,* +V 800,1100,CONT_BODY_P,* +V 800,1500,CONT_BODY_P,* +V 800,1900,CONT_BODY_P,* +V 800,2700,CONT_BODY_P,* +V 800,3100,CONT_BODY_P,* +V 800,4000,CONT_BODY_P,* +V 800,300,CONT_BODY_P,* +V 2800,-200,CONT_BODY_P,* +V 2400,-200,CONT_BODY_P,* +V 1600,-200,CONT_BODY_P,* +V 15200,-200,CONT_BODY_P,* +V 11600,-200,CONT_BODY_P,* +V 5400,-200,CONT_BODY_P,* +V 5800,-200,CONT_BODY_P,* +V 6600,-200,CONT_BODY_P,* +V 7000,-200,CONT_BODY_P,* +V 7800,-200,CONT_BODY_P,* +V 8200,-200,CONT_BODY_P,* +V 9400,-200,CONT_BODY_P,* +V 9000,-200,CONT_BODY_P,* +V 10200,-200,CONT_BODY_P,* +V 10600,-200,CONT_BODY_P,* +V 14000,-200,CONT_BODY_P,* +V 13600,-200,CONT_BODY_P,* +V 14400,-200,CONT_BODY_P,* +V 14800,-200,CONT_BODY_P,* +V 12800,-200,CONT_BODY_P,* +V 13200,-200,CONT_BODY_P,* +V 1200,-200,CONT_BODY_P,* +V 12400,-200,CONT_BODY_P,* +V 12000,-200,CONT_BODY_P,* +V 8600,-200,CONT_BODY_P,* +V 11000,-200,CONT_BODY_P,* +V 9800,-200,CONT_BODY_P,* +V 4400,-200,CONT_BODY_P,* +V 3200,-200,CONT_BODY_P,* +V 2000,-200,CONT_BODY_P,* +V 6200,-200,CONT_BODY_P,* +V 7400,-200,CONT_BODY_P,* +V 800,-200,CONT_BODY_P,* +V 1400,22500,CONT_BODY_N,* +V 16400,22000,CONT_BODY_N,* +V 16400,22500,CONT_BODY_N,* +V 16400,20400,CONT_BODY_N,* +V 16400,20800,CONT_BODY_N,* +V 16400,20000,CONT_BODY_N,* +V 16400,21200,CONT_BODY_N,* +V 16400,21600,CONT_BODY_N,* +V 800,21200,CONT_BODY_N,* +V 800,20800,CONT_BODY_N,* +V 800,20400,CONT_BODY_N,* +V 800,20000,CONT_BODY_N,* +V 800,22500,CONT_BODY_N,* +V 800,22000,CONT_BODY_N,* +V 800,21600,CONT_BODY_N,* +V 16400,10400,CONT_BODY_N,* +V 16400,5100,CONT_BODY_N,* +V 15200,5100,CONT_BODY_N,* +V 11000,12000,CONT_BODY_N,* +V 2100,12000,CONT_BODY_N,* +V 16400,7100,CONT_BODY_N,* +V 16400,11200,CONT_BODY_N,* +V 16400,6300,CONT_BODY_N,* +V 16400,5900,CONT_BODY_N,* +V 16400,12000,CONT_BODY_N,* +V 16400,9500,CONT_BODY_N,* +V 16400,11600,CONT_BODY_N,* +V 16400,7900,CONT_BODY_N,* +V 8200,5100,CONT_BODY_N,* +V 7800,5100,CONT_BODY_N,* +V 10200,5100,CONT_BODY_N,* +V 10600,5100,CONT_BODY_N,* +V 16400,5500,CONT_BODY_N,* +V 16400,9100,CONT_BODY_N,* +V 16400,8300,CONT_BODY_N,* +V 16400,10800,CONT_BODY_N,* +V 4000,12000,CONT_BODY_N,* +V 3600,12000,CONT_BODY_N,* +V 8600,12000,CONT_BODY_N,* +V 9800,12000,CONT_BODY_N,* +V 5800,12000,CONT_BODY_N,* +V 5300,12000,CONT_BODY_N,* +V 4400,12000,CONT_BODY_N,* +V 7000,5100,CONT_BODY_N,* +V 6600,5100,CONT_BODY_N,* +V 7400,12000,CONT_BODY_N,* +V 11000,5100,CONT_BODY_N,* +V 9400,5100,CONT_BODY_N,* +V 9000,5100,CONT_BODY_N,* +V 4400,5100,CONT_BODY_N,* +V 4800,12000,CONT_BODY_N,* +V 3200,5100,CONT_BODY_N,* +V 6300,12000,CONT_BODY_N,* +V 6200,5100,CONT_BODY_N,* +V 8600,5100,CONT_BODY_N,* +V 1200,12000,CONT_BODY_N,* +V 1700,12000,CONT_BODY_N,* +V 3200,12000,CONT_BODY_N,* +V 16000,13600,CONT_BODY_N,* +V 1300,13600,CONT_BODY_N,* +V 16400,14400,CONT_BODY_N,* +V 16400,14800,CONT_BODY_N,* +V 16400,15200,CONT_BODY_N,* +V 16400,13600,CONT_BODY_N,* +V 16400,15600,CONT_BODY_N,* +V 16400,17200,CONT_BODY_N,* +V 16400,16800,CONT_BODY_N,* +V 16400,16000,CONT_BODY_N,* +V 16400,18400,CONT_BODY_N,* +V 16400,18800,CONT_BODY_N,* +V 16400,19200,CONT_BODY_N,* +V 16400,19600,CONT_BODY_N,* +V 16400,17600,CONT_BODY_N,* +V 16400,18000,CONT_BODY_N,* +V 16400,16400,CONT_BODY_N,* +V 16400,14000,CONT_BODY_N,* +V 2000,5100,CONT_BODY_N,* +V 1400,5100,CONT_BODY_N,* +V 1400,5500,CONT_BODY_N,* +V 1400,5900,CONT_BODY_N,* +V 1400,6300,CONT_BODY_N,* +V 2000,10300,CONT_BODY_N,* +V 2000,10700,CONT_BODY_N,* +V 11700,5100,CONT_BODY_N,* +V 16000,11600,CONT_BODY_N,* +V 16000,10400,CONT_BODY_N,* +V 16000,8300,CONT_BODY_N,* +V 16000,10800,CONT_BODY_N,* +V 16000,11200,CONT_BODY_N,* +V 16000,12000,CONT_BODY_N,* +V 16000,9500,CONT_BODY_N,* +V 16000,9100,CONT_BODY_N,* +V 15600,11200,CONT_BODY_N,* +V 15600,10800,CONT_BODY_N,* +V 15600,8300,CONT_BODY_N,* +V 15600,10400,CONT_BODY_N,* +V 15600,11600,CONT_BODY_N,* +V 15600,9100,CONT_BODY_N,* +V 15600,9500,CONT_BODY_N,* +V 15600,12000,CONT_BODY_N,* +V 15200,9100,CONT_BODY_N,* +V 15200,11600,CONT_BODY_N,* +V 15200,10400,CONT_BODY_N,* +V 15200,8300,CONT_BODY_N,* +V 15200,10800,CONT_BODY_N,* +V 15200,11200,CONT_BODY_N,* +V 15200,12000,CONT_BODY_N,* +V 15200,9500,CONT_BODY_N,* +V 14800,12000,CONT_BODY_N,* +V 14800,11200,CONT_BODY_N,* +V 14800,10800,CONT_BODY_N,* +V 14800,8300,CONT_BODY_N,* +V 14800,10400,CONT_BODY_N,* +V 14800,11600,CONT_BODY_N,* +V 14800,9100,CONT_BODY_N,* +V 14800,9500,CONT_BODY_N,* +V 800,10800,CONT_BODY_N,* +V 800,10400,CONT_BODY_N,* +V 800,5100,CONT_BODY_N,* +V 800,7400,CONT_BODY_N,* +V 800,7800,CONT_BODY_N,* +V 800,8200,CONT_BODY_N,* +V 800,8600,CONT_BODY_N,* +V 800,9000,CONT_BODY_N,* +V 800,12000,CONT_BODY_N,* +V 800,11600,CONT_BODY_N,* +V 800,11200,CONT_BODY_N,* +V 800,19600,CONT_BODY_N,* +V 800,19200,CONT_BODY_N,* +V 800,18800,CONT_BODY_N,* +V 800,9400,CONT_BODY_N,* +V 800,5500,CONT_BODY_N,* +V 800,5900,CONT_BODY_N,* +V 800,6300,CONT_BODY_N,* +V 800,7000,CONT_BODY_N,* +V 800,13600,CONT_BODY_N,* +V 800,16800,CONT_BODY_N,* +V 800,17200,CONT_BODY_N,* +V 800,16400,CONT_BODY_N,* +V 800,16000,CONT_BODY_N,* +V 800,18000,CONT_BODY_N,* +V 800,17600,CONT_BODY_N,* +V 800,18400,CONT_BODY_N,* +V 800,15600,CONT_BODY_N,* +V 800,15200,CONT_BODY_N,* +V 800,14800,CONT_BODY_N,* +V 800,14400,CONT_BODY_N,* +V 800,14000,CONT_BODY_N,* +V 1400,20300,CONT_DIF_P,* +V 1400,20700,CONT_DIF_P,* +V 1400,21100,CONT_DIF_P,* +V 1400,21500,CONT_DIF_P,* +V 1400,21900,CONT_DIF_P,* +V 12200,6600,CONT_DIF_P,* +V 13400,6600,CONT_DIF_P,* +V 14000,5800,CONT_DIF_P,* +V 1400,6900,CONT_DIF_P,* +V 1400,11300,CONT_DIF_P,* +V 15200,7500,CONT_DIF_P,* +V 15800,7500,CONT_DIF_P,* +V 14600,7500,CONT_DIF_P,* +V 14000,8200,CONT_DIF_P,* +V 13400,10200,CONT_DIF_P,* +V 12200,10200,CONT_DIF_P,* +V 12200,9000,CONT_DIF_P,* +V 13400,9000,CONT_DIF_P,* +V 12200,7400,CONT_DIF_P,* +V 13400,7400,CONT_DIF_P,* +V 14000,7400,CONT_DIF_P,* +V 14000,6200,CONT_DIF_P,* +V 14000,9400,CONT_DIF_P,* +V 14000,9800,CONT_DIF_P,* +V 14000,6600,CONT_DIF_P,* +V 14000,7000,CONT_DIF_P,* +V 14000,10600,CONT_DIF_P,* +V 14000,11000,CONT_DIF_P,* +V 12800,11000,CONT_DIF_P,* +V 12800,7800,CONT_DIF_P,* +V 12800,8200,CONT_DIF_P,* +V 14000,10200,CONT_DIF_P,* +V 14000,7800,CONT_DIF_P,* +V 14000,9000,CONT_DIF_P,* +V 14000,8600,CONT_DIF_P,* +V 14000,11400,CONT_DIF_P,* +V 12800,11400,CONT_DIF_P,* +V 13400,7800,CONT_DIF_P,* +V 13400,8200,CONT_DIF_P,* +V 13400,11400,CONT_DIF_P,* +V 12800,8600,CONT_DIF_P,* +V 11600,10600,CONT_DIF_P,* +V 12800,9400,CONT_DIF_P,* +V 12800,9800,CONT_DIF_P,* +V 12800,10600,CONT_DIF_P,* +V 13400,6200,CONT_DIF_P,* +V 13400,5800,CONT_DIF_P,* +V 13400,7000,CONT_DIF_P,* +V 12800,10200,CONT_DIF_P,* +V 11600,9400,CONT_DIF_P,* +V 12800,9000,CONT_DIF_P,* +V 13400,10600,CONT_DIF_P,* +V 13400,11000,CONT_DIF_P,* +V 11600,8600,CONT_DIF_P,* +V 11600,8200,CONT_DIF_P,* +V 11600,5800,CONT_DIF_P,* +V 11600,11000,CONT_DIF_P,* +V 12200,11000,CONT_DIF_P,* +V 13400,9800,CONT_DIF_P,* +V 13400,9400,CONT_DIF_P,* +V 13400,8600,CONT_DIF_P,* +V 11600,10200,CONT_DIF_P,* +V 11600,7000,CONT_DIF_P,* +V 11600,6600,CONT_DIF_P,* +V 11600,9800,CONT_DIF_P,* +V 12200,9800,CONT_DIF_P,* +V 11600,6200,CONT_DIF_P,* +V 11600,7400,CONT_DIF_P,* +V 11600,11400,CONT_DIF_P,* +V 12200,6200,CONT_DIF_P,* +V 12200,8600,CONT_DIF_P,* +V 12200,11400,CONT_DIF_P,* +V 12200,8200,CONT_DIF_P,* +V 12200,7800,CONT_DIF_P,* +V 12200,10600,CONT_DIF_P,* +V 11600,9000,CONT_DIF_P,* +V 11600,7800,CONT_DIF_P,* +V 2600,6600,CONT_DIF_P,* +V 2600,6200,CONT_DIF_P,* +V 2600,7400,CONT_DIF_P,* +V 2600,7000,CONT_DIF_P,* +V 3200,9400,CONT_DIF_P,* +V 12200,9400,CONT_DIF_P,* +V 12200,7000,CONT_DIF_P,* +V 12200,5800,CONT_DIF_P,* +V 3200,8200,CONT_DIF_P,* +V 3200,7800,CONT_DIF_P,* +V 3200,11000,CONT_DIF_P,* +V 3200,9800,CONT_DIF_P,* +V 3800,5800,CONT_DIF_P,* +V 2600,5800,CONT_DIF_P,* +V 2600,8200,CONT_DIF_P,* +V 2600,7800,CONT_DIF_P,* +V 3800,9800,CONT_DIF_P,* +V 3200,5800,CONT_DIF_P,* +V 3200,7000,CONT_DIF_P,* +V 3200,6200,CONT_DIF_P,* +V 3800,8600,CONT_DIF_P,* +V 3200,10600,CONT_DIF_P,* +V 3200,8600,CONT_DIF_P,* +V 3200,11400,CONT_DIF_P,* +V 3800,10600,CONT_DIF_P,* +V 3800,6600,CONT_DIF_P,* +V 3800,11000,CONT_DIF_P,* +V 3800,8200,CONT_DIF_P,* +V 4400,7800,CONT_DIF_P,* +V 3800,10200,CONT_DIF_P,* +V 3800,7000,CONT_DIF_P,* +V 3800,9400,CONT_DIF_P,* +V 4400,8600,CONT_DIF_P,* +V 4400,10600,CONT_DIF_P,* +V 4400,9400,CONT_DIF_P,* +V 3800,7800,CONT_DIF_P,* +V 3800,9000,CONT_DIF_P,* +V 3800,11400,CONT_DIF_P,* +V 3800,7400,CONT_DIF_P,* +V 3800,6200,CONT_DIF_P,* +V 5000,9400,CONT_DIF_P,* +V 4400,6200,CONT_DIF_P,* +V 4400,7000,CONT_DIF_P,* +V 4400,5800,CONT_DIF_P,* +V 4400,9800,CONT_DIF_P,* +V 4400,11000,CONT_DIF_P,* +V 4400,8200,CONT_DIF_P,* +V 4400,11400,CONT_DIF_P,* +V 10400,11000,CONT_DIF_P,* +V 5000,5800,CONT_DIF_P,* +V 5000,8200,CONT_DIF_P,* +V 5000,11000,CONT_DIF_P,* +V 5000,6600,CONT_DIF_P,* +V 5000,10600,CONT_DIF_P,* +V 5000,9800,CONT_DIF_P,* +V 5000,10200,CONT_DIF_P,* +V 10400,8200,CONT_DIF_P,* +V 5000,6200,CONT_DIF_P,* +V 5000,7400,CONT_DIF_P,* +V 5000,11400,CONT_DIF_P,* +V 5000,8600,CONT_DIF_P,* +V 5000,9000,CONT_DIF_P,* +V 5000,7800,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 10400,9800,CONT_DIF_P,* +V 10400,9400,CONT_DIF_P,* +V 10400,6200,CONT_DIF_P,* +V 10400,7400,CONT_DIF_P,* +V 10400,11400,CONT_DIF_P,* +V 10400,8600,CONT_DIF_P,* +V 9200,8600,CONT_DIF_P,* +V 10400,7000,CONT_DIF_P,* +V 9200,5800,CONT_DIF_P,* +V 9200,11000,CONT_DIF_P,* +V 9200,10600,CONT_DIF_P,* +V 10400,9000,CONT_DIF_P,* +V 10400,7800,CONT_DIF_P,* +V 10400,10200,CONT_DIF_P,* +V 9200,10200,CONT_DIF_P,* +V 10400,10600,CONT_DIF_P,* +V 9200,6600,CONT_DIF_P,* +V 9200,9800,CONT_DIF_P,* +V 9200,9400,CONT_DIF_P,* +V 9200,6200,CONT_DIF_P,* +V 9200,7400,CONT_DIF_P,* +V 9200,11400,CONT_DIF_P,* +V 11000,5800,CONT_DIF_P,* +V 10400,5800,CONT_DIF_P,* +V 11000,9800,CONT_DIF_P,* +V 11000,10600,CONT_DIF_P,* +V 11000,11000,CONT_DIF_P,* +V 11000,7800,CONT_DIF_P,* +V 9200,9000,CONT_DIF_P,* +V 9200,7800,CONT_DIF_P,* +V 9800,7800,CONT_DIF_P,* +V 10400,6600,CONT_DIF_P,* +V 9800,10600,CONT_DIF_P,* +V 11000,9400,CONT_DIF_P,* +V 11000,8200,CONT_DIF_P,* +V 11000,11400,CONT_DIF_P,* +V 11000,8600,CONT_DIF_P,* +V 11000,6200,CONT_DIF_P,* +V 9800,9800,CONT_DIF_P,* +V 9200,8200,CONT_DIF_P,* +V 9800,7000,CONT_DIF_P,* +V 9800,5800,CONT_DIF_P,* +V 9800,6200,CONT_DIF_P,* +V 9800,8600,CONT_DIF_P,* +V 9800,11400,CONT_DIF_P,* +V 9800,8200,CONT_DIF_P,* +V 5600,6200,CONT_DIF_P,* +V 9200,7000,CONT_DIF_P,* +V 5600,11400,CONT_DIF_P,* +V 5600,8600,CONT_DIF_P,* +V 5600,8200,CONT_DIF_P,* +V 5600,5800,CONT_DIF_P,* +V 9800,11000,CONT_DIF_P,* +V 9800,9400,CONT_DIF_P,* +V 5600,9000,CONT_DIF_P,* +V 11000,7000,CONT_DIF_P,* +V 5600,7800,CONT_DIF_P,* +V 5600,7000,CONT_DIF_P,* +V 5600,6600,CONT_DIF_P,* +V 5600,9800,CONT_DIF_P,* +V 5600,9400,CONT_DIF_P,* +V 5600,10600,CONT_DIF_P,* +V 6200,8600,CONT_DIF_P,* +V 5600,7400,CONT_DIF_P,* +V 6200,8200,CONT_DIF_P,* +V 6200,7800,CONT_DIF_P,* +V 6200,11000,CONT_DIF_P,* +V 6200,9800,CONT_DIF_P,* +V 6200,9400,CONT_DIF_P,* +V 5600,11000,CONT_DIF_P,* +V 6200,7000,CONT_DIF_P,* +V 5600,10200,CONT_DIF_P,* +V 7400,9400,CONT_DIF_P,* +V 7400,9800,CONT_DIF_P,* +V 7400,7000,CONT_DIF_P,* +V 7400,5800,CONT_DIF_P,* +V 7400,6200,CONT_DIF_P,* +V 6200,10600,CONT_DIF_P,* +V 7400,11400,CONT_DIF_P,* +V 6200,11400,CONT_DIF_P,* +V 7400,7800,CONT_DIF_P,* +V 7400,11000,CONT_DIF_P,* +V 7400,10600,CONT_DIF_P,* +V 8600,9400,CONT_DIF_P,* +V 8600,8200,CONT_DIF_P,* +V 6200,5800,CONT_DIF_P,* +V 8600,8600,CONT_DIF_P,* +V 6200,6200,CONT_DIF_P,* +V 8600,5800,CONT_DIF_P,* +V 8600,7000,CONT_DIF_P,* +V 8600,9800,CONT_DIF_P,* +V 8600,10600,CONT_DIF_P,* +V 8600,11000,CONT_DIF_P,* +V 7400,8600,CONT_DIF_P,* +V 6800,9000,CONT_DIF_P,* +V 7400,8200,CONT_DIF_P,* +V 6800,10200,CONT_DIF_P,* +V 6800,7000,CONT_DIF_P,* +V 6800,6600,CONT_DIF_P,* +V 6800,9800,CONT_DIF_P,* +V 6800,9400,CONT_DIF_P,* +V 8600,11400,CONT_DIF_P,* +V 6800,7400,CONT_DIF_P,* +V 8600,6200,CONT_DIF_P,* +V 6800,8600,CONT_DIF_P,* +V 6800,8200,CONT_DIF_P,* +V 6800,5800,CONT_DIF_P,* +V 6800,11000,CONT_DIF_P,* +V 6800,10600,CONT_DIF_P,* +V 8600,7800,CONT_DIF_P,* +V 8000,7800,CONT_DIF_P,* +V 6800,7800,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6600,CONT_DIF_P,* +V 8000,9800,CONT_DIF_P,* +V 8000,9400,CONT_DIF_P,* +V 8000,6200,CONT_DIF_P,* +V 6800,6200,CONT_DIF_P,* +V 8000,7400,CONT_DIF_P,* +V 6800,11400,CONT_DIF_P,* +V 8000,11400,CONT_DIF_P,* +V 8000,8600,CONT_DIF_P,* +V 8000,8200,CONT_DIF_P,* +V 8000,5800,CONT_DIF_P,* +V 8000,11000,CONT_DIF_P,* +V 8000,10600,CONT_DIF_P,* +V 8000,9000,CONT_DIF_P,* +V 8000,10200,CONT_DIF_P,* +V 1400,14300,CONT_DIF_P,* +V 1400,19900,CONT_DIF_P,* +V 1400,19500,CONT_DIF_P,* +V 1400,19100,CONT_DIF_P,* +V 1400,18700,CONT_DIF_P,* +V 1400,18300,CONT_DIF_P,* +V 1400,17500,CONT_DIF_P,* +V 1400,17900,CONT_DIF_P,* +V 12800,5800,CONT_DIF_P,* +V 1400,17100,CONT_DIF_P,* +V 1400,16700,CONT_DIF_P,* +V 1400,16300,CONT_DIF_P,* +V 1400,15900,CONT_DIF_P,* +V 1400,15500,CONT_DIF_P,* +V 1400,15100,CONT_DIF_P,* +V 1400,14700,CONT_DIF_P,* +V 14600,5800,CONT_DIF_P,* +V 15800,6600,CONT_DIF_P,* +V 15800,5800,CONT_DIF_P,* +V 15800,6200,CONT_DIF_P,* +V 12800,6600,CONT_DIF_P,* +V 12800,7000,CONT_DIF_P,* +V 12800,6200,CONT_DIF_P,* +V 12800,7400,CONT_DIF_P,* +V 15800,7000,CONT_DIF_P,* +V 15200,6200,CONT_DIF_P,* +V 15200,5800,CONT_DIF_P,* +V 15200,6600,CONT_DIF_P,* +V 15200,7000,CONT_DIF_P,* +V 14600,7000,CONT_DIF_P,* +V 14600,6600,CONT_DIF_P,* +V 14600,6200,CONT_DIF_P,* +V 1400,27300,CONT_DIF_N,* +V 1400,26100,CONT_DIF_N,* +V 1400,24900,CONT_DIF_N,* +V 1400,25300,CONT_DIF_N,* +V 1400,25700,CONT_DIF_N,* +V 1400,26500,CONT_DIF_N,* +V 1400,26900,CONT_DIF_N,* +V 1400,27700,CONT_DIF_N,* +V 1400,28100,CONT_DIF_N,* +V 13400,2300,CONT_DIF_N,* +V 12200,2300,CONT_DIF_N,* +V 14600,3300,CONT_DIF_N,* +V 15200,2700,CONT_DIF_N,* +V 15200,3100,CONT_DIF_N,* +V 13400,1900,CONT_DIF_N,* +V 13400,700,CONT_DIF_N,* +V 13400,1100,CONT_DIF_N,* +V 14000,2500,CONT_DIF_N,* +V 13400,2800,CONT_DIF_N,* +V 12800,700,CONT_DIF_N,* +V 12800,2500,CONT_DIF_N,* +V 12800,2100,CONT_DIF_N,* +V 11600,2500,CONT_DIF_N,* +V 11600,1200,CONT_DIF_N,* +V 12200,2800,CONT_DIF_N,* +V 13400,1500,CONT_DIF_N,* +V 14000,2900,CONT_DIF_N,* +V 12800,3300,CONT_DIF_N,* +V 12800,2900,CONT_DIF_N,* +V 13400,3300,CONT_DIF_N,* +V 14000,3300,CONT_DIF_N,* +V 12200,1100,CONT_DIF_N,* +V 12200,700,CONT_DIF_N,* +V 12200,1900,CONT_DIF_N,* +V 12200,3300,CONT_DIF_N,* +V 11600,2900,CONT_DIF_N,* +V 11600,3300,CONT_DIF_N,* +V 11600,2100,CONT_DIF_N,* +V 1400,900,CONT_DIF_N,* +V 1400,2500,CONT_DIF_N,* +V 14000,700,CONT_DIF_N,* +V 14000,1200,CONT_DIF_N,* +V 12800,1200,CONT_DIF_N,* +V 11600,700,CONT_DIF_N,* +V 14000,2100,CONT_DIF_N,* +V 12200,1500,CONT_DIF_N,* +V 2000,1100,CONT_DIF_N,* +V 2000,700,CONT_DIF_N,* +V 2600,1300,CONT_DIF_N,* +V 2600,900,CONT_DIF_N,* +V 6800,700,CONT_DIF_N,* +V 6800,1200,CONT_DIF_N,* +V 2600,1700,CONT_DIF_N,* +V 1400,1300,CONT_DIF_N,* +V 3200,1900,CONT_DIF_N,* +V 3200,2700,CONT_DIF_N,* +V 3200,3100,CONT_DIF_N,* +V 3200,700,CONT_DIF_N,* +V 1400,2100,CONT_DIF_N,* +V 1400,2900,CONT_DIF_N,* +V 1400,3300,CONT_DIF_N,* +V 1400,1700,CONT_DIF_N,* +V 3800,900,CONT_DIF_N,* +V 3800,1300,CONT_DIF_N,* +V 3800,1700,CONT_DIF_N,* +V 3800,3300,CONT_DIF_N,* +V 2600,2500,CONT_DIF_N,* +V 2600,2100,CONT_DIF_N,* +V 2600,2900,CONT_DIF_N,* +V 2600,3300,CONT_DIF_N,* +V 4400,700,CONT_DIF_N,* +V 4400,3100,CONT_DIF_N,* +V 4400,2700,CONT_DIF_N,* +V 4400,1900,CONT_DIF_N,* +V 2000,2700,CONT_DIF_N,* +V 2000,1900,CONT_DIF_N,* +V 2000,1500,CONT_DIF_N,* +V 3800,2500,CONT_DIF_N,* +V 5000,1700,CONT_DIF_N,* +V 4400,1500,CONT_DIF_N,* +V 4400,1100,CONT_DIF_N,* +V 3800,2100,CONT_DIF_N,* +V 3800,2900,CONT_DIF_N,* +V 3200,1100,CONT_DIF_N,* +V 3200,1500,CONT_DIF_N,* +V 8000,1200,CONT_DIF_N,* +V 10400,2500,CONT_DIF_N,* +V 10400,1200,CONT_DIF_N,* +V 5000,1300,CONT_DIF_N,* +V 5000,900,CONT_DIF_N,* +V 5000,2500,CONT_DIF_N,* +V 5000,2100,CONT_DIF_N,* +V 5000,2900,CONT_DIF_N,* +V 5000,3300,CONT_DIF_N,* +V 9800,3300,CONT_DIF_N,* +V 11000,1500,CONT_DIF_N,* +V 9200,2900,CONT_DIF_N,* +V 9200,3300,CONT_DIF_N,* +V 9200,2100,CONT_DIF_N,* +V 9800,2800,CONT_DIF_N,* +V 10400,3300,CONT_DIF_N,* +V 10400,2100,CONT_DIF_N,* +V 9200,1200,CONT_DIF_N,* +V 10400,2900,CONT_DIF_N,* +V 9800,1100,CONT_DIF_N,* +V 9800,700,CONT_DIF_N,* +V 9800,1900,CONT_DIF_N,* +V 11000,1900,CONT_DIF_N,* +V 10400,700,CONT_DIF_N,* +V 9200,700,CONT_DIF_N,* +V 11000,700,CONT_DIF_N,* +V 5600,2100,CONT_DIF_N,* +V 5600,1700,CONT_DIF_N,* +V 5600,1300,CONT_DIF_N,* +V 5600,900,CONT_DIF_N,* +V 5600,2900,CONT_DIF_N,* +V 9200,2500,CONT_DIF_N,* +V 8000,700,CONT_DIF_N,* +V 9800,1500,CONT_DIF_N,* +V 6200,1100,CONT_DIF_N,* +V 6200,1500,CONT_DIF_N,* +V 6200,1900,CONT_DIF_N,* +V 6200,2700,CONT_DIF_N,* +V 6200,3100,CONT_DIF_N,* +V 11000,2700,CONT_DIF_N,* +V 11000,3100,CONT_DIF_N,* +V 5600,2500,CONT_DIF_N,* +V 7400,1900,CONT_DIF_N,* +V 8600,1900,CONT_DIF_N,* +V 8600,2700,CONT_DIF_N,* +V 8600,3100,CONT_DIF_N,* +V 8600,700,CONT_DIF_N,* +V 5600,3300,CONT_DIF_N,* +V 11000,1100,CONT_DIF_N,* +V 6200,700,CONT_DIF_N,* +V 6800,3300,CONT_DIF_N,* +V 6800,2100,CONT_DIF_N,* +V 6800,2500,CONT_DIF_N,* +V 8000,2900,CONT_DIF_N,* +V 8000,3300,CONT_DIF_N,* +V 7400,1500,CONT_DIF_N,* +V 7400,1100,CONT_DIF_N,* +V 8000,2100,CONT_DIF_N,* +V 7400,700,CONT_DIF_N,* +V 8000,2500,CONT_DIF_N,* +V 7400,3300,CONT_DIF_N,* +V 7400,2800,CONT_DIF_N,* +V 6800,2900,CONT_DIF_N,* +V 8600,1100,CONT_DIF_N,* +V 8600,1500,CONT_DIF_N,* +V 14600,2700,CONT_DIF_N,* +V 15800,2800,CONT_DIF_N,* +V 15800,3400,CONT_DIF_N,* +V 16900,23200,CONT_VIA,* +V 16300,23200,CONT_VIA,* +V 16900,1600,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/padlib/paliotw_sp.ap b/alliance/src/cells/src/padlib/paliotw_sp.ap new file mode 100644 index 00000000..a34c76be --- /dev/null +++ b/alliance/src/cells/src/padlib/paliotw_sp.ap @@ -0,0 +1,1623 @@ +V ALLIANCE : 4 +H paliotw_sp,P,26/ 0/100,100 +A 0,-700,17200,35600 +C 4900,-700,200,i,0,SOUTH,ALU1 +C 3800,-700,200,t,0,SOUTH,ALU1 +C 15700,-700,200,b,0,SOUTH,ALU1 +C 15700,-700,200,b,1,SOUTH,ALU2 +C 4900,-700,200,i,1,SOUTH,ALU2 +C 3800,-700,200,t,1,SOUTH,ALU2 +C 0,600,1200,ck,0,WEST,ALU2 +C 17200,600,1200,ck,1,EAST,ALU2 +C 0,8400,4000,vddi,0,WEST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 17200,8400,4000,vddi,1,EAST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,16800,12000,vdde,1,EAST,ALU2 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 0,29600,12000,vsse,0,WEST,ALU2 +S 1100,9100,1700,9100,3900,*,RIGHT,PTRANS +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 6400,13000,14100,13000,200,*,RIGHT,ALU1 +S 6400,13100,14100,13100,200,*,RIGHT,ALU1 +S 2700,12600,6000,12600,300,*,RIGHT,ALU1 +S 5900,12500,5900,12900,300,*,UP,ALU1 +S 6400,23200,16900,23200,300,*,RIGHT,ALU2 +S 16200,23200,17000,23200,300,*,RIGHT,ALU1 +S 16400,1600,17000,1600,300,*,LEFT,ALU1 +S 16400,2300,16400,4100,200,*,UP,ALU1 +S 16900,1500,16900,23300,300,*,UP,ALU1 +S 16400,5000,16400,12100,200,*,UP,ALU1 +S 600,5100,16600,5100,400,*,RIGHT,NWELL +S 600,8600,16600,8600,7200,*,RIGHT,NWELL +S 14900,2400,14900,3700,100,*,UP,NTRANS +S 14600,2600,14600,3500,300,*,UP,NDIF +S 15200,2600,15200,3500,300,*,DOWN,NDIF +S 12200,600,12200,3400,200,*,UP,NDIF +S 12800,600,12800,3400,300,*,UP,NDIF +S 13400,600,13400,3400,200,*,UP,NDIF +S 14000,600,14000,3400,300,*,UP,NDIF +S 15800,2600,15800,3500,300,*,UP,NDIF +S 15500,2400,15500,3700,100,*,UP,NTRANS +S 11900,400,11900,3600,100,*,UP,NTRANS +S 12500,400,12500,3600,100,*,UP,NTRANS +S 13100,400,13100,3600,100,*,UP,NTRANS +S 13700,400,13700,3600,100,*,UP,NTRANS +S 11600,600,11600,3400,300,*,UP,NDIF +S 6800,600,6800,3500,300,*,UP,NDIF +S 8600,600,8600,3500,200,*,UP,NDIF +S 7400,600,7400,3500,200,*,UP,NDIF +S 8300,400,8300,3700,100,*,UP,NTRANS +S 7700,400,7700,3700,100,*,UP,NTRANS +S 7100,400,7100,3700,100,*,UP,NTRANS +S 6500,400,6500,3700,100,*,UP,NTRANS +S 6200,600,6200,3500,200,*,UP,NDIF +S 5900,400,5900,3700,100,*,UP,NTRANS +S 5600,600,5600,3500,300,*,UP,NDIF +S 8000,600,8000,3500,300,*,UP,NDIF +S 10400,600,10400,3500,300,*,UP,NDIF +S 8900,400,8900,3700,100,*,UP,NTRANS +S 9200,600,9200,3500,300,*,UP,NDIF +S 9800,600,9800,3500,200,*,UP,NDIF +S 10700,400,10700,3700,100,*,UP,NTRANS +S 5000,600,5000,3500,300,*,UP,NDIF +S 4700,400,4700,3700,100,*,UP,NTRANS +S 4400,600,4400,3500,200,*,UP,NDIF +S 10100,400,10100,3700,100,*,UP,NTRANS +S 9500,400,9500,3700,100,*,UP,NTRANS +S 2900,400,2900,3700,100,*,UP,NTRANS +S 3200,600,3200,3500,200,*,UP,NDIF +S 3800,600,3800,3500,300,*,UP,NDIF +S 3500,400,3500,3700,100,*,UP,NTRANS +S 4100,400,4100,3700,100,*,UP,NTRANS +S 11000,600,11000,3500,300,*,UP,NDIF +S 1400,600,1400,3500,300,*,UP,NDIF +S 2600,600,2600,3500,300,*,UP,NDIF +S 2000,600,2000,3500,200,*,UP,NDIF +S 1700,400,1700,3700,100,*,UP,NTRANS +S 2300,400,2300,3700,100,*,UP,NTRANS +S 12200,5700,12200,11500,300,*,UP,PDIF +S 12800,5700,12800,11500,300,*,UP,PDIF +S 13100,5500,13100,11700,100,*,UP,PTRANS +S 13400,5700,13400,11500,300,*,UP,PDIF +S 13700,5500,13700,11700,100,*,UP,PTRANS +S 14000,5700,14000,11500,300,*,UP,PDIF +S 8300,5400,8300,11700,100,*,UP,PTRANS +S 7700,5400,7700,11700,100,*,UP,PTRANS +S 11900,5500,11900,11700,100,*,UP,PTRANS +S 11600,5700,11600,11500,300,*,UP,PDIF +S 12500,5500,12500,11700,100,*,UP,PTRANS +S 5900,5400,5900,11700,100,*,UP,PTRANS +S 5600,5600,5600,11500,300,*,UP,PDIF +S 8000,5600,8000,11500,300,*,UP,PDIF +S 10400,5600,10400,11500,300,*,UP,PDIF +S 6800,5600,6800,11500,300,*,UP,PDIF +S 8600,5600,8600,11500,300,*,UP,PDIF +S 7400,5600,7400,11500,300,*,UP,PDIF +S 11000,5600,11000,11500,300,*,UP,PDIF +S 9800,5600,9800,11500,300,*,UP,PDIF +S 7100,5400,7100,11700,100,*,UP,PTRANS +S 6500,5400,6500,11700,100,*,UP,PTRANS +S 6200,5600,6200,11500,300,*,UP,PDIF +S 10700,5400,10700,11700,100,*,UP,PTRANS +S 10100,5400,10100,11700,100,*,UP,PTRANS +S 9500,5400,9500,11700,100,*,UP,PTRANS +S 8900,5400,8900,11700,100,*,UP,PTRANS +S 9200,5600,9200,11500,300,*,UP,PDIF +S 3500,5400,3500,11700,100,*,UP,PTRANS +S 4100,5400,4100,11700,100,*,UP,PTRANS +S 4400,5600,4400,11500,300,*,UP,PDIF +S 5000,5600,5000,11500,300,*,UP,PDIF +S 4700,5400,4700,11700,100,*,UP,PTRANS +S 2900,5400,2900,8700,100,*,UP,PTRANS +S 2600,5600,2600,8500,300,*,UP,PDIF +S 3200,5600,3200,11500,300,*,UP,PDIF +S 3800,5600,3800,11500,300,*,UP,PDIF +S 14600,5700,14600,7600,300,*,UP,PDIF +S 15800,5700,15800,7600,300,*,UP,PDIF +S 15200,5700,15200,7600,300,*,UP,PDIF +S 14900,5500,14900,7800,100,*,UP,PTRANS +S 15500,5500,15500,7800,100,*,UP,PTRANS +S 700,12000,16500,12000,300,*,RIGHT,NTIE +S 800,5000,800,12100,300,*,UP,NTIE +S 700,5100,2700,5100,300,*,RIGHT,NTIE +S 11600,5100,14000,5100,300,*,RIGHT,NTIE +S 14500,5100,15300,5100,300,*,RIGHT,NTIE +S 1400,5100,1400,6400,1100,*,DOWN,NTIE +S 15700,5100,16500,5100,300,*,RIGHT,NTIE +S 10100,5100,11000,5100,300,*,RIGHT,NTIE +S 7700,5100,9500,5100,300,*,RIGHT,NTIE +S 16400,5000,16400,12100,300,*,UP,NTIE +S 6100,5100,7100,5100,300,*,RIGHT,NTIE +S 15500,8100,15500,12000,2000,*,DOWN,NTIE +S 2200,8900,2200,9900,300,*,UP,NTIE +S 2000,5000,2000,9100,300,*,UP,NTIE +S 2000,9700,2000,12000,300,*,UP,NTIE +S 800,-300,800,4100,300,*,UP,PTIE +S 700,-200,15300,-200,300,*,RIGHT,PTIE +S 15200,-300,15200,1900,300,*,DOWN,PTIE +S 700,4000,2700,4000,300,*,RIGHT,PTIE +S 15200,1800,16500,1800,300,*,LEFT,PTIE +S 14900,0,14900,1900,300,*,DOWN,PTIE +S 14600,0,14600,1900,300,*,DOWN,PTIE +S 15700,4000,16500,4000,300,*,LEFT,PTIE +S 6100,4000,7100,4000,300,*,RIGHT,PTIE +S 11600,4000,14000,4000,300,*,RIGHT,PTIE +S 7700,4000,10400,4000,300,*,RIGHT,PTIE +S 16400,1700,16400,4100,300,*,UP,PTIE +S 14200,3700,14200,3900,100,*,DOWN,POLY +S 15500,2200,15500,2400,100,*,DOWN,POLY +S 15500,3700,15500,5500,100,*,UP,POLY +S 11300,5500,14900,5500,100,*,RIGHT,POLY +S 11400,4500,11400,5300,100,*,DOWN,POLY +S 10600,4600,11200,4600,100,*,LEFT,POLY +S 10600,3800,10600,4500,100,*,DOWN,POLY +S 14900,3700,14900,4300,100,*,UP,POLY +S 14200,4500,14900,4500,300,*,RIGHT,POLY +S 14300,4700,14300,5300,100,*,DOWN,POLY +S 14200,4700,14200,5300,100,*,DOWN,POLY +S 14300,3700,14300,3900,100,*,DOWN,POLY +S 6500,5400,8300,5400,100,*,RIGHT,POLY +S 6500,3700,8300,3700,100,*,RIGHT,POLY +S 5200,5300,5900,5300,300,*,RIGHT,POLY +S 5900,3700,5900,5400,100,*,UP,POLY +S 11400,3600,14300,3600,100,*,RIGHT,POLY +S 11400,3700,14300,3700,100,*,RIGHT,POLY +S 11400,3800,11400,4100,100,*,DOWN,POLY +S 11300,3600,11300,4100,100,*,DOWN,POLY +S 1700,3700,2900,3700,100,*,RIGHT,POLY +S 4700,200,4700,400,100,*,UP,POLY +S 3500,3700,3500,5400,100,*,UP,POLY +S 4100,3700,4100,5400,100,*,UP,POLY +S 4700,3700,4700,5400,100,*,UP,POLY +S 2900,8700,2900,9000,100,*,UP,POLY +S 3600,4500,4000,4500,300,*,RIGHT,POLY +S 7400,3700,7400,5400,200,*,UP,POLY +S 10700,3700,10700,4500,100,*,DOWN,POLY +S 11300,5400,14900,5400,100,*,RIGHT,POLY +S 11300,4500,11300,5400,100,*,DOWN,POLY +S 10800,4500,11300,4500,100,*,LEFT,POLY +S 9800,4600,9800,5400,300,*,DOWN,POLY +S 8900,3700,10700,3700,100,*,RIGHT,POLY +S 8900,5400,10700,5400,100,*,RIGHT,POLY +S 2900,3700,2900,5400,100,*,UP,POLY +S 700,-200,3400,-200,300,*,RIGHT,ALU1 +S 800,-300,800,4100,300,*,UP,ALU1 +S 2000,-300,2000,4100,200,*,UP,ALU1 +S 3200,-300,3200,4100,200,*,UP,ALU1 +S 3800,-700,3800,11400,200,*,UP,ALU1 +S 4400,-300,4400,4100,200,*,UP,ALU1 +S 11000,-300,11000,3200,200,*,UP,ALU1 +S 15200,-300,15200,4000,200,*,UP,ALU1 +S 15700,-700,15700,2300,200,*,DOWN,ALU1 +S 5300,-200,15300,-200,300,*,RIGHT,ALU1 +S 4900,-700,4900,300,200,*,UP,ALU1 +S 8600,-300,8600,4100,200,*,UP,ALU1 +S 9800,-300,9800,4100,200,*,UP,ALU1 +S 7400,-300,7400,3200,200,*,UP,ALU1 +S 6200,-300,6200,4100,200,*,UP,ALU1 +S 1100,5000,1100,8700,900,*,UP,ALU1 +S 700,5100,2100,5100,300,*,LEFT,ALU1 +S 800,5000,800,12100,300,*,DOWN,ALU1 +S 1400,9800,1400,10900,1500,*,UP,ALU1 +S 700,12000,2300,12000,300,*,RIGHT,ALU1 +S 6000,4000,10400,4000,300,*,RIGHT,ALU1 +S 7700,5100,11800,5100,300,*,RIGHT,ALU1 +S 12800,5800,12800,12900,200,*,UP,ALU1 +S 1400,11300,2700,11300,200,*,RIGHT,ALU1 +S 14900,-100,14900,1900,800,*,DOWN,ALU1 +S 5600,4600,7300,4600,200,*,RIGHT,ALU1 +S 6200,5000,6200,12100,200,*,UP,ALU1 +S 5600,900,5600,11400,200,*,UP,ALU1 +S 5000,900,5000,11400,200,*,UP,ALU1 +S 2700,9000,2700,12700,200,*,UP,ALU1 +S 3200,12000,6400,12000,300,*,RIGHT,ALU1 +S 3200,5000,3200,12100,200,*,UP,ALU1 +S 2600,900,2600,8200,200,*,UP,ALU1 +S 11000,5000,11000,12100,200,*,UP,ALU1 +S 8000,600,8000,3300,200,*,UP,ALU1 +S 9200,600,9200,3300,200,*,UP,ALU1 +S 10400,600,10400,3300,200,*,UP,ALU1 +S 7400,5700,7400,12000,200,*,UP,ALU1 +S 9800,5700,9800,12000,200,*,UP,ALU1 +S 6800,600,6800,3300,200,*,UP,ALU1 +S 8600,5000,8600,12000,200,*,UP,ALU1 +S 10400,5800,10400,12900,200,*,UP,ALU1 +S 9200,5800,9200,12900,200,*,UP,ALU1 +S 8000,5800,8000,12900,200,*,UP,ALU1 +S 6800,5800,6800,12900,200,*,UP,ALU1 +S 4400,5000,4400,12100,200,*,UP,ALU1 +S 1400,900,1400,4500,200,*,UP,ALU1 +S 6200,5100,7100,5100,300,*,RIGHT,ALU1 +S 1400,4500,3300,4500,200,*,RIGHT,ALU1 +S 13400,700,13400,3900,200,*,UP,ALU1 +S 12200,4600,12200,11400,200,*,UP,ALU1 +S 11600,5800,11600,12900,200,*,UP,ALU1 +S 14000,3900,14000,12900,200,*,UP,ALU1 +S 12200,700,12200,3900,200,*,UP,ALU1 +S 12800,600,12800,3300,200,*,UP,ALU1 +S 14000,600,14000,3300,200,*,UP,ALU1 +S 12200,3900,14000,3900,200,*,RIGHT,ALU1 +S 11600,600,11600,4600,200,*,UP,ALU1 +S 11100,3900,11100,4600,200,*,UP,ALU1 +S 9700,4600,11100,4600,200,*,LEFT,ALU1 +S 15000,4500,15800,4500,300,*,LEFT,ALU1 +S 15200,5000,15200,12100,200,*,UP,ALU1 +S 13400,4600,13400,11400,200,*,UP,ALU1 +S 11600,4600,13500,4600,200,*,RIGHT,ALU1 +S 15500,8100,15500,12100,2000,*,DOWN,ALU1 +S 1200,8800,1200,9700,500,*,DOWN,ALU1 +S 1800,9200,1800,9400,200,*,DOWN,ALU1 +S 2000,5700,2000,9300,300,*,DOWN,ALU1 +S 14600,2700,14600,7500,200,*,UP,ALU1 +S 15800,2800,15800,7500,200,*,UP,ALU1 +S 6800,1600,16900,1600,300,*,RIGHT,ALU2 +S 7700,30100,7700,35600,6200,*,UP,ALU1 +S 11800,13400,11800,22700,600,*,UP,NWELL +S 11500,13600,12000,13600,300,*,RIGHT,NTIE +S 11900,13600,11900,22600,300,*,UP,NTIE +S 11500,22500,12000,22500,300,*,RIGHT,NTIE +S 11700,13500,11700,22600,600,*,UP,ALU1 +S 4600,29600,10800,29600,900,*,RIGHT,ALU1 +S 11900,24200,11900,28800,300,*,UP,PTIE +S 11500,28700,12000,28700,300,*,RIGHT,PTIE +S 11400,24300,12000,24300,300,*,RIGHT,PTIE +S 11300,28900,11300,29300,300,*,UP,ALU1 +S 11700,24200,11700,29300,600,*,UP,ALU1 +S 3700,13400,3700,22700,800,*,UP,NWELL +S 4100,24900,4100,28200,300,*,UP,NDIF +S 4100,14100,4100,22000,300,*,UP,PDIF +S 3500,13600,4100,13600,300,*,RIGHT,NTIE +S 3500,13600,3500,22600,300,*,UP,NTIE +S 3500,22500,4100,22500,300,*,RIGHT,NTIE +S 3400,28700,4200,28700,300,*,RIGHT,PTIE +S 3500,24200,3500,28800,300,*,UP,PTIE +S 3400,24300,4200,24300,300,*,RIGHT,PTIE +S 3800,13500,3800,22600,800,*,UP,ALU1 +S 6400,23100,6400,23800,200,*,UP,ALU1 +S 3800,24200,3800,29300,800,*,UP,ALU1 +S 3400,28000,3400,28800,100,*,UP,ALU1 +S 9500,14200,9500,29100,300,*,UP,ALU1 +S 10700,14200,10700,29100,300,*,UP,ALU1 +S 10100,23700,10100,28800,300,*,UP,ALU1 +S 11300,24200,11300,28800,300,*,UP,ALU1 +S 11300,24800,11300,28200,300,*,UP,NDIF +S 10700,24800,10700,28200,300,*,UP,NDIF +S 10100,24800,10100,28200,300,*,UP,NDIF +S 9500,24800,9500,28200,300,*,UP,NDIF +S 9200,24600,9200,28400,100,*,UP,NTRANS +S 9800,24600,9800,28400,100,*,UP,NTRANS +S 10400,24600,10400,28400,100,*,UP,NTRANS +S 11000,24600,11000,28400,100,*,UP,NTRANS +S 9000,28700,11400,28700,300,*,RIGHT,PTIE +S 11300,14100,11300,22000,300,*,UP,PDIF +S 10700,14100,10700,22000,200,*,UP,PDIF +S 10100,14100,10100,22000,200,*,UP,PDIF +S 9500,14100,9500,22000,200,*,UP,PDIF +S 9200,13900,9200,22200,100,*,UP,PTRANS +S 10100,13800,10100,22600,300,*,UP,ALU1 +S 9800,13900,9800,22200,100,*,UP,PTRANS +S 10400,13900,10400,22200,100,*,UP,PTRANS +S 11000,13900,11000,22200,100,*,UP,PTRANS +S 10300,13400,10300,22700,2800,*,UP,NWELL +S 11300,13800,11300,22600,300,*,UP,ALU1 +S 9000,13600,10400,13600,300,*,RIGHT,NTIE +S 11000,13600,11400,13600,300,*,RIGHT,NTIE +S 10700,13300,10700,13900,200,*,UP,POLY +S 9200,13900,11000,13900,100,*,RIGHT,POLY +S 9000,13600,10400,13600,300,*,RIGHT,ALU1 +S 11000,13600,11400,13600,300,*,RIGHT,ALU1 +S 10700,23700,10700,23900,200,*,DOWN,POLY +S 9000,24300,10400,24300,300,*,RIGHT,PTIE +S 11000,24300,11400,24300,300,*,RIGHT,PTIE +S 9200,24600,11000,24600,100,*,RIGHT,POLY +S 10700,23800,10700,24600,200,*,UP,POLY +S 10700,23800,11200,23800,300,*,RIGHT,POLY +S 11200,23200,11200,23800,200,*,UP,ALU1 +S 9000,22500,11400,22500,300,*,RIGHT,NTIE +S 7100,14200,7100,29100,300,*,UP,ALU1 +S 8300,14200,8300,29100,300,*,UP,ALU1 +S 7700,23700,7700,28800,300,*,UP,ALU1 +S 8900,24200,8900,28800,300,*,UP,ALU1 +S 8900,24800,8900,28200,300,*,UP,NDIF +S 8300,24800,8300,28200,300,*,UP,NDIF +S 7700,24800,7700,28200,300,*,UP,NDIF +S 7100,24800,7100,28200,300,*,UP,NDIF +S 6800,24600,6800,28400,100,*,UP,NTRANS +S 7400,24600,7400,28400,100,*,UP,NTRANS +S 8000,24600,8000,28400,100,*,UP,NTRANS +S 8600,24600,8600,28400,100,*,UP,NTRANS +S 6600,28700,9000,28700,300,*,RIGHT,PTIE +S 8900,14100,8900,22000,300,*,UP,PDIF +S 8300,14100,8300,22000,200,*,UP,PDIF +S 7700,14100,7700,22000,200,*,UP,PDIF +S 7100,14100,7100,22000,200,*,UP,PDIF +S 6800,13900,6800,22200,100,*,UP,PTRANS +S 7700,13800,7700,22600,300,*,UP,ALU1 +S 7400,13900,7400,22200,100,*,UP,PTRANS +S 8000,13900,8000,22200,100,*,UP,PTRANS +S 8600,13900,8600,22200,100,*,UP,PTRANS +S 7900,13400,7900,22700,2800,*,UP,NWELL +S 8900,13800,8900,22600,300,*,UP,ALU1 +S 6600,13600,8000,13600,300,*,RIGHT,NTIE +S 8600,13600,9000,13600,300,*,RIGHT,NTIE +S 8300,13300,8300,13900,200,*,UP,POLY +S 6800,13900,8600,13900,100,*,RIGHT,POLY +S 6600,13600,8000,13600,300,*,RIGHT,ALU1 +S 8600,13600,9000,13600,300,*,RIGHT,ALU1 +S 8300,23700,8300,23900,200,*,DOWN,POLY +S 6600,24300,8000,24300,300,*,RIGHT,PTIE +S 8600,24300,9000,24300,300,*,RIGHT,PTIE +S 6800,24600,8600,24600,100,*,RIGHT,POLY +S 8300,23800,8300,24600,200,*,UP,POLY +S 8300,23800,8800,23800,300,*,RIGHT,POLY +S 8800,23200,8800,23800,200,*,UP,ALU1 +S 6600,22500,9000,22500,300,*,RIGHT,NTIE +S 5900,13000,5900,14300,300,*,DOWN,ALU1 +S 6500,13500,6500,22600,300,*,UP,ALU1 +S 4200,13600,5400,13600,300,*,RIGHT,ALU1 +S 5900,13100,5900,13900,200,*,UP,POLY +S 4200,22500,6600,22500,300,*,RIGHT,NTIE +S 5900,23800,6400,23800,300,*,RIGHT,POLY +S 5900,23800,5900,24600,200,*,UP,POLY +S 4400,24600,6200,24600,100,*,RIGHT,POLY +S 6200,24300,6600,24300,300,*,RIGHT,PTIE +S 4200,24300,5600,24300,300,*,RIGHT,PTIE +S 5900,23700,5900,23900,200,*,DOWN,POLY +S 4400,13900,6200,13900,100,*,RIGHT,POLY +S 6200,13600,6600,13600,300,*,RIGHT,NTIE +S 4200,13600,5600,13600,300,*,RIGHT,NTIE +S 5500,13400,5500,22700,2800,*,UP,NWELL +S 6200,13900,6200,22200,100,*,UP,PTRANS +S 5600,13900,5600,22200,100,*,UP,PTRANS +S 5000,13900,5000,22200,100,*,UP,PTRANS +S 5300,13800,5300,22600,300,*,UP,ALU1 +S 4400,13900,4400,22200,100,*,UP,PTRANS +S 4700,14100,4700,22000,200,*,UP,PDIF +S 5300,14100,5300,22000,200,*,UP,PDIF +S 5900,14100,5900,22000,200,*,UP,PDIF +S 6500,14100,6500,22000,300,*,UP,PDIF +S 4200,28700,6600,28700,300,*,RIGHT,PTIE +S 6200,24600,6200,28400,100,*,UP,NTRANS +S 5600,24600,5600,28400,100,*,UP,NTRANS +S 5000,24600,5000,28400,100,*,UP,NTRANS +S 4400,24600,4400,28400,100,*,UP,NTRANS +S 4700,24800,4700,28200,300,*,UP,NDIF +S 5300,24800,5300,28200,300,*,UP,NDIF +S 5900,24800,5900,28200,300,*,UP,NDIF +S 6500,24800,6500,28200,300,*,UP,NDIF +S 6500,24200,6500,28800,300,*,UP,ALU1 +S 5300,23700,5300,28800,300,*,UP,ALU1 +S 5900,14200,5900,29100,300,*,UP,ALU1 +S 4700,14200,4700,29100,300,*,UP,ALU1 +S 5900,13100,6500,13100,200,*,RIGHT,POLY +S 6400,13500,6400,13700,200,*,DOWN,ALU1 +S 0,600,17200,600,1200,ck,RIGHT,ALU2 +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +V 16300,23200,CONT_VIA +V 16900,23200,CONT_VIA +V 16500,1600,CONT_VIA +V 16900,1600,CONT_VIA +V 15800,3400,CONT_DIF_N +V 15800,2800,CONT_DIF_N +V 14600,2700,CONT_DIF_N +V 8600,1500,CONT_DIF_N +V 8600,1100,CONT_DIF_N +V 6800,2900,CONT_DIF_N +V 7400,2800,CONT_DIF_N +V 7400,3300,CONT_DIF_N +V 8000,2500,CONT_DIF_N +V 7400,700,CONT_DIF_N +V 8000,2100,CONT_DIF_N +V 7400,1100,CONT_DIF_N +V 7400,1500,CONT_DIF_N +V 8000,3300,CONT_DIF_N +V 8000,2900,CONT_DIF_N +V 6800,2500,CONT_DIF_N +V 6800,2100,CONT_DIF_N +V 6800,3300,CONT_DIF_N +V 6200,700,CONT_DIF_N +V 11000,1100,CONT_DIF_N +V 5600,3300,CONT_DIF_N +V 8600,700,CONT_DIF_N +V 8600,3100,CONT_DIF_N +V 8600,2700,CONT_DIF_N +V 8600,1900,CONT_DIF_N +V 7400,1900,CONT_DIF_N +V 5600,2500,CONT_DIF_N +V 11000,3100,CONT_DIF_N +V 11000,2700,CONT_DIF_N +V 6200,3100,CONT_DIF_N +V 6200,2700,CONT_DIF_N +V 6200,1900,CONT_DIF_N +V 6200,1500,CONT_DIF_N +V 6200,1100,CONT_DIF_N +V 9800,1500,CONT_DIF_N +V 8000,700,CONT_DIF_N +V 9200,2500,CONT_DIF_N +V 5600,2900,CONT_DIF_N +V 5600,900,CONT_DIF_N +V 5600,1300,CONT_DIF_N +V 5600,1700,CONT_DIF_N +V 5600,2100,CONT_DIF_N +V 11000,700,CONT_DIF_N +V 9200,700,CONT_DIF_N +V 10400,700,CONT_DIF_N +V 11000,1900,CONT_DIF_N +V 9800,1900,CONT_DIF_N +V 9800,700,CONT_DIF_N +V 9800,1100,CONT_DIF_N +V 10400,2900,CONT_DIF_N +V 9200,1200,CONT_DIF_N +V 10400,2100,CONT_DIF_N +V 10400,3300,CONT_DIF_N +V 9800,2800,CONT_DIF_N +V 9200,2100,CONT_DIF_N +V 9200,3300,CONT_DIF_N +V 9200,2900,CONT_DIF_N +V 11000,1500,CONT_DIF_N +V 9800,3300,CONT_DIF_N +V 5000,3300,CONT_DIF_N +V 5000,2900,CONT_DIF_N +V 5000,2100,CONT_DIF_N +V 5000,2500,CONT_DIF_N +V 5000,900,CONT_DIF_N +V 5000,1300,CONT_DIF_N +V 10400,1200,CONT_DIF_N +V 10400,2500,CONT_DIF_N +V 8000,1200,CONT_DIF_N +V 3200,1500,CONT_DIF_N +V 3200,1100,CONT_DIF_N +V 3800,2900,CONT_DIF_N +V 3800,2100,CONT_DIF_N +V 4400,1100,CONT_DIF_N +V 4400,1500,CONT_DIF_N +V 5000,1700,CONT_DIF_N +V 3800,2500,CONT_DIF_N +V 2000,1500,CONT_DIF_N +V 2000,1900,CONT_DIF_N +V 2000,2700,CONT_DIF_N +V 4400,1900,CONT_DIF_N +V 4400,2700,CONT_DIF_N +V 4400,3100,CONT_DIF_N +V 4400,700,CONT_DIF_N +V 2600,3300,CONT_DIF_N +V 2600,2900,CONT_DIF_N +V 2600,2100,CONT_DIF_N +V 2600,2500,CONT_DIF_N +V 3800,3300,CONT_DIF_N +V 3800,1700,CONT_DIF_N +V 3800,1300,CONT_DIF_N +V 3800,900,CONT_DIF_N +V 1400,1700,CONT_DIF_N +V 1400,3300,CONT_DIF_N +V 1400,2900,CONT_DIF_N +V 1400,2100,CONT_DIF_N +V 3200,700,CONT_DIF_N +V 3200,3100,CONT_DIF_N +V 3200,2700,CONT_DIF_N +V 3200,1900,CONT_DIF_N +V 1400,1300,CONT_DIF_N +V 2600,1700,CONT_DIF_N +V 6800,1200,CONT_DIF_N +V 6800,700,CONT_DIF_N +V 2600,900,CONT_DIF_N +V 2600,1300,CONT_DIF_N +V 2000,700,CONT_DIF_N +V 2000,1100,CONT_DIF_N +V 12200,1500,CONT_DIF_N +V 14000,2100,CONT_DIF_N +V 11600,700,CONT_DIF_N +V 12800,1200,CONT_DIF_N +V 14000,1200,CONT_DIF_N +V 14000,700,CONT_DIF_N +V 1400,2500,CONT_DIF_N +V 1400,900,CONT_DIF_N +V 11600,2100,CONT_DIF_N +V 11600,3300,CONT_DIF_N +V 11600,2900,CONT_DIF_N +V 12200,3300,CONT_DIF_N +V 12200,1900,CONT_DIF_N +V 12200,700,CONT_DIF_N +V 12200,1100,CONT_DIF_N +V 14000,3300,CONT_DIF_N +V 13400,3300,CONT_DIF_N +V 12800,2900,CONT_DIF_N +V 12800,3300,CONT_DIF_N +V 14000,2900,CONT_DIF_N +V 13400,1500,CONT_DIF_N +V 12200,2800,CONT_DIF_N +V 11600,1200,CONT_DIF_N +V 11600,2500,CONT_DIF_N +V 12800,2100,CONT_DIF_N +V 12800,2500,CONT_DIF_N +V 12800,700,CONT_DIF_N +V 13400,2800,CONT_DIF_N +V 14000,2500,CONT_DIF_N +V 13400,1100,CONT_DIF_N +V 13400,700,CONT_DIF_N +V 13400,1900,CONT_DIF_N +V 15200,3100,CONT_DIF_N +V 15200,2700,CONT_DIF_N +V 14600,3300,CONT_DIF_N +V 12200,2300,CONT_DIF_N +V 13400,2300,CONT_DIF_N +V 14600,6200,CONT_DIF_P +V 14600,6600,CONT_DIF_P +V 14600,7000,CONT_DIF_P +V 15200,7000,CONT_DIF_P +V 15200,6600,CONT_DIF_P +V 15200,5800,CONT_DIF_P +V 15200,6200,CONT_DIF_P +V 15800,7000,CONT_DIF_P +V 12800,7400,CONT_DIF_P +V 12800,6200,CONT_DIF_P +V 12800,7000,CONT_DIF_P +V 12800,6600,CONT_DIF_P +V 15800,6200,CONT_DIF_P +V 15800,5800,CONT_DIF_P +V 15800,6600,CONT_DIF_P +V 14600,5800,CONT_DIF_P +V 8000,9000,CONT_DIF_P +V 8000,10600,CONT_DIF_P +V 8000,11000,CONT_DIF_P +V 8000,5800,CONT_DIF_P +V 8000,8200,CONT_DIF_P +V 8000,8600,CONT_DIF_P +V 8000,11400,CONT_DIF_P +V 12800,5800,CONT_DIF_P +V 8000,7400,CONT_DIF_P +V 6800,6200,CONT_DIF_P +V 8000,6200,CONT_DIF_P +V 8000,9400,CONT_DIF_P +V 8000,9800,CONT_DIF_P +V 8000,6600,CONT_DIF_P +V 8000,7000,CONT_DIF_P +V 8000,10200,CONT_DIF_P +V 8000,7800,CONT_DIF_P +V 8600,7800,CONT_DIF_P +V 6800,10600,CONT_DIF_P +V 6800,11000,CONT_DIF_P +V 6800,5800,CONT_DIF_P +V 6800,8200,CONT_DIF_P +V 6800,8600,CONT_DIF_P +V 6800,11400,CONT_DIF_P +V 6800,7400,CONT_DIF_P +V 8600,11400,CONT_DIF_P +V 6800,9400,CONT_DIF_P +V 6800,9800,CONT_DIF_P +V 6800,6600,CONT_DIF_P +V 6800,7000,CONT_DIF_P +V 6800,10200,CONT_DIF_P +V 6800,7800,CONT_DIF_P +V 6800,9000,CONT_DIF_P +V 7400,8600,CONT_DIF_P +V 8600,11000,CONT_DIF_P +V 8600,10600,CONT_DIF_P +V 8600,9800,CONT_DIF_P +V 8600,7000,CONT_DIF_P +V 8600,5800,CONT_DIF_P +V 8600,6200,CONT_DIF_P +V 8600,8600,CONT_DIF_P +V 6200,5800,CONT_DIF_P +V 8600,8200,CONT_DIF_P +V 8600,9400,CONT_DIF_P +V 7400,10600,CONT_DIF_P +V 7400,11000,CONT_DIF_P +V 7400,7800,CONT_DIF_P +V 7400,8200,CONT_DIF_P +V 7400,11400,CONT_DIF_P +V 6200,10600,CONT_DIF_P +V 7400,6200,CONT_DIF_P +V 7400,5800,CONT_DIF_P +V 7400,7000,CONT_DIF_P +V 7400,9800,CONT_DIF_P +V 7400,9400,CONT_DIF_P +V 6200,6200,CONT_DIF_P +V 6200,7000,CONT_DIF_P +V 5600,11000,CONT_DIF_P +V 6200,9400,CONT_DIF_P +V 6200,9800,CONT_DIF_P +V 6200,11000,CONT_DIF_P +V 6200,7800,CONT_DIF_P +V 6200,8200,CONT_DIF_P +V 6200,11400,CONT_DIF_P +V 6200,8600,CONT_DIF_P +V 5600,10600,CONT_DIF_P +V 5600,9400,CONT_DIF_P +V 5600,9800,CONT_DIF_P +V 5600,6600,CONT_DIF_P +V 5600,7000,CONT_DIF_P +V 5600,7800,CONT_DIF_P +V 5600,10200,CONT_DIF_P +V 5600,9000,CONT_DIF_P +V 9800,9400,CONT_DIF_P +V 9800,11000,CONT_DIF_P +V 5600,5800,CONT_DIF_P +V 5600,8200,CONT_DIF_P +V 5600,8600,CONT_DIF_P +V 5600,11400,CONT_DIF_P +V 5600,7400,CONT_DIF_P +V 5600,6200,CONT_DIF_P +V 9800,8200,CONT_DIF_P +V 9800,11400,CONT_DIF_P +V 9800,8600,CONT_DIF_P +V 9800,6200,CONT_DIF_P +V 9800,5800,CONT_DIF_P +V 9800,7000,CONT_DIF_P +V 11000,7000,CONT_DIF_P +V 9800,9800,CONT_DIF_P +V 11000,6200,CONT_DIF_P +V 11000,8600,CONT_DIF_P +V 11000,11400,CONT_DIF_P +V 11000,8200,CONT_DIF_P +V 11000,9400,CONT_DIF_P +V 9800,10600,CONT_DIF_P +V 9200,7000,CONT_DIF_P +V 9800,7800,CONT_DIF_P +V 9200,7800,CONT_DIF_P +V 9200,9000,CONT_DIF_P +V 11000,7800,CONT_DIF_P +V 11000,11000,CONT_DIF_P +V 11000,10600,CONT_DIF_P +V 11000,9800,CONT_DIF_P +V 9200,8200,CONT_DIF_P +V 11000,5800,CONT_DIF_P +V 9200,11400,CONT_DIF_P +V 9200,7400,CONT_DIF_P +V 9200,6200,CONT_DIF_P +V 9200,9400,CONT_DIF_P +V 9200,9800,CONT_DIF_P +V 9200,6600,CONT_DIF_P +V 10400,6600,CONT_DIF_P +V 9200,10200,CONT_DIF_P +V 10400,10200,CONT_DIF_P +V 10400,7800,CONT_DIF_P +V 10400,9000,CONT_DIF_P +V 9200,10600,CONT_DIF_P +V 9200,11000,CONT_DIF_P +V 9200,5800,CONT_DIF_P +V 10400,5800,CONT_DIF_P +V 9200,8600,CONT_DIF_P +V 10400,8600,CONT_DIF_P +V 10400,11400,CONT_DIF_P +V 10400,7400,CONT_DIF_P +V 10400,6200,CONT_DIF_P +V 10400,9400,CONT_DIF_P +V 10400,9800,CONT_DIF_P +V 10400,10600,CONT_DIF_P +V 5000,7800,CONT_DIF_P +V 5000,9000,CONT_DIF_P +V 5000,8600,CONT_DIF_P +V 5000,11400,CONT_DIF_P +V 5000,7400,CONT_DIF_P +V 5000,6200,CONT_DIF_P +V 10400,8200,CONT_DIF_P +V 10400,7000,CONT_DIF_P +V 5000,9800,CONT_DIF_P +V 5000,10600,CONT_DIF_P +V 5000,6600,CONT_DIF_P +V 5000,11000,CONT_DIF_P +V 5000,8200,CONT_DIF_P +V 5000,5800,CONT_DIF_P +V 10400,11000,CONT_DIF_P +V 5000,7000,CONT_DIF_P +V 4400,8200,CONT_DIF_P +V 4400,11000,CONT_DIF_P +V 4400,9800,CONT_DIF_P +V 4400,5800,CONT_DIF_P +V 4400,7000,CONT_DIF_P +V 4400,6200,CONT_DIF_P +V 5000,9400,CONT_DIF_P +V 5000,10200,CONT_DIF_P +V 3800,7400,CONT_DIF_P +V 3800,11400,CONT_DIF_P +V 3800,9000,CONT_DIF_P +V 3800,7800,CONT_DIF_P +V 4400,9400,CONT_DIF_P +V 4400,10600,CONT_DIF_P +V 4400,8600,CONT_DIF_P +V 4400,11400,CONT_DIF_P +V 3800,7000,CONT_DIF_P +V 3800,10200,CONT_DIF_P +V 4400,7800,CONT_DIF_P +V 3800,8200,CONT_DIF_P +V 3800,11000,CONT_DIF_P +V 3800,6600,CONT_DIF_P +V 3800,10600,CONT_DIF_P +V 3800,6200,CONT_DIF_P +V 3200,8600,CONT_DIF_P +V 3200,10600,CONT_DIF_P +V 3800,8600,CONT_DIF_P +V 3200,6200,CONT_DIF_P +V 3200,7000,CONT_DIF_P +V 3200,5800,CONT_DIF_P +V 3800,9800,CONT_DIF_P +V 3800,9400,CONT_DIF_P +V 2600,8200,CONT_DIF_P +V 2600,5800,CONT_DIF_P +V 3800,5800,CONT_DIF_P +V 3200,9800,CONT_DIF_P +V 3200,11000,CONT_DIF_P +V 3200,7800,CONT_DIF_P +V 3200,8200,CONT_DIF_P +V 3200,11400,CONT_DIF_P +V 12200,7000,CONT_DIF_P +V 12200,9400,CONT_DIF_P +V 3200,9400,CONT_DIF_P +V 2600,7000,CONT_DIF_P +V 2600,7400,CONT_DIF_P +V 2600,6200,CONT_DIF_P +V 2600,6600,CONT_DIF_P +V 2600,7800,CONT_DIF_P +V 11600,9000,CONT_DIF_P +V 12200,10600,CONT_DIF_P +V 12200,7800,CONT_DIF_P +V 12200,8200,CONT_DIF_P +V 12200,11400,CONT_DIF_P +V 12200,8600,CONT_DIF_P +V 12200,6200,CONT_DIF_P +V 12200,5800,CONT_DIF_P +V 11600,7400,CONT_DIF_P +V 11600,6200,CONT_DIF_P +V 12200,9800,CONT_DIF_P +V 11600,9800,CONT_DIF_P +V 11600,6600,CONT_DIF_P +V 11600,7000,CONT_DIF_P +V 11600,10200,CONT_DIF_P +V 11600,7800,CONT_DIF_P +V 13400,9400,CONT_DIF_P +V 13400,9800,CONT_DIF_P +V 12200,11000,CONT_DIF_P +V 11600,11000,CONT_DIF_P +V 11600,5800,CONT_DIF_P +V 11600,8200,CONT_DIF_P +V 11600,8600,CONT_DIF_P +V 11600,11400,CONT_DIF_P +V 13400,10600,CONT_DIF_P +V 12800,9000,CONT_DIF_P +V 11600,9400,CONT_DIF_P +V 12800,10200,CONT_DIF_P +V 13400,7000,CONT_DIF_P +V 13400,5800,CONT_DIF_P +V 13400,6200,CONT_DIF_P +V 13400,8600,CONT_DIF_P +V 12800,9800,CONT_DIF_P +V 12800,9400,CONT_DIF_P +V 11600,10600,CONT_DIF_P +V 12800,8600,CONT_DIF_P +V 13400,11400,CONT_DIF_P +V 13400,8200,CONT_DIF_P +V 13400,7800,CONT_DIF_P +V 13400,11000,CONT_DIF_P +V 14000,11400,CONT_DIF_P +V 14000,8600,CONT_DIF_P +V 14000,9000,CONT_DIF_P +V 14000,7800,CONT_DIF_P +V 14000,10200,CONT_DIF_P +V 12800,8200,CONT_DIF_P +V 12800,7800,CONT_DIF_P +V 12800,10600,CONT_DIF_P +V 14000,11000,CONT_DIF_P +V 14000,10600,CONT_DIF_P +V 14000,7000,CONT_DIF_P +V 14000,6600,CONT_DIF_P +V 14000,9800,CONT_DIF_P +V 14000,9400,CONT_DIF_P +V 14000,6200,CONT_DIF_P +V 12800,11400,CONT_DIF_P +V 13400,7400,CONT_DIF_P +V 12200,7400,CONT_DIF_P +V 13400,9000,CONT_DIF_P +V 12200,9000,CONT_DIF_P +V 12200,10200,CONT_DIF_P +V 13400,10200,CONT_DIF_P +V 14000,8200,CONT_DIF_P +V 12800,11000,CONT_DIF_P +V 15800,7500,CONT_DIF_P +V 15200,7500,CONT_DIF_P +V 1400,11300,CONT_DIF_P +V 1400,6900,CONT_DIF_P +V 14000,5800,CONT_DIF_P +V 13400,6600,CONT_DIF_P +V 12200,6600,CONT_DIF_P +V 14000,7400,CONT_DIF_P +V 14600,7500,CONT_DIF_P +V 800,5900,CONT_BODY_N +V 800,5500,CONT_BODY_N +V 800,9400,CONT_BODY_N +V 800,12000,CONT_BODY_N +V 800,9000,CONT_BODY_N +V 800,8600,CONT_BODY_N +V 800,8200,CONT_BODY_N +V 800,7800,CONT_BODY_N +V 800,7400,CONT_BODY_N +V 800,7000,CONT_BODY_N +V 800,6300,CONT_BODY_N +V 800,5100,CONT_BODY_N +V 800,10400,CONT_BODY_N +V 800,10800,CONT_BODY_N +V 800,11200,CONT_BODY_N +V 800,11600,CONT_BODY_N +V 14800,9500,CONT_BODY_N +V 14800,9100,CONT_BODY_N +V 14800,11600,CONT_BODY_N +V 14800,10400,CONT_BODY_N +V 14800,8300,CONT_BODY_N +V 14800,10800,CONT_BODY_N +V 14800,11200,CONT_BODY_N +V 14800,12000,CONT_BODY_N +V 15200,9500,CONT_BODY_N +V 15200,12000,CONT_BODY_N +V 15200,11200,CONT_BODY_N +V 15200,10800,CONT_BODY_N +V 15200,8300,CONT_BODY_N +V 15200,10400,CONT_BODY_N +V 15200,11600,CONT_BODY_N +V 15200,9100,CONT_BODY_N +V 15600,12000,CONT_BODY_N +V 15600,9500,CONT_BODY_N +V 15600,9100,CONT_BODY_N +V 15600,11600,CONT_BODY_N +V 15600,10400,CONT_BODY_N +V 15600,8300,CONT_BODY_N +V 15600,10800,CONT_BODY_N +V 15600,11200,CONT_BODY_N +V 16000,9100,CONT_BODY_N +V 16000,9500,CONT_BODY_N +V 16000,12000,CONT_BODY_N +V 16000,11200,CONT_BODY_N +V 16000,10800,CONT_BODY_N +V 16000,8300,CONT_BODY_N +V 16000,10400,CONT_BODY_N +V 16000,11600,CONT_BODY_N +V 11700,5100,CONT_BODY_N +V 2000,10700,CONT_BODY_N +V 2000,10300,CONT_BODY_N +V 1400,6300,CONT_BODY_N +V 1400,5900,CONT_BODY_N +V 1400,5500,CONT_BODY_N +V 1400,5100,CONT_BODY_N +V 2000,5100,CONT_BODY_N +V 3200,12000,CONT_BODY_N +V 1700,12000,CONT_BODY_N +V 1200,12000,CONT_BODY_N +V 6600,5100,CONT_BODY_N +V 7000,5100,CONT_BODY_N +V 8600,5100,CONT_BODY_N +V 6200,5100,CONT_BODY_N +V 6300,12000,CONT_BODY_N +V 3200,5100,CONT_BODY_N +V 3600,12000,CONT_BODY_N +V 4000,12000,CONT_BODY_N +V 4800,12000,CONT_BODY_N +V 4400,5100,CONT_BODY_N +V 9000,5100,CONT_BODY_N +V 9400,5100,CONT_BODY_N +V 11000,5100,CONT_BODY_N +V 7400,12000,CONT_BODY_N +V 7800,5100,CONT_BODY_N +V 8200,5100,CONT_BODY_N +V 4400,12000,CONT_BODY_N +V 5300,12000,CONT_BODY_N +V 5800,12000,CONT_BODY_N +V 9800,12000,CONT_BODY_N +V 8600,12000,CONT_BODY_N +V 16400,11200,CONT_BODY_N +V 16400,7100,CONT_BODY_N +V 16400,10800,CONT_BODY_N +V 16400,8300,CONT_BODY_N +V 16400,9100,CONT_BODY_N +V 16400,5500,CONT_BODY_N +V 10600,5100,CONT_BODY_N +V 10200,5100,CONT_BODY_N +V 16400,5100,CONT_BODY_N +V 16400,10400,CONT_BODY_N +V 16400,7900,CONT_BODY_N +V 16400,11600,CONT_BODY_N +V 16400,9500,CONT_BODY_N +V 16400,12000,CONT_BODY_N +V 16400,5900,CONT_BODY_N +V 16400,6300,CONT_BODY_N +V 2100,12000,CONT_BODY_N +V 11000,12000,CONT_BODY_N +V 15200,5100,CONT_BODY_N +V 800,-200,CONT_BODY_P +V 7400,-200,CONT_BODY_P +V 6200,-200,CONT_BODY_P +V 2000,-200,CONT_BODY_P +V 3200,-200,CONT_BODY_P +V 4400,-200,CONT_BODY_P +V 9800,-200,CONT_BODY_P +V 11000,-200,CONT_BODY_P +V 8600,-200,CONT_BODY_P +V 12000,-200,CONT_BODY_P +V 12400,-200,CONT_BODY_P +V 1200,-200,CONT_BODY_P +V 13200,-200,CONT_BODY_P +V 12800,-200,CONT_BODY_P +V 14800,-200,CONT_BODY_P +V 14400,-200,CONT_BODY_P +V 13600,-200,CONT_BODY_P +V 14000,-200,CONT_BODY_P +V 10600,-200,CONT_BODY_P +V 10200,-200,CONT_BODY_P +V 9000,-200,CONT_BODY_P +V 9400,-200,CONT_BODY_P +V 8200,-200,CONT_BODY_P +V 7800,-200,CONT_BODY_P +V 7000,-200,CONT_BODY_P +V 6600,-200,CONT_BODY_P +V 5800,-200,CONT_BODY_P +V 5400,-200,CONT_BODY_P +V 11600,-200,CONT_BODY_P +V 15200,-200,CONT_BODY_P +V 1600,-200,CONT_BODY_P +V 2400,-200,CONT_BODY_P +V 2800,-200,CONT_BODY_P +V 800,300,CONT_BODY_P +V 800,4000,CONT_BODY_P +V 800,3100,CONT_BODY_P +V 800,2700,CONT_BODY_P +V 800,1900,CONT_BODY_P +V 800,1500,CONT_BODY_P +V 800,1100,CONT_BODY_P +V 800,700,CONT_BODY_P +V 15200,200,CONT_BODY_P +V 14700,1800,CONT_BODY_P +V 14700,1400,CONT_BODY_P +V 15200,1400,CONT_BODY_P +V 14700,1000,CONT_BODY_P +V 15200,1000,CONT_BODY_P +V 14700,600,CONT_BODY_P +V 15200,600,CONT_BODY_P +V 14700,200,CONT_BODY_P +V 8600,4000,CONT_BODY_P +V 6200,4000,CONT_BODY_P +V 10300,4000,CONT_BODY_P +V 9900,4000,CONT_BODY_P +V 9400,4000,CONT_BODY_P +V 15200,1800,CONT_BODY_P +V 3200,4000,CONT_BODY_P +V 4400,4000,CONT_BODY_P +V 6600,4000,CONT_BODY_P +V 7000,4000,CONT_BODY_P +V 8200,4000,CONT_BODY_P +V 9000,4000,CONT_BODY_P +V 7800,4000,CONT_BODY_P +V 2000,4000,CONT_BODY_P +V 16400,4000,CONT_BODY_P +V 16400,4000,CONT_BODY_P +V 15200,4000,CONT_BODY_P +V 16400,3200,CONT_BODY_P +V 16400,2800,CONT_BODY_P +V 7400,4600,CONT_POLY +V 4900,300,CONT_POLY +V 3300,4500,CONT_POLY +V 2700,8900,CONT_POLY +V 5100,5300,CONT_POLY +V 14500,3800,CONT_POLY +V 15700,2300,CONT_POLY +V 1800,9400,CONT_POLY +V 11100,4000,CONT_POLY +V 15100,4500,CONT_POLY +V 9800,4600,CONT_POLY +V 4900,-700,CONT_VIA +V 3800,-700,CONT_VIA +V 15700,-700,CONT_VIA +V 800,3500,CONT_VIA +V 800,2300,CONT_VIA +V 800,6600,CONT_VIA +V 800,9800,CONT_VIA +V 14800,8700,CONT_VIA +V 14800,10000,CONT_VIA +V 15200,10000,CONT_VIA +V 15200,8700,CONT_VIA +V 15600,8700,CONT_VIA +V 15600,10000,CONT_VIA +V 16000,10000,CONT_VIA +V 16000,8700,CONT_VIA +V 2000,9900,CONT_VIA +V 6200,6600,CONT_VIA +V 6200,7400,CONT_VIA +V 8600,3500,CONT_VIA +V 10400,1600,CONT_VIA +V 9200,1600,CONT_VIA +V 7400,9000,CONT_VIA +V 7400,10200,CONT_VIA +V 11000,2300,CONT_VIA +V 11000,6600,CONT_VIA +V 7400,6600,CONT_VIA +V 8600,2300,CONT_VIA +V 8600,6600,CONT_VIA +V 8600,10200,CONT_VIA +V 8600,9000,CONT_VIA +V 8600,7400,CONT_VIA +V 9800,9000,CONT_VIA +V 8000,1600,CONT_VIA +V 6200,9000,CONT_VIA +V 6200,10200,CONT_VIA +V 6200,3500,CONT_VIA +V 6200,2300,CONT_VIA +V 7400,2300,CONT_VIA +V 7400,7400,CONT_VIA +V 4400,7400,CONT_VIA +V 4400,6600,CONT_VIA +V 4400,2300,CONT_VIA +V 11000,10200,CONT_VIA +V 11000,9000,CONT_VIA +V 11000,7400,CONT_VIA +V 9800,2300,CONT_VIA +V 9800,7400,CONT_VIA +V 3200,7400,CONT_VIA +V 3200,9000,CONT_VIA +V 2000,2300,CONT_VIA +V 9800,10200,CONT_VIA +V 9800,6600,CONT_VIA +V 4400,3500,CONT_VIA +V 4400,10200,CONT_VIA +V 4400,9000,CONT_VIA +V 2000,3200,CONT_VIA +V 6800,1600,CONT_VIA +V 3200,10200,CONT_VIA +V 3200,3500,CONT_VIA +V 3200,2300,CONT_VIA +V 3200,6600,CONT_VIA +V 16400,7500,CONT_VIA +V 16400,10000,CONT_VIA +V 16400,6700,CONT_VIA +V 16400,8700,CONT_VIA +V 11600,1600,CONT_VIA +V 12800,1600,CONT_VIA +V 14000,1600,CONT_VIA +V 15200,3500,CONT_VIA +V 16400,2400,CONT_VIA +V 16400,3600,CONT_VIA +V 2000,5800,CONT_VIA +V 11900,18800,CONT_BODY_N +V 11900,18400,CONT_BODY_N +V 11900,14400,CONT_BODY_N +V 11900,14000,CONT_BODY_N +V 11900,16400,CONT_BODY_N +V 11900,18000,CONT_BODY_N +V 11900,17600,CONT_BODY_N +V 11900,20000,CONT_BODY_N +V 11900,19600,CONT_BODY_N +V 11900,19200,CONT_BODY_N +V 11500,13600,CONT_BODY_N +V 11900,16000,CONT_BODY_N +V 11900,16800,CONT_BODY_N +V 11900,17200,CONT_BODY_N +V 11900,15600,CONT_BODY_N +V 11900,13600,CONT_BODY_N +V 11900,15200,CONT_BODY_N +V 11900,14800,CONT_BODY_N +V 11900,21600,CONT_BODY_N +V 11900,21200,CONT_BODY_N +V 11900,20800,CONT_BODY_N +V 11900,20400,CONT_BODY_N +V 11900,22500,CONT_BODY_N +V 11900,22000,CONT_BODY_N +V 11600,19100,CONT_VIA +V 11600,14300,CONT_VIA +V 11600,15900,CONT_VIA +V 11600,15500,CONT_VIA +V 11600,18300,CONT_VIA +V 11600,17100,CONT_VIA +V 11600,17900,CONT_VIA +V 11600,19500,CONT_VIA +V 11600,14700,CONT_VIA +V 11600,16700,CONT_VIA +V 11600,13900,CONT_VIA +V 11600,21500,CONT_VIA +V 11600,21900,CONT_VIA +V 11600,20300,CONT_VIA +V 11600,20700,CONT_VIA +V 11600,22500,CONT_VIA +V 11900,27500,CONT_BODY_P +V 11900,27100,CONT_BODY_P +V 11900,26700,CONT_BODY_P +V 11900,26300,CONT_BODY_P +V 11900,24700,CONT_BODY_P +V 11900,25100,CONT_BODY_P +V 11900,25500,CONT_BODY_P +V 11900,24300,CONT_BODY_P +V 11900,28700,CONT_BODY_P +V 11900,28300,CONT_BODY_P +V 11900,27900,CONT_VIA +V 11600,24300,CONT_VIA +V 11900,25900,CONT_VIA +V 11300,29200,CONT_VIA +V 11900,29200,CONT_VIA +V 4100,28100,CONT_DIF_N +V 4100,27700,CONT_DIF_N +V 4100,26900,CONT_DIF_N +V 4100,26500,CONT_DIF_N +V 4100,25700,CONT_DIF_N +V 4100,25300,CONT_DIF_N +V 4100,24900,CONT_DIF_N +V 4100,26100,CONT_DIF_N +V 4100,27300,CONT_DIF_N +V 4100,14700,CONT_DIF_P +V 4100,15100,CONT_DIF_P +V 4100,15500,CONT_DIF_P +V 4100,15900,CONT_DIF_P +V 4100,16300,CONT_DIF_P +V 4100,16700,CONT_DIF_P +V 4100,17100,CONT_DIF_P +V 4100,17900,CONT_DIF_P +V 4100,17500,CONT_DIF_P +V 4100,18300,CONT_DIF_P +V 4100,18700,CONT_DIF_P +V 4100,19100,CONT_DIF_P +V 4100,19500,CONT_DIF_P +V 4100,19900,CONT_DIF_P +V 4100,14300,CONT_DIF_P +V 4100,21900,CONT_DIF_P +V 4100,21500,CONT_DIF_P +V 4100,21100,CONT_DIF_P +V 4100,20700,CONT_DIF_P +V 4100,20300,CONT_DIF_P +V 3500,16800,CONT_BODY_N +V 3500,13600,CONT_BODY_N +V 4000,13600,CONT_BODY_N +V 3500,14000,CONT_BODY_N +V 3500,14400,CONT_BODY_N +V 3500,14800,CONT_BODY_N +V 3500,15200,CONT_BODY_N +V 3500,15600,CONT_BODY_N +V 3500,19600,CONT_BODY_N +V 3500,18400,CONT_BODY_N +V 3500,20000,CONT_BODY_N +V 3500,17600,CONT_BODY_N +V 3500,18000,CONT_BODY_N +V 3500,16000,CONT_BODY_N +V 3500,16400,CONT_BODY_N +V 3500,17200,CONT_BODY_N +V 3500,18800,CONT_BODY_N +V 3500,19200,CONT_BODY_N +V 3500,20400,CONT_BODY_N +V 3500,20800,CONT_BODY_N +V 3500,21200,CONT_BODY_N +V 3500,21600,CONT_BODY_N +V 3500,22000,CONT_BODY_N +V 4100,22500,CONT_BODY_N +V 3500,22500,CONT_BODY_N +V 3500,27500,CONT_BODY_P +V 3500,27100,CONT_BODY_P +V 3500,26700,CONT_BODY_P +V 3500,26300,CONT_BODY_P +V 3500,25900,CONT_BODY_P +V 3500,28700,CONT_BODY_P +V 3500,24700,CONT_BODY_P +V 3500,25100,CONT_BODY_P +V 3500,25500,CONT_BODY_P +V 3900,24300,CONT_BODY_P +V 3500,24300,CONT_BODY_P +V 3900,28700,CONT_BODY_P +V 3500,28300,CONT_BODY_P +V 3500,27900,CONT_BODY_P +V 3800,16000,CONT_VIA +V 3800,16400,CONT_VIA +V 3800,14000,CONT_VIA +V 3800,19600,CONT_VIA +V 3800,19200,CONT_VIA +V 3800,18000,CONT_VIA +V 3800,15600,CONT_VIA +V 3800,15200,CONT_VIA +V 3800,14800,CONT_VIA +V 3800,14400,CONT_VIA +V 3800,16800,CONT_VIA +V 3800,17600,CONT_VIA +V 3800,17200,CONT_VIA +V 3800,18800,CONT_VIA +V 3800,18400,CONT_VIA +V 3800,20000,CONT_VIA +V 6400,23200,CONT_VIA +V 3500,29200,CONT_VIA +V 4000,29200,CONT_VIA +V 3800,27100,CONT_VIA +V 3800,26700,CONT_VIA +V 3800,22000,CONT_VIA +V 3800,21600,CONT_VIA +V 3800,21200,CONT_VIA +V 3800,22500,CONT_VIA +V 3800,20800,CONT_VIA +V 3800,20400,CONT_VIA +V 3800,25900,CONT_VIA +V 3800,24700,CONT_VIA +V 3800,25100,CONT_VIA +V 3800,25500,CONT_VIA +V 3800,26300,CONT_VIA +V 3800,28300,CONT_VIA +V 3800,27900,CONT_VIA +V 3800,27500,CONT_VIA +V 11300,27700,CONT_DIF_N +V 11300,26100,CONT_DIF_N +V 11300,25700,CONT_DIF_N +V 11300,27300,CONT_DIF_N +V 11300,26900,CONT_DIF_N +V 11300,25300,CONT_DIF_N +V 11300,26500,CONT_VIA +V 11300,24900,CONT_VIA +V 11300,28100,CONT_VIA +V 10100,24900,CONT_VIA +V 10100,25300,CONT_DIF_N +V 10100,26900,CONT_DIF_N +V 10100,27300,CONT_DIF_N +V 10100,26500,CONT_DIF_N +V 10100,28100,CONT_DIF_N +V 10100,25700,CONT_DIF_N +V 10100,27700,CONT_VIA +V 10100,26100,CONT_VIA +V 11300,28700,CONT_BODY_P +V 10100,28700,CONT_BODY_P +V 9200,13600,CONT_BODY_N +V 10300,13600,CONT_BODY_N +V 9700,13600,CONT_BODY_N +V 11100,13600,CONT_BODY_N +V 10700,13100,CONT_POLY +V 10000,13600,CONT_VIA +V 9500,25000,CONT_DIF_N +V 9500,27400,CONT_DIF_N +V 9500,27800,CONT_DIF_N +V 9500,25400,CONT_DIF_N +V 9500,25800,CONT_DIF_N +V 9500,26200,CONT_DIF_N +V 9500,26600,CONT_DIF_N +V 9500,27000,CONT_DIF_N +V 10700,25800,CONT_DIF_N +V 10700,26200,CONT_DIF_N +V 10700,25400,CONT_DIF_N +V 10700,25000,CONT_DIF_N +V 10700,27800,CONT_DIF_N +V 10700,26600,CONT_DIF_N +V 10700,27000,CONT_DIF_N +V 10700,27400,CONT_DIF_N +V 10100,14300,CONT_DIF_P +V 9500,14700,CONT_DIF_P +V 10100,14700,CONT_DIF_P +V 9500,15100,CONT_DIF_P +V 9500,14300,CONT_DIF_P +V 10700,14300,CONT_DIF_P +V 11300,14300,CONT_DIF_P +V 10700,14700,CONT_DIF_P +V 11300,14700,CONT_DIF_P +V 10700,15100,CONT_DIF_P +V 10100,15500,CONT_DIF_P +V 9500,15500,CONT_DIF_P +V 9500,19500,CONT_DIF_P +V 9500,17900,CONT_DIF_P +V 10100,17900,CONT_DIF_P +V 9500,18300,CONT_DIF_P +V 10100,18300,CONT_DIF_P +V 9500,18700,CONT_DIF_P +V 9500,19100,CONT_DIF_P +V 10100,19100,CONT_DIF_P +V 10100,19500,CONT_DIF_P +V 9500,16300,CONT_DIF_P +V 9500,15900,CONT_DIF_P +V 10100,15900,CONT_DIF_P +V 9500,17500,CONT_DIF_P +V 9500,17100,CONT_DIF_P +V 9500,16700,CONT_DIF_P +V 10100,16700,CONT_DIF_P +V 10100,17100,CONT_DIF_P +V 10700,15500,CONT_DIF_P +V 11300,15500,CONT_DIF_P +V 11300,19500,CONT_DIF_P +V 10700,18300,CONT_DIF_P +V 10700,18700,CONT_DIF_P +V 10700,19100,CONT_DIF_P +V 11300,19100,CONT_DIF_P +V 10700,19500,CONT_DIF_P +V 10700,17500,CONT_DIF_P +V 10700,17100,CONT_DIF_P +V 10700,17900,CONT_DIF_P +V 11300,17900,CONT_DIF_P +V 11300,18300,CONT_DIF_P +V 10700,16300,CONT_DIF_P +V 10700,15900,CONT_DIF_P +V 11300,15900,CONT_DIF_P +V 11300,17100,CONT_DIF_P +V 11300,16700,CONT_DIF_P +V 10700,16700,CONT_DIF_P +V 10100,15100,CONT_VIA +V 11300,15100,CONT_VIA +V 10100,17500,CONT_VIA +V 10100,18700,CONT_VIA +V 10100,16300,CONT_VIA +V 11300,18700,CONT_VIA +V 11300,17500,CONT_VIA +V 11300,16300,CONT_VIA +V 9500,19900,CONT_DIF_P +V 10700,19900,CONT_DIF_P +V 10100,19900,CONT_VIA +V 11300,19900,CONT_VIA +V 9500,20300,CONT_DIF_P +V 10700,20300,CONT_DIF_P +V 10100,20300,CONT_DIF_P +V 11300,20300,CONT_DIF_P +V 10100,20700,CONT_DIF_P +V 11300,20700,CONT_DIF_P +V 10700,20700,CONT_DIF_P +V 9500,20700,CONT_DIF_P +V 9500,21100,CONT_DIF_P +V 10700,21100,CONT_DIF_P +V 11300,21100,CONT_VIA +V 10100,21100,CONT_VIA +V 9500,21500,CONT_DIF_P +V 10100,21500,CONT_DIF_P +V 10700,21500,CONT_DIF_P +V 11300,21500,CONT_DIF_P +V 10100,24300,CONT_BODY_P +V 11300,24300,CONT_BODY_P +V 11200,23800,CONT_POLY +V 10100,23800,CONT_VIA +V 11200,23200,CONT_VIA +V 11300,22500,CONT_BODY_N +V 10100,22500,CONT_BODY_N +V 11300,21900,CONT_DIF_P +V 10700,21900,CONT_DIF_P +V 10100,21900,CONT_DIF_P +V 9500,21900,CONT_DIF_P +V 8900,27700,CONT_DIF_N +V 8900,26100,CONT_DIF_N +V 8900,25700,CONT_DIF_N +V 8900,27300,CONT_DIF_N +V 8900,26900,CONT_DIF_N +V 8900,25300,CONT_DIF_N +V 8900,26500,CONT_VIA +V 8900,24900,CONT_VIA +V 8900,28100,CONT_VIA +V 7700,24900,CONT_VIA +V 7700,25300,CONT_DIF_N +V 7700,26900,CONT_DIF_N +V 7700,27300,CONT_DIF_N +V 7700,26500,CONT_DIF_N +V 7700,28100,CONT_DIF_N +V 7700,25700,CONT_DIF_N +V 7700,27700,CONT_VIA +V 7700,26100,CONT_VIA +V 8900,28700,CONT_BODY_P +V 7700,28700,CONT_BODY_P +V 6800,13600,CONT_BODY_N +V 7900,13600,CONT_BODY_N +V 7300,13600,CONT_BODY_N +V 8700,13600,CONT_BODY_N +V 8300,13100,CONT_POLY +V 7600,13600,CONT_VIA +V 7100,25000,CONT_DIF_N +V 7100,27400,CONT_DIF_N +V 7100,27800,CONT_DIF_N +V 7100,25400,CONT_DIF_N +V 7100,25800,CONT_DIF_N +V 7100,26200,CONT_DIF_N +V 7100,26600,CONT_DIF_N +V 7100,27000,CONT_DIF_N +V 8300,25800,CONT_DIF_N +V 8300,26200,CONT_DIF_N +V 8300,25400,CONT_DIF_N +V 8300,25000,CONT_DIF_N +V 8300,27800,CONT_DIF_N +V 8300,26600,CONT_DIF_N +V 8300,27000,CONT_DIF_N +V 8300,27400,CONT_DIF_N +V 7700,14300,CONT_DIF_P +V 7100,14700,CONT_DIF_P +V 7700,14700,CONT_DIF_P +V 7100,15100,CONT_DIF_P +V 7100,14300,CONT_DIF_P +V 8300,14300,CONT_DIF_P +V 8900,14300,CONT_DIF_P +V 8300,14700,CONT_DIF_P +V 8900,14700,CONT_DIF_P +V 8300,15100,CONT_DIF_P +V 7700,15500,CONT_DIF_P +V 7100,15500,CONT_DIF_P +V 7100,19500,CONT_DIF_P +V 7100,17900,CONT_DIF_P +V 7700,17900,CONT_DIF_P +V 7100,18300,CONT_DIF_P +V 7700,18300,CONT_DIF_P +V 7100,18700,CONT_DIF_P +V 7100,19100,CONT_DIF_P +V 7700,19100,CONT_DIF_P +V 7700,19500,CONT_DIF_P +V 7100,16300,CONT_DIF_P +V 7100,15900,CONT_DIF_P +V 7700,15900,CONT_DIF_P +V 7100,17500,CONT_DIF_P +V 7100,17100,CONT_DIF_P +V 7100,16700,CONT_DIF_P +V 7700,16700,CONT_DIF_P +V 7700,17100,CONT_DIF_P +V 8300,15500,CONT_DIF_P +V 8900,15500,CONT_DIF_P +V 8900,19500,CONT_DIF_P +V 8300,18300,CONT_DIF_P +V 8300,18700,CONT_DIF_P +V 8300,19100,CONT_DIF_P +V 8900,19100,CONT_DIF_P +V 8300,19500,CONT_DIF_P +V 8300,17500,CONT_DIF_P +V 8300,17100,CONT_DIF_P +V 8300,17900,CONT_DIF_P +V 8900,17900,CONT_DIF_P +V 8900,18300,CONT_DIF_P +V 8300,16300,CONT_DIF_P +V 8300,15900,CONT_DIF_P +V 8900,15900,CONT_DIF_P +V 8900,17100,CONT_DIF_P +V 8900,16700,CONT_DIF_P +V 8300,16700,CONT_DIF_P +V 7700,15100,CONT_VIA +V 8900,15100,CONT_VIA +V 7700,17500,CONT_VIA +V 7700,18700,CONT_VIA +V 7700,16300,CONT_VIA +V 8900,18700,CONT_VIA +V 8900,17500,CONT_VIA +V 8900,16300,CONT_VIA +V 7100,19900,CONT_DIF_P +V 8300,19900,CONT_DIF_P +V 7700,19900,CONT_VIA +V 8900,19900,CONT_VIA +V 7100,20300,CONT_DIF_P +V 8300,20300,CONT_DIF_P +V 7700,20300,CONT_DIF_P +V 8900,20300,CONT_DIF_P +V 7700,20700,CONT_DIF_P +V 8900,20700,CONT_DIF_P +V 8300,20700,CONT_DIF_P +V 7100,20700,CONT_DIF_P +V 7100,21100,CONT_DIF_P +V 8300,21100,CONT_DIF_P +V 8900,21100,CONT_VIA +V 7700,21100,CONT_VIA +V 7100,21500,CONT_DIF_P +V 7700,21500,CONT_DIF_P +V 8300,21500,CONT_DIF_P +V 8900,21500,CONT_DIF_P +V 7700,24300,CONT_BODY_P +V 8900,24300,CONT_BODY_P +V 8800,23800,CONT_POLY +V 7700,23800,CONT_VIA +V 8800,23200,CONT_VIA +V 8900,22500,CONT_BODY_N +V 7700,22500,CONT_BODY_N +V 8900,21900,CONT_DIF_P +V 8300,21900,CONT_DIF_P +V 7700,21900,CONT_DIF_P +V 7100,21900,CONT_DIF_P +V 4400,13600,CONT_BODY_N +V 5300,13600,CONT_VIA +V 4700,21900,CONT_DIF_P +V 5300,21900,CONT_DIF_P +V 5900,21900,CONT_DIF_P +V 6500,21900,CONT_DIF_P +V 5300,22500,CONT_BODY_N +V 6500,22500,CONT_BODY_N +V 5300,23800,CONT_VIA +V 6400,23800,CONT_POLY +V 6500,24300,CONT_BODY_P +V 5300,24300,CONT_BODY_P +V 6500,21500,CONT_DIF_P +V 5900,21500,CONT_DIF_P +V 5300,21500,CONT_DIF_P +V 4700,21500,CONT_DIF_P +V 5300,21100,CONT_VIA +V 6500,21100,CONT_VIA +V 5900,21100,CONT_DIF_P +V 4700,21100,CONT_DIF_P +V 4700,20700,CONT_DIF_P +V 5900,20700,CONT_DIF_P +V 6500,20700,CONT_DIF_P +V 5300,20700,CONT_DIF_P +V 6500,20300,CONT_DIF_P +V 5300,20300,CONT_DIF_P +V 5900,20300,CONT_DIF_P +V 4700,20300,CONT_DIF_P +V 6500,19900,CONT_VIA +V 5300,19900,CONT_VIA +V 5900,19900,CONT_DIF_P +V 4700,19900,CONT_DIF_P +V 6500,16300,CONT_VIA +V 6500,17500,CONT_VIA +V 6500,18700,CONT_VIA +V 5300,16300,CONT_VIA +V 5300,18700,CONT_VIA +V 5300,17500,CONT_VIA +V 6500,15100,CONT_VIA +V 5300,15100,CONT_VIA +V 5900,16700,CONT_DIF_P +V 6500,16700,CONT_DIF_P +V 6500,17100,CONT_DIF_P +V 6500,15900,CONT_DIF_P +V 5900,15900,CONT_DIF_P +V 5900,16300,CONT_DIF_P +V 6500,18300,CONT_DIF_P +V 6500,17900,CONT_DIF_P +V 5900,17900,CONT_DIF_P +V 5900,17100,CONT_DIF_P +V 5900,17500,CONT_DIF_P +V 5900,19500,CONT_DIF_P +V 6500,19100,CONT_DIF_P +V 5900,19100,CONT_DIF_P +V 5900,18700,CONT_DIF_P +V 5900,18300,CONT_DIF_P +V 6500,19500,CONT_DIF_P +V 6500,15500,CONT_DIF_P +V 5900,15500,CONT_DIF_P +V 5300,17100,CONT_DIF_P +V 5300,16700,CONT_DIF_P +V 4700,16700,CONT_DIF_P +V 4700,17100,CONT_DIF_P +V 4700,17500,CONT_DIF_P +V 5300,15900,CONT_DIF_P +V 4700,15900,CONT_DIF_P +V 4700,16300,CONT_DIF_P +V 5300,19500,CONT_DIF_P +V 5300,19100,CONT_DIF_P +V 4700,19100,CONT_DIF_P +V 4700,18700,CONT_DIF_P +V 5300,18300,CONT_DIF_P +V 4700,18300,CONT_DIF_P +V 5300,17900,CONT_DIF_P +V 4700,17900,CONT_DIF_P +V 4700,19500,CONT_DIF_P +V 4700,15500,CONT_DIF_P +V 5300,15500,CONT_DIF_P +V 5900,15100,CONT_DIF_P +V 6500,14700,CONT_DIF_P +V 5900,14700,CONT_DIF_P +V 6500,14300,CONT_DIF_P +V 5900,14300,CONT_DIF_P +V 4700,14300,CONT_DIF_P +V 4700,15100,CONT_DIF_P +V 5300,14700,CONT_DIF_P +V 4700,14700,CONT_DIF_P +V 5300,14300,CONT_DIF_P +V 5900,27400,CONT_DIF_N +V 5900,27000,CONT_DIF_N +V 5900,26600,CONT_DIF_N +V 5900,27800,CONT_DIF_N +V 5900,25000,CONT_DIF_N +V 5900,25400,CONT_DIF_N +V 5900,26200,CONT_DIF_N +V 5900,25800,CONT_DIF_N +V 4700,27000,CONT_DIF_N +V 4700,26600,CONT_DIF_N +V 4700,26200,CONT_DIF_N +V 4700,25800,CONT_DIF_N +V 4700,25400,CONT_DIF_N +V 4700,27800,CONT_DIF_N +V 4700,27400,CONT_DIF_N +V 4700,25000,CONT_DIF_N +V 4900,13600,CONT_BODY_N +V 5300,28700,CONT_BODY_P +V 6500,28700,CONT_BODY_P +V 5300,26100,CONT_VIA +V 5300,27700,CONT_VIA +V 5300,25700,CONT_DIF_N +V 5300,28100,CONT_DIF_N +V 5300,26500,CONT_DIF_N +V 5300,27300,CONT_DIF_N +V 5300,26900,CONT_DIF_N +V 5300,25300,CONT_DIF_N +V 5300,24900,CONT_VIA +V 6500,28100,CONT_VIA +V 6500,24900,CONT_VIA +V 6500,26500,CONT_VIA +V 6500,25300,CONT_DIF_N +V 6500,26900,CONT_DIF_N +V 6500,27300,CONT_DIF_N +V 6500,25700,CONT_DIF_N +V 6500,26100,CONT_DIF_N +V 6500,27700,CONT_DIF_N +V 6500,13100,CONT_POLY +V 6400,13600,CONT_BODY_N +EOF diff --git a/alliance/src/cells/src/padlib/palo_sp.ap b/alliance/src/cells/src/padlib/palo_sp.ap new file mode 100644 index 00000000..e80dbc87 --- /dev/null +++ b/alliance/src/cells/src/padlib/palo_sp.ap @@ -0,0 +1,1512 @@ +V ALLIANCE : 6 +H palo_sp,P,13/10/2000,100 +A 0,-700,17200,35600 +C 0,600,1200,ck,0,WEST,ALU2 +C 17200,600,1200,ck,1,EAST,ALU2 +C 0,8400,4000,vddi,0,WEST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 17200,8400,4000,vddi,1,EAST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,16800,12000,vdde,1,EAST,ALU2 +C 4700,-700,200,i,1,SOUTH,ALU2 +C 4700,-700,200,i,0,SOUTH,ALU1 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 0,29600,12000,vsse,0,WEST,ALU2 +S 15900,1600,16900,1600,200,*,LEFT,ALU1 +S 15800,24300,16400,24300,200,*,RIGHT,ALU1 +S 15800,24300,15800,28800,200,*,UP,ALU1 +S 16200,24300,16200,29300,600,*,UP,ALU1 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2 +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +S 13500,22500,15900,22500,300,*,RIGHT,NTIE +S 15700,23200,15700,23800,200,*,UP,ALU1 +S 15200,23800,15700,23800,300,*,RIGHT,POLY +S 15200,23800,15200,24600,200,*,UP,POLY +S 13700,24600,15500,24600,100,*,RIGHT,POLY +S 15500,24300,15900,24300,300,*,RIGHT,PTIE +S 13500,24300,14900,24300,300,*,RIGHT,PTIE +S 15200,23700,15200,23900,200,*,DOWN,POLY +S 13500,13600,14900,13600,200,*,RIGHT,ALU1 +S 13700,13900,15500,13900,100,*,RIGHT,POLY +S 15200,13300,15200,13900,200,*,UP,POLY +S 15500,13600,15900,13600,300,*,RIGHT,NTIE +S 13500,13600,14900,13600,300,*,RIGHT,NTIE +S 14800,13400,14800,22700,2800,*,UP,NWELL +S 15500,13900,15500,22200,100,*,UP,PTRANS +S 14900,13900,14900,22200,100,*,UP,PTRANS +S 14300,13900,14300,22200,100,*,UP,PTRANS +S 13700,13900,13700,22200,100,*,UP,PTRANS +S 14000,14100,14000,22000,200,*,UP,PDIF +S 14600,14100,14600,22000,200,*,UP,PDIF +S 15200,14100,15200,22000,200,*,UP,PDIF +S 15800,14100,15800,22000,300,*,UP,PDIF +S 13500,28700,15900,28700,300,*,RIGHT,PTIE +S 15500,24600,15500,28400,100,*,UP,NTRANS +S 14900,24600,14900,28400,100,*,UP,NTRANS +S 14300,24600,14300,28400,100,*,UP,NTRANS +S 13700,24600,13700,28400,100,*,UP,NTRANS +S 14000,24800,14000,28200,300,*,UP,NDIF +S 14600,24800,14600,28200,300,*,UP,NDIF +S 15200,24800,15200,28200,300,*,UP,NDIF +S 15800,24800,15800,28200,300,*,UP,NDIF +S 14600,23700,14600,28800,200,*,UP,ALU1 +S 15200,14200,15200,29100,200,*,UP,ALU1 +S 14000,14200,14000,29100,200,*,UP,ALU1 +S 11100,22500,13500,22500,300,*,RIGHT,NTIE +S 13300,23200,13300,23800,200,*,UP,ALU1 +S 12800,23800,13300,23800,300,*,RIGHT,POLY +S 12800,23800,12800,24600,200,*,UP,POLY +S 11300,24600,13100,24600,100,*,RIGHT,POLY +S 13100,24300,13500,24300,300,*,RIGHT,PTIE +S 11100,24300,12500,24300,300,*,RIGHT,PTIE +S 12800,23700,12800,23900,200,*,DOWN,POLY +S 13100,13600,13500,13600,200,*,RIGHT,ALU1 +S 11100,13600,12500,13600,200,*,RIGHT,ALU1 +S 11300,13900,13100,13900,100,*,RIGHT,POLY +S 12800,13300,12800,13900,200,*,UP,POLY +S 13100,13600,13500,13600,300,*,RIGHT,NTIE +S 11100,13600,12500,13600,300,*,RIGHT,NTIE +S 12400,13400,12400,22700,2800,*,UP,NWELL +S 13100,13900,13100,22200,100,*,UP,PTRANS +S 12500,13900,12500,22200,100,*,UP,PTRANS +S 11900,13900,11900,22200,100,*,UP,PTRANS +S 11300,13900,11300,22200,100,*,UP,PTRANS +S 11600,14100,11600,22000,200,*,UP,PDIF +S 12200,14100,12200,22000,200,*,UP,PDIF +S 12800,14100,12800,22000,200,*,UP,PDIF +S 13400,14100,13400,22000,300,*,UP,PDIF +S 11100,28700,13500,28700,300,*,RIGHT,PTIE +S 13100,24600,13100,28400,100,*,UP,NTRANS +S 12500,24600,12500,28400,100,*,UP,NTRANS +S 11900,24600,11900,28400,100,*,UP,NTRANS +S 11300,24600,11300,28400,100,*,UP,NTRANS +S 11600,24800,11600,28200,300,*,UP,NDIF +S 12200,24800,12200,28200,300,*,UP,NDIF +S 12800,24800,12800,28200,300,*,UP,NDIF +S 13400,24800,13400,28200,300,*,UP,NDIF +S 12800,14200,12800,29100,200,*,UP,ALU1 +S 11600,14200,11600,29100,200,*,UP,ALU1 +S 8700,22500,11100,22500,300,*,RIGHT,NTIE +S 10900,23200,10900,23800,200,*,UP,ALU1 +S 10400,23800,10900,23800,300,*,RIGHT,POLY +S 10400,23800,10400,24600,200,*,UP,POLY +S 8900,24600,10700,24600,100,*,RIGHT,POLY +S 10700,24300,11100,24300,300,*,RIGHT,PTIE +S 8700,24300,10100,24300,300,*,RIGHT,PTIE +S 10400,23700,10400,23900,200,*,DOWN,POLY +S 10700,13600,11100,13600,200,*,RIGHT,ALU1 +S 8700,13600,10100,13600,200,*,RIGHT,ALU1 +S 8900,13900,10700,13900,100,*,RIGHT,POLY +S 10400,13300,10400,13900,200,*,UP,POLY +S 10700,13600,11100,13600,300,*,RIGHT,NTIE +S 8700,13600,10100,13600,300,*,RIGHT,NTIE +S 10000,13400,10000,22700,2800,*,UP,NWELL +S 10700,13900,10700,22200,100,*,UP,PTRANS +S 10100,13900,10100,22200,100,*,UP,PTRANS +S 9500,13900,9500,22200,100,*,UP,PTRANS +S 8900,13900,8900,22200,100,*,UP,PTRANS +S 9200,14100,9200,22000,200,*,UP,PDIF +S 9800,14100,9800,22000,200,*,UP,PDIF +S 10400,14100,10400,22000,200,*,UP,PDIF +S 11000,14100,11000,22000,300,*,UP,PDIF +S 8700,28700,11100,28700,300,*,RIGHT,PTIE +S 10700,24600,10700,28400,100,*,UP,NTRANS +S 10100,24600,10100,28400,100,*,UP,NTRANS +S 9500,24600,9500,28400,100,*,UP,NTRANS +S 8900,24600,8900,28400,100,*,UP,NTRANS +S 9200,24800,9200,28200,300,*,UP,NDIF +S 9800,24800,9800,28200,300,*,UP,NDIF +S 10400,24800,10400,28200,300,*,UP,NDIF +S 11000,24800,11000,28200,300,*,UP,NDIF +S 10400,14200,10400,29100,200,*,UP,ALU1 +S 9200,14200,9200,29100,200,*,UP,ALU1 +S 6300,22500,8700,22500,300,*,RIGHT,NTIE +S 8500,23200,8500,23800,200,*,UP,ALU1 +S 8000,23800,8500,23800,300,*,RIGHT,POLY +S 8000,23800,8000,24600,200,*,UP,POLY +S 6500,24600,8300,24600,100,*,RIGHT,POLY +S 8300,24300,8700,24300,300,*,RIGHT,PTIE +S 6300,24300,7700,24300,300,*,RIGHT,PTIE +S 8000,23700,8000,23900,200,*,DOWN,POLY +S 8300,13600,8700,13600,200,*,RIGHT,ALU1 +S 6300,13600,7700,13600,200,*,RIGHT,ALU1 +S 6500,13900,8300,13900,100,*,RIGHT,POLY +S 8000,13300,8000,13900,200,*,UP,POLY +S 8300,13600,8700,13600,300,*,RIGHT,NTIE +S 6300,13600,7700,13600,300,*,RIGHT,NTIE +S 7600,13400,7600,22700,2800,*,UP,NWELL +S 8300,13900,8300,22200,100,*,UP,PTRANS +S 7700,13900,7700,22200,100,*,UP,PTRANS +S 7100,13900,7100,22200,100,*,UP,PTRANS +S 6500,13900,6500,22200,100,*,UP,PTRANS +S 6800,14100,6800,22000,200,*,UP,PDIF +S 7400,14100,7400,22000,200,*,UP,PDIF +S 8000,14100,8000,22000,200,*,UP,PDIF +S 8600,14100,8600,22000,300,*,UP,PDIF +S 6300,28700,8700,28700,300,*,RIGHT,PTIE +S 8300,24600,8300,28400,100,*,UP,NTRANS +S 7700,24600,7700,28400,100,*,UP,NTRANS +S 7100,24600,7100,28400,100,*,UP,NTRANS +S 6500,24600,6500,28400,100,*,UP,NTRANS +S 6800,24800,6800,28200,300,*,UP,NDIF +S 7400,24800,7400,28200,300,*,UP,NDIF +S 8000,24800,8000,28200,300,*,UP,NDIF +S 8600,24800,8600,28200,300,*,UP,NDIF +S 8000,14200,8000,29100,200,*,UP,ALU1 +S 6800,14200,6800,29100,200,*,UP,ALU1 +S 3900,22500,6300,22500,300,*,RIGHT,NTIE +S 6100,23200,6100,23800,200,*,UP,ALU1 +S 5600,23800,6100,23800,300,*,RIGHT,POLY +S 5600,23800,5600,24600,200,*,UP,POLY +S 4100,24600,5900,24600,100,*,RIGHT,POLY +S 5900,24300,6300,24300,300,*,RIGHT,PTIE +S 3900,24300,5300,24300,300,*,RIGHT,PTIE +S 5600,23700,5600,23900,200,*,DOWN,POLY +S 5900,13600,6300,13600,200,*,RIGHT,ALU1 +S 3900,13600,5300,13600,200,*,RIGHT,ALU1 +S 4100,13900,5900,13900,100,*,RIGHT,POLY +S 5600,13300,5600,13900,200,*,UP,POLY +S 5900,13600,6300,13600,300,*,RIGHT,NTIE +S 3900,13600,5300,13600,300,*,RIGHT,NTIE +S 5200,13400,5200,22700,2800,*,UP,NWELL +S 5900,13900,5900,22200,100,*,UP,PTRANS +S 5300,13900,5300,22200,100,*,UP,PTRANS +S 4700,13900,4700,22200,100,*,UP,PTRANS +S 4100,13900,4100,22200,100,*,UP,PTRANS +S 4400,14100,4400,22000,200,*,UP,PDIF +S 5000,14100,5000,22000,200,*,UP,PDIF +S 5600,14100,5600,22000,200,*,UP,PDIF +S 6200,14100,6200,22000,300,*,UP,PDIF +S 3900,28700,6300,28700,300,*,RIGHT,PTIE +S 5900,24600,5900,28400,100,*,UP,NTRANS +S 5300,24600,5300,28400,100,*,UP,NTRANS +S 4700,24600,4700,28400,100,*,UP,NTRANS +S 4100,24600,4100,28400,100,*,UP,NTRANS +S 4400,24800,4400,28200,300,*,UP,NDIF +S 5000,24800,5000,28200,300,*,UP,NDIF +S 5600,24800,5600,28200,300,*,UP,NDIF +S 6200,24800,6200,28200,300,*,UP,NDIF +S 5000,23700,5000,28800,200,*,UP,ALU1 +S 5600,14200,5600,29100,200,*,UP,ALU1 +S 4400,14200,4400,29100,200,*,UP,ALU1 +S 1500,22500,3900,22500,300,*,RIGHT,NTIE +S 3700,23200,3700,23800,200,*,UP,ALU1 +S 3200,23800,3700,23800,300,*,RIGHT,POLY +S 3200,23800,3200,24600,200,*,UP,POLY +S 1700,24600,3500,24600,100,*,RIGHT,POLY +S 3500,24300,3900,24300,300,*,RIGHT,PTIE +S 1500,24300,2900,24300,300,*,RIGHT,PTIE +S 3200,23700,3200,23900,200,*,DOWN,POLY +S 3500,13600,3900,13600,200,*,RIGHT,ALU1 +S 1500,13600,2900,13600,200,*,RIGHT,ALU1 +S 1700,13900,3500,13900,100,*,RIGHT,POLY +S 3200,13300,3200,13900,200,*,UP,POLY +S 3500,13600,3900,13600,300,*,RIGHT,NTIE +S 1500,13600,2900,13600,300,*,RIGHT,NTIE +S 2800,13400,2800,22700,2800,*,UP,NWELL +S 3500,13900,3500,22200,100,*,UP,PTRANS +S 2900,13900,2900,22200,100,*,UP,PTRANS +S 2300,13900,2300,22200,100,*,UP,PTRANS +S 1700,13900,1700,22200,100,*,UP,PTRANS +S 2000,14100,2000,22000,200,*,UP,PDIF +S 2600,14100,2600,22000,200,*,UP,PDIF +S 3200,14100,3200,22000,200,*,UP,PDIF +S 3800,14100,3800,22000,300,*,UP,PDIF +S 1500,28700,3900,28700,300,*,RIGHT,PTIE +S 3500,24600,3500,28400,100,*,UP,NTRANS +S 2900,24600,2900,28400,100,*,UP,NTRANS +S 2300,24600,2300,28400,100,*,UP,NTRANS +S 1700,24600,1700,28400,100,*,UP,NTRANS +S 2000,24800,2000,28200,300,*,UP,NDIF +S 2600,24800,2600,28200,300,*,UP,NDIF +S 3200,24800,3200,28200,300,*,UP,NDIF +S 3800,24800,3800,28200,300,*,UP,NDIF +S 2600,23700,2600,28800,200,*,UP,ALU1 +S 3200,14200,3200,29100,200,*,UP,ALU1 +S 2000,14200,2000,29100,200,*,UP,ALU1 +S 3800,-300,3800,4100,700,*,UP,ALU1 +S 3500,4000,4300,4000,300,*,RIGHT,PTIE +S 3800,5000,3800,12100,700,*,UP,ALU1 +S 3500,5100,4300,5100,300,*,RIGHT,NTIE +S 3600,5000,3600,12100,300,*,UP,NTIE +S 3600,-300,3600,4100,300,*,UP,PTIE +S 4200,600,4200,3500,300,*,UP,NDIF +S 100,600,17200,600,1200,ck,RIGHT,ALU2 +S 5400,4600,7100,4600,200,*,RIGHT,ALU1 +S 5400,900,5400,11400,200,*,UP,ALU1 +S 4800,900,4800,11400,200,*,UP,ALU1 +S 7800,600,7800,3300,200,*,UP,ALU1 +S 4200,5000,4200,12100,200,*,UP,ALU1 +S 4200,-300,4200,4100,200,*,UP,ALU1 +S 7200,3700,7200,5400,200,*,UP,POLY +S 6300,5400,8100,5400,100,*,RIGHT,POLY +S 6300,3700,8100,3700,100,*,RIGHT,POLY +S 5000,5300,5700,5300,300,*,RIGHT,POLY +S 5700,3700,5700,5400,100,*,UP,POLY +S 4500,3700,4500,5400,100,*,UP,POLY +S 5900,4000,6900,4000,300,*,RIGHT,PTIE +S 5900,5100,6900,5100,300,*,RIGHT,NTIE +S 6600,5600,6600,11500,300,*,UP,PDIF +S 8400,5600,8400,11500,300,*,UP,PDIF +S 7200,5600,7200,11500,300,*,UP,PDIF +S 8100,5400,8100,11700,100,*,UP,PTRANS +S 7500,5400,7500,11700,100,*,UP,PTRANS +S 6300,5400,6300,11700,100,*,UP,PTRANS +S 6000,5600,6000,11500,300,*,UP,PDIF +S 5700,5400,5700,11700,100,*,UP,PTRANS +S 5400,5600,5400,11500,300,*,UP,PDIF +S 7800,5600,7800,11500,300,*,UP,PDIF +S 6900,5400,6900,11700,100,*,UP,PTRANS +S 4800,5600,4800,11500,300,*,UP,PDIF +S 4500,5400,4500,11700,100,*,UP,PTRANS +S 4200,5600,4200,11500,300,*,UP,PDIF +S 7800,600,7800,3500,300,*,UP,NDIF +S 6600,600,6600,3500,300,*,UP,NDIF +S 8400,600,8400,3500,200,*,UP,NDIF +S 7200,600,7200,3500,200,*,UP,NDIF +S 8100,400,8100,3700,100,*,UP,NTRANS +S 7500,400,7500,3700,100,*,UP,NTRANS +S 6900,400,6900,3700,100,*,UP,NTRANS +S 6300,400,6300,3700,100,*,UP,NTRANS +S 6000,600,6000,3500,200,*,UP,NDIF +S 5700,400,5700,3700,100,*,UP,NTRANS +S 5400,600,5400,3500,300,*,UP,NDIF +S 4800,600,4800,3500,300,*,UP,NDIF +S 4500,400,4500,3700,100,*,UP,NTRANS +S 4200,600,4200,3500,200,*,UP,NDIF +S 4500,200,4500,400,100,*,UP,POLY +S 4700,-700,4700,300,200,*,UP,ALU1 +S 6600,600,6600,3300,200,*,UP,ALU1 +S 6000,5100,6900,5100,200,*,RIGHT,ALU1 +S 8400,600,8400,3500,300,*,UP,NDIF +S 9000,5000,9000,12100,300,*,UP,NTIE +S 9000,-300,9000,4100,300,*,UP,PTIE +S 3500,-200,9100,-200,300,*,RIGHT,PTIE +S 7500,4000,9100,4000,300,*,RIGHT,PTIE +S 7500,5100,9100,5100,300,*,RIGHT,NTIE +S 3400,8600,9200,8600,7200,*,RIGHT,NWELL +S 3400,5100,9200,5100,400,*,RIGHT,NWELL +S 3500,12000,9000,12000,300,*,RIGHT,NTIE +S 8600,30100,8600,35600,12600,*,UP,ALU1 +S 15800,28900,15800,29300,200,*,UP,ALU1 +S 1900,29600,15300,29600,900,*,RIGHT,ALU1 +S 1100,24200,1100,29300,800,*,UP,ALU1 +S 700,28000,700,28800,100,*,UP,ALU1 +S 1100,13500,1100,22600,800,*,UP,ALU1 +S 16400,24200,16400,28800,300,*,UP,PTIE +S 16000,28700,16500,28700,300,*,RIGHT,PTIE +S 15900,24300,16500,24300,300,*,RIGHT,PTIE +S 700,28700,1500,28700,300,*,RIGHT,PTIE +S 800,24200,800,28800,300,*,UP,PTIE +S 700,24300,1500,24300,300,*,RIGHT,PTIE +S 15900,22500,16500,22500,300,*,RIGHT,NTIE +S 800,22500,1400,22500,300,*,RIGHT,NTIE +S 15900,13600,16500,13600,300,*,RIGHT,NTIE +S 16400,13500,16400,22600,300,*,UP,NTIE +S 800,13600,1400,13600,300,*,RIGHT,NTIE +S 800,13600,800,22600,300,*,UP,NTIE +S 1400,14100,1400,22000,300,*,UP,PDIF +S 1400,24900,1400,28200,300,*,UP,NDIF +S 16300,13400,16300,22700,600,*,UP,NWELL +S 1000,13400,1000,22700,800,*,UP,NWELL +S 16900,1600,16900,23300,200,*,UP,ALU1 +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 16300,23200,16900,23200,200,*,RIGHT,ALU1 +S 7200,-200,7200,3200,200,*,UP,ALU1 +S 9000,-200,9000,4100,200,*,UP,ALU1 +S 8400,-200,8400,4100,200,*,UP,ALU1 +S 7200,5800,7200,12000,200,*,UP,ALU1 +S 8400,5100,8400,12000,200,*,UP,ALU1 +S 9000,5200,9000,12100,200,*,UP,ALU1 +S 7500,5100,9000,5100,200,*,RIGHT,ALU1 +S 3500,5100,4200,5100,200,*,RIGHT,ALU1 +S 6000,5100,6000,12000,200,*,UP,ALU1 +S 7400,13600,7400,22600,200,*,UP,ALU1 +S 6200,13700,6200,22600,200,*,UP,ALU1 +S 5000,13600,5000,22600,200,*,UP,ALU1 +S 3800,13600,3800,22600,200,*,UP,ALU1 +S 2600,13600,2600,22600,200,*,UP,ALU1 +S 8600,13600,8600,22600,200,*,UP,ALU1 +S 9800,13700,9800,22600,200,*,UP,ALU1 +S 11000,13600,11000,22600,200,*,UP,ALU1 +S 12200,13700,12200,22600,200,*,UP,ALU1 +S 13400,13600,13400,22600,200,*,UP,ALU1 +S 14600,13600,14600,22600,200,*,UP,ALU1 +S 16200,13600,16200,22600,600,*,UP,ALU1 +S 15800,13700,15800,22600,200,*,UP,ALU1 +S 15500,13600,16400,13600,200,*,RIGHT,ALU1 +S 3100,13100,16900,13100,200,*,RIGHT,ALU1 +S 7800,5800,7800,13100,200,*,UP,ALU1 +S 6600,5800,6600,13000,200,*,UP,ALU1 +S 3500,12000,6000,12000,200,*,RIGHT,ALU1 +S 13400,24300,13400,28800,200,*,UP,ALU1 +S 12200,23800,12200,28800,200,*,UP,ALU1 +S 11000,24300,11000,28800,200,*,UP,ALU1 +S 9800,23800,9800,28800,200,*,UP,ALU1 +S 8600,24300,8600,28800,200,*,UP,ALU1 +S 7400,23900,7400,28800,200,*,UP,ALU1 +S 6200,24300,6200,28800,200,*,UP,ALU1 +S 3800,24400,3800,28800,200,*,UP,ALU1 +S 6000,4000,9100,4000,200,*,RIGHT,ALU1 +S 6000,-200,6000,4000,200,*,UP,ALU1 +S 5200,-200,9000,-200,200,*,RIGHT,ALU1 +S 6600,1600,16900,1600,200,*,RIGHT,ALU2 +S 3700,23200,16900,23200,200,*,RIGHT,ALU2 +V 15900,1600,CONT_VIA,* +V 16400,1600,CONT_VIA,* +V 14000,21900,CONT_DIF_P,* +V 14600,21900,CONT_DIF_P,* +V 15200,21900,CONT_DIF_P,* +V 15800,21900,CONT_DIF_P,* +V 14600,22500,CONT_BODY_N,* +V 15800,22500,CONT_BODY_N,* +V 15700,23200,CONT_VIA,* +V 14600,23800,CONT_VIA,* +V 15700,23800,CONT_POLY,* +V 15800,24300,CONT_BODY_P,* +V 14600,24300,CONT_BODY_P,* +V 15800,21500,CONT_DIF_P,* +V 15200,21500,CONT_DIF_P,* +V 14600,21500,CONT_DIF_P,* +V 14000,21500,CONT_DIF_P,* +V 14600,21100,CONT_VIA,* +V 15200,21100,CONT_DIF_P,* +V 14000,21100,CONT_DIF_P,* +V 14000,20700,CONT_DIF_P,* +V 15200,20700,CONT_DIF_P,* +V 15800,20700,CONT_DIF_P,* +V 14600,20700,CONT_DIF_P,* +V 15800,20300,CONT_DIF_P,* +V 14600,20300,CONT_DIF_P,* +V 15200,20300,CONT_DIF_P,* +V 14000,20300,CONT_DIF_P,* +V 14600,19900,CONT_VIA,* +V 15200,19900,CONT_DIF_P,* +V 14000,19900,CONT_DIF_P,* +V 14600,16300,CONT_VIA,* +V 14600,18700,CONT_VIA,* +V 14600,17500,CONT_VIA,* +V 14600,15100,CONT_VIA,* +V 15200,16700,CONT_DIF_P,* +V 15800,16700,CONT_DIF_P,* +V 15800,17100,CONT_DIF_P,* +V 15800,15900,CONT_DIF_P,* +V 15200,15900,CONT_DIF_P,* +V 15200,16300,CONT_DIF_P,* +V 15800,18300,CONT_DIF_P,* +V 15800,17900,CONT_DIF_P,* +V 15200,17900,CONT_DIF_P,* +V 15200,17100,CONT_DIF_P,* +V 15200,17500,CONT_DIF_P,* +V 15200,19500,CONT_DIF_P,* +V 15800,19100,CONT_DIF_P,* +V 15200,19100,CONT_DIF_P,* +V 15200,18700,CONT_DIF_P,* +V 15200,18300,CONT_DIF_P,* +V 15800,19500,CONT_DIF_P,* +V 15800,15500,CONT_DIF_P,* +V 15200,15500,CONT_DIF_P,* +V 14600,17100,CONT_DIF_P,* +V 14600,16700,CONT_DIF_P,* +V 14000,16700,CONT_DIF_P,* +V 14000,17100,CONT_DIF_P,* +V 14000,17500,CONT_DIF_P,* +V 14600,15900,CONT_DIF_P,* +V 14000,15900,CONT_DIF_P,* +V 14000,16300,CONT_DIF_P,* +V 14600,19500,CONT_DIF_P,* +V 14600,19100,CONT_DIF_P,* +V 14000,19100,CONT_DIF_P,* +V 14000,18700,CONT_DIF_P,* +V 14600,18300,CONT_DIF_P,* +V 14000,18300,CONT_DIF_P,* +V 14600,17900,CONT_DIF_P,* +V 14000,17900,CONT_DIF_P,* +V 14000,19500,CONT_DIF_P,* +V 14000,15500,CONT_DIF_P,* +V 14600,15500,CONT_DIF_P,* +V 15200,15100,CONT_DIF_P,* +V 15800,14700,CONT_DIF_P,* +V 15200,14700,CONT_DIF_P,* +V 15800,14300,CONT_DIF_P,* +V 15200,14300,CONT_DIF_P,* +V 14000,14300,CONT_DIF_P,* +V 14000,15100,CONT_DIF_P,* +V 14600,14700,CONT_DIF_P,* +V 14000,14700,CONT_DIF_P,* +V 14600,14300,CONT_DIF_P,* +V 15200,27400,CONT_DIF_N,* +V 15200,27000,CONT_DIF_N,* +V 15200,26600,CONT_DIF_N,* +V 15200,27800,CONT_DIF_N,* +V 15200,25000,CONT_DIF_N,* +V 15200,25400,CONT_DIF_N,* +V 15200,26200,CONT_DIF_N,* +V 15200,25800,CONT_DIF_N,* +V 14000,27000,CONT_DIF_N,* +V 14000,26600,CONT_DIF_N,* +V 14000,26200,CONT_DIF_N,* +V 14000,25800,CONT_DIF_N,* +V 14000,25400,CONT_DIF_N,* +V 14000,27800,CONT_DIF_N,* +V 14000,27400,CONT_DIF_N,* +V 14000,25000,CONT_DIF_N,* +V 14500,13600,CONT_VIA,* +V 15200,13100,CONT_POLY,* +V 15600,13600,CONT_BODY_N,* +V 14200,13600,CONT_BODY_N,* +V 14800,13600,CONT_BODY_N,* +V 13700,13600,CONT_BODY_N,* +V 14600,28700,CONT_BODY_P,* +V 15800,28700,CONT_BODY_P,* +V 14600,26100,CONT_VIA,* +V 14600,27700,CONT_VIA,* +V 14600,25700,CONT_DIF_N,* +V 14600,28100,CONT_DIF_N,* +V 14600,26500,CONT_DIF_N,* +V 14600,27300,CONT_DIF_N,* +V 14600,26900,CONT_DIF_N,* +V 14600,25300,CONT_DIF_N,* +V 14600,24900,CONT_VIA,* +V 15800,28100,CONT_VIA,* +V 15800,24900,CONT_VIA,* +V 15800,26500,CONT_VIA,* +V 15800,25300,CONT_DIF_N,* +V 15800,26900,CONT_DIF_N,* +V 15800,27300,CONT_DIF_N,* +V 15800,25700,CONT_DIF_N,* +V 15800,26100,CONT_DIF_N,* +V 15800,27700,CONT_DIF_N,* +V 11600,21900,CONT_DIF_P,* +V 12200,21900,CONT_DIF_P,* +V 12800,21900,CONT_DIF_P,* +V 13400,21900,CONT_DIF_P,* +V 12200,22500,CONT_BODY_N,* +V 13400,22500,CONT_BODY_N,* +V 13300,23200,CONT_VIA,* +V 12200,23800,CONT_VIA,* +V 13300,23800,CONT_POLY,* +V 13400,24300,CONT_BODY_P,* +V 12200,24300,CONT_BODY_P,* +V 13400,21500,CONT_DIF_P,* +V 12800,21500,CONT_DIF_P,* +V 12200,21500,CONT_DIF_P,* +V 11600,21500,CONT_DIF_P,* +V 12200,21100,CONT_VIA,* +V 13400,21100,CONT_VIA,* +V 12800,21100,CONT_DIF_P,* +V 11600,21100,CONT_DIF_P,* +V 11600,20700,CONT_DIF_P,* +V 12800,20700,CONT_DIF_P,* +V 13400,20700,CONT_DIF_P,* +V 12200,20700,CONT_DIF_P,* +V 13400,20300,CONT_DIF_P,* +V 12200,20300,CONT_DIF_P,* +V 12800,20300,CONT_DIF_P,* +V 11600,20300,CONT_DIF_P,* +V 13400,19900,CONT_VIA,* +V 12200,19900,CONT_VIA,* +V 12800,19900,CONT_DIF_P,* +V 11600,19900,CONT_DIF_P,* +V 13400,16300,CONT_VIA,* +V 13400,17500,CONT_VIA,* +V 13400,18700,CONT_VIA,* +V 12200,16300,CONT_VIA,* +V 12200,18700,CONT_VIA,* +V 12200,17500,CONT_VIA,* +V 13400,15100,CONT_VIA,* +V 12200,15100,CONT_VIA,* +V 12800,16700,CONT_DIF_P,* +V 13400,16700,CONT_DIF_P,* +V 13400,17100,CONT_DIF_P,* +V 13400,15900,CONT_DIF_P,* +V 12800,15900,CONT_DIF_P,* +V 12800,16300,CONT_DIF_P,* +V 13400,18300,CONT_DIF_P,* +V 13400,17900,CONT_DIF_P,* +V 12800,17900,CONT_DIF_P,* +V 12800,17100,CONT_DIF_P,* +V 12800,17500,CONT_DIF_P,* +V 12800,19500,CONT_DIF_P,* +V 13400,19100,CONT_DIF_P,* +V 12800,19100,CONT_DIF_P,* +V 12800,18700,CONT_DIF_P,* +V 12800,18300,CONT_DIF_P,* +V 13400,19500,CONT_DIF_P,* +V 13400,15500,CONT_DIF_P,* +V 12800,15500,CONT_DIF_P,* +V 12200,17100,CONT_DIF_P,* +V 12200,16700,CONT_DIF_P,* +V 11600,16700,CONT_DIF_P,* +V 11600,17100,CONT_DIF_P,* +V 11600,17500,CONT_DIF_P,* +V 12200,15900,CONT_DIF_P,* +V 11600,15900,CONT_DIF_P,* +V 11600,16300,CONT_DIF_P,* +V 12200,19500,CONT_DIF_P,* +V 12200,19100,CONT_DIF_P,* +V 11600,19100,CONT_DIF_P,* +V 11600,18700,CONT_DIF_P,* +V 12200,18300,CONT_DIF_P,* +V 11600,18300,CONT_DIF_P,* +V 12200,17900,CONT_DIF_P,* +V 11600,17900,CONT_DIF_P,* +V 11600,19500,CONT_DIF_P,* +V 11600,15500,CONT_DIF_P,* +V 12200,15500,CONT_DIF_P,* +V 12800,15100,CONT_DIF_P,* +V 13400,14700,CONT_DIF_P,* +V 12800,14700,CONT_DIF_P,* +V 13400,14300,CONT_DIF_P,* +V 12800,14300,CONT_DIF_P,* +V 11600,14300,CONT_DIF_P,* +V 11600,15100,CONT_DIF_P,* +V 12200,14700,CONT_DIF_P,* +V 11600,14700,CONT_DIF_P,* +V 12200,14300,CONT_DIF_P,* +V 12800,27400,CONT_DIF_N,* +V 12800,27000,CONT_DIF_N,* +V 12800,26600,CONT_DIF_N,* +V 12800,27800,CONT_DIF_N,* +V 12800,25000,CONT_DIF_N,* +V 12800,25400,CONT_DIF_N,* +V 12800,26200,CONT_DIF_N,* +V 12800,25800,CONT_DIF_N,* +V 11600,27000,CONT_DIF_N,* +V 11600,26600,CONT_DIF_N,* +V 11600,26200,CONT_DIF_N,* +V 11600,25800,CONT_DIF_N,* +V 11600,25400,CONT_DIF_N,* +V 11600,27800,CONT_DIF_N,* +V 11600,27400,CONT_DIF_N,* +V 11600,25000,CONT_DIF_N,* +V 12100,13600,CONT_VIA,* +V 12800,13100,CONT_POLY,* +V 13200,13600,CONT_BODY_N,* +V 11800,13600,CONT_BODY_N,* +V 12400,13600,CONT_BODY_N,* +V 11300,13600,CONT_BODY_N,* +V 12200,28700,CONT_BODY_P,* +V 13400,28700,CONT_BODY_P,* +V 12200,26100,CONT_VIA,* +V 12200,27700,CONT_VIA,* +V 12200,25700,CONT_DIF_N,* +V 12200,28100,CONT_DIF_N,* +V 12200,26500,CONT_DIF_N,* +V 12200,27300,CONT_DIF_N,* +V 12200,26900,CONT_DIF_N,* +V 12200,25300,CONT_DIF_N,* +V 12200,24900,CONT_VIA,* +V 13400,28100,CONT_VIA,* +V 13400,24900,CONT_VIA,* +V 13400,26500,CONT_VIA,* +V 13400,25300,CONT_DIF_N,* +V 13400,26900,CONT_DIF_N,* +V 13400,27300,CONT_DIF_N,* +V 13400,25700,CONT_DIF_N,* +V 13400,26100,CONT_DIF_N,* +V 13400,27700,CONT_DIF_N,* +V 9200,21900,CONT_DIF_P,* +V 9800,21900,CONT_DIF_P,* +V 10400,21900,CONT_DIF_P,* +V 11000,21900,CONT_DIF_P,* +V 9800,22500,CONT_BODY_N,* +V 11000,22500,CONT_BODY_N,* +V 10900,23200,CONT_VIA,* +V 9800,23800,CONT_VIA,* +V 10900,23800,CONT_POLY,* +V 11000,24300,CONT_BODY_P,* +V 9800,24300,CONT_BODY_P,* +V 11000,21500,CONT_DIF_P,* +V 10400,21500,CONT_DIF_P,* +V 9800,21500,CONT_DIF_P,* +V 9200,21500,CONT_DIF_P,* +V 9800,21100,CONT_VIA,* +V 11000,21100,CONT_VIA,* +V 10400,21100,CONT_DIF_P,* +V 9200,21100,CONT_DIF_P,* +V 9200,20700,CONT_DIF_P,* +V 10400,20700,CONT_DIF_P,* +V 11000,20700,CONT_DIF_P,* +V 9800,20700,CONT_DIF_P,* +V 11000,20300,CONT_DIF_P,* +V 9800,20300,CONT_DIF_P,* +V 10400,20300,CONT_DIF_P,* +V 9200,20300,CONT_DIF_P,* +V 11000,19900,CONT_VIA,* +V 9800,19900,CONT_VIA,* +V 10400,19900,CONT_DIF_P,* +V 9200,19900,CONT_DIF_P,* +V 11000,16300,CONT_VIA,* +V 11000,17500,CONT_VIA,* +V 11000,18700,CONT_VIA,* +V 9800,16300,CONT_VIA,* +V 9800,18700,CONT_VIA,* +V 9800,17500,CONT_VIA,* +V 11000,15100,CONT_VIA,* +V 9800,15100,CONT_VIA,* +V 10400,16700,CONT_DIF_P,* +V 11000,16700,CONT_DIF_P,* +V 11000,17100,CONT_DIF_P,* +V 11000,15900,CONT_DIF_P,* +V 10400,15900,CONT_DIF_P,* +V 10400,16300,CONT_DIF_P,* +V 11000,18300,CONT_DIF_P,* +V 11000,17900,CONT_DIF_P,* +V 10400,17900,CONT_DIF_P,* +V 10400,17100,CONT_DIF_P,* +V 10400,17500,CONT_DIF_P,* +V 10400,19500,CONT_DIF_P,* +V 11000,19100,CONT_DIF_P,* +V 10400,19100,CONT_DIF_P,* +V 10400,18700,CONT_DIF_P,* +V 10400,18300,CONT_DIF_P,* +V 11000,19500,CONT_DIF_P,* +V 11000,15500,CONT_DIF_P,* +V 10400,15500,CONT_DIF_P,* +V 9800,17100,CONT_DIF_P,* +V 9800,16700,CONT_DIF_P,* +V 9200,16700,CONT_DIF_P,* +V 9200,17100,CONT_DIF_P,* +V 9200,17500,CONT_DIF_P,* +V 9800,15900,CONT_DIF_P,* +V 9200,15900,CONT_DIF_P,* +V 9200,16300,CONT_DIF_P,* +V 9800,19500,CONT_DIF_P,* +V 9800,19100,CONT_DIF_P,* +V 9200,19100,CONT_DIF_P,* +V 9200,18700,CONT_DIF_P,* +V 9800,18300,CONT_DIF_P,* +V 9200,18300,CONT_DIF_P,* +V 9800,17900,CONT_DIF_P,* +V 9200,17900,CONT_DIF_P,* +V 9200,19500,CONT_DIF_P,* +V 9200,15500,CONT_DIF_P,* +V 9800,15500,CONT_DIF_P,* +V 10400,15100,CONT_DIF_P,* +V 11000,14700,CONT_DIF_P,* +V 10400,14700,CONT_DIF_P,* +V 11000,14300,CONT_DIF_P,* +V 10400,14300,CONT_DIF_P,* +V 9200,14300,CONT_DIF_P,* +V 9200,15100,CONT_DIF_P,* +V 9800,14700,CONT_DIF_P,* +V 9200,14700,CONT_DIF_P,* +V 9800,14300,CONT_DIF_P,* +V 10400,27400,CONT_DIF_N,* +V 10400,27000,CONT_DIF_N,* +V 10400,26600,CONT_DIF_N,* +V 10400,27800,CONT_DIF_N,* +V 10400,25000,CONT_DIF_N,* +V 10400,25400,CONT_DIF_N,* +V 10400,26200,CONT_DIF_N,* +V 10400,25800,CONT_DIF_N,* +V 9200,27000,CONT_DIF_N,* +V 9200,26600,CONT_DIF_N,* +V 9200,26200,CONT_DIF_N,* +V 9200,25800,CONT_DIF_N,* +V 9200,25400,CONT_DIF_N,* +V 9200,27800,CONT_DIF_N,* +V 9200,27400,CONT_DIF_N,* +V 9200,25000,CONT_DIF_N,* +V 9700,13600,CONT_VIA,* +V 10400,13100,CONT_POLY,* +V 10800,13600,CONT_BODY_N,* +V 9400,13600,CONT_BODY_N,* +V 10000,13600,CONT_BODY_N,* +V 8900,13600,CONT_BODY_N,* +V 9800,28700,CONT_BODY_P,* +V 11000,28700,CONT_BODY_P,* +V 9800,26100,CONT_VIA,* +V 9800,27700,CONT_VIA,* +V 9800,25700,CONT_DIF_N,* +V 9800,28100,CONT_DIF_N,* +V 9800,26500,CONT_DIF_N,* +V 9800,27300,CONT_DIF_N,* +V 9800,26900,CONT_DIF_N,* +V 9800,25300,CONT_DIF_N,* +V 9800,24900,CONT_VIA,* +V 11000,28100,CONT_VIA,* +V 11000,24900,CONT_VIA,* +V 11000,26500,CONT_VIA,* +V 11000,25300,CONT_DIF_N,* +V 11000,26900,CONT_DIF_N,* +V 11000,27300,CONT_DIF_N,* +V 11000,25700,CONT_DIF_N,* +V 11000,26100,CONT_DIF_N,* +V 11000,27700,CONT_DIF_N,* +V 6800,21900,CONT_DIF_P,* +V 7400,21900,CONT_DIF_P,* +V 8000,21900,CONT_DIF_P,* +V 8600,21900,CONT_DIF_P,* +V 7400,22500,CONT_BODY_N,* +V 8600,22500,CONT_BODY_N,* +V 8500,23200,CONT_VIA,* +V 7400,23800,CONT_VIA,* +V 8500,23800,CONT_POLY,* +V 8600,24300,CONT_BODY_P,* +V 7400,24300,CONT_BODY_P,* +V 8600,21500,CONT_DIF_P,* +V 8000,21500,CONT_DIF_P,* +V 7400,21500,CONT_DIF_P,* +V 6800,21500,CONT_DIF_P,* +V 7400,21100,CONT_VIA,* +V 8600,21100,CONT_VIA,* +V 8000,21100,CONT_DIF_P,* +V 6800,21100,CONT_DIF_P,* +V 6800,20700,CONT_DIF_P,* +V 8000,20700,CONT_DIF_P,* +V 8600,20700,CONT_DIF_P,* +V 7400,20700,CONT_DIF_P,* +V 8600,20300,CONT_DIF_P,* +V 7400,20300,CONT_DIF_P,* +V 8000,20300,CONT_DIF_P,* +V 6800,20300,CONT_DIF_P,* +V 8600,19900,CONT_VIA,* +V 7400,19900,CONT_VIA,* +V 8000,19900,CONT_DIF_P,* +V 6800,19900,CONT_DIF_P,* +V 8600,16300,CONT_VIA,* +V 8600,17500,CONT_VIA,* +V 8600,18700,CONT_VIA,* +V 7400,16300,CONT_VIA,* +V 7400,18700,CONT_VIA,* +V 7400,17500,CONT_VIA,* +V 8600,15100,CONT_VIA,* +V 7400,15100,CONT_VIA,* +V 8000,16700,CONT_DIF_P,* +V 8600,16700,CONT_DIF_P,* +V 8600,17100,CONT_DIF_P,* +V 8600,15900,CONT_DIF_P,* +V 8000,15900,CONT_DIF_P,* +V 8000,16300,CONT_DIF_P,* +V 8600,18300,CONT_DIF_P,* +V 8600,17900,CONT_DIF_P,* +V 8000,17900,CONT_DIF_P,* +V 8000,17100,CONT_DIF_P,* +V 8000,17500,CONT_DIF_P,* +V 8000,19500,CONT_DIF_P,* +V 8600,19100,CONT_DIF_P,* +V 8000,19100,CONT_DIF_P,* +V 8000,18700,CONT_DIF_P,* +V 8000,18300,CONT_DIF_P,* +V 8600,19500,CONT_DIF_P,* +V 8600,15500,CONT_DIF_P,* +V 8000,15500,CONT_DIF_P,* +V 7400,17100,CONT_DIF_P,* +V 7400,16700,CONT_DIF_P,* +V 6800,16700,CONT_DIF_P,* +V 6800,17100,CONT_DIF_P,* +V 6800,17500,CONT_DIF_P,* +V 7400,15900,CONT_DIF_P,* +V 6800,15900,CONT_DIF_P,* +V 6800,16300,CONT_DIF_P,* +V 7400,19500,CONT_DIF_P,* +V 7400,19100,CONT_DIF_P,* +V 6800,19100,CONT_DIF_P,* +V 6800,18700,CONT_DIF_P,* +V 7400,18300,CONT_DIF_P,* +V 6800,18300,CONT_DIF_P,* +V 7400,17900,CONT_DIF_P,* +V 6800,17900,CONT_DIF_P,* +V 6800,19500,CONT_DIF_P,* +V 6800,15500,CONT_DIF_P,* +V 7400,15500,CONT_DIF_P,* +V 8000,15100,CONT_DIF_P,* +V 8600,14700,CONT_DIF_P,* +V 8000,14700,CONT_DIF_P,* +V 8600,14300,CONT_DIF_P,* +V 8000,14300,CONT_DIF_P,* +V 6800,14300,CONT_DIF_P,* +V 6800,15100,CONT_DIF_P,* +V 7400,14700,CONT_DIF_P,* +V 6800,14700,CONT_DIF_P,* +V 7400,14300,CONT_DIF_P,* +V 8000,27400,CONT_DIF_N,* +V 8000,27000,CONT_DIF_N,* +V 8000,26600,CONT_DIF_N,* +V 8000,27800,CONT_DIF_N,* +V 8000,25000,CONT_DIF_N,* +V 8000,25400,CONT_DIF_N,* +V 8000,26200,CONT_DIF_N,* +V 8000,25800,CONT_DIF_N,* +V 6800,27000,CONT_DIF_N,* +V 6800,26600,CONT_DIF_N,* +V 6800,26200,CONT_DIF_N,* +V 6800,25800,CONT_DIF_N,* +V 6800,25400,CONT_DIF_N,* +V 6800,27800,CONT_DIF_N,* +V 6800,27400,CONT_DIF_N,* +V 6800,25000,CONT_DIF_N,* +V 7300,13600,CONT_VIA,* +V 8000,13100,CONT_POLY,* +V 8400,13600,CONT_BODY_N,* +V 7000,13600,CONT_BODY_N,* +V 7600,13600,CONT_BODY_N,* +V 6500,13600,CONT_BODY_N,* +V 7400,28700,CONT_BODY_P,* +V 8600,28700,CONT_BODY_P,* +V 7400,26100,CONT_VIA,* +V 7400,27700,CONT_VIA,* +V 7400,25700,CONT_DIF_N,* +V 7400,28100,CONT_DIF_N,* +V 7400,26500,CONT_DIF_N,* +V 7400,27300,CONT_DIF_N,* +V 7400,26900,CONT_DIF_N,* +V 7400,25300,CONT_DIF_N,* +V 7400,24900,CONT_VIA,* +V 8600,28100,CONT_VIA,* +V 8600,24900,CONT_VIA,* +V 8600,26500,CONT_VIA,* +V 8600,25300,CONT_DIF_N,* +V 8600,26900,CONT_DIF_N,* +V 8600,27300,CONT_DIF_N,* +V 8600,25700,CONT_DIF_N,* +V 8600,26100,CONT_DIF_N,* +V 8600,27700,CONT_DIF_N,* +V 4400,21900,CONT_DIF_P,* +V 5000,21900,CONT_DIF_P,* +V 5600,21900,CONT_DIF_P,* +V 6200,21900,CONT_DIF_P,* +V 5000,22500,CONT_BODY_N,* +V 6200,22500,CONT_BODY_N,* +V 6100,23200,CONT_VIA,* +V 5000,23800,CONT_VIA,* +V 6100,23800,CONT_POLY,* +V 6200,24300,CONT_BODY_P,* +V 5000,24300,CONT_BODY_P,* +V 6200,21500,CONT_DIF_P,* +V 5600,21500,CONT_DIF_P,* +V 5000,21500,CONT_DIF_P,* +V 4400,21500,CONT_DIF_P,* +V 5000,21100,CONT_VIA,* +V 6200,21100,CONT_VIA,* +V 5600,21100,CONT_DIF_P,* +V 4400,21100,CONT_DIF_P,* +V 4400,20700,CONT_DIF_P,* +V 5600,20700,CONT_DIF_P,* +V 6200,20700,CONT_DIF_P,* +V 5000,20700,CONT_DIF_P,* +V 6200,20300,CONT_DIF_P,* +V 5000,20300,CONT_DIF_P,* +V 5600,20300,CONT_DIF_P,* +V 4400,20300,CONT_DIF_P,* +V 6200,19900,CONT_VIA,* +V 5000,19900,CONT_VIA,* +V 5600,19900,CONT_DIF_P,* +V 4400,19900,CONT_DIF_P,* +V 6200,16300,CONT_VIA,* +V 6200,17500,CONT_VIA,* +V 6200,18700,CONT_VIA,* +V 5000,16300,CONT_VIA,* +V 5000,18700,CONT_VIA,* +V 5000,17500,CONT_VIA,* +V 6200,15100,CONT_VIA,* +V 5000,15100,CONT_VIA,* +V 5600,16700,CONT_DIF_P,* +V 6200,16700,CONT_DIF_P,* +V 6200,17100,CONT_DIF_P,* +V 6200,15900,CONT_DIF_P,* +V 5600,15900,CONT_DIF_P,* +V 5600,16300,CONT_DIF_P,* +V 6200,18300,CONT_DIF_P,* +V 6200,17900,CONT_DIF_P,* +V 5600,17900,CONT_DIF_P,* +V 5600,17100,CONT_DIF_P,* +V 5600,17500,CONT_DIF_P,* +V 5600,19500,CONT_DIF_P,* +V 6200,19100,CONT_DIF_P,* +V 5600,19100,CONT_DIF_P,* +V 5600,18700,CONT_DIF_P,* +V 5600,18300,CONT_DIF_P,* +V 6200,19500,CONT_DIF_P,* +V 6200,15500,CONT_DIF_P,* +V 5600,15500,CONT_DIF_P,* +V 5000,17100,CONT_DIF_P,* +V 5000,16700,CONT_DIF_P,* +V 4400,16700,CONT_DIF_P,* +V 4400,17100,CONT_DIF_P,* +V 4400,17500,CONT_DIF_P,* +V 5000,15900,CONT_DIF_P,* +V 4400,15900,CONT_DIF_P,* +V 4400,16300,CONT_DIF_P,* +V 5000,19500,CONT_DIF_P,* +V 5000,19100,CONT_DIF_P,* +V 4400,19100,CONT_DIF_P,* +V 4400,18700,CONT_DIF_P,* +V 5000,18300,CONT_DIF_P,* +V 4400,18300,CONT_DIF_P,* +V 5000,17900,CONT_DIF_P,* +V 4400,17900,CONT_DIF_P,* +V 4400,19500,CONT_DIF_P,* +V 4400,15500,CONT_DIF_P,* +V 5000,15500,CONT_DIF_P,* +V 5600,15100,CONT_DIF_P,* +V 6200,14700,CONT_DIF_P,* +V 5600,14700,CONT_DIF_P,* +V 6200,14300,CONT_DIF_P,* +V 5600,14300,CONT_DIF_P,* +V 4400,14300,CONT_DIF_P,* +V 4400,15100,CONT_DIF_P,* +V 5000,14700,CONT_DIF_P,* +V 4400,14700,CONT_DIF_P,* +V 5000,14300,CONT_DIF_P,* +V 5600,27400,CONT_DIF_N,* +V 5600,27000,CONT_DIF_N,* +V 5600,26600,CONT_DIF_N,* +V 5600,27800,CONT_DIF_N,* +V 5600,25000,CONT_DIF_N,* +V 5600,25400,CONT_DIF_N,* +V 5600,26200,CONT_DIF_N,* +V 5600,25800,CONT_DIF_N,* +V 4400,27000,CONT_DIF_N,* +V 4400,26600,CONT_DIF_N,* +V 4400,26200,CONT_DIF_N,* +V 4400,25800,CONT_DIF_N,* +V 4400,25400,CONT_DIF_N,* +V 4400,27800,CONT_DIF_N,* +V 4400,27400,CONT_DIF_N,* +V 4400,25000,CONT_DIF_N,* +V 4900,13600,CONT_VIA,* +V 5600,13100,CONT_POLY,* +V 6000,13600,CONT_BODY_N,* +V 4600,13600,CONT_BODY_N,* +V 5200,13600,CONT_BODY_N,* +V 4100,13600,CONT_BODY_N,* +V 5000,28700,CONT_BODY_P,* +V 6200,28700,CONT_BODY_P,* +V 5000,26100,CONT_VIA,* +V 5000,27700,CONT_VIA,* +V 5000,25700,CONT_DIF_N,* +V 5000,28100,CONT_DIF_N,* +V 5000,26500,CONT_DIF_N,* +V 5000,27300,CONT_DIF_N,* +V 5000,26900,CONT_DIF_N,* +V 5000,25300,CONT_DIF_N,* +V 5000,24900,CONT_VIA,* +V 6200,28100,CONT_VIA,* +V 6200,24900,CONT_VIA,* +V 6200,26500,CONT_VIA,* +V 6200,25300,CONT_DIF_N,* +V 6200,26900,CONT_DIF_N,* +V 6200,27300,CONT_DIF_N,* +V 6200,25700,CONT_DIF_N,* +V 6200,26100,CONT_DIF_N,* +V 6200,27700,CONT_DIF_N,* +V 2000,21900,CONT_DIF_P,* +V 2600,21900,CONT_DIF_P,* +V 3200,21900,CONT_DIF_P,* +V 3800,21900,CONT_DIF_P,* +V 2600,22500,CONT_BODY_N,* +V 3800,22500,CONT_BODY_N,* +V 3700,23200,CONT_VIA,* +V 2600,23800,CONT_VIA,* +V 3700,23800,CONT_POLY,* +V 3800,24300,CONT_BODY_P,* +V 2600,24300,CONT_BODY_P,* +V 3800,21500,CONT_DIF_P,* +V 3200,21500,CONT_DIF_P,* +V 2600,21500,CONT_DIF_P,* +V 2000,21500,CONT_DIF_P,* +V 2600,21100,CONT_VIA,* +V 3800,21100,CONT_VIA,* +V 3200,21100,CONT_DIF_P,* +V 2000,21100,CONT_DIF_P,* +V 2000,20700,CONT_DIF_P,* +V 3200,20700,CONT_DIF_P,* +V 3800,20700,CONT_DIF_P,* +V 2600,20700,CONT_DIF_P,* +V 3800,20300,CONT_DIF_P,* +V 2600,20300,CONT_DIF_P,* +V 3200,20300,CONT_DIF_P,* +V 2000,20300,CONT_DIF_P,* +V 3800,19900,CONT_VIA,* +V 2600,19900,CONT_VIA,* +V 3200,19900,CONT_DIF_P,* +V 2000,19900,CONT_DIF_P,* +V 3800,16300,CONT_VIA,* +V 3800,17500,CONT_VIA,* +V 3800,18700,CONT_VIA,* +V 2600,16300,CONT_VIA,* +V 2600,18700,CONT_VIA,* +V 2600,17500,CONT_VIA,* +V 3800,15100,CONT_VIA,* +V 2600,15100,CONT_VIA,* +V 3200,16700,CONT_DIF_P,* +V 3800,16700,CONT_DIF_P,* +V 3800,17100,CONT_DIF_P,* +V 3800,15900,CONT_DIF_P,* +V 3200,15900,CONT_DIF_P,* +V 3200,16300,CONT_DIF_P,* +V 3800,18300,CONT_DIF_P,* +V 3800,17900,CONT_DIF_P,* +V 3200,17900,CONT_DIF_P,* +V 3200,17100,CONT_DIF_P,* +V 3200,17500,CONT_DIF_P,* +V 3200,19500,CONT_DIF_P,* +V 3800,19100,CONT_DIF_P,* +V 3200,19100,CONT_DIF_P,* +V 3200,18700,CONT_DIF_P,* +V 3200,18300,CONT_DIF_P,* +V 3800,19500,CONT_DIF_P,* +V 3800,15500,CONT_DIF_P,* +V 3200,15500,CONT_DIF_P,* +V 2600,17100,CONT_DIF_P,* +V 2600,16700,CONT_DIF_P,* +V 2000,16700,CONT_DIF_P,* +V 2000,17100,CONT_DIF_P,* +V 2000,17500,CONT_DIF_P,* +V 2600,15900,CONT_DIF_P,* +V 2000,15900,CONT_DIF_P,* +V 2000,16300,CONT_DIF_P,* +V 2600,19500,CONT_DIF_P,* +V 2600,19100,CONT_DIF_P,* +V 2000,19100,CONT_DIF_P,* +V 2000,18700,CONT_DIF_P,* +V 2600,18300,CONT_DIF_P,* +V 2000,18300,CONT_DIF_P,* +V 2600,17900,CONT_DIF_P,* +V 2000,17900,CONT_DIF_P,* +V 2000,19500,CONT_DIF_P,* +V 2000,15500,CONT_DIF_P,* +V 2600,15500,CONT_DIF_P,* +V 3200,15100,CONT_DIF_P,* +V 3800,14700,CONT_DIF_P,* +V 3200,14700,CONT_DIF_P,* +V 3800,14300,CONT_DIF_P,* +V 3200,14300,CONT_DIF_P,* +V 2000,14300,CONT_DIF_P,* +V 2000,15100,CONT_DIF_P,* +V 2600,14700,CONT_DIF_P,* +V 2000,14700,CONT_DIF_P,* +V 2600,14300,CONT_DIF_P,* +V 3200,27400,CONT_DIF_N,* +V 3200,27000,CONT_DIF_N,* +V 3200,26600,CONT_DIF_N,* +V 3200,27800,CONT_DIF_N,* +V 3200,25000,CONT_DIF_N,* +V 3200,25400,CONT_DIF_N,* +V 3200,26200,CONT_DIF_N,* +V 3200,25800,CONT_DIF_N,* +V 2000,27000,CONT_DIF_N,* +V 2000,26600,CONT_DIF_N,* +V 2000,26200,CONT_DIF_N,* +V 2000,25800,CONT_DIF_N,* +V 2000,25400,CONT_DIF_N,* +V 2000,27800,CONT_DIF_N,* +V 2000,27400,CONT_DIF_N,* +V 2000,25000,CONT_DIF_N,* +V 2500,13600,CONT_VIA,* +V 3200,13100,CONT_POLY,* +V 3600,13600,CONT_BODY_N,* +V 2200,13600,CONT_BODY_N,* +V 2800,13600,CONT_BODY_N,* +V 1700,13600,CONT_BODY_N,* +V 2600,28700,CONT_BODY_P,* +V 3800,28700,CONT_BODY_P,* +V 2600,26100,CONT_VIA,* +V 2600,27700,CONT_VIA,* +V 2600,25700,CONT_DIF_N,* +V 2600,28100,CONT_DIF_N,* +V 2600,26500,CONT_DIF_N,* +V 2600,27300,CONT_DIF_N,* +V 2600,26900,CONT_DIF_N,* +V 2600,25300,CONT_DIF_N,* +V 2600,24900,CONT_VIA,* +V 3800,28100,CONT_VIA,* +V 3800,24900,CONT_VIA,* +V 3800,26500,CONT_VIA,* +V 3800,25300,CONT_DIF_N,* +V 3800,26900,CONT_DIF_N,* +V 3800,27300,CONT_DIF_N,* +V 3800,25700,CONT_DIF_N,* +V 3800,26100,CONT_DIF_N,* +V 3800,27700,CONT_DIF_N,* +V 3600,9800,CONT_BODY_N,* +V 3600,5100,CONT_BODY_N,* +V 3600,10800,CONT_BODY_N,* +V 3600,11200,CONT_BODY_N,* +V 3600,11600,CONT_BODY_N,* +V 3600,12000,CONT_BODY_N,* +V 3600,9000,CONT_BODY_N,* +V 3600,8200,CONT_BODY_N,* +V 3600,7800,CONT_BODY_N,* +V 3600,7400,CONT_BODY_N,* +V 3600,7000,CONT_BODY_N,* +V 3600,6300,CONT_BODY_N,* +V 3600,5900,CONT_BODY_N,* +V 3600,5500,CONT_BODY_N,* +V 3600,10400,CONT_BODY_N,* +V 3600,9400,CONT_BODY_N,* +V 3600,8600,CONT_BODY_N,* +V 3600,-200,CONT_BODY_P,* +V 3600,4000,CONT_BODY_P,* +V 3600,3100,CONT_BODY_P,* +V 3600,2700,CONT_BODY_P,* +V 3600,1900,CONT_BODY_P,* +V 3600,1500,CONT_BODY_P,* +V 3600,1100,CONT_BODY_P,* +V 3600,700,CONT_BODY_P,* +V 3600,300,CONT_BODY_P,* +V 3600,3500,CONT_VIA,* +V 3600,2300,CONT_VIA,* +V 3600,6600,CONT_VIA,* +V 8400,3500,CONT_VIA,* +V 7200,9000,CONT_VIA,* +V 7200,10200,CONT_VIA,* +V 7200,6600,CONT_VIA,* +V 8400,2300,CONT_VIA,* +V 8400,6600,CONT_VIA,* +V 8400,10200,CONT_VIA,* +V 8400,9000,CONT_VIA,* +V 8400,7400,CONT_VIA,* +V 6000,6600,CONT_VIA,* +V 6000,7400,CONT_VIA,* +V 6000,9000,CONT_VIA,* +V 6000,10200,CONT_VIA,* +V 6000,3500,CONT_VIA,* +V 6000,2300,CONT_VIA,* +V 7200,2300,CONT_VIA,* +V 7200,7400,CONT_VIA,* +V 7800,1600,CONT_VIA,* +V 4200,3500,CONT_VIA,* +V 4200,10200,CONT_VIA,* +V 4200,9000,CONT_VIA,* +V 4200,7400,CONT_VIA,* +V 4200,6600,CONT_VIA,* +V 4200,2300,CONT_VIA,* +V 4900,5300,CONT_POLY,* +V 7200,4600,CONT_POLY,* +V 8400,4000,CONT_BODY_P,* +V 6000,4000,CONT_BODY_P,* +V 7600,4000,CONT_BODY_P,* +V 4200,4000,CONT_BODY_P,* +V 7200,-200,CONT_BODY_P,* +V 6000,-200,CONT_BODY_P,* +V 4200,-200,CONT_BODY_P,* +V 8400,-200,CONT_BODY_P,* +V 7200,12000,CONT_BODY_N,* +V 6400,5100,CONT_BODY_N,* +V 6800,5100,CONT_BODY_N,* +V 8400,5100,CONT_BODY_N,* +V 6000,5100,CONT_BODY_N,* +V 6100,12000,CONT_BODY_N,* +V 4200,5100,CONT_BODY_N,* +V 7800,9000,CONT_DIF_P,* +V 7800,10600,CONT_DIF_P,* +V 7800,11000,CONT_DIF_P,* +V 7800,5800,CONT_DIF_P,* +V 7800,8200,CONT_DIF_P,* +V 7800,8600,CONT_DIF_P,* +V 7800,11400,CONT_DIF_P,* +V 7800,7400,CONT_DIF_P,* +V 6600,6200,CONT_DIF_P,* +V 7800,6200,CONT_DIF_P,* +V 7800,9400,CONT_DIF_P,* +V 7800,9800,CONT_DIF_P,* +V 7800,6600,CONT_DIF_P,* +V 7800,7000,CONT_DIF_P,* +V 7800,10200,CONT_DIF_P,* +V 7800,7800,CONT_DIF_P,* +V 8400,7800,CONT_DIF_P,* +V 6600,10600,CONT_DIF_P,* +V 6600,11000,CONT_DIF_P,* +V 6600,5800,CONT_DIF_P,* +V 6600,8200,CONT_DIF_P,* +V 6600,8600,CONT_DIF_P,* +V 6600,11400,CONT_DIF_P,* +V 6600,7400,CONT_DIF_P,* +V 8400,11400,CONT_DIF_P,* +V 6600,9400,CONT_DIF_P,* +V 6600,9800,CONT_DIF_P,* +V 6600,6600,CONT_DIF_P,* +V 6600,7000,CONT_DIF_P,* +V 6600,10200,CONT_DIF_P,* +V 6600,7800,CONT_DIF_P,* +V 6600,9000,CONT_DIF_P,* +V 7200,8600,CONT_DIF_P,* +V 8400,11000,CONT_DIF_P,* +V 8400,10600,CONT_DIF_P,* +V 8400,9800,CONT_DIF_P,* +V 8400,7000,CONT_DIF_P,* +V 8400,5800,CONT_DIF_P,* +V 8400,6200,CONT_DIF_P,* +V 8400,8600,CONT_DIF_P,* +V 6000,5800,CONT_DIF_P,* +V 8400,8200,CONT_DIF_P,* +V 8400,9400,CONT_DIF_P,* +V 7200,10600,CONT_DIF_P,* +V 7200,11000,CONT_DIF_P,* +V 7200,7800,CONT_DIF_P,* +V 7200,8200,CONT_DIF_P,* +V 7200,11400,CONT_DIF_P,* +V 6000,10600,CONT_DIF_P,* +V 7200,6200,CONT_DIF_P,* +V 7200,5800,CONT_DIF_P,* +V 7200,7000,CONT_DIF_P,* +V 7200,9800,CONT_DIF_P,* +V 7200,9400,CONT_DIF_P,* +V 6000,6200,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 5400,11000,CONT_DIF_P,* +V 6000,9400,CONT_DIF_P,* +V 6000,9800,CONT_DIF_P,* +V 6000,11000,CONT_DIF_P,* +V 6000,7800,CONT_DIF_P,* +V 6000,8200,CONT_DIF_P,* +V 6000,11400,CONT_DIF_P,* +V 6000,8600,CONT_DIF_P,* +V 5400,10600,CONT_DIF_P,* +V 5400,9400,CONT_DIF_P,* +V 5400,9800,CONT_DIF_P,* +V 5400,6600,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 5400,7800,CONT_DIF_P,* +V 5400,10200,CONT_DIF_P,* +V 5400,9000,CONT_DIF_P,* +V 5400,5800,CONT_DIF_P,* +V 5400,8200,CONT_DIF_P,* +V 5400,8600,CONT_DIF_P,* +V 5400,11400,CONT_DIF_P,* +V 5400,7400,CONT_DIF_P,* +V 5400,6200,CONT_DIF_P,* +V 4800,7000,CONT_DIF_P,* +V 4800,7800,CONT_DIF_P,* +V 4800,9000,CONT_DIF_P,* +V 4800,8600,CONT_DIF_P,* +V 4800,11400,CONT_DIF_P,* +V 4800,7400,CONT_DIF_P,* +V 4800,6200,CONT_DIF_P,* +V 4800,9800,CONT_DIF_P,* +V 4800,10600,CONT_DIF_P,* +V 4800,6600,CONT_DIF_P,* +V 4800,11000,CONT_DIF_P,* +V 4800,8200,CONT_DIF_P,* +V 4800,5800,CONT_DIF_P,* +V 4800,10200,CONT_DIF_P,* +V 4800,9400,CONT_DIF_P,* +V 4200,11000,CONT_DIF_P,* +V 4200,9800,CONT_DIF_P,* +V 4200,5800,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 4200,6200,CONT_DIF_P,* +V 4200,9400,CONT_DIF_P,* +V 4200,10600,CONT_DIF_P,* +V 4200,8600,CONT_DIF_P,* +V 4200,11400,CONT_DIF_P,* +V 4200,8200,CONT_DIF_P,* +V 4200,7800,CONT_DIF_P,* +V 7800,2100,CONT_DIF_N,* +V 6600,2900,CONT_DIF_N,* +V 7200,2800,CONT_DIF_N,* +V 7200,3300,CONT_DIF_N,* +V 7800,2500,CONT_DIF_N,* +V 7200,700,CONT_DIF_N,* +V 7800,3300,CONT_DIF_N,* +V 7800,2900,CONT_DIF_N,* +V 6600,2500,CONT_DIF_N,* +V 6600,2100,CONT_DIF_N,* +V 6600,3300,CONT_DIF_N,* +V 6000,700,CONT_DIF_N,* +V 8400,1500,CONT_DIF_N,* +V 8400,1100,CONT_DIF_N,* +V 8400,700,CONT_DIF_N,* +V 8400,3100,CONT_DIF_N,* +V 8400,2700,CONT_DIF_N,* +V 8400,1900,CONT_DIF_N,* +V 7200,1900,CONT_DIF_N,* +V 5400,2500,CONT_DIF_N,* +V 7200,1100,CONT_DIF_N,* +V 7200,1500,CONT_DIF_N,* +V 6000,3100,CONT_DIF_N,* +V 6000,2700,CONT_DIF_N,* +V 6000,1900,CONT_DIF_N,* +V 6000,1500,CONT_DIF_N,* +V 6000,1100,CONT_DIF_N,* +V 5400,3300,CONT_DIF_N,* +V 5400,2900,CONT_DIF_N,* +V 5400,900,CONT_DIF_N,* +V 5400,1300,CONT_DIF_N,* +V 5400,1700,CONT_DIF_N,* +V 5400,2100,CONT_DIF_N,* +V 7800,700,CONT_DIF_N,* +V 4800,2100,CONT_DIF_N,* +V 4800,2500,CONT_DIF_N,* +V 4800,900,CONT_DIF_N,* +V 4800,1300,CONT_DIF_N,* +V 4800,1700,CONT_DIF_N,* +V 4800,3300,CONT_DIF_N,* +V 4800,2900,CONT_DIF_N,* +V 4200,1100,CONT_DIF_N,* +V 4200,1500,CONT_DIF_N,* +V 4200,1900,CONT_DIF_N,* +V 4200,2700,CONT_DIF_N,* +V 4200,3100,CONT_DIF_N,* +V 4200,700,CONT_DIF_N,* +V 7800,1200,CONT_DIF_N,* +V 4700,300,CONT_POLY,* +V 4700,-700,CONT_VIA,* +V 6600,1600,CONT_VIA,* +V 6600,1200,CONT_DIF_N,* +V 6600,700,CONT_DIF_N,* +V 6400,4000,CONT_BODY_P,* +V 6800,4000,CONT_BODY_P,* +V 8000,4000,CONT_BODY_P,* +V 8000,-200,CONT_BODY_P,* +V 7600,-200,CONT_BODY_P,* +V 6800,-200,CONT_BODY_P,* +V 6400,-200,CONT_BODY_P,* +V 5600,-200,CONT_BODY_P,* +V 5200,-200,CONT_BODY_P,* +V 4600,12000,CONT_BODY_N,* +V 4200,12000,CONT_BODY_N,* +V 5100,12000,CONT_BODY_N,* +V 5600,12000,CONT_BODY_N,* +V 8400,12000,CONT_BODY_N,* +V 7600,5100,CONT_BODY_N,* +V 8000,5100,CONT_BODY_N,* +V 9000,10000,CONT_VIA,* +V 9000,7500,CONT_VIA,* +V 9000,8700,CONT_VIA,* +V 9000,6700,CONT_VIA,* +V 9000,5100,CONT_BODY_N,* +V 9000,11200,CONT_BODY_N,* +V 9000,6300,CONT_BODY_N,* +V 9000,5900,CONT_BODY_N,* +V 9000,12000,CONT_BODY_N,* +V 9000,9500,CONT_BODY_N,* +V 9000,10400,CONT_BODY_N,* +V 9000,5500,CONT_BODY_N,* +V 9000,9100,CONT_BODY_N,* +V 9000,8300,CONT_BODY_N,* +V 9000,10800,CONT_BODY_N,* +V 9000,11600,CONT_BODY_N,* +V 9000,7900,CONT_BODY_N,* +V 9000,7100,CONT_BODY_N,* +V 9000,3600,CONT_VIA,* +V 9000,2400,CONT_VIA,* +V 9000,3200,CONT_BODY_P,* +V 9000,800,CONT_BODY_P,* +V 9000,300,CONT_BODY_P,* +V 9000,4000,CONT_BODY_P,* +V 9000,1200,CONT_BODY_P,* +V 9000,1600,CONT_BODY_P,* +V 9000,2000,CONT_BODY_P,* +V 9000,2800,CONT_BODY_P,* +V 9000,-200,CONT_BODY_P,* +V 16400,27900,CONT_VIA,* +V 16100,24300,CONT_VIA,* +V 16400,25900,CONT_VIA,* +V 15800,29200,CONT_VIA,* +V 16400,29200,CONT_VIA,* +V 16400,23200,CONT_VIA,* +V 16900,23200,CONT_VIA,* +V 1200,28700,CONT_BODY_P,* +V 16400,24700,CONT_BODY_P,* +V 16400,25100,CONT_BODY_P,* +V 16400,25500,CONT_BODY_P,* +V 16400,24300,CONT_BODY_P,* +V 1200,24300,CONT_BODY_P,* +V 16400,28700,CONT_BODY_P,* +V 16400,28300,CONT_BODY_P,* +V 16400,27500,CONT_BODY_P,* +V 16400,27100,CONT_BODY_P,* +V 16400,26700,CONT_BODY_P,* +V 16400,26300,CONT_BODY_P,* +V 800,27100,CONT_BODY_P,* +V 800,26700,CONT_BODY_P,* +V 800,26300,CONT_BODY_P,* +V 800,25900,CONT_BODY_P,* +V 800,28700,CONT_BODY_P,* +V 800,24700,CONT_BODY_P,* +V 800,25100,CONT_BODY_P,* +V 800,25500,CONT_BODY_P,* +V 800,24300,CONT_BODY_P,* +V 800,28300,CONT_BODY_P,* +V 800,27900,CONT_BODY_P,* +V 800,27500,CONT_BODY_P,* +V 16400,22000,CONT_BODY_N,* +V 16400,21600,CONT_BODY_N,* +V 16400,21200,CONT_BODY_N,* +V 16400,20800,CONT_BODY_N,* +V 1400,22500,CONT_BODY_N,* +V 16400,20400,CONT_BODY_N,* +V 16400,22500,CONT_BODY_N,* +V 16400,20000,CONT_BODY_N,* +V 800,22500,CONT_BODY_N,* +V 800,20000,CONT_BODY_N,* +V 800,20400,CONT_BODY_N,* +V 800,20800,CONT_BODY_N,* +V 800,21200,CONT_BODY_N,* +V 800,21600,CONT_BODY_N,* +V 800,22000,CONT_BODY_N,* +V 1300,13600,CONT_BODY_N,* +V 16400,18400,CONT_BODY_N,* +V 16400,18000,CONT_BODY_N,* +V 16400,17600,CONT_BODY_N,* +V 16400,19600,CONT_BODY_N,* +V 16400,19200,CONT_BODY_N,* +V 16400,18800,CONT_BODY_N,* +V 16000,13600,CONT_BODY_N,* +V 16400,13600,CONT_BODY_N,* +V 16400,15600,CONT_BODY_N,* +V 16400,15200,CONT_BODY_N,* +V 16400,14800,CONT_BODY_N,* +V 16400,14400,CONT_BODY_N,* +V 16400,14000,CONT_BODY_N,* +V 16400,16400,CONT_BODY_N,* +V 16400,16000,CONT_BODY_N,* +V 16400,16800,CONT_BODY_N,* +V 16400,17200,CONT_BODY_N,* +V 800,13600,CONT_BODY_N,* +V 800,14000,CONT_BODY_N,* +V 800,14400,CONT_BODY_N,* +V 800,14800,CONT_BODY_N,* +V 800,15200,CONT_BODY_N,* +V 800,15600,CONT_BODY_N,* +V 800,19600,CONT_BODY_N,* +V 800,18400,CONT_BODY_N,* +V 800,17600,CONT_BODY_N,* +V 800,18000,CONT_BODY_N,* +V 800,16000,CONT_BODY_N,* +V 800,16400,CONT_BODY_N,* +V 800,17200,CONT_BODY_N,* +V 800,16800,CONT_BODY_N,* +V 800,18800,CONT_BODY_N,* +V 800,19200,CONT_BODY_N,* +V 1400,21900,CONT_DIF_P,* +V 1400,21500,CONT_DIF_P,* +V 1400,21100,CONT_DIF_P,* +V 1400,20700,CONT_DIF_P,* +V 1400,20300,CONT_DIF_P,* +V 1400,16300,CONT_DIF_P,* +V 1400,16700,CONT_DIF_P,* +V 1400,17100,CONT_DIF_P,* +V 1400,19100,CONT_DIF_P,* +V 1400,19500,CONT_DIF_P,* +V 1400,19900,CONT_DIF_P,* +V 1400,14300,CONT_DIF_P,* +V 1400,14700,CONT_DIF_P,* +V 1400,15100,CONT_DIF_P,* +V 1400,15500,CONT_DIF_P,* +V 1400,15900,CONT_DIF_P,* +V 1400,17900,CONT_DIF_P,* +V 1400,17500,CONT_DIF_P,* +V 1400,18300,CONT_DIF_P,* +V 1400,18700,CONT_DIF_P,* +V 1400,25700,CONT_DIF_N,* +V 1400,25300,CONT_DIF_N,* +V 1400,24900,CONT_DIF_N,* +V 1400,26100,CONT_DIF_N,* +V 1400,27300,CONT_DIF_N,* +V 1400,28100,CONT_DIF_N,* +V 1400,27700,CONT_DIF_N,* +V 1400,26900,CONT_DIF_N,* +V 1400,26500,CONT_DIF_N,* +V 16900,1600,CONT_VIA,* +B 1100,26700,800,5100,CONT_VIA,* +B 16100,18100,600,9000,CONT_VIA,* +B 1100,18000,600,9100,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/padlib/palot_sp.ap b/alliance/src/cells/src/padlib/palot_sp.ap new file mode 100644 index 00000000..21813c53 --- /dev/null +++ b/alliance/src/cells/src/padlib/palot_sp.ap @@ -0,0 +1,1946 @@ +V ALLIANCE : 6 +H palot_sp,P,13/10/2000,100 +A 0,-700,17200,35600 +C 17200,16800,12000,vdde,1,EAST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,8400,4000,vddi,1,EAST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 0,8400,4000,vddi,0,WEST,ALU2 +C 17200,600,1200,ck,1,EAST,ALU2 +C 0,600,1200,ck,0,WEST,ALU2 +C 4600,-700,200,i,1,SOUTH,ALU2 +C 4600,-700,200,i,0,SOUTH,ALU1 +C 15400,-700,200,b,1,SOUTH,ALU2 +C 15400,-700,200,b,0,SOUTH,ALU1 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 0,29600,12000,vsse,0,WEST,ALU2 +S 15700,23200,16900,23200,200,*,RIGHT,ALU1 +S 16900,1600,16900,23200,200,*,UP,ALU1 +S 3700,23200,16900,23200,200,*,RIGHT,ALU2 +S 6500,1600,16900,1600,200,*,RIGHT,ALU2 +S 16400,1600,16900,1600,200,*,LEFT,ALU1 +S 15800,24300,16400,24300,200,*,RIGHT,ALU1 +S 15800,24300,15800,28800,200,*,UP,ALU1 +S 16200,24300,16200,29300,600,*,UP,ALU1 +S 13400,24300,13400,28800,200,*,UP,ALU1 +S 11000,24300,11000,28800,200,*,UP,ALU1 +S 8600,24300,8600,28800,200,*,UP,ALU1 +S 6200,24300,6200,28800,200,*,UP,ALU1 +S 3800,24400,3800,28800,200,*,UP,ALU1 +S 14800,4500,15500,4500,200,*,LEFT,ALU1 +S 5100,-200,14900,-200,200,*,RIGHT,ALU1 +S 14900,-200,14900,4000,200,*,UP,ALU1 +S 7400,5100,11400,5100,200,*,RIGHT,ALU1 +S 3200,12000,6000,12000,200,*,RIGHT,ALU1 +S 2100,5100,4100,5100,200,*,LEFT,ALU1 +S 2100,5100,2100,12100,200,*,DOWN,ALU1 +S 2400,5100,2400,8700,800,*,UP,ALU1 +S 2400,8700,2400,9900,500,*,DOWN,ALU1 +S 2100,10300,3300,10300,1000,*,LEFT,ALU1 +S 3300,9900,3300,11900,200,*,DOWN,ALU1 +S 10700,-200,10700,3200,200,*,UP,ALU1 +S 9500,-200,9500,4000,200,*,UP,ALU1 +S 8300,-200,8300,4000,200,*,UP,ALU1 +S 7100,-200,7100,3200,200,*,UP,ALU1 +S 5900,-200,5900,4000,200,*,UP,ALU1 +S 5900,4000,10100,4000,200,*,RIGHT,ALU1 +S 4100,5100,4100,12000,200,*,UP,ALU1 +S 8300,5100,8300,12000,200,*,UP,ALU1 +S 5900,5100,5900,12000,200,*,UP,ALU1 +S 10700,5100,10700,12100,200,*,UP,ALU1 +S 11300,4600,13100,4600,200,*,RIGHT,ALU1 +S 14600,13600,14600,22600,200,*,UP,ALU1 +S 2600,12600,3300,12600,200,*,LEFT,ALU1 +S 2700,11300,2700,12600,200,*,UP,ALU1 +S 3200,12600,3200,13100,200,*,UP,ALU1 +S 3700,13600,5300,13600,200,*,RIGHT,ALU1 +S 3800,13700,3800,22600,200,*,UP,ALU1 +S 15500,13600,16400,13600,200,*,RIGHT,ALU1 +S 16200,13600,16200,22600,600,*,UP,ALU1 +S 15800,13700,15800,22600,200,*,UP,ALU1 +S 13400,13600,13400,22600,200,*,UP,ALU1 +S 12200,13600,12200,22600,200,*,UP,ALU1 +S 11000,13600,11000,22600,200,*,UP,ALU1 +S 9800,13600,9800,22600,200,*,UP,ALU1 +S 8600,13600,8600,22600,200,*,UP,ALU1 +S 7400,13600,7400,22600,200,*,UP,ALU1 +S 6200,13600,6200,22600,200,*,UP,ALU1 +S 5000,13600,5000,22600,200,*,UP,ALU1 +S 2600,13600,2600,22600,200,*,UP,ALU1 +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2 +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +S 0,600,17200,600,1200,ck,RIGHT,ALU2 +S 3200,13100,3800,13100,200,*,RIGHT,POLY +S 2000,14200,2000,29100,200,*,UP,ALU1 +S 3200,14200,3200,29100,200,*,UP,ALU1 +S 2600,23700,2600,28800,200,*,UP,ALU1 +S 3800,24800,3800,28200,300,*,UP,NDIF +S 3200,24800,3200,28200,300,*,UP,NDIF +S 2600,24800,2600,28200,300,*,UP,NDIF +S 2000,24800,2000,28200,300,*,UP,NDIF +S 1700,24600,1700,28400,100,*,UP,NTRANS +S 2300,24600,2300,28400,100,*,UP,NTRANS +S 2900,24600,2900,28400,100,*,UP,NTRANS +S 3500,24600,3500,28400,100,*,UP,NTRANS +S 1500,28700,3900,28700,300,*,RIGHT,PTIE +S 3800,14100,3800,22000,300,*,UP,PDIF +S 3200,14100,3200,22000,200,*,UP,PDIF +S 2600,14100,2600,22000,200,*,UP,PDIF +S 2000,14100,2000,22000,200,*,UP,PDIF +S 1700,13900,1700,22200,100,*,UP,PTRANS +S 2300,13900,2300,22200,100,*,UP,PTRANS +S 2900,13900,2900,22200,100,*,UP,PTRANS +S 3500,13900,3500,22200,100,*,UP,PTRANS +S 2800,13400,2800,22700,2800,*,UP,NWELL +S 1500,13600,2900,13600,300,*,RIGHT,NTIE +S 3500,13600,3900,13600,300,*,RIGHT,NTIE +S 1700,13900,3500,13900,100,*,RIGHT,POLY +S 3200,23700,3200,23900,200,*,DOWN,POLY +S 1500,24300,2900,24300,300,*,RIGHT,PTIE +S 3500,24300,3900,24300,300,*,RIGHT,PTIE +S 1700,24600,3500,24600,100,*,RIGHT,POLY +S 3200,23800,3200,24600,200,*,UP,POLY +S 3200,23800,3700,23800,300,*,RIGHT,POLY +S 1500,22500,3900,22500,300,*,RIGHT,NTIE +S 3200,13100,3200,13900,200,*,UP,POLY +S 1500,13600,2700,13600,200,*,RIGHT,ALU1 +S 3200,13000,3200,14300,200,*,DOWN,ALU1 +S 3900,22500,6300,22500,300,*,RIGHT,NTIE +S 6100,23200,6100,23800,200,*,UP,ALU1 +S 5600,23800,6100,23800,300,*,RIGHT,POLY +S 5600,23800,5600,24600,200,*,UP,POLY +S 4100,24600,5900,24600,100,*,RIGHT,POLY +S 5900,24300,6300,24300,300,*,RIGHT,PTIE +S 3900,24300,5300,24300,300,*,RIGHT,PTIE +S 5600,23700,5600,23900,200,*,DOWN,POLY +S 5900,13600,6300,13600,200,*,RIGHT,ALU1 +S 4100,13900,5900,13900,100,*,RIGHT,POLY +S 5600,13300,5600,13900,200,*,UP,POLY +S 5900,13600,6300,13600,300,*,RIGHT,NTIE +S 3900,13600,5300,13600,300,*,RIGHT,NTIE +S 5200,13400,5200,22700,2800,*,UP,NWELL +S 5900,13900,5900,22200,100,*,UP,PTRANS +S 5300,13900,5300,22200,100,*,UP,PTRANS +S 4700,13900,4700,22200,100,*,UP,PTRANS +S 4100,13900,4100,22200,100,*,UP,PTRANS +S 4400,14100,4400,22000,200,*,UP,PDIF +S 5000,14100,5000,22000,200,*,UP,PDIF +S 5600,14100,5600,22000,200,*,UP,PDIF +S 6200,14100,6200,22000,300,*,UP,PDIF +S 3900,28700,6300,28700,300,*,RIGHT,PTIE +S 5900,24600,5900,28400,100,*,UP,NTRANS +S 5300,24600,5300,28400,100,*,UP,NTRANS +S 4700,24600,4700,28400,100,*,UP,NTRANS +S 4100,24600,4100,28400,100,*,UP,NTRANS +S 4400,24800,4400,28200,300,*,UP,NDIF +S 5000,24800,5000,28200,300,*,UP,NDIF +S 5600,24800,5600,28200,300,*,UP,NDIF +S 6200,24800,6200,28200,300,*,UP,NDIF +S 5000,23700,5000,28800,200,*,UP,ALU1 +S 5600,14200,5600,29100,200,*,UP,ALU1 +S 4400,14200,4400,29100,200,*,UP,ALU1 +S 6300,22500,8700,22500,300,*,RIGHT,NTIE +S 8500,23200,8500,23800,200,*,UP,ALU1 +S 8000,23800,8500,23800,300,*,RIGHT,POLY +S 8000,23800,8000,24600,200,*,UP,POLY +S 6500,24600,8300,24600,100,*,RIGHT,POLY +S 8300,24300,8700,24300,300,*,RIGHT,PTIE +S 6300,24300,7700,24300,300,*,RIGHT,PTIE +S 8000,23700,8000,23900,200,*,DOWN,POLY +S 8300,13600,8700,13600,200,*,RIGHT,ALU1 +S 6300,13600,7700,13600,200,*,RIGHT,ALU1 +S 6500,13900,8300,13900,100,*,RIGHT,POLY +S 8000,13300,8000,13900,200,*,UP,POLY +S 8300,13600,8700,13600,300,*,RIGHT,NTIE +S 6300,13600,7700,13600,300,*,RIGHT,NTIE +S 7600,13400,7600,22700,2800,*,UP,NWELL +S 8300,13900,8300,22200,100,*,UP,PTRANS +S 7700,13900,7700,22200,100,*,UP,PTRANS +S 7100,13900,7100,22200,100,*,UP,PTRANS +S 6500,13900,6500,22200,100,*,UP,PTRANS +S 6800,14100,6800,22000,200,*,UP,PDIF +S 7400,14100,7400,22000,200,*,UP,PDIF +S 8000,14100,8000,22000,200,*,UP,PDIF +S 8600,14100,8600,22000,300,*,UP,PDIF +S 6300,28700,8700,28700,300,*,RIGHT,PTIE +S 8300,24600,8300,28400,100,*,UP,NTRANS +S 7700,24600,7700,28400,100,*,UP,NTRANS +S 7100,24600,7100,28400,100,*,UP,NTRANS +S 6500,24600,6500,28400,100,*,UP,NTRANS +S 6800,24800,6800,28200,300,*,UP,NDIF +S 7400,24800,7400,28200,300,*,UP,NDIF +S 8000,24800,8000,28200,300,*,UP,NDIF +S 8600,24800,8600,28200,300,*,UP,NDIF +S 7400,23700,7400,28800,200,*,UP,ALU1 +S 8000,14200,8000,29100,200,*,UP,ALU1 +S 6800,14200,6800,29100,200,*,UP,ALU1 +S 8700,22500,11100,22500,300,*,RIGHT,NTIE +S 10900,23200,10900,23800,200,*,UP,ALU1 +S 10400,23800,10900,23800,300,*,RIGHT,POLY +S 10400,23800,10400,24600,200,*,UP,POLY +S 8900,24600,10700,24600,100,*,RIGHT,POLY +S 10700,24300,11100,24300,300,*,RIGHT,PTIE +S 8700,24300,10100,24300,300,*,RIGHT,PTIE +S 10400,23700,10400,23900,200,*,DOWN,POLY +S 10700,13600,11100,13600,200,*,RIGHT,ALU1 +S 8700,13600,10100,13600,200,*,RIGHT,ALU1 +S 8900,13900,10700,13900,100,*,RIGHT,POLY +S 10400,13300,10400,13900,200,*,UP,POLY +S 10700,13600,11100,13600,300,*,RIGHT,NTIE +S 8700,13600,10100,13600,300,*,RIGHT,NTIE +S 10000,13400,10000,22700,2800,*,UP,NWELL +S 10700,13900,10700,22200,100,*,UP,PTRANS +S 10100,13900,10100,22200,100,*,UP,PTRANS +S 9500,13900,9500,22200,100,*,UP,PTRANS +S 8900,13900,8900,22200,100,*,UP,PTRANS +S 9200,14100,9200,22000,200,*,UP,PDIF +S 9800,14100,9800,22000,200,*,UP,PDIF +S 10400,14100,10400,22000,200,*,UP,PDIF +S 11000,14100,11000,22000,300,*,UP,PDIF +S 8700,28700,11100,28700,300,*,RIGHT,PTIE +S 10700,24600,10700,28400,100,*,UP,NTRANS +S 10100,24600,10100,28400,100,*,UP,NTRANS +S 9500,24600,9500,28400,100,*,UP,NTRANS +S 8900,24600,8900,28400,100,*,UP,NTRANS +S 9200,24800,9200,28200,300,*,UP,NDIF +S 9800,24800,9800,28200,300,*,UP,NDIF +S 10400,24800,10400,28200,300,*,UP,NDIF +S 11000,24800,11000,28200,300,*,UP,NDIF +S 9800,23700,9800,28800,200,*,UP,ALU1 +S 10400,14200,10400,29100,200,*,UP,ALU1 +S 9200,14200,9200,29100,200,*,UP,ALU1 +S 11100,22500,13500,22500,300,*,RIGHT,NTIE +S 13300,23200,13300,23800,200,*,UP,ALU1 +S 12800,23800,13300,23800,300,*,RIGHT,POLY +S 12800,23800,12800,24600,200,*,UP,POLY +S 11300,24600,13100,24600,100,*,RIGHT,POLY +S 13100,24300,13500,24300,300,*,RIGHT,PTIE +S 11100,24300,12500,24300,300,*,RIGHT,PTIE +S 12800,23700,12800,23900,200,*,DOWN,POLY +S 13100,13600,13500,13600,200,*,RIGHT,ALU1 +S 11100,13600,12500,13600,200,*,RIGHT,ALU1 +S 11300,13900,13100,13900,100,*,RIGHT,POLY +S 12800,13300,12800,13900,200,*,UP,POLY +S 13100,13600,13500,13600,300,*,RIGHT,NTIE +S 11100,13600,12500,13600,300,*,RIGHT,NTIE +S 12400,13400,12400,22700,2800,*,UP,NWELL +S 13100,13900,13100,22200,100,*,UP,PTRANS +S 12500,13900,12500,22200,100,*,UP,PTRANS +S 11900,13900,11900,22200,100,*,UP,PTRANS +S 11300,13900,11300,22200,100,*,UP,PTRANS +S 11600,14100,11600,22000,200,*,UP,PDIF +S 12200,14100,12200,22000,200,*,UP,PDIF +S 12800,14100,12800,22000,200,*,UP,PDIF +S 13400,14100,13400,22000,300,*,UP,PDIF +S 11100,28700,13500,28700,300,*,RIGHT,PTIE +S 13100,24600,13100,28400,100,*,UP,NTRANS +S 12500,24600,12500,28400,100,*,UP,NTRANS +S 11900,24600,11900,28400,100,*,UP,NTRANS +S 11300,24600,11300,28400,100,*,UP,NTRANS +S 11600,24800,11600,28200,300,*,UP,NDIF +S 12200,24800,12200,28200,300,*,UP,NDIF +S 12800,24800,12800,28200,300,*,UP,NDIF +S 13400,24800,13400,28200,300,*,UP,NDIF +S 12200,23700,12200,28800,200,*,UP,ALU1 +S 12800,14200,12800,29100,200,*,UP,ALU1 +S 11600,14200,11600,29100,200,*,UP,ALU1 +S 13500,22500,15900,22500,300,*,RIGHT,NTIE +S 15700,23200,15700,23800,200,*,UP,ALU1 +S 15200,23800,15700,23800,300,*,RIGHT,POLY +S 15200,23800,15200,24600,200,*,UP,POLY +S 13700,24600,15500,24600,100,*,RIGHT,POLY +S 15500,24300,15900,24300,300,*,RIGHT,PTIE +S 13500,24300,14900,24300,300,*,RIGHT,PTIE +S 15200,23700,15200,23900,200,*,DOWN,POLY +S 13500,13600,14900,13600,200,*,RIGHT,ALU1 +S 13700,13900,15500,13900,100,*,RIGHT,POLY +S 15200,13300,15200,13900,200,*,UP,POLY +S 15500,13600,15900,13600,300,*,RIGHT,NTIE +S 13500,13600,14900,13600,300,*,RIGHT,NTIE +S 14800,13400,14800,22700,2800,*,UP,NWELL +S 15500,13900,15500,22200,100,*,UP,PTRANS +S 14900,13900,14900,22200,100,*,UP,PTRANS +S 14300,13900,14300,22200,100,*,UP,PTRANS +S 13700,13900,13700,22200,100,*,UP,PTRANS +S 14000,14100,14000,22000,200,*,UP,PDIF +S 14600,14100,14600,22000,200,*,UP,PDIF +S 15200,14100,15200,22000,200,*,UP,PDIF +S 15800,14100,15800,22000,300,*,UP,PDIF +S 13500,28700,15900,28700,300,*,RIGHT,PTIE +S 15500,24600,15500,28400,100,*,UP,NTRANS +S 14900,24600,14900,28400,100,*,UP,NTRANS +S 14300,24600,14300,28400,100,*,UP,NTRANS +S 13700,24600,13700,28400,100,*,UP,NTRANS +S 14000,24800,14000,28200,300,*,UP,NDIF +S 14600,24800,14600,28200,300,*,UP,NDIF +S 15200,24800,15200,28200,300,*,UP,NDIF +S 15800,24800,15800,28200,300,*,UP,NDIF +S 14600,23700,14600,28800,200,*,UP,ALU1 +S 15200,14200,15200,29100,200,*,UP,ALU1 +S 14000,14200,14000,29100,200,*,UP,ALU1 +S 11000,5500,14600,5500,100,*,RIGHT,POLY +S 15200,3700,15200,5500,100,*,UP,POLY +S 14600,-100,14600,1900,800,*,DOWN,ALU1 +S 14300,0,14300,1900,300,*,DOWN,PTIE +S 14600,0,14600,1900,300,*,DOWN,PTIE +S 14900,-300,14900,1900,300,*,DOWN,PTIE +S 14900,1800,16200,1800,300,*,LEFT,PTIE +S 16100,1700,16100,4100,300,*,UP,PTIE +S 14900,2600,14900,3500,300,*,DOWN,NDIF +S 15400,-700,15400,2300,200,*,DOWN,ALU1 +S 14300,2600,14300,3500,300,*,UP,NDIF +S 14600,2400,14600,3700,100,*,UP,NTRANS +S 15200,2400,15200,3700,100,*,UP,NTRANS +S 15500,2600,15500,3500,300,*,UP,NDIF +S 15200,2200,15200,2400,100,*,DOWN,POLY +S 12500,5800,12500,12900,200,*,UP,ALU1 +S 13900,3700,13900,3900,100,*,DOWN,POLY +S 14000,3700,14000,3900,100,*,DOWN,POLY +S 13900,4700,13900,5300,100,*,DOWN,POLY +S 14000,4700,14000,5300,100,*,DOWN,POLY +S 13900,4500,14600,4500,300,*,RIGHT,POLY +S 14600,3700,14600,4300,100,*,UP,POLY +S 14200,5100,15000,5100,300,*,RIGHT,NTIE +S 11300,5100,13700,5100,300,*,RIGHT,NTIE +S 7400,4000,10100,4000,300,*,RIGHT,PTIE +S 10300,3800,10300,4500,100,*,DOWN,POLY +S 10300,4600,10900,4600,100,*,LEFT,POLY +S 11100,4500,11100,5300,100,*,DOWN,POLY +S 11000,3600,11000,4100,100,*,DOWN,POLY +S 11100,3800,11100,4100,100,*,DOWN,POLY +S 11100,3700,14000,3700,100,*,RIGHT,POLY +S 11100,3600,14000,3600,100,*,RIGHT,POLY +S 11300,4000,13700,4000,300,*,RIGHT,PTIE +S 13700,5700,13700,11500,300,*,UP,PDIF +S 13400,5500,13400,11700,100,*,UP,PTRANS +S 13100,5700,13100,11500,300,*,UP,PDIF +S 12800,5500,12800,11700,100,*,UP,PTRANS +S 12500,5700,12500,11500,300,*,UP,PDIF +S 11900,5700,11900,11500,300,*,UP,PDIF +S 12200,5500,12200,11700,100,*,UP,PTRANS +S 11300,5700,11300,11500,300,*,UP,PDIF +S 11600,5500,11600,11700,100,*,UP,PTRANS +S 13700,600,13700,3400,300,*,UP,NDIF +S 13100,600,13100,3400,200,*,UP,NDIF +S 12500,600,12500,3400,300,*,UP,NDIF +S 11900,600,11900,3400,200,*,UP,NDIF +S 11300,600,11300,3400,300,*,UP,NDIF +S 13400,400,13400,3600,100,*,UP,NTRANS +S 12800,400,12800,3600,100,*,UP,NTRANS +S 12200,400,12200,3600,100,*,UP,NTRANS +S 11600,400,11600,3600,100,*,UP,NTRANS +S 16100,2300,16100,4100,200,*,UP,ALU1 +S 4700,900,4700,11400,200,*,UP,ALU1 +S 5300,900,5300,11400,200,*,UP,ALU1 +S 5300,4600,7000,4600,200,*,RIGHT,ALU1 +S 9500,5700,9500,12000,200,*,UP,ALU1 +S 7100,5700,7100,12000,200,*,UP,ALU1 +S 10100,600,10100,3300,200,*,UP,ALU1 +S 8900,600,8900,3300,200,*,UP,ALU1 +S 7700,600,7700,3300,200,*,UP,ALU1 +S 6500,5800,6500,12900,200,*,UP,ALU1 +S 7700,5800,7700,12900,200,*,UP,ALU1 +S 8900,5800,8900,12900,200,*,UP,ALU1 +S 10100,5800,10100,12900,200,*,UP,ALU1 +S 6500,600,6500,3300,200,*,UP,ALU1 +S 5900,5100,6800,5100,200,*,RIGHT,ALU1 +S 4600,-700,4600,300,200,*,UP,ALU1 +S 5600,3700,5600,5400,100,*,UP,POLY +S 4900,5300,5600,5300,300,*,RIGHT,POLY +S 6200,3700,8000,3700,100,*,RIGHT,POLY +S 6200,5400,8000,5400,100,*,RIGHT,POLY +S 7100,3700,7100,5400,200,*,UP,POLY +S 4400,3700,4400,5400,100,*,UP,POLY +S 4400,200,4400,400,100,*,UP,POLY +S 5800,4000,6800,4000,300,*,RIGHT,PTIE +S 5800,5100,6800,5100,300,*,RIGHT,NTIE +S 7400,5400,7400,11700,100,*,UP,PTRANS +S 8000,5400,8000,11700,100,*,UP,PTRANS +S 7100,5600,7100,11500,300,*,UP,PDIF +S 8300,5600,8300,11500,300,*,UP,PDIF +S 6500,5600,6500,11500,300,*,UP,PDIF +S 10100,5600,10100,11500,300,*,UP,PDIF +S 7700,5600,7700,11500,300,*,UP,PDIF +S 5300,5600,5300,11500,300,*,UP,PDIF +S 5600,5400,5600,11700,100,*,UP,PTRANS +S 5900,5600,5900,11500,300,*,UP,PDIF +S 6200,5400,6200,11700,100,*,UP,PTRANS +S 6800,5400,6800,11700,100,*,UP,PTRANS +S 9500,5600,9500,11500,300,*,UP,PDIF +S 10700,5600,10700,11500,300,*,UP,PDIF +S 8900,5600,8900,11500,300,*,UP,PDIF +S 8600,5400,8600,11700,100,*,UP,PTRANS +S 9200,5400,9200,11700,100,*,UP,PTRANS +S 9800,5400,9800,11700,100,*,UP,PTRANS +S 10400,5400,10400,11700,100,*,UP,PTRANS +S 4400,5400,4400,11700,100,*,UP,PTRANS +S 4700,5600,4700,11500,300,*,UP,PDIF +S 4100,5600,4100,11500,300,*,UP,PDIF +S 7400,400,7400,3700,100,*,UP,NTRANS +S 8000,400,8000,3700,100,*,UP,NTRANS +S 7100,600,7100,3500,200,*,UP,NDIF +S 8300,600,8300,3500,200,*,UP,NDIF +S 6500,600,6500,3500,300,*,UP,NDIF +S 7700,600,7700,3500,300,*,UP,NDIF +S 5300,600,5300,3500,300,*,UP,NDIF +S 5600,400,5600,3700,100,*,UP,NTRANS +S 5900,600,5900,3500,200,*,UP,NDIF +S 6200,400,6200,3700,100,*,UP,NTRANS +S 6800,400,6800,3700,100,*,UP,NTRANS +S 10400,400,10400,3700,100,*,UP,NTRANS +S 9500,600,9500,3500,200,*,UP,NDIF +S 8900,600,8900,3500,300,*,UP,NDIF +S 8600,400,8600,3700,100,*,UP,NTRANS +S 10100,600,10100,3500,300,*,UP,NDIF +S 9200,400,9200,3700,100,*,UP,NTRANS +S 9800,400,9800,3700,100,*,UP,NTRANS +S 4100,600,4100,3500,200,*,UP,NDIF +S 4400,400,4400,3700,100,*,UP,NTRANS +S 4700,600,4700,3500,300,*,UP,NDIF +S 16100,5000,16100,12100,200,*,UP,ALU1 +S 16100,5000,16100,12100,300,*,UP,NTIE +S 13100,700,13100,3900,200,*,UP,ALU1 +S 11300,600,11300,4600,200,*,UP,ALU1 +S 11900,3900,13700,3900,200,*,RIGHT,ALU1 +S 13700,600,13700,3300,200,*,UP,ALU1 +S 12500,600,12500,3300,200,*,UP,ALU1 +S 11900,700,11900,3900,200,*,UP,ALU1 +S 13700,3900,13700,12900,200,*,UP,ALU1 +S 11300,5800,11300,12900,200,*,UP,ALU1 +S 11900,4600,11900,11400,200,*,UP,ALU1 +S 13100,4600,13100,11400,200,*,UP,ALU1 +S 8600,5400,10400,5400,100,*,RIGHT,POLY +S 8600,3700,10400,3700,100,*,RIGHT,POLY +S 9500,4600,9500,5400,300,*,DOWN,POLY +S 10500,4500,11000,4500,100,*,LEFT,POLY +S 11000,4500,11000,5400,100,*,DOWN,POLY +S 7400,5100,9200,5100,300,*,RIGHT,NTIE +S 9800,5100,10700,5100,300,*,RIGHT,NTIE +S 10700,600,10700,3500,300,*,UP,NDIF +S 14900,5000,14900,12100,200,*,UP,ALU1 +S 11000,5400,14600,5400,100,*,RIGHT,POLY +S 15400,4000,16200,4000,300,*,LEFT,PTIE +S 15400,5100,16200,5100,300,*,RIGHT,NTIE +S 9400,4600,10800,4600,200,*,LEFT,ALU1 +S 10400,3700,10400,4500,100,*,DOWN,POLY +S 10800,3900,10800,4600,200,*,UP,ALU1 +S 15200,8100,15200,12100,2000,*,DOWN,ALU1 +S 15200,8100,15200,12000,2000,*,DOWN,NTIE +S 15200,5500,15200,7800,100,*,UP,PTRANS +S 14600,5500,14600,7800,100,*,UP,PTRANS +S 14900,5700,14900,7600,300,*,UP,PDIF +S 15500,5700,15500,7600,300,*,UP,PDIF +S 14300,5700,14300,7600,300,*,UP,PDIF +S 15500,2800,15500,7500,200,*,UP,ALU1 +S 14300,2700,14300,7500,200,*,UP,ALU1 +S 3300,5700,3300,9300,200,*,DOWN,ALU1 +S 3100,9200,3100,9400,200,*,DOWN,ALU1 +S 2700,5100,2700,6400,1100,*,DOWN,NTIE +S 3300,9700,3300,12000,300,*,UP,NTIE +S 3300,5000,3300,9100,300,*,UP,NTIE +S 3500,8900,3500,9900,300,*,UP,NTIE +S 2000,5100,4000,5100,300,*,RIGHT,NTIE +S 2100,5000,2100,12100,300,*,UP,NTIE +S 2000,12000,16200,12000,300,*,RIGHT,NTIE +S 4100,600,4100,3500,300,*,UP,NDIF +S 3500,-300,3500,4100,300,*,UP,PTIE +S 3400,4000,4200,4000,300,*,RIGHT,PTIE +S 3400,-200,15000,-200,300,*,RIGHT,PTIE +S 3800,-300,3800,4100,800,*,UP,ALU1 +S 1900,5100,16300,5100,400,*,RIGHT,NWELL +S 1900,8600,16300,8600,7200,*,RIGHT,NWELL +S 8600,30100,8600,35600,12600,*,UP,ALU1 +S 3700,23100,3700,23800,200,*,UP,ALU1 +S 1900,29600,15300,29600,900,*,RIGHT,ALU1 +S 15800,28900,15800,29300,200,*,UP,ALU1 +S 700,28000,700,28800,100,*,UP,ALU1 +S 1100,24200,1100,29300,800,*,UP,ALU1 +S 3700,13000,15300,13000,200,*,RIGHT,ALU1 +S 3700,13100,15300,13100,200,*,RIGHT,ALU1 +S 1100,13500,1100,22600,800,*,UP,ALU1 +S 15900,24300,16500,24300,300,*,RIGHT,PTIE +S 16000,28700,16500,28700,300,*,RIGHT,PTIE +S 16400,24200,16400,28800,300,*,UP,PTIE +S 700,24300,1500,24300,300,*,RIGHT,PTIE +S 800,24200,800,28800,300,*,UP,PTIE +S 700,28700,1500,28700,300,*,RIGHT,PTIE +S 16000,22500,16500,22500,300,*,RIGHT,NTIE +S 800,22500,1400,22500,300,*,RIGHT,NTIE +S 16400,13600,16400,22600,300,*,UP,NTIE +S 16000,13600,16500,13600,300,*,RIGHT,NTIE +S 800,13600,800,22600,300,*,UP,NTIE +S 800,13600,1400,13600,300,*,RIGHT,NTIE +S 1400,14100,1400,22000,300,*,UP,PDIF +S 1400,24900,1400,28200,300,*,UP,NDIF +S 16300,13400,16300,22700,600,*,UP,NWELL +S 1000,13400,1000,22700,800,*,UP,NWELL +S 2400,9100,3000,9100,3900,*,RIGHT,PTRANS +V 16400,1600,CONT_VIA,* +B 1100,18100,800,9000,CONT_VIA,* +B 15200,9200,2000,2200,CONT_VIA,* +B 16100,18100,800,9000,CONT_VIA,* +B 1100,26700,800,5100,CONT_VIA,* +B 10800,4600,200,200,CONT_TURN1,* +B 11300,4600,200,200,CONT_TURN1,* +B 13100,4600,200,200,CONT_TURN1,* +B 11900,3900,200,200,CONT_TURN1,* +B 13700,3900,200,200,CONT_TURN1,* +V 3700,13600,CONT_BODY_N,* +V 3800,13100,CONT_POLY,* +V 3800,27700,CONT_DIF_N,* +V 3800,26100,CONT_DIF_N,* +V 3800,25700,CONT_DIF_N,* +V 3800,27300,CONT_DIF_N,* +V 3800,26900,CONT_DIF_N,* +V 3800,25300,CONT_DIF_N,* +V 3800,26500,CONT_VIA,* +V 3800,24900,CONT_VIA,* +V 3800,28100,CONT_VIA,* +V 2600,24900,CONT_VIA,* +V 2600,25300,CONT_DIF_N,* +V 2600,26900,CONT_DIF_N,* +V 2600,27300,CONT_DIF_N,* +V 2600,26500,CONT_DIF_N,* +V 2600,28100,CONT_DIF_N,* +V 2600,25700,CONT_DIF_N,* +V 2600,27700,CONT_VIA,* +V 2600,26100,CONT_VIA,* +V 3800,28700,CONT_BODY_P,* +V 2600,28700,CONT_BODY_P,* +V 2200,13600,CONT_BODY_N,* +V 2000,25000,CONT_DIF_N,* +V 2000,27400,CONT_DIF_N,* +V 2000,27800,CONT_DIF_N,* +V 2000,25400,CONT_DIF_N,* +V 2000,25800,CONT_DIF_N,* +V 2000,26200,CONT_DIF_N,* +V 2000,26600,CONT_DIF_N,* +V 2000,27000,CONT_DIF_N,* +V 3200,25800,CONT_DIF_N,* +V 3200,26200,CONT_DIF_N,* +V 3200,25400,CONT_DIF_N,* +V 3200,25000,CONT_DIF_N,* +V 3200,27800,CONT_DIF_N,* +V 3200,26600,CONT_DIF_N,* +V 3200,27000,CONT_DIF_N,* +V 3200,27400,CONT_DIF_N,* +V 2600,14300,CONT_DIF_P,* +V 2000,14700,CONT_DIF_P,* +V 2600,14700,CONT_DIF_P,* +V 2000,15100,CONT_DIF_P,* +V 2000,14300,CONT_DIF_P,* +V 3200,14300,CONT_DIF_P,* +V 3800,14300,CONT_DIF_P,* +V 3200,14700,CONT_DIF_P,* +V 3800,14700,CONT_DIF_P,* +V 3200,15100,CONT_DIF_P,* +V 2600,15500,CONT_DIF_P,* +V 2000,15500,CONT_DIF_P,* +V 2000,19500,CONT_DIF_P,* +V 2000,17900,CONT_DIF_P,* +V 2600,17900,CONT_DIF_P,* +V 2000,18300,CONT_DIF_P,* +V 2600,18300,CONT_DIF_P,* +V 2000,18700,CONT_DIF_P,* +V 2000,19100,CONT_DIF_P,* +V 2600,19100,CONT_DIF_P,* +V 2600,19500,CONT_DIF_P,* +V 2000,16300,CONT_DIF_P,* +V 2000,15900,CONT_DIF_P,* +V 2600,15900,CONT_DIF_P,* +V 2000,17500,CONT_DIF_P,* +V 2000,17100,CONT_DIF_P,* +V 2000,16700,CONT_DIF_P,* +V 2600,16700,CONT_DIF_P,* +V 2600,17100,CONT_DIF_P,* +V 3200,15500,CONT_DIF_P,* +V 3800,15500,CONT_DIF_P,* +V 3800,19500,CONT_DIF_P,* +V 3200,18300,CONT_DIF_P,* +V 3200,18700,CONT_DIF_P,* +V 3200,19100,CONT_DIF_P,* +V 3800,19100,CONT_DIF_P,* +V 3200,19500,CONT_DIF_P,* +V 3200,17500,CONT_DIF_P,* +V 3200,17100,CONT_DIF_P,* +V 3200,17900,CONT_DIF_P,* +V 3800,17900,CONT_DIF_P,* +V 3800,18300,CONT_DIF_P,* +V 3200,16300,CONT_DIF_P,* +V 3200,15900,CONT_DIF_P,* +V 3800,15900,CONT_DIF_P,* +V 3800,17100,CONT_DIF_P,* +V 3800,16700,CONT_DIF_P,* +V 3200,16700,CONT_DIF_P,* +V 2600,15100,CONT_VIA,* +V 3800,15100,CONT_VIA,* +V 2600,17500,CONT_VIA,* +V 2600,18700,CONT_VIA,* +V 2600,16300,CONT_VIA,* +V 3800,18700,CONT_VIA,* +V 3800,17500,CONT_VIA,* +V 3800,16300,CONT_VIA,* +V 2000,19900,CONT_DIF_P,* +V 3200,19900,CONT_DIF_P,* +V 2600,19900,CONT_VIA,* +V 3800,19900,CONT_VIA,* +V 2000,20300,CONT_DIF_P,* +V 3200,20300,CONT_DIF_P,* +V 2600,20300,CONT_DIF_P,* +V 3800,20300,CONT_DIF_P,* +V 2600,20700,CONT_DIF_P,* +V 3800,20700,CONT_DIF_P,* +V 3200,20700,CONT_DIF_P,* +V 2000,20700,CONT_DIF_P,* +V 2000,21100,CONT_DIF_P,* +V 3200,21100,CONT_DIF_P,* +V 3800,21100,CONT_VIA,* +V 2600,21100,CONT_VIA,* +V 2000,21500,CONT_DIF_P,* +V 2600,21500,CONT_DIF_P,* +V 3200,21500,CONT_DIF_P,* +V 3800,21500,CONT_DIF_P,* +V 2600,24300,CONT_BODY_P,* +V 3800,24300,CONT_BODY_P,* +V 3700,23800,CONT_POLY,* +V 2600,23800,CONT_VIA,* +V 3800,22500,CONT_BODY_N,* +V 2600,22500,CONT_BODY_N,* +V 3800,21900,CONT_DIF_P,* +V 3200,21900,CONT_DIF_P,* +V 2600,21900,CONT_DIF_P,* +V 2000,21900,CONT_DIF_P,* +V 2600,13600,CONT_VIA,* +V 1700,13600,CONT_BODY_N,* +V 4400,21900,CONT_DIF_P,* +V 5000,21900,CONT_DIF_P,* +V 5600,21900,CONT_DIF_P,* +V 6200,21900,CONT_DIF_P,* +V 5000,22500,CONT_BODY_N,* +V 6200,22500,CONT_BODY_N,* +V 6100,23200,CONT_VIA,* +V 5000,23800,CONT_VIA,* +V 6100,23800,CONT_POLY,* +V 6200,24300,CONT_BODY_P,* +V 5000,24300,CONT_BODY_P,* +V 6200,21500,CONT_DIF_P,* +V 5600,21500,CONT_DIF_P,* +V 5000,21500,CONT_DIF_P,* +V 4400,21500,CONT_DIF_P,* +V 5000,21100,CONT_VIA,* +V 6200,21100,CONT_VIA,* +V 5600,21100,CONT_DIF_P,* +V 4400,21100,CONT_DIF_P,* +V 4400,20700,CONT_DIF_P,* +V 5600,20700,CONT_DIF_P,* +V 6200,20700,CONT_DIF_P,* +V 5000,20700,CONT_DIF_P,* +V 6200,20300,CONT_DIF_P,* +V 5000,20300,CONT_DIF_P,* +V 5600,20300,CONT_DIF_P,* +V 4400,20300,CONT_DIF_P,* +V 6200,19900,CONT_VIA,* +V 5000,19900,CONT_VIA,* +V 5600,19900,CONT_DIF_P,* +V 4400,19900,CONT_DIF_P,* +V 6200,16300,CONT_VIA,* +V 6200,17500,CONT_VIA,* +V 6200,18700,CONT_VIA,* +V 5000,16300,CONT_VIA,* +V 5000,18700,CONT_VIA,* +V 5000,17500,CONT_VIA,* +V 6200,15100,CONT_VIA,* +V 5000,15100,CONT_VIA,* +V 5600,16700,CONT_DIF_P,* +V 6200,16700,CONT_DIF_P,* +V 6200,17100,CONT_DIF_P,* +V 6200,15900,CONT_DIF_P,* +V 5600,15900,CONT_DIF_P,* +V 5600,16300,CONT_DIF_P,* +V 6200,18300,CONT_DIF_P,* +V 6200,17900,CONT_DIF_P,* +V 5600,17900,CONT_DIF_P,* +V 5600,17100,CONT_DIF_P,* +V 5600,17500,CONT_DIF_P,* +V 5600,19500,CONT_DIF_P,* +V 6200,19100,CONT_DIF_P,* +V 5600,19100,CONT_DIF_P,* +V 5600,18700,CONT_DIF_P,* +V 5600,18300,CONT_DIF_P,* +V 6200,19500,CONT_DIF_P,* +V 6200,15500,CONT_DIF_P,* +V 5600,15500,CONT_DIF_P,* +V 5000,17100,CONT_DIF_P,* +V 5000,16700,CONT_DIF_P,* +V 4400,16700,CONT_DIF_P,* +V 4400,17100,CONT_DIF_P,* +V 4400,17500,CONT_DIF_P,* +V 5000,15900,CONT_DIF_P,* +V 4400,15900,CONT_DIF_P,* +V 4400,16300,CONT_DIF_P,* +V 5000,19500,CONT_DIF_P,* +V 5000,19100,CONT_DIF_P,* +V 4400,19100,CONT_DIF_P,* +V 4400,18700,CONT_DIF_P,* +V 5000,18300,CONT_DIF_P,* +V 4400,18300,CONT_DIF_P,* +V 5000,17900,CONT_DIF_P,* +V 4400,17900,CONT_DIF_P,* +V 4400,19500,CONT_DIF_P,* +V 4400,15500,CONT_DIF_P,* +V 5000,15500,CONT_DIF_P,* +V 5600,15100,CONT_DIF_P,* +V 6200,14700,CONT_DIF_P,* +V 5600,14700,CONT_DIF_P,* +V 6200,14300,CONT_DIF_P,* +V 5600,14300,CONT_DIF_P,* +V 4400,14300,CONT_DIF_P,* +V 4400,15100,CONT_DIF_P,* +V 5000,14700,CONT_DIF_P,* +V 4400,14700,CONT_DIF_P,* +V 5000,14300,CONT_DIF_P,* +V 5600,27400,CONT_DIF_N,* +V 5600,27000,CONT_DIF_N,* +V 5600,26600,CONT_DIF_N,* +V 5600,27800,CONT_DIF_N,* +V 5600,25000,CONT_DIF_N,* +V 5600,25400,CONT_DIF_N,* +V 5600,26200,CONT_DIF_N,* +V 5600,25800,CONT_DIF_N,* +V 4400,27000,CONT_DIF_N,* +V 4400,26600,CONT_DIF_N,* +V 4400,26200,CONT_DIF_N,* +V 4400,25800,CONT_DIF_N,* +V 4400,25400,CONT_DIF_N,* +V 4400,27800,CONT_DIF_N,* +V 4400,27400,CONT_DIF_N,* +V 4400,25000,CONT_DIF_N,* +V 4900,13600,CONT_VIA,* +V 5600,13100,CONT_POLY,* +V 6000,13600,CONT_BODY_N,* +V 4600,13600,CONT_BODY_N,* +V 5200,13600,CONT_BODY_N,* +V 4100,13600,CONT_BODY_N,* +V 5000,28700,CONT_BODY_P,* +V 6200,28700,CONT_BODY_P,* +V 5000,26100,CONT_VIA,* +V 5000,27700,CONT_VIA,* +V 5000,25700,CONT_DIF_N,* +V 5000,28100,CONT_DIF_N,* +V 5000,26500,CONT_DIF_N,* +V 5000,27300,CONT_DIF_N,* +V 5000,26900,CONT_DIF_N,* +V 5000,25300,CONT_DIF_N,* +V 5000,24900,CONT_VIA,* +V 6200,28100,CONT_VIA,* +V 6200,24900,CONT_VIA,* +V 6200,26500,CONT_VIA,* +V 6200,25300,CONT_DIF_N,* +V 6200,26900,CONT_DIF_N,* +V 6200,27300,CONT_DIF_N,* +V 6200,25700,CONT_DIF_N,* +V 6200,26100,CONT_DIF_N,* +V 6200,27700,CONT_DIF_N,* +V 6800,21900,CONT_DIF_P,* +V 7400,21900,CONT_DIF_P,* +V 8000,21900,CONT_DIF_P,* +V 8600,21900,CONT_DIF_P,* +V 7400,22500,CONT_BODY_N,* +V 8600,22500,CONT_BODY_N,* +V 8500,23200,CONT_VIA,* +V 7400,23800,CONT_VIA,* +V 8500,23800,CONT_POLY,* +V 8600,24300,CONT_BODY_P,* +V 7400,24300,CONT_BODY_P,* +V 8600,21500,CONT_DIF_P,* +V 8000,21500,CONT_DIF_P,* +V 7400,21500,CONT_DIF_P,* +V 6800,21500,CONT_DIF_P,* +V 7400,21100,CONT_VIA,* +V 8600,21100,CONT_VIA,* +V 8000,21100,CONT_DIF_P,* +V 6800,21100,CONT_DIF_P,* +V 6800,20700,CONT_DIF_P,* +V 8000,20700,CONT_DIF_P,* +V 8600,20700,CONT_DIF_P,* +V 7400,20700,CONT_DIF_P,* +V 8600,20300,CONT_DIF_P,* +V 7400,20300,CONT_DIF_P,* +V 8000,20300,CONT_DIF_P,* +V 6800,20300,CONT_DIF_P,* +V 8600,19900,CONT_VIA,* +V 7400,19900,CONT_VIA,* +V 8000,19900,CONT_DIF_P,* +V 6800,19900,CONT_DIF_P,* +V 8600,16300,CONT_VIA,* +V 8600,17500,CONT_VIA,* +V 8600,18700,CONT_VIA,* +V 7400,16300,CONT_VIA,* +V 7400,18700,CONT_VIA,* +V 7400,17500,CONT_VIA,* +V 8600,15100,CONT_VIA,* +V 7400,15100,CONT_VIA,* +V 8000,16700,CONT_DIF_P,* +V 8600,16700,CONT_DIF_P,* +V 8600,17100,CONT_DIF_P,* +V 8600,15900,CONT_DIF_P,* +V 8000,15900,CONT_DIF_P,* +V 8000,16300,CONT_DIF_P,* +V 8600,18300,CONT_DIF_P,* +V 8600,17900,CONT_DIF_P,* +V 8000,17900,CONT_DIF_P,* +V 8000,17100,CONT_DIF_P,* +V 8000,17500,CONT_DIF_P,* +V 8000,19500,CONT_DIF_P,* +V 8600,19100,CONT_DIF_P,* +V 8000,19100,CONT_DIF_P,* +V 8000,18700,CONT_DIF_P,* +V 8000,18300,CONT_DIF_P,* +V 8600,19500,CONT_DIF_P,* +V 8600,15500,CONT_DIF_P,* +V 8000,15500,CONT_DIF_P,* +V 7400,17100,CONT_DIF_P,* +V 7400,16700,CONT_DIF_P,* +V 6800,16700,CONT_DIF_P,* +V 6800,17100,CONT_DIF_P,* +V 6800,17500,CONT_DIF_P,* +V 7400,15900,CONT_DIF_P,* +V 6800,15900,CONT_DIF_P,* +V 6800,16300,CONT_DIF_P,* +V 7400,19500,CONT_DIF_P,* +V 7400,19100,CONT_DIF_P,* +V 6800,19100,CONT_DIF_P,* +V 6800,18700,CONT_DIF_P,* +V 7400,18300,CONT_DIF_P,* +V 6800,18300,CONT_DIF_P,* +V 7400,17900,CONT_DIF_P,* +V 6800,17900,CONT_DIF_P,* +V 6800,19500,CONT_DIF_P,* +V 6800,15500,CONT_DIF_P,* +V 7400,15500,CONT_DIF_P,* +V 8000,15100,CONT_DIF_P,* +V 8600,14700,CONT_DIF_P,* +V 8000,14700,CONT_DIF_P,* +V 8600,14300,CONT_DIF_P,* +V 8000,14300,CONT_DIF_P,* +V 6800,14300,CONT_DIF_P,* +V 6800,15100,CONT_DIF_P,* +V 7400,14700,CONT_DIF_P,* +V 6800,14700,CONT_DIF_P,* +V 7400,14300,CONT_DIF_P,* +V 8000,27400,CONT_DIF_N,* +V 8000,27000,CONT_DIF_N,* +V 8000,26600,CONT_DIF_N,* +V 8000,27800,CONT_DIF_N,* +V 8000,25000,CONT_DIF_N,* +V 8000,25400,CONT_DIF_N,* +V 8000,26200,CONT_DIF_N,* +V 8000,25800,CONT_DIF_N,* +V 6800,27000,CONT_DIF_N,* +V 6800,26600,CONT_DIF_N,* +V 6800,26200,CONT_DIF_N,* +V 6800,25800,CONT_DIF_N,* +V 6800,25400,CONT_DIF_N,* +V 6800,27800,CONT_DIF_N,* +V 6800,27400,CONT_DIF_N,* +V 6800,25000,CONT_DIF_N,* +V 7300,13600,CONT_VIA,* +V 8000,13100,CONT_POLY,* +V 8400,13600,CONT_BODY_N,* +V 7000,13600,CONT_BODY_N,* +V 7600,13600,CONT_BODY_N,* +V 6500,13600,CONT_BODY_N,* +V 7400,28700,CONT_BODY_P,* +V 8600,28700,CONT_BODY_P,* +V 7400,26100,CONT_VIA,* +V 7400,27700,CONT_VIA,* +V 7400,25700,CONT_DIF_N,* +V 7400,28100,CONT_DIF_N,* +V 7400,26500,CONT_DIF_N,* +V 7400,27300,CONT_DIF_N,* +V 7400,26900,CONT_DIF_N,* +V 7400,25300,CONT_DIF_N,* +V 7400,24900,CONT_VIA,* +V 8600,28100,CONT_VIA,* +V 8600,24900,CONT_VIA,* +V 8600,26500,CONT_VIA,* +V 8600,25300,CONT_DIF_N,* +V 8600,26900,CONT_DIF_N,* +V 8600,27300,CONT_DIF_N,* +V 8600,25700,CONT_DIF_N,* +V 8600,26100,CONT_DIF_N,* +V 8600,27700,CONT_DIF_N,* +V 9200,21900,CONT_DIF_P,* +V 9800,21900,CONT_DIF_P,* +V 10400,21900,CONT_DIF_P,* +V 11000,21900,CONT_DIF_P,* +V 9800,22500,CONT_BODY_N,* +V 11000,22500,CONT_BODY_N,* +V 10900,23200,CONT_VIA,* +V 9800,23800,CONT_VIA,* +V 10900,23800,CONT_POLY,* +V 11000,24300,CONT_BODY_P,* +V 9800,24300,CONT_BODY_P,* +V 11000,21500,CONT_DIF_P,* +V 10400,21500,CONT_DIF_P,* +V 9800,21500,CONT_DIF_P,* +V 9200,21500,CONT_DIF_P,* +V 9800,21100,CONT_VIA,* +V 11000,21100,CONT_VIA,* +V 10400,21100,CONT_DIF_P,* +V 9200,21100,CONT_DIF_P,* +V 9200,20700,CONT_DIF_P,* +V 10400,20700,CONT_DIF_P,* +V 11000,20700,CONT_DIF_P,* +V 9800,20700,CONT_DIF_P,* +V 11000,20300,CONT_DIF_P,* +V 9800,20300,CONT_DIF_P,* +V 10400,20300,CONT_DIF_P,* +V 9200,20300,CONT_DIF_P,* +V 11000,19900,CONT_VIA,* +V 9800,19900,CONT_VIA,* +V 10400,19900,CONT_DIF_P,* +V 9200,19900,CONT_DIF_P,* +V 11000,16300,CONT_VIA,* +V 11000,17500,CONT_VIA,* +V 11000,18700,CONT_VIA,* +V 9800,16300,CONT_VIA,* +V 9800,18700,CONT_VIA,* +V 9800,17500,CONT_VIA,* +V 11000,15100,CONT_VIA,* +V 9800,15100,CONT_VIA,* +V 10400,16700,CONT_DIF_P,* +V 11000,16700,CONT_DIF_P,* +V 11000,17100,CONT_DIF_P,* +V 11000,15900,CONT_DIF_P,* +V 10400,15900,CONT_DIF_P,* +V 10400,16300,CONT_DIF_P,* +V 11000,18300,CONT_DIF_P,* +V 11000,17900,CONT_DIF_P,* +V 10400,17900,CONT_DIF_P,* +V 10400,17100,CONT_DIF_P,* +V 10400,17500,CONT_DIF_P,* +V 10400,19500,CONT_DIF_P,* +V 11000,19100,CONT_DIF_P,* +V 10400,19100,CONT_DIF_P,* +V 10400,18700,CONT_DIF_P,* +V 10400,18300,CONT_DIF_P,* +V 11000,19500,CONT_DIF_P,* +V 11000,15500,CONT_DIF_P,* +V 10400,15500,CONT_DIF_P,* +V 9800,17100,CONT_DIF_P,* +V 9800,16700,CONT_DIF_P,* +V 9200,16700,CONT_DIF_P,* +V 9200,17100,CONT_DIF_P,* +V 9200,17500,CONT_DIF_P,* +V 9800,15900,CONT_DIF_P,* +V 9200,15900,CONT_DIF_P,* +V 9200,16300,CONT_DIF_P,* +V 9800,19500,CONT_DIF_P,* +V 9800,19100,CONT_DIF_P,* +V 9200,19100,CONT_DIF_P,* +V 9200,18700,CONT_DIF_P,* +V 9800,18300,CONT_DIF_P,* +V 9200,18300,CONT_DIF_P,* +V 9800,17900,CONT_DIF_P,* +V 9200,17900,CONT_DIF_P,* +V 9200,19500,CONT_DIF_P,* +V 9200,15500,CONT_DIF_P,* +V 9800,15500,CONT_DIF_P,* +V 10400,15100,CONT_DIF_P,* +V 11000,14700,CONT_DIF_P,* +V 10400,14700,CONT_DIF_P,* +V 11000,14300,CONT_DIF_P,* +V 10400,14300,CONT_DIF_P,* +V 9200,14300,CONT_DIF_P,* +V 9200,15100,CONT_DIF_P,* +V 9800,14700,CONT_DIF_P,* +V 9200,14700,CONT_DIF_P,* +V 9800,14300,CONT_DIF_P,* +V 10400,27400,CONT_DIF_N,* +V 10400,27000,CONT_DIF_N,* +V 10400,26600,CONT_DIF_N,* +V 10400,27800,CONT_DIF_N,* +V 10400,25000,CONT_DIF_N,* +V 10400,25400,CONT_DIF_N,* +V 10400,26200,CONT_DIF_N,* +V 10400,25800,CONT_DIF_N,* +V 9200,27000,CONT_DIF_N,* +V 9200,26600,CONT_DIF_N,* +V 9200,26200,CONT_DIF_N,* +V 9200,25800,CONT_DIF_N,* +V 9200,25400,CONT_DIF_N,* +V 9200,27800,CONT_DIF_N,* +V 9200,27400,CONT_DIF_N,* +V 9200,25000,CONT_DIF_N,* +V 9700,13600,CONT_VIA,* +V 10400,13100,CONT_POLY,* +V 10800,13600,CONT_BODY_N,* +V 9400,13600,CONT_BODY_N,* +V 10000,13600,CONT_BODY_N,* +V 8900,13600,CONT_BODY_N,* +V 9800,28700,CONT_BODY_P,* +V 11000,28700,CONT_BODY_P,* +V 9800,26100,CONT_VIA,* +V 9800,27700,CONT_VIA,* +V 9800,25700,CONT_DIF_N,* +V 9800,28100,CONT_DIF_N,* +V 9800,26500,CONT_DIF_N,* +V 9800,27300,CONT_DIF_N,* +V 9800,26900,CONT_DIF_N,* +V 9800,25300,CONT_DIF_N,* +V 9800,24900,CONT_VIA,* +V 11000,28100,CONT_VIA,* +V 11000,24900,CONT_VIA,* +V 11000,26500,CONT_VIA,* +V 11000,25300,CONT_DIF_N,* +V 11000,26900,CONT_DIF_N,* +V 11000,27300,CONT_DIF_N,* +V 11000,25700,CONT_DIF_N,* +V 11000,26100,CONT_DIF_N,* +V 11000,27700,CONT_DIF_N,* +V 11600,21900,CONT_DIF_P,* +V 12200,21900,CONT_DIF_P,* +V 12800,21900,CONT_DIF_P,* +V 13400,21900,CONT_DIF_P,* +V 12200,22500,CONT_BODY_N,* +V 13400,22500,CONT_BODY_N,* +V 13300,23200,CONT_VIA,* +V 12200,23800,CONT_VIA,* +V 13300,23800,CONT_POLY,* +V 13400,24300,CONT_BODY_P,* +V 12200,24300,CONT_BODY_P,* +V 13400,21500,CONT_DIF_P,* +V 12800,21500,CONT_DIF_P,* +V 12200,21500,CONT_DIF_P,* +V 11600,21500,CONT_DIF_P,* +V 12200,21100,CONT_VIA,* +V 13400,21100,CONT_VIA,* +V 12800,21100,CONT_DIF_P,* +V 11600,21100,CONT_DIF_P,* +V 11600,20700,CONT_DIF_P,* +V 12800,20700,CONT_DIF_P,* +V 13400,20700,CONT_DIF_P,* +V 12200,20700,CONT_DIF_P,* +V 13400,20300,CONT_DIF_P,* +V 12200,20300,CONT_DIF_P,* +V 12800,20300,CONT_DIF_P,* +V 11600,20300,CONT_DIF_P,* +V 13400,19900,CONT_VIA,* +V 12200,19900,CONT_VIA,* +V 12800,19900,CONT_DIF_P,* +V 11600,19900,CONT_DIF_P,* +V 13400,16300,CONT_VIA,* +V 13400,17500,CONT_VIA,* +V 13400,18700,CONT_VIA,* +V 12200,16300,CONT_VIA,* +V 12200,18700,CONT_VIA,* +V 12200,17500,CONT_VIA,* +V 13400,15100,CONT_VIA,* +V 12200,15100,CONT_VIA,* +V 12800,16700,CONT_DIF_P,* +V 13400,16700,CONT_DIF_P,* +V 13400,17100,CONT_DIF_P,* +V 13400,15900,CONT_DIF_P,* +V 12800,15900,CONT_DIF_P,* +V 12800,16300,CONT_DIF_P,* +V 13400,18300,CONT_DIF_P,* +V 13400,17900,CONT_DIF_P,* +V 12800,17900,CONT_DIF_P,* +V 12800,17100,CONT_DIF_P,* +V 12800,17500,CONT_DIF_P,* +V 12800,19500,CONT_DIF_P,* +V 13400,19100,CONT_DIF_P,* +V 12800,19100,CONT_DIF_P,* +V 12800,18700,CONT_DIF_P,* +V 12800,18300,CONT_DIF_P,* +V 13400,19500,CONT_DIF_P,* +V 13400,15500,CONT_DIF_P,* +V 12800,15500,CONT_DIF_P,* +V 12200,17100,CONT_DIF_P,* +V 12200,16700,CONT_DIF_P,* +V 11600,16700,CONT_DIF_P,* +V 11600,17100,CONT_DIF_P,* +V 11600,17500,CONT_DIF_P,* +V 12200,15900,CONT_DIF_P,* +V 11600,15900,CONT_DIF_P,* +V 11600,16300,CONT_DIF_P,* +V 12200,19500,CONT_DIF_P,* +V 12200,19100,CONT_DIF_P,* +V 11600,19100,CONT_DIF_P,* +V 11600,18700,CONT_DIF_P,* +V 12200,18300,CONT_DIF_P,* +V 11600,18300,CONT_DIF_P,* +V 12200,17900,CONT_DIF_P,* +V 11600,17900,CONT_DIF_P,* +V 11600,19500,CONT_DIF_P,* +V 11600,15500,CONT_DIF_P,* +V 12200,15500,CONT_DIF_P,* +V 12800,15100,CONT_DIF_P,* +V 13400,14700,CONT_DIF_P,* +V 12800,14700,CONT_DIF_P,* +V 13400,14300,CONT_DIF_P,* +V 12800,14300,CONT_DIF_P,* +V 11600,14300,CONT_DIF_P,* +V 11600,15100,CONT_DIF_P,* +V 12200,14700,CONT_DIF_P,* +V 11600,14700,CONT_DIF_P,* +V 12200,14300,CONT_DIF_P,* +V 12800,27400,CONT_DIF_N,* +V 12800,27000,CONT_DIF_N,* +V 12800,26600,CONT_DIF_N,* +V 12800,27800,CONT_DIF_N,* +V 12800,25000,CONT_DIF_N,* +V 12800,25400,CONT_DIF_N,* +V 12800,26200,CONT_DIF_N,* +V 12800,25800,CONT_DIF_N,* +V 11600,27000,CONT_DIF_N,* +V 11600,26600,CONT_DIF_N,* +V 11600,26200,CONT_DIF_N,* +V 11600,25800,CONT_DIF_N,* +V 11600,25400,CONT_DIF_N,* +V 11600,27800,CONT_DIF_N,* +V 11600,27400,CONT_DIF_N,* +V 11600,25000,CONT_DIF_N,* +V 12100,13600,CONT_VIA,* +V 12800,13100,CONT_POLY,* +V 13200,13600,CONT_BODY_N,* +V 11800,13600,CONT_BODY_N,* +V 12400,13600,CONT_BODY_N,* +V 11300,13600,CONT_BODY_N,* +V 12200,28700,CONT_BODY_P,* +V 13400,28700,CONT_BODY_P,* +V 12200,26100,CONT_VIA,* +V 12200,27700,CONT_VIA,* +V 12200,25700,CONT_DIF_N,* +V 12200,28100,CONT_DIF_N,* +V 12200,26500,CONT_DIF_N,* +V 12200,27300,CONT_DIF_N,* +V 12200,26900,CONT_DIF_N,* +V 12200,25300,CONT_DIF_N,* +V 12200,24900,CONT_VIA,* +V 13400,28100,CONT_VIA,* +V 13400,24900,CONT_VIA,* +V 13400,26500,CONT_VIA,* +V 13400,25300,CONT_DIF_N,* +V 13400,26900,CONT_DIF_N,* +V 13400,27300,CONT_DIF_N,* +V 13400,25700,CONT_DIF_N,* +V 13400,26100,CONT_DIF_N,* +V 13400,27700,CONT_DIF_N,* +V 14000,21900,CONT_DIF_P,* +V 14600,21900,CONT_DIF_P,* +V 15200,21900,CONT_DIF_P,* +V 15800,21900,CONT_DIF_P,* +V 14600,22500,CONT_BODY_N,* +V 15800,22500,CONT_BODY_N,* +V 15700,23200,CONT_VIA,* +V 14600,23800,CONT_VIA,* +V 15700,23800,CONT_POLY,* +V 15800,24300,CONT_BODY_P,* +V 14600,24300,CONT_BODY_P,* +V 15800,21500,CONT_DIF_P,* +V 15200,21500,CONT_DIF_P,* +V 14600,21500,CONT_DIF_P,* +V 14000,21500,CONT_DIF_P,* +V 14600,21100,CONT_VIA,* +V 15200,21100,CONT_DIF_P,* +V 14000,21100,CONT_DIF_P,* +V 14000,20700,CONT_DIF_P,* +V 15200,20700,CONT_DIF_P,* +V 15800,20700,CONT_DIF_P,* +V 14600,20700,CONT_DIF_P,* +V 15800,20300,CONT_DIF_P,* +V 14600,20300,CONT_DIF_P,* +V 15200,20300,CONT_DIF_P,* +V 14000,20300,CONT_DIF_P,* +V 14600,19900,CONT_VIA,* +V 15200,19900,CONT_DIF_P,* +V 14000,19900,CONT_DIF_P,* +V 14600,16300,CONT_VIA,* +V 14600,18700,CONT_VIA,* +V 14600,17500,CONT_VIA,* +V 14600,15100,CONT_VIA,* +V 15200,16700,CONT_DIF_P,* +V 15800,16700,CONT_DIF_P,* +V 15800,17100,CONT_DIF_P,* +V 15800,15900,CONT_DIF_P,* +V 15200,15900,CONT_DIF_P,* +V 15200,16300,CONT_DIF_P,* +V 15800,18300,CONT_DIF_P,* +V 15800,17900,CONT_DIF_P,* +V 15200,17900,CONT_DIF_P,* +V 15200,17100,CONT_DIF_P,* +V 15200,17500,CONT_DIF_P,* +V 15200,19500,CONT_DIF_P,* +V 15800,19100,CONT_DIF_P,* +V 15200,19100,CONT_DIF_P,* +V 15200,18700,CONT_DIF_P,* +V 15200,18300,CONT_DIF_P,* +V 15800,19500,CONT_DIF_P,* +V 15800,15500,CONT_DIF_P,* +V 15200,15500,CONT_DIF_P,* +V 14600,17100,CONT_DIF_P,* +V 14600,16700,CONT_DIF_P,* +V 14000,16700,CONT_DIF_P,* +V 14000,17100,CONT_DIF_P,* +V 14000,17500,CONT_DIF_P,* +V 14600,15900,CONT_DIF_P,* +V 14000,15900,CONT_DIF_P,* +V 14000,16300,CONT_DIF_P,* +V 14600,19500,CONT_DIF_P,* +V 14600,19100,CONT_DIF_P,* +V 14000,19100,CONT_DIF_P,* +V 14000,18700,CONT_DIF_P,* +V 14600,18300,CONT_DIF_P,* +V 14000,18300,CONT_DIF_P,* +V 14600,17900,CONT_DIF_P,* +V 14000,17900,CONT_DIF_P,* +V 14000,19500,CONT_DIF_P,* +V 14000,15500,CONT_DIF_P,* +V 14600,15500,CONT_DIF_P,* +V 15200,15100,CONT_DIF_P,* +V 15800,14700,CONT_DIF_P,* +V 15200,14700,CONT_DIF_P,* +V 15800,14300,CONT_DIF_P,* +V 15200,14300,CONT_DIF_P,* +V 14000,14300,CONT_DIF_P,* +V 14000,15100,CONT_DIF_P,* +V 14600,14700,CONT_DIF_P,* +V 14000,14700,CONT_DIF_P,* +V 14600,14300,CONT_DIF_P,* +V 15200,27400,CONT_DIF_N,* +V 15200,27000,CONT_DIF_N,* +V 15200,26600,CONT_DIF_N,* +V 15200,27800,CONT_DIF_N,* +V 15200,25000,CONT_DIF_N,* +V 15200,25400,CONT_DIF_N,* +V 15200,26200,CONT_DIF_N,* +V 15200,25800,CONT_DIF_N,* +V 14000,27000,CONT_DIF_N,* +V 14000,26600,CONT_DIF_N,* +V 14000,26200,CONT_DIF_N,* +V 14000,25800,CONT_DIF_N,* +V 14000,25400,CONT_DIF_N,* +V 14000,27800,CONT_DIF_N,* +V 14000,27400,CONT_DIF_N,* +V 14000,25000,CONT_DIF_N,* +V 14500,13600,CONT_VIA,* +V 15200,13100,CONT_POLY,* +V 15600,13600,CONT_BODY_N,* +V 14200,13600,CONT_BODY_N,* +V 14800,13600,CONT_BODY_N,* +V 13700,13600,CONT_BODY_N,* +V 14600,28700,CONT_BODY_P,* +V 15800,28700,CONT_BODY_P,* +V 14600,26100,CONT_VIA,* +V 14600,27700,CONT_VIA,* +V 14600,25700,CONT_DIF_N,* +V 14600,28100,CONT_DIF_N,* +V 14600,26500,CONT_DIF_N,* +V 14600,27300,CONT_DIF_N,* +V 14600,26900,CONT_DIF_N,* +V 14600,25300,CONT_DIF_N,* +V 14600,24900,CONT_VIA,* +V 15800,28100,CONT_VIA,* +V 15800,24900,CONT_VIA,* +V 15800,26500,CONT_VIA,* +V 15800,25300,CONT_DIF_N,* +V 15800,26900,CONT_DIF_N,* +V 15800,27300,CONT_DIF_N,* +V 15800,25700,CONT_DIF_N,* +V 15800,26100,CONT_DIF_N,* +V 15800,27700,CONT_DIF_N,* +V 15500,7000,CONT_DIF_P,* +V 14900,6200,CONT_DIF_P,* +V 14900,5800,CONT_DIF_P,* +V 14900,6600,CONT_DIF_P,* +V 14900,7000,CONT_DIF_P,* +V 14300,7000,CONT_DIF_P,* +V 14300,6600,CONT_DIF_P,* +V 14300,6200,CONT_DIF_P,* +V 14300,5800,CONT_DIF_P,* +V 15500,6600,CONT_DIF_P,* +V 15500,5800,CONT_DIF_P,* +V 15500,6200,CONT_DIF_P,* +V 14500,12000,CONT_BODY_N,* +V 14500,11200,CONT_BODY_N,* +V 14500,10800,CONT_BODY_N,* +V 14500,8300,CONT_BODY_N,* +V 14500,10400,CONT_BODY_N,* +V 14500,11600,CONT_BODY_N,* +V 14500,9100,CONT_BODY_N,* +V 14500,9500,CONT_BODY_N,* +V 14900,9100,CONT_BODY_N,* +V 14900,11600,CONT_BODY_N,* +V 14900,10400,CONT_BODY_N,* +V 14900,8300,CONT_BODY_N,* +V 14900,10800,CONT_BODY_N,* +V 14900,11200,CONT_BODY_N,* +V 14900,12000,CONT_BODY_N,* +V 14900,9500,CONT_BODY_N,* +V 15300,11200,CONT_BODY_N,* +V 15300,10800,CONT_BODY_N,* +V 15300,8300,CONT_BODY_N,* +V 15300,10400,CONT_BODY_N,* +V 15300,11600,CONT_BODY_N,* +V 15300,9100,CONT_BODY_N,* +V 15300,9500,CONT_BODY_N,* +V 15300,12000,CONT_BODY_N,* +V 15700,11600,CONT_BODY_N,* +V 15700,10400,CONT_BODY_N,* +V 15700,8300,CONT_BODY_N,* +V 15700,10800,CONT_BODY_N,* +V 15700,11200,CONT_BODY_N,* +V 15700,12000,CONT_BODY_N,* +V 15700,9500,CONT_BODY_N,* +V 15700,9100,CONT_BODY_N,* +V 14900,200,CONT_BODY_P,* +V 14400,200,CONT_BODY_P,* +V 14900,600,CONT_BODY_P,* +V 14400,600,CONT_BODY_P,* +V 14900,1000,CONT_BODY_P,* +V 14400,1000,CONT_BODY_P,* +V 14900,1400,CONT_BODY_P,* +V 14400,1400,CONT_BODY_P,* +V 14400,1800,CONT_BODY_P,* +V 14900,1800,CONT_BODY_P,* +V 14300,2700,CONT_DIF_N,* +V 15500,2800,CONT_DIF_N,* +V 15500,3400,CONT_DIF_N,* +V 15400,2300,CONT_POLY,* +V 12500,6600,CONT_DIF_P,* +V 12500,7000,CONT_DIF_P,* +V 12500,6200,CONT_DIF_P,* +V 12500,7400,CONT_DIF_P,* +V 12500,5800,CONT_DIF_P,* +V 11400,5100,CONT_BODY_N,* +V 14200,3800,CONT_POLY,* +V 9100,4000,CONT_BODY_P,* +V 9600,4000,CONT_BODY_P,* +V 10000,4000,CONT_BODY_P,* +V 7100,10200,CONT_VIA,* +V 7100,9000,CONT_VIA,* +V 8900,1600,CONT_VIA,* +V 10100,1600,CONT_VIA,* +V 8300,3500,CONT_VIA,* +V 5900,7400,CONT_VIA,* +V 5900,6600,CONT_VIA,* +V 8300,7400,CONT_VIA,* +V 8300,9000,CONT_VIA,* +V 8300,10200,CONT_VIA,* +V 8300,6600,CONT_VIA,* +V 8300,2300,CONT_VIA,* +V 7100,6600,CONT_VIA,* +V 10700,6600,CONT_VIA,* +V 10700,2300,CONT_VIA,* +V 7100,7400,CONT_VIA,* +V 7100,2300,CONT_VIA,* +V 5900,2300,CONT_VIA,* +V 5900,3500,CONT_VIA,* +V 5900,10200,CONT_VIA,* +V 5900,9000,CONT_VIA,* +V 7700,1600,CONT_VIA,* +V 9500,9000,CONT_VIA,* +V 9500,7400,CONT_VIA,* +V 9500,2300,CONT_VIA,* +V 10700,7400,CONT_VIA,* +V 10700,9000,CONT_VIA,* +V 10700,10200,CONT_VIA,* +V 4100,2300,CONT_VIA,* +V 4100,6600,CONT_VIA,* +V 4100,7400,CONT_VIA,* +V 4100,9000,CONT_VIA,* +V 4100,10200,CONT_VIA,* +V 4100,3500,CONT_VIA,* +V 9500,6600,CONT_VIA,* +V 9500,10200,CONT_VIA,* +V 6500,1600,CONT_VIA,* +V 4600,-700,CONT_VIA,* +V 4800,5300,CONT_POLY,* +V 4600,300,CONT_POLY,* +V 7100,4600,CONT_POLY,* +V 5900,4000,CONT_BODY_P,* +V 8300,4000,CONT_BODY_P,* +V 4100,4000,CONT_BODY_P,* +V 7500,4000,CONT_BODY_P,* +V 8700,4000,CONT_BODY_P,* +V 7900,4000,CONT_BODY_P,* +V 6700,4000,CONT_BODY_P,* +V 6300,4000,CONT_BODY_P,* +V 5900,-200,CONT_BODY_P,* +V 7100,-200,CONT_BODY_P,* +V 12100,-200,CONT_BODY_P,* +V 11700,-200,CONT_BODY_P,* +V 8300,-200,CONT_BODY_P,* +V 10700,-200,CONT_BODY_P,* +V 9500,-200,CONT_BODY_P,* +V 4100,-200,CONT_BODY_P,* +V 9900,-200,CONT_BODY_P,* +V 10300,-200,CONT_BODY_P,* +V 13700,-200,CONT_BODY_P,* +V 13300,-200,CONT_BODY_P,* +V 14100,-200,CONT_BODY_P,* +V 14500,-200,CONT_BODY_P,* +V 12500,-200,CONT_BODY_P,* +V 12900,-200,CONT_BODY_P,* +V 5100,-200,CONT_BODY_P,* +V 5500,-200,CONT_BODY_P,* +V 6300,-200,CONT_BODY_P,* +V 6700,-200,CONT_BODY_P,* +V 7500,-200,CONT_BODY_P,* +V 7900,-200,CONT_BODY_P,* +V 9100,-200,CONT_BODY_P,* +V 8700,-200,CONT_BODY_P,* +V 6000,12000,CONT_BODY_N,* +V 5900,5100,CONT_BODY_N,* +V 8300,5100,CONT_BODY_N,* +V 6700,5100,CONT_BODY_N,* +V 6300,5100,CONT_BODY_N,* +V 7100,12000,CONT_BODY_N,* +V 10700,5100,CONT_BODY_N,* +V 9100,5100,CONT_BODY_N,* +V 8700,5100,CONT_BODY_N,* +V 4100,5100,CONT_BODY_N,* +V 4500,12000,CONT_BODY_N,* +V 3700,12000,CONT_BODY_N,* +V 8300,12000,CONT_BODY_N,* +V 9500,12000,CONT_BODY_N,* +V 5500,12000,CONT_BODY_N,* +V 5000,12000,CONT_BODY_N,* +V 4100,12000,CONT_BODY_N,* +V 7900,5100,CONT_BODY_N,* +V 7500,5100,CONT_BODY_N,* +V 9900,5100,CONT_BODY_N,* +V 10300,5100,CONT_BODY_N,* +V 7700,11400,CONT_DIF_P,* +V 7700,8600,CONT_DIF_P,* +V 7700,8200,CONT_DIF_P,* +V 7700,5800,CONT_DIF_P,* +V 7700,11000,CONT_DIF_P,* +V 7700,10600,CONT_DIF_P,* +V 7700,9000,CONT_DIF_P,* +V 7700,10200,CONT_DIF_P,* +V 7700,7000,CONT_DIF_P,* +V 7700,6600,CONT_DIF_P,* +V 7700,9800,CONT_DIF_P,* +V 7700,9400,CONT_DIF_P,* +V 7700,6200,CONT_DIF_P,* +V 6500,6200,CONT_DIF_P,* +V 7700,7400,CONT_DIF_P,* +V 6500,11400,CONT_DIF_P,* +V 6500,8600,CONT_DIF_P,* +V 6500,8200,CONT_DIF_P,* +V 6500,5800,CONT_DIF_P,* +V 6500,11000,CONT_DIF_P,* +V 6500,10600,CONT_DIF_P,* +V 8300,7800,CONT_DIF_P,* +V 7700,7800,CONT_DIF_P,* +V 6500,7800,CONT_DIF_P,* +V 6500,10200,CONT_DIF_P,* +V 6500,7000,CONT_DIF_P,* +V 6500,6600,CONT_DIF_P,* +V 6500,9800,CONT_DIF_P,* +V 6500,9400,CONT_DIF_P,* +V 8300,11400,CONT_DIF_P,* +V 6500,7400,CONT_DIF_P,* +V 8300,6200,CONT_DIF_P,* +V 8300,5800,CONT_DIF_P,* +V 8300,7000,CONT_DIF_P,* +V 8300,9800,CONT_DIF_P,* +V 8300,10600,CONT_DIF_P,* +V 8300,11000,CONT_DIF_P,* +V 7100,8600,CONT_DIF_P,* +V 6500,9000,CONT_DIF_P,* +V 7100,8200,CONT_DIF_P,* +V 7100,7800,CONT_DIF_P,* +V 7100,11000,CONT_DIF_P,* +V 7100,10600,CONT_DIF_P,* +V 8300,9400,CONT_DIF_P,* +V 8300,8200,CONT_DIF_P,* +V 5900,5800,CONT_DIF_P,* +V 8300,8600,CONT_DIF_P,* +V 5900,6200,CONT_DIF_P,* +V 7100,9400,CONT_DIF_P,* +V 7100,9800,CONT_DIF_P,* +V 7100,7000,CONT_DIF_P,* +V 7100,5800,CONT_DIF_P,* +V 7100,6200,CONT_DIF_P,* +V 5900,10600,CONT_DIF_P,* +V 7100,11400,CONT_DIF_P,* +V 5900,11400,CONT_DIF_P,* +V 5900,8200,CONT_DIF_P,* +V 5900,7800,CONT_DIF_P,* +V 5900,11000,CONT_DIF_P,* +V 5900,9800,CONT_DIF_P,* +V 5900,9400,CONT_DIF_P,* +V 5300,11000,CONT_DIF_P,* +V 5900,7000,CONT_DIF_P,* +V 5300,10200,CONT_DIF_P,* +V 5300,7800,CONT_DIF_P,* +V 5300,7000,CONT_DIF_P,* +V 5300,6600,CONT_DIF_P,* +V 5300,9800,CONT_DIF_P,* +V 5300,9400,CONT_DIF_P,* +V 5300,10600,CONT_DIF_P,* +V 5900,8600,CONT_DIF_P,* +V 5300,7400,CONT_DIF_P,* +V 5300,11400,CONT_DIF_P,* +V 5300,8600,CONT_DIF_P,* +V 5300,8200,CONT_DIF_P,* +V 5300,5800,CONT_DIF_P,* +V 9500,11000,CONT_DIF_P,* +V 9500,9400,CONT_DIF_P,* +V 5300,9000,CONT_DIF_P,* +V 10700,7000,CONT_DIF_P,* +V 9500,7000,CONT_DIF_P,* +V 9500,5800,CONT_DIF_P,* +V 9500,6200,CONT_DIF_P,* +V 9500,8600,CONT_DIF_P,* +V 9500,11400,CONT_DIF_P,* +V 9500,8200,CONT_DIF_P,* +V 5300,6200,CONT_DIF_P,* +V 8900,7000,CONT_DIF_P,* +V 9500,10600,CONT_DIF_P,* +V 10700,9400,CONT_DIF_P,* +V 10700,8200,CONT_DIF_P,* +V 10700,11400,CONT_DIF_P,* +V 10700,8600,CONT_DIF_P,* +V 10700,6200,CONT_DIF_P,* +V 9500,9800,CONT_DIF_P,* +V 8900,8200,CONT_DIF_P,* +V 10700,9800,CONT_DIF_P,* +V 10700,10600,CONT_DIF_P,* +V 10700,11000,CONT_DIF_P,* +V 10700,7800,CONT_DIF_P,* +V 8900,9000,CONT_DIF_P,* +V 8900,7800,CONT_DIF_P,* +V 9500,7800,CONT_DIF_P,* +V 10100,6600,CONT_DIF_P,* +V 8900,6600,CONT_DIF_P,* +V 8900,9800,CONT_DIF_P,* +V 8900,9400,CONT_DIF_P,* +V 8900,6200,CONT_DIF_P,* +V 8900,7400,CONT_DIF_P,* +V 8900,11400,CONT_DIF_P,* +V 10700,5800,CONT_DIF_P,* +V 10100,5800,CONT_DIF_P,* +V 8900,5800,CONT_DIF_P,* +V 8900,11000,CONT_DIF_P,* +V 8900,10600,CONT_DIF_P,* +V 10100,9000,CONT_DIF_P,* +V 10100,7800,CONT_DIF_P,* +V 10100,10200,CONT_DIF_P,* +V 8900,10200,CONT_DIF_P,* +V 10100,10600,CONT_DIF_P,* +V 10100,9800,CONT_DIF_P,* +V 10100,9400,CONT_DIF_P,* +V 10100,6200,CONT_DIF_P,* +V 10100,7400,CONT_DIF_P,* +V 10100,11400,CONT_DIF_P,* +V 10100,8600,CONT_DIF_P,* +V 8900,8600,CONT_DIF_P,* +V 10100,7000,CONT_DIF_P,* +V 10100,8200,CONT_DIF_P,* +V 4700,6200,CONT_DIF_P,* +V 4700,7400,CONT_DIF_P,* +V 4700,11400,CONT_DIF_P,* +V 4700,8600,CONT_DIF_P,* +V 4700,9000,CONT_DIF_P,* +V 4700,7800,CONT_DIF_P,* +V 4700,7000,CONT_DIF_P,* +V 10100,11000,CONT_DIF_P,* +V 4700,5800,CONT_DIF_P,* +V 4700,8200,CONT_DIF_P,* +V 4700,11000,CONT_DIF_P,* +V 4700,6600,CONT_DIF_P,* +V 4700,10600,CONT_DIF_P,* +V 4700,9800,CONT_DIF_P,* +V 4700,10200,CONT_DIF_P,* +V 4700,9400,CONT_DIF_P,* +V 4100,6200,CONT_DIF_P,* +V 4100,7000,CONT_DIF_P,* +V 4100,5800,CONT_DIF_P,* +V 4100,9800,CONT_DIF_P,* +V 4100,11000,CONT_DIF_P,* +V 4100,8200,CONT_DIF_P,* +V 4100,11400,CONT_DIF_P,* +V 4100,8600,CONT_DIF_P,* +V 4100,10600,CONT_DIF_P,* +V 4100,9400,CONT_DIF_P,* +V 4100,7800,CONT_DIF_P,* +V 7700,2100,CONT_DIF_N,* +V 7100,700,CONT_DIF_N,* +V 7700,2500,CONT_DIF_N,* +V 7100,3300,CONT_DIF_N,* +V 7100,2800,CONT_DIF_N,* +V 6500,2900,CONT_DIF_N,* +V 8300,1100,CONT_DIF_N,* +V 8300,1500,CONT_DIF_N,* +V 5900,700,CONT_DIF_N,* +V 6500,3300,CONT_DIF_N,* +V 6500,2100,CONT_DIF_N,* +V 6500,2500,CONT_DIF_N,* +V 7700,2900,CONT_DIF_N,* +V 7700,3300,CONT_DIF_N,* +V 7100,1500,CONT_DIF_N,* +V 7100,1100,CONT_DIF_N,* +V 5300,2500,CONT_DIF_N,* +V 7100,1900,CONT_DIF_N,* +V 8300,1900,CONT_DIF_N,* +V 8300,2700,CONT_DIF_N,* +V 8300,3100,CONT_DIF_N,* +V 8300,700,CONT_DIF_N,* +V 5300,3300,CONT_DIF_N,* +V 10700,1100,CONT_DIF_N,* +V 9500,1500,CONT_DIF_N,* +V 5900,1100,CONT_DIF_N,* +V 5900,1500,CONT_DIF_N,* +V 5900,1900,CONT_DIF_N,* +V 5900,2700,CONT_DIF_N,* +V 5900,3100,CONT_DIF_N,* +V 10700,2700,CONT_DIF_N,* +V 10700,3100,CONT_DIF_N,* +V 10700,700,CONT_DIF_N,* +V 5300,2100,CONT_DIF_N,* +V 5300,1700,CONT_DIF_N,* +V 5300,1300,CONT_DIF_N,* +V 5300,900,CONT_DIF_N,* +V 5300,2900,CONT_DIF_N,* +V 8900,2500,CONT_DIF_N,* +V 7700,700,CONT_DIF_N,* +V 8900,1200,CONT_DIF_N,* +V 10100,2900,CONT_DIF_N,* +V 9500,1100,CONT_DIF_N,* +V 9500,700,CONT_DIF_N,* +V 9500,1900,CONT_DIF_N,* +V 10700,1900,CONT_DIF_N,* +V 10100,700,CONT_DIF_N,* +V 8900,700,CONT_DIF_N,* +V 9500,3300,CONT_DIF_N,* +V 10700,1500,CONT_DIF_N,* +V 8900,2900,CONT_DIF_N,* +V 8900,3300,CONT_DIF_N,* +V 8900,2100,CONT_DIF_N,* +V 9500,2800,CONT_DIF_N,* +V 10100,3300,CONT_DIF_N,* +V 10100,2100,CONT_DIF_N,* +V 10100,2500,CONT_DIF_N,* +V 10100,1200,CONT_DIF_N,* +V 4700,1300,CONT_DIF_N,* +V 4700,900,CONT_DIF_N,* +V 4700,2500,CONT_DIF_N,* +V 4700,2100,CONT_DIF_N,* +V 4700,2900,CONT_DIF_N,* +V 4700,3300,CONT_DIF_N,* +V 4700,1700,CONT_DIF_N,* +V 4100,1500,CONT_DIF_N,* +V 4100,1100,CONT_DIF_N,* +V 7700,1200,CONT_DIF_N,* +V 4100,700,CONT_DIF_N,* +V 4100,3100,CONT_DIF_N,* +V 4100,2700,CONT_DIF_N,* +V 4100,1900,CONT_DIF_N,* +V 6500,700,CONT_DIF_N,* +V 6500,1200,CONT_DIF_N,* +V 16100,7500,CONT_VIA,* +V 16100,6700,CONT_VIA,* +V 16100,5500,CONT_BODY_N,* +V 16100,9100,CONT_BODY_N,* +V 16100,8300,CONT_BODY_N,* +V 16100,10800,CONT_BODY_N,* +V 16100,7100,CONT_BODY_N,* +V 16100,11200,CONT_BODY_N,* +V 16100,6300,CONT_BODY_N,* +V 16100,5900,CONT_BODY_N,* +V 16100,12000,CONT_BODY_N,* +V 16100,9500,CONT_BODY_N,* +V 16100,11600,CONT_BODY_N,* +V 16100,7900,CONT_BODY_N,* +V 16100,10400,CONT_BODY_N,* +V 16100,5100,CONT_BODY_N,* +V 13700,1600,CONT_VIA,* +V 12500,1600,CONT_VIA,* +V 11300,1600,CONT_VIA,* +V 11900,9400,CONT_DIF_P,* +V 11900,7000,CONT_DIF_P,* +V 11900,5800,CONT_DIF_P,* +V 11900,6200,CONT_DIF_P,* +V 11900,8600,CONT_DIF_P,* +V 11900,11400,CONT_DIF_P,* +V 11900,8200,CONT_DIF_P,* +V 11900,7800,CONT_DIF_P,* +V 11900,10600,CONT_DIF_P,* +V 11300,9000,CONT_DIF_P,* +V 11300,7800,CONT_DIF_P,* +V 11300,10200,CONT_DIF_P,* +V 11300,7000,CONT_DIF_P,* +V 11300,6600,CONT_DIF_P,* +V 11300,9800,CONT_DIF_P,* +V 11900,9800,CONT_DIF_P,* +V 11300,6200,CONT_DIF_P,* +V 11300,7400,CONT_DIF_P,* +V 11300,11400,CONT_DIF_P,* +V 11300,8600,CONT_DIF_P,* +V 11300,8200,CONT_DIF_P,* +V 11300,5800,CONT_DIF_P,* +V 11300,11000,CONT_DIF_P,* +V 11900,11000,CONT_DIF_P,* +V 13100,9800,CONT_DIF_P,* +V 13100,9400,CONT_DIF_P,* +V 13100,8600,CONT_DIF_P,* +V 13100,6200,CONT_DIF_P,* +V 13100,5800,CONT_DIF_P,* +V 13100,7000,CONT_DIF_P,* +V 12500,10200,CONT_DIF_P,* +V 11300,9400,CONT_DIF_P,* +V 12500,9000,CONT_DIF_P,* +V 13100,10600,CONT_DIF_P,* +V 13100,11000,CONT_DIF_P,* +V 13100,7800,CONT_DIF_P,* +V 13100,8200,CONT_DIF_P,* +V 13100,11400,CONT_DIF_P,* +V 12500,8600,CONT_DIF_P,* +V 11300,10600,CONT_DIF_P,* +V 12500,9400,CONT_DIF_P,* +V 12500,9800,CONT_DIF_P,* +V 12500,10600,CONT_DIF_P,* +V 12500,7800,CONT_DIF_P,* +V 12500,8200,CONT_DIF_P,* +V 13700,10200,CONT_DIF_P,* +V 13700,7800,CONT_DIF_P,* +V 13700,9000,CONT_DIF_P,* +V 13700,8600,CONT_DIF_P,* +V 13700,11400,CONT_DIF_P,* +V 12500,11400,CONT_DIF_P,* +V 13700,6200,CONT_DIF_P,* +V 13700,9400,CONT_DIF_P,* +V 13700,9800,CONT_DIF_P,* +V 13700,6600,CONT_DIF_P,* +V 13700,7000,CONT_DIF_P,* +V 13700,10600,CONT_DIF_P,* +V 13700,11000,CONT_DIF_P,* +V 12500,11000,CONT_DIF_P,* +V 13700,8200,CONT_DIF_P,* +V 13100,10200,CONT_DIF_P,* +V 11900,10200,CONT_DIF_P,* +V 11900,9000,CONT_DIF_P,* +V 13100,9000,CONT_DIF_P,* +V 11900,7400,CONT_DIF_P,* +V 13100,7400,CONT_DIF_P,* +V 13700,7400,CONT_DIF_P,* +V 11900,6600,CONT_DIF_P,* +V 13100,6600,CONT_DIF_P,* +V 13700,5800,CONT_DIF_P,* +V 13700,700,CONT_DIF_N,* +V 13700,1200,CONT_DIF_N,* +V 12500,1200,CONT_DIF_N,* +V 11300,700,CONT_DIF_N,* +V 13700,2100,CONT_DIF_N,* +V 11900,1500,CONT_DIF_N,* +V 13700,3300,CONT_DIF_N,* +V 11900,1100,CONT_DIF_N,* +V 11900,700,CONT_DIF_N,* +V 11900,1900,CONT_DIF_N,* +V 11900,3300,CONT_DIF_N,* +V 11300,2900,CONT_DIF_N,* +V 11300,3300,CONT_DIF_N,* +V 11300,2100,CONT_DIF_N,* +V 11300,2500,CONT_DIF_N,* +V 11300,1200,CONT_DIF_N,* +V 11900,2800,CONT_DIF_N,* +V 13100,1500,CONT_DIF_N,* +V 13700,2900,CONT_DIF_N,* +V 12500,3300,CONT_DIF_N,* +V 12500,2900,CONT_DIF_N,* +V 13100,3300,CONT_DIF_N,* +V 13100,1900,CONT_DIF_N,* +V 13100,700,CONT_DIF_N,* +V 13100,1100,CONT_DIF_N,* +V 13700,2500,CONT_DIF_N,* +V 13100,2800,CONT_DIF_N,* +V 12500,700,CONT_DIF_N,* +V 12500,2500,CONT_DIF_N,* +V 12500,2100,CONT_DIF_N,* +V 13100,2300,CONT_DIF_N,* +V 11900,2300,CONT_DIF_N,* +V 9500,4600,CONT_POLY,* +V 14900,3500,CONT_VIA,* +V 14900,-200,CONT_BODY_P,* +V 14900,5100,CONT_BODY_N,* +V 14300,3300,CONT_DIF_N,* +V 14900,2700,CONT_DIF_N,* +V 14900,3100,CONT_DIF_N,* +V 16100,4000,CONT_BODY_P,* +V 16100,4000,CONT_BODY_P,* +V 16100,2800,CONT_BODY_P,* +V 16100,3200,CONT_BODY_P,* +V 16100,3600,CONT_VIA,* +V 16100,2400,CONT_VIA,* +V 14800,4500,CONT_POLY,* +V 10700,12000,CONT_BODY_N,* +V 15400,-700,CONT_VIA,* +V 11300,-200,CONT_BODY_P,* +V 10800,4000,CONT_POLY,* +V 14900,4000,CONT_BODY_P,* +V 14900,7500,CONT_DIF_P,* +V 15500,7500,CONT_DIF_P,* +V 14300,7500,CONT_DIF_P,* +V 3300,5800,CONT_VIA,* +V 2100,9800,CONT_VIA,* +V 2100,6600,CONT_VIA,* +V 3300,9900,CONT_VIA,* +V 3100,9400,CONT_POLY,* +V 2100,5100,CONT_BODY_N,* +V 2100,11600,CONT_BODY_N,* +V 2100,11200,CONT_BODY_N,* +V 2100,10800,CONT_BODY_N,* +V 2100,10400,CONT_BODY_N,* +V 2100,7000,CONT_BODY_N,* +V 2100,7400,CONT_BODY_N,* +V 2100,7800,CONT_BODY_N,* +V 2100,8200,CONT_BODY_N,* +V 2100,8600,CONT_BODY_N,* +V 2100,9000,CONT_BODY_N,* +V 2100,12000,CONT_BODY_N,* +V 2100,9400,CONT_BODY_N,* +V 2100,5500,CONT_BODY_N,* +V 2100,5900,CONT_BODY_N,* +V 2100,6300,CONT_BODY_N,* +V 2700,5500,CONT_BODY_N,* +V 2700,5900,CONT_BODY_N,* +V 2700,6300,CONT_BODY_N,* +V 3300,10300,CONT_BODY_N,* +V 3300,10700,CONT_BODY_N,* +V 3300,5100,CONT_BODY_N,* +V 2700,5100,CONT_BODY_N,* +V 2700,6900,CONT_DIF_P,* +V 2700,11300,CONT_DIF_P,* +V 3300,12000,CONT_BODY_N,* +V 3300,11300,CONT_BODY_N,* +V 3500,2300,CONT_VIA,* +V 3500,3500,CONT_VIA,* +V 3500,4000,CONT_BODY_P,* +V 3500,300,CONT_BODY_P,* +V 3500,700,CONT_BODY_P,* +V 3500,1100,CONT_BODY_P,* +V 3500,1500,CONT_BODY_P,* +V 3500,1900,CONT_BODY_P,* +V 3500,2700,CONT_BODY_P,* +V 3500,3100,CONT_BODY_P,* +V 3500,-200,CONT_BODY_P,* +V 16400,29200,CONT_VIA,* +V 15800,29200,CONT_VIA,* +V 16400,25900,CONT_VIA,* +V 16100,24300,CONT_VIA,* +V 16400,27900,CONT_VIA,* +V 3700,23200,CONT_VIA,* +V 16400,28300,CONT_BODY_P,* +V 16400,28700,CONT_BODY_P,* +V 16400,24300,CONT_BODY_P,* +V 16400,25500,CONT_BODY_P,* +V 16400,25100,CONT_BODY_P,* +V 16400,24700,CONT_BODY_P,* +V 16400,26300,CONT_BODY_P,* +V 16400,26700,CONT_BODY_P,* +V 16400,27100,CONT_BODY_P,* +V 16400,27500,CONT_BODY_P,* +V 1200,28700,CONT_BODY_P,* +V 1200,24300,CONT_BODY_P,* +V 800,28300,CONT_BODY_P,* +V 800,24300,CONT_BODY_P,* +V 800,25500,CONT_BODY_P,* +V 800,25100,CONT_BODY_P,* +V 800,24700,CONT_BODY_P,* +V 800,28700,CONT_BODY_P,* +V 800,25900,CONT_BODY_P,* +V 800,26300,CONT_BODY_P,* +V 800,26700,CONT_BODY_P,* +V 800,27100,CONT_BODY_P,* +V 800,27500,CONT_BODY_P,* +V 800,27900,CONT_BODY_P,* +V 1400,22500,CONT_BODY_N,* +V 16400,22000,CONT_BODY_N,* +V 16400,22500,CONT_BODY_N,* +V 16400,20400,CONT_BODY_N,* +V 16400,20800,CONT_BODY_N,* +V 16400,20000,CONT_BODY_N,* +V 16400,21200,CONT_BODY_N,* +V 16400,21600,CONT_BODY_N,* +V 800,21200,CONT_BODY_N,* +V 800,20800,CONT_BODY_N,* +V 800,20400,CONT_BODY_N,* +V 800,20000,CONT_BODY_N,* +V 800,22500,CONT_BODY_N,* +V 800,22000,CONT_BODY_N,* +V 800,21600,CONT_BODY_N,* +V 1300,13600,CONT_BODY_N,* +V 16400,13600,CONT_BODY_N,* +V 16400,15600,CONT_BODY_N,* +V 16400,17200,CONT_BODY_N,* +V 16400,16800,CONT_BODY_N,* +V 16400,16000,CONT_BODY_N,* +V 16000,13600,CONT_BODY_N,* +V 16400,19600,CONT_BODY_N,* +V 16400,17600,CONT_BODY_N,* +V 16400,18000,CONT_BODY_N,* +V 16400,16400,CONT_BODY_N,* +V 16400,14000,CONT_BODY_N,* +V 16400,14400,CONT_BODY_N,* +V 16400,14800,CONT_BODY_N,* +V 16400,15200,CONT_BODY_N,* +V 16400,18400,CONT_BODY_N,* +V 16400,18800,CONT_BODY_N,* +V 16400,19200,CONT_BODY_N,* +V 800,18000,CONT_BODY_N,* +V 800,17600,CONT_BODY_N,* +V 800,18400,CONT_BODY_N,* +V 800,19600,CONT_BODY_N,* +V 800,19200,CONT_BODY_N,* +V 800,18800,CONT_BODY_N,* +V 800,14800,CONT_BODY_N,* +V 800,14400,CONT_BODY_N,* +V 800,14000,CONT_BODY_N,* +V 800,13600,CONT_BODY_N,* +V 800,16800,CONT_BODY_N,* +V 800,17200,CONT_BODY_N,* +V 800,16400,CONT_BODY_N,* +V 800,16000,CONT_BODY_N,* +V 800,15600,CONT_BODY_N,* +V 800,15200,CONT_BODY_N,* +V 1400,20300,CONT_DIF_P,* +V 1400,20700,CONT_DIF_P,* +V 1400,21100,CONT_DIF_P,* +V 1400,21500,CONT_DIF_P,* +V 1400,21900,CONT_DIF_P,* +V 1400,17500,CONT_DIF_P,* +V 1400,17900,CONT_DIF_P,* +V 1400,15100,CONT_DIF_P,* +V 1400,14700,CONT_DIF_P,* +V 1400,14300,CONT_DIF_P,* +V 1400,19900,CONT_DIF_P,* +V 1400,19500,CONT_DIF_P,* +V 1400,19100,CONT_DIF_P,* +V 1400,18700,CONT_DIF_P,* +V 1400,18300,CONT_DIF_P,* +V 1400,17100,CONT_DIF_P,* +V 1400,16700,CONT_DIF_P,* +V 1400,16300,CONT_DIF_P,* +V 1400,15900,CONT_DIF_P,* +V 1400,15500,CONT_DIF_P,* +V 1400,27300,CONT_DIF_N,* +V 1400,26100,CONT_DIF_N,* +V 1400,24900,CONT_DIF_N,* +V 1400,25300,CONT_DIF_N,* +V 1400,25700,CONT_DIF_N,* +V 1400,26500,CONT_DIF_N,* +V 1400,26900,CONT_DIF_N,* +V 1400,27700,CONT_DIF_N,* +V 1400,28100,CONT_DIF_N,* +V 16900,23200,CONT_VIA,* +V 16300,23200,CONT_VIA,* +V 16900,1600,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/padlib/palotw_sp.ap b/alliance/src/cells/src/padlib/palotw_sp.ap new file mode 100644 index 00000000..fa8d41c8 --- /dev/null +++ b/alliance/src/cells/src/padlib/palotw_sp.ap @@ -0,0 +1,1502 @@ +V ALLIANCE : 4 +H palotw_sp,P,26/ 0/100,100 +A 0,-700,17200,35600 +C 0,29600,12000,vsse,0,WEST,ALU2 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 17200,16800,12000,vdde,1,EAST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,8400,4000,vddi,1,EAST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 0,8400,4000,vddi,0,WEST,ALU2 +C 17200,600,1200,ck,1,EAST,ALU2 +C 0,600,1200,ck,0,WEST,ALU2 +C 4600,-700,200,i,1,SOUTH,ALU2 +C 4600,-700,200,i,0,SOUTH,ALU1 +C 15400,-700,200,b,1,SOUTH,ALU2 +C 15400,-700,200,b,0,SOUTH,ALU1 +S 2400,9100,3000,9100,3900,*,RIGHT,PTRANS +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 1900,5100,16300,5100,400,*,RIGHT,NWELL +S 1900,8600,16300,8600,7200,*,RIGHT,NWELL +S 7700,30100,7700,35600,6200,*,UP,ALU1 +S 11000,5500,14600,5500,100,*,RIGHT,POLY +S 15200,3700,15200,5500,100,*,UP,POLY +S 14600,-100,14600,1900,800,*,DOWN,ALU1 +S 14300,0,14300,1900,300,*,DOWN,PTIE +S 14600,0,14600,1900,300,*,DOWN,PTIE +S 14900,-300,14900,1900,300,*,DOWN,PTIE +S 14900,1800,16200,1800,300,*,LEFT,PTIE +S 16100,1700,16100,4100,300,*,UP,PTIE +S 14900,2600,14900,3500,300,*,DOWN,NDIF +S 15400,-700,15400,2300,200,*,DOWN,ALU1 +S 14300,2600,14300,3500,300,*,UP,NDIF +S 14600,2400,14600,3700,100,*,UP,NTRANS +S 15200,2400,15200,3700,100,*,UP,NTRANS +S 15500,2600,15500,3500,300,*,UP,NDIF +S 15200,2200,15200,2400,100,*,DOWN,POLY +S 12500,5800,12500,12900,200,*,UP,ALU1 +S 7400,5100,11500,5100,300,*,RIGHT,ALU1 +S 14900,-300,14900,4000,200,*,UP,ALU1 +S 13900,3700,13900,3900,100,*,DOWN,POLY +S 14000,3700,14000,3900,100,*,DOWN,POLY +S 13900,4700,13900,5300,100,*,DOWN,POLY +S 14000,4700,14000,5300,100,*,DOWN,POLY +S 13900,4500,14600,4500,300,*,RIGHT,POLY +S 14600,3700,14600,4300,100,*,UP,POLY +S 14200,5100,15000,5100,300,*,RIGHT,NTIE +S 11300,5100,13700,5100,300,*,RIGHT,NTIE +S 7400,4000,10100,4000,300,*,RIGHT,PTIE +S 5700,4000,10100,4000,300,*,RIGHT,ALU1 +S 10300,3800,10300,4500,100,*,DOWN,POLY +S 10300,4600,10900,4600,100,*,LEFT,POLY +S 11100,4500,11100,5300,100,*,DOWN,POLY +S 11000,3600,11000,4100,100,*,DOWN,POLY +S 11100,3800,11100,4100,100,*,DOWN,POLY +S 11100,3700,14000,3700,100,*,RIGHT,POLY +S 11100,3600,14000,3600,100,*,RIGHT,POLY +S 11300,4000,13700,4000,300,*,RIGHT,PTIE +S 13700,5700,13700,11500,300,*,UP,PDIF +S 13400,5500,13400,11700,100,*,UP,PTRANS +S 13100,5700,13100,11500,300,*,UP,PDIF +S 12800,5500,12800,11700,100,*,UP,PTRANS +S 12500,5700,12500,11500,300,*,UP,PDIF +S 11900,5700,11900,11500,300,*,UP,PDIF +S 12200,5500,12200,11700,100,*,UP,PTRANS +S 11300,5700,11300,11500,300,*,UP,PDIF +S 11600,5500,11600,11700,100,*,UP,PTRANS +S 13700,600,13700,3400,300,*,UP,NDIF +S 13100,600,13100,3400,200,*,UP,NDIF +S 12500,600,12500,3400,300,*,UP,NDIF +S 11900,600,11900,3400,200,*,UP,NDIF +S 11300,600,11300,3400,300,*,UP,NDIF +S 13400,400,13400,3600,100,*,UP,NTRANS +S 12800,400,12800,3600,100,*,UP,NTRANS +S 12200,400,12200,3600,100,*,UP,NTRANS +S 11600,400,11600,3600,100,*,UP,NTRANS +S 16100,2300,16100,4100,300,*,UP,ALU1 +S 16200,1600,16800,1600,300,*,LEFT,ALU1 +S 16000,23200,16800,23200,300,*,RIGHT,ALU1 +S 100,600,17200,600,1200,ck,RIGHT,ALU2 +S 6500,1600,16600,1600,300,*,RIGHT,ALU2 +S 4700,900,4700,11400,200,*,UP,ALU1 +S 5300,900,5300,11400,200,*,UP,ALU1 +S 5900,5000,5900,12100,200,*,UP,ALU1 +S 5300,4600,7000,4600,200,*,RIGHT,ALU1 +S 9500,5700,9500,12000,200,*,UP,ALU1 +S 7100,5700,7100,12000,200,*,UP,ALU1 +S 10100,600,10100,3300,200,*,UP,ALU1 +S 8900,600,8900,3300,200,*,UP,ALU1 +S 7700,600,7700,3300,200,*,UP,ALU1 +S 10700,5000,10700,12100,200,*,UP,ALU1 +S 4100,5000,4100,12100,200,*,UP,ALU1 +S 6500,5800,6500,12900,200,*,UP,ALU1 +S 7700,5800,7700,12900,200,*,UP,ALU1 +S 8900,5800,8900,12900,200,*,UP,ALU1 +S 10100,5800,10100,12900,200,*,UP,ALU1 +S 8300,5000,8300,12000,200,*,UP,ALU1 +S 6500,600,6500,3300,200,*,UP,ALU1 +S 5900,5100,6800,5100,300,*,RIGHT,ALU1 +S 10700,-300,10700,3200,200,*,UP,ALU1 +S 4100,-300,4100,4100,200,*,UP,ALU1 +S 5900,-300,5900,4100,200,*,UP,ALU1 +S 7100,-300,7100,3200,200,*,UP,ALU1 +S 9500,-300,9500,4100,200,*,UP,ALU1 +S 8300,-300,8300,4100,200,*,UP,ALU1 +S 4600,-700,4600,300,200,*,UP,ALU1 +S 5600,3700,5600,5400,100,*,UP,POLY +S 4900,5300,5600,5300,300,*,RIGHT,POLY +S 6200,3700,8000,3700,100,*,RIGHT,POLY +S 6200,5400,8000,5400,100,*,RIGHT,POLY +S 7100,3700,7100,5400,200,*,UP,POLY +S 4400,3700,4400,5400,100,*,UP,POLY +S 4400,200,4400,400,100,*,UP,POLY +S 5800,4000,6800,4000,300,*,RIGHT,PTIE +S 5800,5100,6800,5100,300,*,RIGHT,NTIE +S 7400,5400,7400,11700,100,*,UP,PTRANS +S 8000,5400,8000,11700,100,*,UP,PTRANS +S 7100,5600,7100,11500,300,*,UP,PDIF +S 8300,5600,8300,11500,300,*,UP,PDIF +S 6500,5600,6500,11500,300,*,UP,PDIF +S 10100,5600,10100,11500,300,*,UP,PDIF +S 7700,5600,7700,11500,300,*,UP,PDIF +S 5300,5600,5300,11500,300,*,UP,PDIF +S 5600,5400,5600,11700,100,*,UP,PTRANS +S 5900,5600,5900,11500,300,*,UP,PDIF +S 6200,5400,6200,11700,100,*,UP,PTRANS +S 6800,5400,6800,11700,100,*,UP,PTRANS +S 9500,5600,9500,11500,300,*,UP,PDIF +S 10700,5600,10700,11500,300,*,UP,PDIF +S 8900,5600,8900,11500,300,*,UP,PDIF +S 8600,5400,8600,11700,100,*,UP,PTRANS +S 9200,5400,9200,11700,100,*,UP,PTRANS +S 9800,5400,9800,11700,100,*,UP,PTRANS +S 10400,5400,10400,11700,100,*,UP,PTRANS +S 4400,5400,4400,11700,100,*,UP,PTRANS +S 4700,5600,4700,11500,300,*,UP,PDIF +S 4100,5600,4100,11500,300,*,UP,PDIF +S 7400,400,7400,3700,100,*,UP,NTRANS +S 8000,400,8000,3700,100,*,UP,NTRANS +S 7100,600,7100,3500,200,*,UP,NDIF +S 8300,600,8300,3500,200,*,UP,NDIF +S 6500,600,6500,3500,300,*,UP,NDIF +S 7700,600,7700,3500,300,*,UP,NDIF +S 5300,600,5300,3500,300,*,UP,NDIF +S 5600,400,5600,3700,100,*,UP,NTRANS +S 5900,600,5900,3500,200,*,UP,NDIF +S 6200,400,6200,3700,100,*,UP,NTRANS +S 6800,400,6800,3700,100,*,UP,NTRANS +S 10400,400,10400,3700,100,*,UP,NTRANS +S 9500,600,9500,3500,200,*,UP,NDIF +S 8900,600,8900,3500,300,*,UP,NDIF +S 8600,400,8600,3700,100,*,UP,NTRANS +S 10100,600,10100,3500,300,*,UP,NDIF +S 9200,400,9200,3700,100,*,UP,NTRANS +S 9800,400,9800,3700,100,*,UP,NTRANS +S 4100,600,4100,3500,200,*,UP,NDIF +S 4400,400,4400,3700,100,*,UP,NTRANS +S 4700,600,4700,3500,300,*,UP,NDIF +S 16100,5000,16100,12100,300,*,UP,ALU1 +S 16100,5000,16100,12100,300,*,UP,NTIE +S 13100,700,13100,3900,200,*,UP,ALU1 +S 11300,600,11300,4600,200,*,UP,ALU1 +S 11900,3900,13700,3900,200,*,RIGHT,ALU1 +S 13700,600,13700,3300,200,*,UP,ALU1 +S 12500,600,12500,3300,200,*,UP,ALU1 +S 11900,700,11900,3900,200,*,UP,ALU1 +S 13700,3900,13700,12900,200,*,UP,ALU1 +S 11300,5800,11300,12900,200,*,UP,ALU1 +S 11900,4600,11900,11400,200,*,UP,ALU1 +S 11300,4600,13200,4600,200,*,RIGHT,ALU1 +S 13100,4600,13100,11400,200,*,UP,ALU1 +S 16700,1500,16700,23300,300,*,UP,ALU1 +S 8600,5400,10400,5400,100,*,RIGHT,POLY +S 8600,3700,10400,3700,100,*,RIGHT,POLY +S 9500,4600,9500,5400,300,*,DOWN,POLY +S 10500,4500,11000,4500,100,*,LEFT,POLY +S 11000,4500,11000,5400,100,*,DOWN,POLY +S 7400,5100,9200,5100,300,*,RIGHT,NTIE +S 9800,5100,10700,5100,300,*,RIGHT,NTIE +S 10700,600,10700,3500,300,*,UP,NDIF +S 14900,5000,14900,12100,200,*,UP,ALU1 +S 11000,5400,14600,5400,100,*,RIGHT,POLY +S 15400,4000,16200,4000,300,*,LEFT,PTIE +S 5000,-200,15000,-200,300,*,RIGHT,ALU1 +S 14700,4500,15500,4500,300,*,LEFT,ALU1 +S 15400,5100,16200,5100,300,*,RIGHT,NTIE +S 9400,4600,10800,4600,200,*,LEFT,ALU1 +S 10400,3700,10400,4500,100,*,DOWN,POLY +S 10800,3900,10800,4600,200,*,UP,ALU1 +S 15200,8100,15200,12100,2000,*,DOWN,ALU1 +S 15200,8100,15200,12000,2000,*,DOWN,NTIE +S 15200,5500,15200,7800,100,*,UP,PTRANS +S 14600,5500,14600,7800,100,*,UP,PTRANS +S 14900,5700,14900,7600,300,*,UP,PDIF +S 15500,5700,15500,7600,300,*,UP,PDIF +S 14300,5700,14300,7600,300,*,UP,PDIF +S 15500,2800,15500,7500,200,*,UP,ALU1 +S 14300,2700,14300,7500,200,*,UP,ALU1 +S 3400,28000,3400,28800,100,*,UP,ALU1 +S 3800,24200,3800,29300,800,*,UP,ALU1 +S 6400,23100,6400,23800,200,*,UP,ALU1 +S 3800,13500,3800,22600,800,*,UP,ALU1 +S 3400,24300,4200,24300,300,*,RIGHT,PTIE +S 3500,24200,3500,28800,300,*,UP,PTIE +S 3400,28700,4200,28700,300,*,RIGHT,PTIE +S 3500,22500,4100,22500,300,*,RIGHT,NTIE +S 3500,13600,3500,22600,300,*,UP,NTIE +S 3500,13600,4100,13600,300,*,RIGHT,NTIE +S 4100,14100,4100,22000,300,*,UP,PDIF +S 4100,24900,4100,28200,300,*,UP,NDIF +S 3700,13400,3700,22700,800,*,UP,NWELL +S 5900,12500,5900,12900,300,*,UP,ALU1 +S 11700,24200,11700,29300,600,*,UP,ALU1 +S 11300,28900,11300,29300,300,*,UP,ALU1 +S 11400,24300,12000,24300,300,*,RIGHT,PTIE +S 11500,28700,12000,28700,300,*,RIGHT,PTIE +S 11900,24200,11900,28800,300,*,UP,PTIE +S 4600,29600,10800,29600,900,*,RIGHT,ALU1 +S 11700,13500,11700,22600,600,*,UP,ALU1 +S 11500,22500,12000,22500,300,*,RIGHT,NTIE +S 11900,13600,11900,22600,300,*,UP,NTIE +S 11500,13600,12000,13600,300,*,RIGHT,NTIE +S 11800,13400,11800,22700,600,*,UP,NWELL +S 6400,13000,13800,13000,200,*,RIGHT,ALU1 +S 6400,13100,13800,13100,200,*,RIGHT,ALU1 +S 6400,23200,16700,23200,300,*,RIGHT,ALU2 +S 3300,5700,3300,9300,300,*,DOWN,ALU1 +S 3100,9200,3100,9400,200,*,DOWN,ALU1 +S 2500,8800,2500,9700,500,*,DOWN,ALU1 +S 2700,9800,2700,10900,1500,*,UP,ALU1 +S 2100,5000,2100,12100,300,*,DOWN,ALU1 +S 2400,5000,2400,8700,900,*,UP,ALU1 +S 3300,9700,3300,12000,300,*,UP,NTIE +S 3300,5000,3300,9100,300,*,UP,NTIE +S 3500,8900,3500,9900,300,*,UP,NTIE +S 2700,5100,2700,6400,1100,*,DOWN,NTIE +S 2000,5100,4000,5100,300,*,RIGHT,NTIE +S 2100,5000,2100,12100,300,*,UP,NTIE +S 2000,12000,16200,12000,300,*,RIGHT,NTIE +S 2700,11300,2700,12600,200,*,UP,ALU1 +S 2700,12600,6000,12600,300,*,RIGHT,ALU1 +S 3200,12000,6100,12000,300,*,RIGHT,ALU1 +S 3300,10900,3300,12100,300,*,DOWN,ALU1 +S 2000,5100,4100,5100,300,*,LEFT,ALU1 +S 4100,600,4100,3500,300,*,UP,NDIF +S 3500,-300,3500,4100,300,*,UP,ALU1 +S 3500,-300,3500,4100,300,*,UP,PTIE +S 3400,-200,15000,-200,300,*,RIGHT,PTIE +S 3400,4000,4200,4000,300,*,RIGHT,PTIE +S 5900,13000,5900,14300,300,*,DOWN,ALU1 +S 6500,13500,6500,22600,300,*,UP,ALU1 +S 4200,13600,5400,13600,300,*,RIGHT,ALU1 +S 5900,13100,5900,13900,200,*,UP,POLY +S 4200,22500,6600,22500,300,*,RIGHT,NTIE +S 5900,23800,6400,23800,300,*,RIGHT,POLY +S 5900,23800,5900,24600,200,*,UP,POLY +S 4400,24600,6200,24600,100,*,RIGHT,POLY +S 6200,24300,6600,24300,300,*,RIGHT,PTIE +S 4200,24300,5600,24300,300,*,RIGHT,PTIE +S 5900,23700,5900,23900,200,*,DOWN,POLY +S 4400,13900,6200,13900,100,*,RIGHT,POLY +S 6200,13600,6600,13600,300,*,RIGHT,NTIE +S 4200,13600,5600,13600,300,*,RIGHT,NTIE +S 5500,13400,5500,22700,2800,*,UP,NWELL +S 6200,13900,6200,22200,100,*,UP,PTRANS +S 5600,13900,5600,22200,100,*,UP,PTRANS +S 5000,13900,5000,22200,100,*,UP,PTRANS +S 5300,13800,5300,22600,300,*,UP,ALU1 +S 4400,13900,4400,22200,100,*,UP,PTRANS +S 4700,14100,4700,22000,200,*,UP,PDIF +S 5300,14100,5300,22000,200,*,UP,PDIF +S 5900,14100,5900,22000,200,*,UP,PDIF +S 6500,14100,6500,22000,300,*,UP,PDIF +S 4200,28700,6600,28700,300,*,RIGHT,PTIE +S 6200,24600,6200,28400,100,*,UP,NTRANS +S 5600,24600,5600,28400,100,*,UP,NTRANS +S 5000,24600,5000,28400,100,*,UP,NTRANS +S 4400,24600,4400,28400,100,*,UP,NTRANS +S 4700,24800,4700,28200,300,*,UP,NDIF +S 5300,24800,5300,28200,300,*,UP,NDIF +S 5900,24800,5900,28200,300,*,UP,NDIF +S 6500,24800,6500,28200,300,*,UP,NDIF +S 6500,24200,6500,28800,300,*,UP,ALU1 +S 5300,23700,5300,28800,300,*,UP,ALU1 +S 5900,14200,5900,29100,300,*,UP,ALU1 +S 4700,14200,4700,29100,300,*,UP,ALU1 +S 5900,13100,6500,13100,200,*,RIGHT,POLY +S 6400,13500,6400,13700,200,*,DOWN,ALU1 +S 7100,14200,7100,29100,300,*,UP,ALU1 +S 8300,14200,8300,29100,300,*,UP,ALU1 +S 7700,23700,7700,28800,300,*,UP,ALU1 +S 8900,24200,8900,28800,300,*,UP,ALU1 +S 8900,24800,8900,28200,300,*,UP,NDIF +S 8300,24800,8300,28200,300,*,UP,NDIF +S 7700,24800,7700,28200,300,*,UP,NDIF +S 7100,24800,7100,28200,300,*,UP,NDIF +S 6800,24600,6800,28400,100,*,UP,NTRANS +S 7400,24600,7400,28400,100,*,UP,NTRANS +S 8000,24600,8000,28400,100,*,UP,NTRANS +S 8600,24600,8600,28400,100,*,UP,NTRANS +S 6600,28700,9000,28700,300,*,RIGHT,PTIE +S 8900,14100,8900,22000,300,*,UP,PDIF +S 8300,14100,8300,22000,200,*,UP,PDIF +S 7700,14100,7700,22000,200,*,UP,PDIF +S 7100,14100,7100,22000,200,*,UP,PDIF +S 6800,13900,6800,22200,100,*,UP,PTRANS +S 7700,13800,7700,22600,300,*,UP,ALU1 +S 7400,13900,7400,22200,100,*,UP,PTRANS +S 8000,13900,8000,22200,100,*,UP,PTRANS +S 8600,13900,8600,22200,100,*,UP,PTRANS +S 7900,13400,7900,22700,2800,*,UP,NWELL +S 8900,13800,8900,22600,300,*,UP,ALU1 +S 6600,13600,8000,13600,300,*,RIGHT,NTIE +S 8600,13600,9000,13600,300,*,RIGHT,NTIE +S 8300,13300,8300,13900,200,*,UP,POLY +S 6800,13900,8600,13900,100,*,RIGHT,POLY +S 6600,13600,8000,13600,300,*,RIGHT,ALU1 +S 8600,13600,9000,13600,300,*,RIGHT,ALU1 +S 8300,23700,8300,23900,200,*,DOWN,POLY +S 6600,24300,8000,24300,300,*,RIGHT,PTIE +S 8600,24300,9000,24300,300,*,RIGHT,PTIE +S 6800,24600,8600,24600,100,*,RIGHT,POLY +S 8300,23800,8300,24600,200,*,UP,POLY +S 8300,23800,8800,23800,300,*,RIGHT,POLY +S 8800,23200,8800,23800,200,*,UP,ALU1 +S 6600,22500,9000,22500,300,*,RIGHT,NTIE +S 9500,14200,9500,29100,300,*,UP,ALU1 +S 10700,14200,10700,29100,300,*,UP,ALU1 +S 10100,23700,10100,28800,300,*,UP,ALU1 +S 11300,24200,11300,28800,300,*,UP,ALU1 +S 11300,24800,11300,28200,300,*,UP,NDIF +S 10700,24800,10700,28200,300,*,UP,NDIF +S 10100,24800,10100,28200,300,*,UP,NDIF +S 9500,24800,9500,28200,300,*,UP,NDIF +S 9200,24600,9200,28400,100,*,UP,NTRANS +S 9800,24600,9800,28400,100,*,UP,NTRANS +S 10400,24600,10400,28400,100,*,UP,NTRANS +S 11000,24600,11000,28400,100,*,UP,NTRANS +S 9000,28700,11400,28700,300,*,RIGHT,PTIE +S 11300,14100,11300,22000,300,*,UP,PDIF +S 10700,14100,10700,22000,200,*,UP,PDIF +S 10100,14100,10100,22000,200,*,UP,PDIF +S 9500,14100,9500,22000,200,*,UP,PDIF +S 9200,13900,9200,22200,100,*,UP,PTRANS +S 10100,13800,10100,22600,300,*,UP,ALU1 +S 9800,13900,9800,22200,100,*,UP,PTRANS +S 10400,13900,10400,22200,100,*,UP,PTRANS +S 11000,13900,11000,22200,100,*,UP,PTRANS +S 10300,13400,10300,22700,2800,*,UP,NWELL +S 11300,13800,11300,22600,300,*,UP,ALU1 +S 9000,13600,10400,13600,300,*,RIGHT,NTIE +S 11000,13600,11400,13600,300,*,RIGHT,NTIE +S 10700,13300,10700,13900,200,*,UP,POLY +S 9200,13900,11000,13900,100,*,RIGHT,POLY +S 9000,13600,10400,13600,300,*,RIGHT,ALU1 +S 11000,13600,11400,13600,300,*,RIGHT,ALU1 +S 10700,23700,10700,23900,200,*,DOWN,POLY +S 9000,24300,10400,24300,300,*,RIGHT,PTIE +S 11000,24300,11400,24300,300,*,RIGHT,PTIE +S 9200,24600,11000,24600,100,*,RIGHT,POLY +S 10700,23800,10700,24600,200,*,UP,POLY +S 10700,23800,11200,23800,300,*,RIGHT,POLY +S 11200,23200,11200,23800,200,*,UP,ALU1 +S 9000,22500,11400,22500,300,*,RIGHT,NTIE +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +V 15500,7000,CONT_DIF_P +V 14900,6200,CONT_DIF_P +V 14900,5800,CONT_DIF_P +V 14900,6600,CONT_DIF_P +V 14900,7000,CONT_DIF_P +V 14300,7000,CONT_DIF_P +V 14300,6600,CONT_DIF_P +V 14300,6200,CONT_DIF_P +V 14300,5800,CONT_DIF_P +V 15500,6600,CONT_DIF_P +V 15500,5800,CONT_DIF_P +V 15500,6200,CONT_DIF_P +V 14500,12000,CONT_BODY_N +V 14500,11200,CONT_BODY_N +V 14500,10800,CONT_BODY_N +V 14500,8300,CONT_BODY_N +V 14500,10400,CONT_BODY_N +V 14500,11600,CONT_BODY_N +V 14500,9100,CONT_BODY_N +V 14500,9500,CONT_BODY_N +V 14500,10000,CONT_VIA +V 14500,8700,CONT_VIA +V 14900,9100,CONT_BODY_N +V 14900,11600,CONT_BODY_N +V 14900,10400,CONT_BODY_N +V 14900,8300,CONT_BODY_N +V 14900,10800,CONT_BODY_N +V 14900,11200,CONT_BODY_N +V 14900,12000,CONT_BODY_N +V 14900,9500,CONT_BODY_N +V 14900,8700,CONT_VIA +V 14900,10000,CONT_VIA +V 15300,11200,CONT_BODY_N +V 15300,10800,CONT_BODY_N +V 15300,8300,CONT_BODY_N +V 15300,10400,CONT_BODY_N +V 15300,11600,CONT_BODY_N +V 15300,9100,CONT_BODY_N +V 15300,9500,CONT_BODY_N +V 15300,12000,CONT_BODY_N +V 15300,10000,CONT_VIA +V 15300,8700,CONT_VIA +V 15700,11600,CONT_BODY_N +V 15700,10400,CONT_BODY_N +V 15700,8300,CONT_BODY_N +V 15700,10800,CONT_BODY_N +V 15700,11200,CONT_BODY_N +V 15700,12000,CONT_BODY_N +V 15700,9500,CONT_BODY_N +V 15700,9100,CONT_BODY_N +V 15700,8700,CONT_VIA +V 15700,10000,CONT_VIA +V 14900,200,CONT_BODY_P +V 14400,200,CONT_BODY_P +V 14900,600,CONT_BODY_P +V 14400,600,CONT_BODY_P +V 14900,1000,CONT_BODY_P +V 14400,1000,CONT_BODY_P +V 14900,1400,CONT_BODY_P +V 14400,1400,CONT_BODY_P +V 14400,1800,CONT_BODY_P +V 14900,1800,CONT_BODY_P +V 14300,2700,CONT_DIF_N +V 15500,2800,CONT_DIF_N +V 15500,3400,CONT_DIF_N +V 15400,2300,CONT_POLY +V 12500,6600,CONT_DIF_P +V 12500,7000,CONT_DIF_P +V 12500,6200,CONT_DIF_P +V 12500,7400,CONT_DIF_P +V 12500,5800,CONT_DIF_P +V 11400,5100,CONT_BODY_N +V 14200,3800,CONT_POLY +V 9100,4000,CONT_BODY_P +V 9600,4000,CONT_BODY_P +V 10000,4000,CONT_BODY_P +V 16300,1600,CONT_VIA +V 16100,23200,CONT_VIA +V 16700,23200,CONT_VIA +V 7100,10200,CONT_VIA +V 7100,9000,CONT_VIA +V 8900,1600,CONT_VIA +V 10100,1600,CONT_VIA +V 8300,3500,CONT_VIA +V 5900,7400,CONT_VIA +V 5900,6600,CONT_VIA +V 8300,7400,CONT_VIA +V 8300,9000,CONT_VIA +V 8300,10200,CONT_VIA +V 8300,6600,CONT_VIA +V 8300,2300,CONT_VIA +V 7100,6600,CONT_VIA +V 10700,6600,CONT_VIA +V 10700,2300,CONT_VIA +V 7100,7400,CONT_VIA +V 7100,2300,CONT_VIA +V 5900,2300,CONT_VIA +V 5900,3500,CONT_VIA +V 5900,10200,CONT_VIA +V 5900,9000,CONT_VIA +V 7700,1600,CONT_VIA +V 9500,9000,CONT_VIA +V 9500,7400,CONT_VIA +V 9500,2300,CONT_VIA +V 10700,7400,CONT_VIA +V 10700,9000,CONT_VIA +V 10700,10200,CONT_VIA +V 4100,2300,CONT_VIA +V 4100,6600,CONT_VIA +V 4100,7400,CONT_VIA +V 4100,9000,CONT_VIA +V 4100,10200,CONT_VIA +V 4100,3500,CONT_VIA +V 9500,6600,CONT_VIA +V 9500,10200,CONT_VIA +V 6500,1600,CONT_VIA +V 4600,-700,CONT_VIA +V 4800,5300,CONT_POLY +V 4600,300,CONT_POLY +V 7100,4600,CONT_POLY +V 5900,4000,CONT_BODY_P +V 8300,4000,CONT_BODY_P +V 4100,4000,CONT_BODY_P +V 7500,4000,CONT_BODY_P +V 8700,4000,CONT_BODY_P +V 7900,4000,CONT_BODY_P +V 6700,4000,CONT_BODY_P +V 6300,4000,CONT_BODY_P +V 5900,-200,CONT_BODY_P +V 7100,-200,CONT_BODY_P +V 12100,-200,CONT_BODY_P +V 11700,-200,CONT_BODY_P +V 8300,-200,CONT_BODY_P +V 10700,-200,CONT_BODY_P +V 9500,-200,CONT_BODY_P +V 4100,-200,CONT_BODY_P +V 9900,-200,CONT_BODY_P +V 10300,-200,CONT_BODY_P +V 13700,-200,CONT_BODY_P +V 13300,-200,CONT_BODY_P +V 14100,-200,CONT_BODY_P +V 14500,-200,CONT_BODY_P +V 12500,-200,CONT_BODY_P +V 12900,-200,CONT_BODY_P +V 5100,-200,CONT_BODY_P +V 5500,-200,CONT_BODY_P +V 6300,-200,CONT_BODY_P +V 6700,-200,CONT_BODY_P +V 7500,-200,CONT_BODY_P +V 7900,-200,CONT_BODY_P +V 9100,-200,CONT_BODY_P +V 8700,-200,CONT_BODY_P +V 6000,12000,CONT_BODY_N +V 5900,5100,CONT_BODY_N +V 8300,5100,CONT_BODY_N +V 6700,5100,CONT_BODY_N +V 6300,5100,CONT_BODY_N +V 7100,12000,CONT_BODY_N +V 10700,5100,CONT_BODY_N +V 9100,5100,CONT_BODY_N +V 8700,5100,CONT_BODY_N +V 4100,5100,CONT_BODY_N +V 4500,12000,CONT_BODY_N +V 8300,12000,CONT_BODY_N +V 9500,12000,CONT_BODY_N +V 5500,12000,CONT_BODY_N +V 5000,12000,CONT_BODY_N +V 4100,12000,CONT_BODY_N +V 7900,5100,CONT_BODY_N +V 7500,5100,CONT_BODY_N +V 9900,5100,CONT_BODY_N +V 10300,5100,CONT_BODY_N +V 7700,11400,CONT_DIF_P +V 7700,8600,CONT_DIF_P +V 7700,8200,CONT_DIF_P +V 7700,5800,CONT_DIF_P +V 7700,11000,CONT_DIF_P +V 7700,10600,CONT_DIF_P +V 7700,9000,CONT_DIF_P +V 7700,10200,CONT_DIF_P +V 7700,7000,CONT_DIF_P +V 7700,6600,CONT_DIF_P +V 7700,9800,CONT_DIF_P +V 7700,9400,CONT_DIF_P +V 7700,6200,CONT_DIF_P +V 6500,6200,CONT_DIF_P +V 7700,7400,CONT_DIF_P +V 6500,11400,CONT_DIF_P +V 6500,8600,CONT_DIF_P +V 6500,8200,CONT_DIF_P +V 6500,5800,CONT_DIF_P +V 6500,11000,CONT_DIF_P +V 6500,10600,CONT_DIF_P +V 8300,7800,CONT_DIF_P +V 7700,7800,CONT_DIF_P +V 6500,7800,CONT_DIF_P +V 6500,10200,CONT_DIF_P +V 6500,7000,CONT_DIF_P +V 6500,6600,CONT_DIF_P +V 6500,9800,CONT_DIF_P +V 6500,9400,CONT_DIF_P +V 8300,11400,CONT_DIF_P +V 6500,7400,CONT_DIF_P +V 8300,6200,CONT_DIF_P +V 8300,5800,CONT_DIF_P +V 8300,7000,CONT_DIF_P +V 8300,9800,CONT_DIF_P +V 8300,10600,CONT_DIF_P +V 8300,11000,CONT_DIF_P +V 7100,8600,CONT_DIF_P +V 6500,9000,CONT_DIF_P +V 7100,8200,CONT_DIF_P +V 7100,7800,CONT_DIF_P +V 7100,11000,CONT_DIF_P +V 7100,10600,CONT_DIF_P +V 8300,9400,CONT_DIF_P +V 8300,8200,CONT_DIF_P +V 5900,5800,CONT_DIF_P +V 8300,8600,CONT_DIF_P +V 5900,6200,CONT_DIF_P +V 7100,9400,CONT_DIF_P +V 7100,9800,CONT_DIF_P +V 7100,7000,CONT_DIF_P +V 7100,5800,CONT_DIF_P +V 7100,6200,CONT_DIF_P +V 5900,10600,CONT_DIF_P +V 7100,11400,CONT_DIF_P +V 5900,11400,CONT_DIF_P +V 5900,8200,CONT_DIF_P +V 5900,7800,CONT_DIF_P +V 5900,11000,CONT_DIF_P +V 5900,9800,CONT_DIF_P +V 5900,9400,CONT_DIF_P +V 5300,11000,CONT_DIF_P +V 5900,7000,CONT_DIF_P +V 5300,10200,CONT_DIF_P +V 5300,7800,CONT_DIF_P +V 5300,7000,CONT_DIF_P +V 5300,6600,CONT_DIF_P +V 5300,9800,CONT_DIF_P +V 5300,9400,CONT_DIF_P +V 5300,10600,CONT_DIF_P +V 5900,8600,CONT_DIF_P +V 5300,7400,CONT_DIF_P +V 5300,11400,CONT_DIF_P +V 5300,8600,CONT_DIF_P +V 5300,8200,CONT_DIF_P +V 5300,5800,CONT_DIF_P +V 9500,11000,CONT_DIF_P +V 9500,9400,CONT_DIF_P +V 5300,9000,CONT_DIF_P +V 10700,7000,CONT_DIF_P +V 9500,7000,CONT_DIF_P +V 9500,5800,CONT_DIF_P +V 9500,6200,CONT_DIF_P +V 9500,8600,CONT_DIF_P +V 9500,11400,CONT_DIF_P +V 9500,8200,CONT_DIF_P +V 5300,6200,CONT_DIF_P +V 8900,7000,CONT_DIF_P +V 9500,10600,CONT_DIF_P +V 10700,9400,CONT_DIF_P +V 10700,8200,CONT_DIF_P +V 10700,11400,CONT_DIF_P +V 10700,8600,CONT_DIF_P +V 10700,6200,CONT_DIF_P +V 9500,9800,CONT_DIF_P +V 8900,8200,CONT_DIF_P +V 10700,9800,CONT_DIF_P +V 10700,10600,CONT_DIF_P +V 10700,11000,CONT_DIF_P +V 10700,7800,CONT_DIF_P +V 8900,9000,CONT_DIF_P +V 8900,7800,CONT_DIF_P +V 9500,7800,CONT_DIF_P +V 10100,6600,CONT_DIF_P +V 8900,6600,CONT_DIF_P +V 8900,9800,CONT_DIF_P +V 8900,9400,CONT_DIF_P +V 8900,6200,CONT_DIF_P +V 8900,7400,CONT_DIF_P +V 8900,11400,CONT_DIF_P +V 10700,5800,CONT_DIF_P +V 10100,5800,CONT_DIF_P +V 8900,5800,CONT_DIF_P +V 8900,11000,CONT_DIF_P +V 8900,10600,CONT_DIF_P +V 10100,9000,CONT_DIF_P +V 10100,7800,CONT_DIF_P +V 10100,10200,CONT_DIF_P +V 8900,10200,CONT_DIF_P +V 10100,10600,CONT_DIF_P +V 10100,9800,CONT_DIF_P +V 10100,9400,CONT_DIF_P +V 10100,6200,CONT_DIF_P +V 10100,7400,CONT_DIF_P +V 10100,11400,CONT_DIF_P +V 10100,8600,CONT_DIF_P +V 8900,8600,CONT_DIF_P +V 10100,7000,CONT_DIF_P +V 10100,8200,CONT_DIF_P +V 4700,6200,CONT_DIF_P +V 4700,7400,CONT_DIF_P +V 4700,11400,CONT_DIF_P +V 4700,8600,CONT_DIF_P +V 4700,9000,CONT_DIF_P +V 4700,7800,CONT_DIF_P +V 4700,7000,CONT_DIF_P +V 10100,11000,CONT_DIF_P +V 4700,5800,CONT_DIF_P +V 4700,8200,CONT_DIF_P +V 4700,11000,CONT_DIF_P +V 4700,6600,CONT_DIF_P +V 4700,10600,CONT_DIF_P +V 4700,9800,CONT_DIF_P +V 4700,10200,CONT_DIF_P +V 4700,9400,CONT_DIF_P +V 4100,6200,CONT_DIF_P +V 4100,7000,CONT_DIF_P +V 4100,5800,CONT_DIF_P +V 4100,9800,CONT_DIF_P +V 4100,11000,CONT_DIF_P +V 4100,8200,CONT_DIF_P +V 4100,11400,CONT_DIF_P +V 4100,8600,CONT_DIF_P +V 4100,10600,CONT_DIF_P +V 4100,9400,CONT_DIF_P +V 4100,7800,CONT_DIF_P +V 7700,2100,CONT_DIF_N +V 7100,700,CONT_DIF_N +V 7700,2500,CONT_DIF_N +V 7100,3300,CONT_DIF_N +V 7100,2800,CONT_DIF_N +V 6500,2900,CONT_DIF_N +V 8300,1100,CONT_DIF_N +V 8300,1500,CONT_DIF_N +V 5900,700,CONT_DIF_N +V 6500,3300,CONT_DIF_N +V 6500,2100,CONT_DIF_N +V 6500,2500,CONT_DIF_N +V 7700,2900,CONT_DIF_N +V 7700,3300,CONT_DIF_N +V 7100,1500,CONT_DIF_N +V 7100,1100,CONT_DIF_N +V 5300,2500,CONT_DIF_N +V 7100,1900,CONT_DIF_N +V 8300,1900,CONT_DIF_N +V 8300,2700,CONT_DIF_N +V 8300,3100,CONT_DIF_N +V 8300,700,CONT_DIF_N +V 5300,3300,CONT_DIF_N +V 10700,1100,CONT_DIF_N +V 9500,1500,CONT_DIF_N +V 5900,1100,CONT_DIF_N +V 5900,1500,CONT_DIF_N +V 5900,1900,CONT_DIF_N +V 5900,2700,CONT_DIF_N +V 5900,3100,CONT_DIF_N +V 10700,2700,CONT_DIF_N +V 10700,3100,CONT_DIF_N +V 10700,700,CONT_DIF_N +V 5300,2100,CONT_DIF_N +V 5300,1700,CONT_DIF_N +V 5300,1300,CONT_DIF_N +V 5300,900,CONT_DIF_N +V 5300,2900,CONT_DIF_N +V 8900,2500,CONT_DIF_N +V 7700,700,CONT_DIF_N +V 8900,1200,CONT_DIF_N +V 10100,2900,CONT_DIF_N +V 9500,1100,CONT_DIF_N +V 9500,700,CONT_DIF_N +V 9500,1900,CONT_DIF_N +V 10700,1900,CONT_DIF_N +V 10100,700,CONT_DIF_N +V 8900,700,CONT_DIF_N +V 9500,3300,CONT_DIF_N +V 10700,1500,CONT_DIF_N +V 8900,2900,CONT_DIF_N +V 8900,3300,CONT_DIF_N +V 8900,2100,CONT_DIF_N +V 9500,2800,CONT_DIF_N +V 10100,3300,CONT_DIF_N +V 10100,2100,CONT_DIF_N +V 10100,2500,CONT_DIF_N +V 10100,1200,CONT_DIF_N +V 4700,1300,CONT_DIF_N +V 4700,900,CONT_DIF_N +V 4700,2500,CONT_DIF_N +V 4700,2100,CONT_DIF_N +V 4700,2900,CONT_DIF_N +V 4700,3300,CONT_DIF_N +V 4700,1700,CONT_DIF_N +V 4100,1500,CONT_DIF_N +V 4100,1100,CONT_DIF_N +V 7700,1200,CONT_DIF_N +V 4100,700,CONT_DIF_N +V 4100,3100,CONT_DIF_N +V 4100,2700,CONT_DIF_N +V 4100,1900,CONT_DIF_N +V 6500,700,CONT_DIF_N +V 6500,1200,CONT_DIF_N +V 16100,7500,CONT_VIA +V 16100,8700,CONT_VIA +V 16100,6700,CONT_VIA +V 16100,10000,CONT_VIA +V 16100,5500,CONT_BODY_N +V 16100,9100,CONT_BODY_N +V 16100,8300,CONT_BODY_N +V 16100,10800,CONT_BODY_N +V 16100,7100,CONT_BODY_N +V 16100,11200,CONT_BODY_N +V 16100,6300,CONT_BODY_N +V 16100,5900,CONT_BODY_N +V 16100,12000,CONT_BODY_N +V 16100,9500,CONT_BODY_N +V 16100,11600,CONT_BODY_N +V 16100,7900,CONT_BODY_N +V 16100,10400,CONT_BODY_N +V 16100,5100,CONT_BODY_N +V 13700,1600,CONT_VIA +V 12500,1600,CONT_VIA +V 11300,1600,CONT_VIA +V 11900,9400,CONT_DIF_P +V 11900,7000,CONT_DIF_P +V 11900,5800,CONT_DIF_P +V 11900,6200,CONT_DIF_P +V 11900,8600,CONT_DIF_P +V 11900,11400,CONT_DIF_P +V 11900,8200,CONT_DIF_P +V 11900,7800,CONT_DIF_P +V 11900,10600,CONT_DIF_P +V 11300,9000,CONT_DIF_P +V 11300,7800,CONT_DIF_P +V 11300,10200,CONT_DIF_P +V 11300,7000,CONT_DIF_P +V 11300,6600,CONT_DIF_P +V 11300,9800,CONT_DIF_P +V 11900,9800,CONT_DIF_P +V 11300,6200,CONT_DIF_P +V 11300,7400,CONT_DIF_P +V 11300,11400,CONT_DIF_P +V 11300,8600,CONT_DIF_P +V 11300,8200,CONT_DIF_P +V 11300,5800,CONT_DIF_P +V 11300,11000,CONT_DIF_P +V 11900,11000,CONT_DIF_P +V 13100,9800,CONT_DIF_P +V 13100,9400,CONT_DIF_P +V 13100,8600,CONT_DIF_P +V 13100,6200,CONT_DIF_P +V 13100,5800,CONT_DIF_P +V 13100,7000,CONT_DIF_P +V 12500,10200,CONT_DIF_P +V 11300,9400,CONT_DIF_P +V 12500,9000,CONT_DIF_P +V 13100,10600,CONT_DIF_P +V 13100,11000,CONT_DIF_P +V 13100,7800,CONT_DIF_P +V 13100,8200,CONT_DIF_P +V 13100,11400,CONT_DIF_P +V 12500,8600,CONT_DIF_P +V 11300,10600,CONT_DIF_P +V 12500,9400,CONT_DIF_P +V 12500,9800,CONT_DIF_P +V 12500,10600,CONT_DIF_P +V 12500,7800,CONT_DIF_P +V 12500,8200,CONT_DIF_P +V 13700,10200,CONT_DIF_P +V 13700,7800,CONT_DIF_P +V 13700,9000,CONT_DIF_P +V 13700,8600,CONT_DIF_P +V 13700,11400,CONT_DIF_P +V 12500,11400,CONT_DIF_P +V 13700,6200,CONT_DIF_P +V 13700,9400,CONT_DIF_P +V 13700,9800,CONT_DIF_P +V 13700,6600,CONT_DIF_P +V 13700,7000,CONT_DIF_P +V 13700,10600,CONT_DIF_P +V 13700,11000,CONT_DIF_P +V 12500,11000,CONT_DIF_P +V 13700,8200,CONT_DIF_P +V 13100,10200,CONT_DIF_P +V 11900,10200,CONT_DIF_P +V 11900,9000,CONT_DIF_P +V 13100,9000,CONT_DIF_P +V 11900,7400,CONT_DIF_P +V 13100,7400,CONT_DIF_P +V 13700,7400,CONT_DIF_P +V 11900,6600,CONT_DIF_P +V 13100,6600,CONT_DIF_P +V 13700,5800,CONT_DIF_P +V 13700,700,CONT_DIF_N +V 13700,1200,CONT_DIF_N +V 12500,1200,CONT_DIF_N +V 11300,700,CONT_DIF_N +V 13700,2100,CONT_DIF_N +V 11900,1500,CONT_DIF_N +V 13700,3300,CONT_DIF_N +V 11900,1100,CONT_DIF_N +V 11900,700,CONT_DIF_N +V 11900,1900,CONT_DIF_N +V 11900,3300,CONT_DIF_N +V 11300,2900,CONT_DIF_N +V 11300,3300,CONT_DIF_N +V 11300,2100,CONT_DIF_N +V 11300,2500,CONT_DIF_N +V 11300,1200,CONT_DIF_N +V 11900,2800,CONT_DIF_N +V 13100,1500,CONT_DIF_N +V 13700,2900,CONT_DIF_N +V 12500,3300,CONT_DIF_N +V 12500,2900,CONT_DIF_N +V 13100,3300,CONT_DIF_N +V 13100,1900,CONT_DIF_N +V 13100,700,CONT_DIF_N +V 13100,1100,CONT_DIF_N +V 13700,2500,CONT_DIF_N +V 13100,2800,CONT_DIF_N +V 12500,700,CONT_DIF_N +V 12500,2500,CONT_DIF_N +V 12500,2100,CONT_DIF_N +V 13100,2300,CONT_DIF_N +V 11900,2300,CONT_DIF_N +V 16700,1600,CONT_VIA +V 9500,4600,CONT_POLY +V 14900,3500,CONT_VIA +V 14900,-200,CONT_BODY_P +V 14900,5100,CONT_BODY_N +V 14300,3300,CONT_DIF_N +V 14900,2700,CONT_DIF_N +V 14900,3100,CONT_DIF_N +V 16100,4000,CONT_BODY_P +V 16100,4000,CONT_BODY_P +V 16100,2800,CONT_BODY_P +V 16100,3200,CONT_BODY_P +V 16100,3600,CONT_VIA +V 16100,2400,CONT_VIA +V 14800,4500,CONT_POLY +V 10700,12000,CONT_BODY_N +V 15400,-700,CONT_VIA +V 11300,-200,CONT_BODY_P +V 10800,4000,CONT_POLY +V 14900,4000,CONT_BODY_P +V 14900,7500,CONT_DIF_P +V 15500,7500,CONT_DIF_P +V 14300,7500,CONT_DIF_P +V 3800,27500,CONT_VIA +V 3800,27900,CONT_VIA +V 3800,28300,CONT_VIA +V 3800,26300,CONT_VIA +V 3800,25500,CONT_VIA +V 3800,25100,CONT_VIA +V 3800,24700,CONT_VIA +V 3800,25900,CONT_VIA +V 3800,20400,CONT_VIA +V 3800,20800,CONT_VIA +V 3800,22500,CONT_VIA +V 3800,21200,CONT_VIA +V 3800,21600,CONT_VIA +V 3800,22000,CONT_VIA +V 3800,26700,CONT_VIA +V 3800,27100,CONT_VIA +V 4000,29200,CONT_VIA +V 3500,29200,CONT_VIA +V 6400,23200,CONT_VIA +V 3800,20000,CONT_VIA +V 3800,18400,CONT_VIA +V 3800,18800,CONT_VIA +V 3800,17200,CONT_VIA +V 3800,17600,CONT_VIA +V 3800,16800,CONT_VIA +V 3800,14400,CONT_VIA +V 3800,14800,CONT_VIA +V 3800,15200,CONT_VIA +V 3800,15600,CONT_VIA +V 3800,18000,CONT_VIA +V 3800,19200,CONT_VIA +V 3800,19600,CONT_VIA +V 3800,14000,CONT_VIA +V 3800,16400,CONT_VIA +V 3800,16000,CONT_VIA +V 3500,27900,CONT_BODY_P +V 3500,28300,CONT_BODY_P +V 3900,28700,CONT_BODY_P +V 3500,24300,CONT_BODY_P +V 3900,24300,CONT_BODY_P +V 3500,25500,CONT_BODY_P +V 3500,25100,CONT_BODY_P +V 3500,24700,CONT_BODY_P +V 3500,28700,CONT_BODY_P +V 3500,25900,CONT_BODY_P +V 3500,26300,CONT_BODY_P +V 3500,26700,CONT_BODY_P +V 3500,27100,CONT_BODY_P +V 3500,27500,CONT_BODY_P +V 3500,22500,CONT_BODY_N +V 4100,22500,CONT_BODY_N +V 3500,22000,CONT_BODY_N +V 3500,21600,CONT_BODY_N +V 3500,21200,CONT_BODY_N +V 3500,20800,CONT_BODY_N +V 3500,20400,CONT_BODY_N +V 3500,19200,CONT_BODY_N +V 3500,18800,CONT_BODY_N +V 3500,17200,CONT_BODY_N +V 3500,16400,CONT_BODY_N +V 3500,16000,CONT_BODY_N +V 3500,18000,CONT_BODY_N +V 3500,17600,CONT_BODY_N +V 3500,20000,CONT_BODY_N +V 3500,18400,CONT_BODY_N +V 3500,19600,CONT_BODY_N +V 3500,15600,CONT_BODY_N +V 3500,15200,CONT_BODY_N +V 3500,14800,CONT_BODY_N +V 3500,14400,CONT_BODY_N +V 3500,14000,CONT_BODY_N +V 4000,13600,CONT_BODY_N +V 3500,13600,CONT_BODY_N +V 3500,16800,CONT_BODY_N +V 4100,20300,CONT_DIF_P +V 4100,20700,CONT_DIF_P +V 4100,21100,CONT_DIF_P +V 4100,21500,CONT_DIF_P +V 4100,21900,CONT_DIF_P +V 4100,14300,CONT_DIF_P +V 4100,19900,CONT_DIF_P +V 4100,19500,CONT_DIF_P +V 4100,19100,CONT_DIF_P +V 4100,18700,CONT_DIF_P +V 4100,18300,CONT_DIF_P +V 4100,17500,CONT_DIF_P +V 4100,17900,CONT_DIF_P +V 4100,17100,CONT_DIF_P +V 4100,16700,CONT_DIF_P +V 4100,16300,CONT_DIF_P +V 4100,15900,CONT_DIF_P +V 4100,15500,CONT_DIF_P +V 4100,15100,CONT_DIF_P +V 4100,14700,CONT_DIF_P +V 4100,27300,CONT_DIF_N +V 4100,26100,CONT_DIF_N +V 4100,24900,CONT_DIF_N +V 4100,25300,CONT_DIF_N +V 4100,25700,CONT_DIF_N +V 4100,26500,CONT_DIF_N +V 4100,26900,CONT_DIF_N +V 4100,27700,CONT_DIF_N +V 4100,28100,CONT_DIF_N +V 11900,29200,CONT_VIA +V 11300,29200,CONT_VIA +V 11900,25900,CONT_VIA +V 11600,24300,CONT_VIA +V 11900,27900,CONT_VIA +V 11900,28300,CONT_BODY_P +V 11900,28700,CONT_BODY_P +V 11900,24300,CONT_BODY_P +V 11900,25500,CONT_BODY_P +V 11900,25100,CONT_BODY_P +V 11900,24700,CONT_BODY_P +V 11900,26300,CONT_BODY_P +V 11900,26700,CONT_BODY_P +V 11900,27100,CONT_BODY_P +V 11900,27500,CONT_BODY_P +V 11600,22500,CONT_VIA +V 11600,20700,CONT_VIA +V 11600,20300,CONT_VIA +V 11600,21900,CONT_VIA +V 11600,21500,CONT_VIA +V 11600,13900,CONT_VIA +V 11600,16700,CONT_VIA +V 11600,14700,CONT_VIA +V 11600,19500,CONT_VIA +V 11600,17900,CONT_VIA +V 11600,17100,CONT_VIA +V 11600,18300,CONT_VIA +V 11600,15500,CONT_VIA +V 11600,15900,CONT_VIA +V 11600,14300,CONT_VIA +V 11600,19100,CONT_VIA +V 11900,22000,CONT_BODY_N +V 11900,22500,CONT_BODY_N +V 11900,20400,CONT_BODY_N +V 11900,20800,CONT_BODY_N +V 11900,21200,CONT_BODY_N +V 11900,21600,CONT_BODY_N +V 11900,14800,CONT_BODY_N +V 11900,15200,CONT_BODY_N +V 11900,13600,CONT_BODY_N +V 11900,15600,CONT_BODY_N +V 11900,17200,CONT_BODY_N +V 11900,16800,CONT_BODY_N +V 11900,16000,CONT_BODY_N +V 11500,13600,CONT_BODY_N +V 11900,19200,CONT_BODY_N +V 11900,19600,CONT_BODY_N +V 11900,20000,CONT_BODY_N +V 11900,17600,CONT_BODY_N +V 11900,18000,CONT_BODY_N +V 11900,16400,CONT_BODY_N +V 11900,14000,CONT_BODY_N +V 11900,14400,CONT_BODY_N +V 11900,18400,CONT_BODY_N +V 11900,18800,CONT_BODY_N +V 3300,5800,CONT_VIA +V 3300,9900,CONT_VIA +V 2100,9800,CONT_VIA +V 2100,6600,CONT_VIA +V 3100,9400,CONT_POLY +V 3300,5100,CONT_BODY_N +V 2700,5100,CONT_BODY_N +V 2700,5500,CONT_BODY_N +V 2700,5900,CONT_BODY_N +V 2700,6300,CONT_BODY_N +V 3300,10300,CONT_BODY_N +V 3300,10700,CONT_BODY_N +V 2100,11600,CONT_BODY_N +V 2100,11200,CONT_BODY_N +V 2100,10800,CONT_BODY_N +V 2100,10400,CONT_BODY_N +V 2100,5100,CONT_BODY_N +V 2100,6300,CONT_BODY_N +V 2100,7000,CONT_BODY_N +V 2100,7400,CONT_BODY_N +V 2100,7800,CONT_BODY_N +V 2100,8200,CONT_BODY_N +V 2100,8600,CONT_BODY_N +V 2100,9000,CONT_BODY_N +V 2100,12000,CONT_BODY_N +V 2100,9400,CONT_BODY_N +V 2100,5500,CONT_BODY_N +V 2100,5900,CONT_BODY_N +V 2700,6900,CONT_DIF_P +V 2700,11300,CONT_DIF_P +V 3600,12000,CONT_BODY_N +V 3300,11500,CONT_BODY_N +V 3500,2300,CONT_VIA +V 3500,3500,CONT_VIA +V 3500,700,CONT_BODY_P +V 3500,1100,CONT_BODY_P +V 3500,1500,CONT_BODY_P +V 3500,1900,CONT_BODY_P +V 3500,2700,CONT_BODY_P +V 3500,3100,CONT_BODY_P +V 3500,4000,CONT_BODY_P +V 3500,300,CONT_BODY_P +V 3500,-200,CONT_BODY_P +V 4400,13600,CONT_BODY_N +V 5300,13600,CONT_VIA +V 4700,21900,CONT_DIF_P +V 5300,21900,CONT_DIF_P +V 5900,21900,CONT_DIF_P +V 6500,21900,CONT_DIF_P +V 5300,22500,CONT_BODY_N +V 6500,22500,CONT_BODY_N +V 5300,23800,CONT_VIA +V 6400,23800,CONT_POLY +V 6500,24300,CONT_BODY_P +V 5300,24300,CONT_BODY_P +V 6500,21500,CONT_DIF_P +V 5900,21500,CONT_DIF_P +V 5300,21500,CONT_DIF_P +V 4700,21500,CONT_DIF_P +V 5300,21100,CONT_VIA +V 6500,21100,CONT_VIA +V 5900,21100,CONT_DIF_P +V 4700,21100,CONT_DIF_P +V 4700,20700,CONT_DIF_P +V 5900,20700,CONT_DIF_P +V 6500,20700,CONT_DIF_P +V 5300,20700,CONT_DIF_P +V 6500,20300,CONT_DIF_P +V 5300,20300,CONT_DIF_P +V 5900,20300,CONT_DIF_P +V 4700,20300,CONT_DIF_P +V 6500,19900,CONT_VIA +V 5300,19900,CONT_VIA +V 5900,19900,CONT_DIF_P +V 4700,19900,CONT_DIF_P +V 6500,16300,CONT_VIA +V 6500,17500,CONT_VIA +V 6500,18700,CONT_VIA +V 5300,16300,CONT_VIA +V 5300,18700,CONT_VIA +V 5300,17500,CONT_VIA +V 6500,15100,CONT_VIA +V 5300,15100,CONT_VIA +V 5900,16700,CONT_DIF_P +V 6500,16700,CONT_DIF_P +V 6500,17100,CONT_DIF_P +V 6500,15900,CONT_DIF_P +V 5900,15900,CONT_DIF_P +V 5900,16300,CONT_DIF_P +V 6500,18300,CONT_DIF_P +V 6500,17900,CONT_DIF_P +V 5900,17900,CONT_DIF_P +V 5900,17100,CONT_DIF_P +V 5900,17500,CONT_DIF_P +V 5900,19500,CONT_DIF_P +V 6500,19100,CONT_DIF_P +V 5900,19100,CONT_DIF_P +V 5900,18700,CONT_DIF_P +V 5900,18300,CONT_DIF_P +V 6500,19500,CONT_DIF_P +V 6500,15500,CONT_DIF_P +V 5900,15500,CONT_DIF_P +V 5300,17100,CONT_DIF_P +V 5300,16700,CONT_DIF_P +V 4700,16700,CONT_DIF_P +V 4700,17100,CONT_DIF_P +V 4700,17500,CONT_DIF_P +V 5300,15900,CONT_DIF_P +V 4700,15900,CONT_DIF_P +V 4700,16300,CONT_DIF_P +V 5300,19500,CONT_DIF_P +V 5300,19100,CONT_DIF_P +V 4700,19100,CONT_DIF_P +V 4700,18700,CONT_DIF_P +V 5300,18300,CONT_DIF_P +V 4700,18300,CONT_DIF_P +V 5300,17900,CONT_DIF_P +V 4700,17900,CONT_DIF_P +V 4700,19500,CONT_DIF_P +V 4700,15500,CONT_DIF_P +V 5300,15500,CONT_DIF_P +V 5900,15100,CONT_DIF_P +V 6500,14700,CONT_DIF_P +V 5900,14700,CONT_DIF_P +V 6500,14300,CONT_DIF_P +V 5900,14300,CONT_DIF_P +V 4700,14300,CONT_DIF_P +V 4700,15100,CONT_DIF_P +V 5300,14700,CONT_DIF_P +V 4700,14700,CONT_DIF_P +V 5300,14300,CONT_DIF_P +V 5900,27400,CONT_DIF_N +V 5900,27000,CONT_DIF_N +V 5900,26600,CONT_DIF_N +V 5900,27800,CONT_DIF_N +V 5900,25000,CONT_DIF_N +V 5900,25400,CONT_DIF_N +V 5900,26200,CONT_DIF_N +V 5900,25800,CONT_DIF_N +V 4700,27000,CONT_DIF_N +V 4700,26600,CONT_DIF_N +V 4700,26200,CONT_DIF_N +V 4700,25800,CONT_DIF_N +V 4700,25400,CONT_DIF_N +V 4700,27800,CONT_DIF_N +V 4700,27400,CONT_DIF_N +V 4700,25000,CONT_DIF_N +V 4900,13600,CONT_BODY_N +V 5300,28700,CONT_BODY_P +V 6500,28700,CONT_BODY_P +V 5300,26100,CONT_VIA +V 5300,27700,CONT_VIA +V 5300,25700,CONT_DIF_N +V 5300,28100,CONT_DIF_N +V 5300,26500,CONT_DIF_N +V 5300,27300,CONT_DIF_N +V 5300,26900,CONT_DIF_N +V 5300,25300,CONT_DIF_N +V 5300,24900,CONT_VIA +V 6500,28100,CONT_VIA +V 6500,24900,CONT_VIA +V 6500,26500,CONT_VIA +V 6500,25300,CONT_DIF_N +V 6500,26900,CONT_DIF_N +V 6500,27300,CONT_DIF_N +V 6500,25700,CONT_DIF_N +V 6500,26100,CONT_DIF_N +V 6500,27700,CONT_DIF_N +V 6500,13100,CONT_POLY +V 6400,13600,CONT_BODY_N +V 8900,27700,CONT_DIF_N +V 8900,26100,CONT_DIF_N +V 8900,25700,CONT_DIF_N +V 8900,27300,CONT_DIF_N +V 8900,26900,CONT_DIF_N +V 8900,25300,CONT_DIF_N +V 8900,26500,CONT_VIA +V 8900,24900,CONT_VIA +V 8900,28100,CONT_VIA +V 7700,24900,CONT_VIA +V 7700,25300,CONT_DIF_N +V 7700,26900,CONT_DIF_N +V 7700,27300,CONT_DIF_N +V 7700,26500,CONT_DIF_N +V 7700,28100,CONT_DIF_N +V 7700,25700,CONT_DIF_N +V 7700,27700,CONT_VIA +V 7700,26100,CONT_VIA +V 8900,28700,CONT_BODY_P +V 7700,28700,CONT_BODY_P +V 6800,13600,CONT_BODY_N +V 7900,13600,CONT_BODY_N +V 7300,13600,CONT_BODY_N +V 8700,13600,CONT_BODY_N +V 8300,13100,CONT_POLY +V 7600,13600,CONT_VIA +V 7100,25000,CONT_DIF_N +V 7100,27400,CONT_DIF_N +V 7100,27800,CONT_DIF_N +V 7100,25400,CONT_DIF_N +V 7100,25800,CONT_DIF_N +V 7100,26200,CONT_DIF_N +V 7100,26600,CONT_DIF_N +V 7100,27000,CONT_DIF_N +V 8300,25800,CONT_DIF_N +V 8300,26200,CONT_DIF_N +V 8300,25400,CONT_DIF_N +V 8300,25000,CONT_DIF_N +V 8300,27800,CONT_DIF_N +V 8300,26600,CONT_DIF_N +V 8300,27000,CONT_DIF_N +V 8300,27400,CONT_DIF_N +V 7700,14300,CONT_DIF_P +V 7100,14700,CONT_DIF_P +V 7700,14700,CONT_DIF_P +V 7100,15100,CONT_DIF_P +V 7100,14300,CONT_DIF_P +V 8300,14300,CONT_DIF_P +V 8900,14300,CONT_DIF_P +V 8300,14700,CONT_DIF_P +V 8900,14700,CONT_DIF_P +V 8300,15100,CONT_DIF_P +V 7700,15500,CONT_DIF_P +V 7100,15500,CONT_DIF_P +V 7100,19500,CONT_DIF_P +V 7100,17900,CONT_DIF_P +V 7700,17900,CONT_DIF_P +V 7100,18300,CONT_DIF_P +V 7700,18300,CONT_DIF_P +V 7100,18700,CONT_DIF_P +V 7100,19100,CONT_DIF_P +V 7700,19100,CONT_DIF_P +V 7700,19500,CONT_DIF_P +V 7100,16300,CONT_DIF_P +V 7100,15900,CONT_DIF_P +V 7700,15900,CONT_DIF_P +V 7100,17500,CONT_DIF_P +V 7100,17100,CONT_DIF_P +V 7100,16700,CONT_DIF_P +V 7700,16700,CONT_DIF_P +V 7700,17100,CONT_DIF_P +V 8300,15500,CONT_DIF_P +V 8900,15500,CONT_DIF_P +V 8900,19500,CONT_DIF_P +V 8300,18300,CONT_DIF_P +V 8300,18700,CONT_DIF_P +V 8300,19100,CONT_DIF_P +V 8900,19100,CONT_DIF_P +V 8300,19500,CONT_DIF_P +V 8300,17500,CONT_DIF_P +V 8300,17100,CONT_DIF_P +V 8300,17900,CONT_DIF_P +V 8900,17900,CONT_DIF_P +V 8900,18300,CONT_DIF_P +V 8300,16300,CONT_DIF_P +V 8300,15900,CONT_DIF_P +V 8900,15900,CONT_DIF_P +V 8900,17100,CONT_DIF_P +V 8900,16700,CONT_DIF_P +V 8300,16700,CONT_DIF_P +V 7700,15100,CONT_VIA +V 8900,15100,CONT_VIA +V 7700,17500,CONT_VIA +V 7700,18700,CONT_VIA +V 7700,16300,CONT_VIA +V 8900,18700,CONT_VIA +V 8900,17500,CONT_VIA +V 8900,16300,CONT_VIA +V 7100,19900,CONT_DIF_P +V 8300,19900,CONT_DIF_P +V 7700,19900,CONT_VIA +V 8900,19900,CONT_VIA +V 7100,20300,CONT_DIF_P +V 8300,20300,CONT_DIF_P +V 7700,20300,CONT_DIF_P +V 8900,20300,CONT_DIF_P +V 7700,20700,CONT_DIF_P +V 8900,20700,CONT_DIF_P +V 8300,20700,CONT_DIF_P +V 7100,20700,CONT_DIF_P +V 7100,21100,CONT_DIF_P +V 8300,21100,CONT_DIF_P +V 8900,21100,CONT_VIA +V 7700,21100,CONT_VIA +V 7100,21500,CONT_DIF_P +V 7700,21500,CONT_DIF_P +V 8300,21500,CONT_DIF_P +V 8900,21500,CONT_DIF_P +V 7700,24300,CONT_BODY_P +V 8900,24300,CONT_BODY_P +V 8800,23800,CONT_POLY +V 7700,23800,CONT_VIA +V 8800,23200,CONT_VIA +V 8900,22500,CONT_BODY_N +V 7700,22500,CONT_BODY_N +V 8900,21900,CONT_DIF_P +V 8300,21900,CONT_DIF_P +V 7700,21900,CONT_DIF_P +V 7100,21900,CONT_DIF_P +V 11300,27700,CONT_DIF_N +V 11300,26100,CONT_DIF_N +V 11300,25700,CONT_DIF_N +V 11300,27300,CONT_DIF_N +V 11300,26900,CONT_DIF_N +V 11300,25300,CONT_DIF_N +V 11300,26500,CONT_VIA +V 11300,24900,CONT_VIA +V 11300,28100,CONT_VIA +V 10100,24900,CONT_VIA +V 10100,25300,CONT_DIF_N +V 10100,26900,CONT_DIF_N +V 10100,27300,CONT_DIF_N +V 10100,26500,CONT_DIF_N +V 10100,28100,CONT_DIF_N +V 10100,25700,CONT_DIF_N +V 10100,27700,CONT_VIA +V 10100,26100,CONT_VIA +V 11300,28700,CONT_BODY_P +V 10100,28700,CONT_BODY_P +V 9200,13600,CONT_BODY_N +V 10300,13600,CONT_BODY_N +V 9700,13600,CONT_BODY_N +V 11100,13600,CONT_BODY_N +V 10700,13100,CONT_POLY +V 10000,13600,CONT_VIA +V 9500,25000,CONT_DIF_N +V 9500,27400,CONT_DIF_N +V 9500,27800,CONT_DIF_N +V 9500,25400,CONT_DIF_N +V 9500,25800,CONT_DIF_N +V 9500,26200,CONT_DIF_N +V 9500,26600,CONT_DIF_N +V 9500,27000,CONT_DIF_N +V 10700,25800,CONT_DIF_N +V 10700,26200,CONT_DIF_N +V 10700,25400,CONT_DIF_N +V 10700,25000,CONT_DIF_N +V 10700,27800,CONT_DIF_N +V 10700,26600,CONT_DIF_N +V 10700,27000,CONT_DIF_N +V 10700,27400,CONT_DIF_N +V 10100,14300,CONT_DIF_P +V 9500,14700,CONT_DIF_P +V 10100,14700,CONT_DIF_P +V 9500,15100,CONT_DIF_P +V 9500,14300,CONT_DIF_P +V 10700,14300,CONT_DIF_P +V 11300,14300,CONT_DIF_P +V 10700,14700,CONT_DIF_P +V 11300,14700,CONT_DIF_P +V 10700,15100,CONT_DIF_P +V 10100,15500,CONT_DIF_P +V 9500,15500,CONT_DIF_P +V 9500,19500,CONT_DIF_P +V 9500,17900,CONT_DIF_P +V 10100,17900,CONT_DIF_P +V 9500,18300,CONT_DIF_P +V 10100,18300,CONT_DIF_P +V 9500,18700,CONT_DIF_P +V 9500,19100,CONT_DIF_P +V 10100,19100,CONT_DIF_P +V 10100,19500,CONT_DIF_P +V 9500,16300,CONT_DIF_P +V 9500,15900,CONT_DIF_P +V 10100,15900,CONT_DIF_P +V 9500,17500,CONT_DIF_P +V 9500,17100,CONT_DIF_P +V 9500,16700,CONT_DIF_P +V 10100,16700,CONT_DIF_P +V 10100,17100,CONT_DIF_P +V 10700,15500,CONT_DIF_P +V 11300,15500,CONT_DIF_P +V 11300,19500,CONT_DIF_P +V 10700,18300,CONT_DIF_P +V 10700,18700,CONT_DIF_P +V 10700,19100,CONT_DIF_P +V 11300,19100,CONT_DIF_P +V 10700,19500,CONT_DIF_P +V 10700,17500,CONT_DIF_P +V 10700,17100,CONT_DIF_P +V 10700,17900,CONT_DIF_P +V 11300,17900,CONT_DIF_P +V 11300,18300,CONT_DIF_P +V 10700,16300,CONT_DIF_P +V 10700,15900,CONT_DIF_P +V 11300,15900,CONT_DIF_P +V 11300,17100,CONT_DIF_P +V 11300,16700,CONT_DIF_P +V 10700,16700,CONT_DIF_P +V 10100,15100,CONT_VIA +V 11300,15100,CONT_VIA +V 10100,17500,CONT_VIA +V 10100,18700,CONT_VIA +V 10100,16300,CONT_VIA +V 11300,18700,CONT_VIA +V 11300,17500,CONT_VIA +V 11300,16300,CONT_VIA +V 9500,19900,CONT_DIF_P +V 10700,19900,CONT_DIF_P +V 10100,19900,CONT_VIA +V 11300,19900,CONT_VIA +V 9500,20300,CONT_DIF_P +V 10700,20300,CONT_DIF_P +V 10100,20300,CONT_DIF_P +V 11300,20300,CONT_DIF_P +V 10100,20700,CONT_DIF_P +V 11300,20700,CONT_DIF_P +V 10700,20700,CONT_DIF_P +V 9500,20700,CONT_DIF_P +V 9500,21100,CONT_DIF_P +V 10700,21100,CONT_DIF_P +V 11300,21100,CONT_VIA +V 10100,21100,CONT_VIA +V 9500,21500,CONT_DIF_P +V 10100,21500,CONT_DIF_P +V 10700,21500,CONT_DIF_P +V 11300,21500,CONT_DIF_P +V 10100,24300,CONT_BODY_P +V 11300,24300,CONT_BODY_P +V 11200,23800,CONT_POLY +V 10100,23800,CONT_VIA +V 11200,23200,CONT_VIA +V 11300,22500,CONT_BODY_N +V 10100,22500,CONT_BODY_N +V 11300,21900,CONT_DIF_P +V 10700,21900,CONT_DIF_P +V 10100,21900,CONT_DIF_P +V 9500,21900,CONT_DIF_P +EOF diff --git a/alliance/src/cells/src/padlib/palow_sp.ap b/alliance/src/cells/src/padlib/palow_sp.ap new file mode 100644 index 00000000..01f349c9 --- /dev/null +++ b/alliance/src/cells/src/padlib/palow_sp.ap @@ -0,0 +1,1064 @@ +V ALLIANCE : 3 +H palow_sp,P,11/ 9/95 +A 0,-7,172,356 +C 0,6,12,ck,0,WEST,ALU2 +C 172,6,12,ck,1,EAST,ALU2 +C 0,84,40,vddi,0,WEST,ALU2 +C 0,40,40,vssi,0,WEST,ALU2 +C 172,40,40,vssi,1,EAST,ALU2 +C 172,84,40,vddi,1,EAST,ALU2 +C 0,168,120,vdde,0,WEST,ALU2 +C 172,168,120,vdde,1,EAST,ALU2 +C 75,-7,2,i,1,SOUTH,ALU2 +C 75,-7,2,i,0,SOUTH,ALU1 +C 172,296,120,vsse,1,EAST,ALU2 +C 0,296,120,vsse,0,WEST,ALU2 +S 0,6,172,6,12,ck,RIGHT,ALU2 +S 0,40,172,40,40,vssi,RIGHT,ALU2 +S 0,84,172,84,40,vddi,RIGHT,ALU2 +S 0,168,172,168,120,vdde,RIGHT,ALU2 +S 0,296,172,296,120,vsse,RIGHT,ALU2 +S 126,225,132,225,3,*,RIGHT,NTIE +S 126,136,132,136,3,*,RIGHT,NTIE +S 134,16,144,16,3,*,RIGHT,ALU1 +S 125,289,125,293,3,*,UP,ALU1 +S 129,242,129,293,6,*,UP,ALU1 +S 129,135,129,226,6,*,UP,ALU1 +S 131,242,131,288,3,*,UP,PTIE +S 127,287,132,287,3,*,RIGHT,PTIE +S 126,243,132,243,3,*,RIGHT,PTIE +S 131,135,131,226,3,*,UP,NTIE +S 130,134,130,227,6,*,UP,NWELL +S 50,242,50,293,8,*,UP,ALU1 +S 46,280,46,288,1,*,UP,ALU1 +S 50,135,50,226,8,*,UP,ALU1 +S 46,287,54,287,3,*,RIGHT,PTIE +S 47,242,47,288,3,*,UP,PTIE +S 46,243,54,243,3,*,RIGHT,PTIE +S 47,225,53,225,3,*,RIGHT,NTIE +S 47,136,53,136,3,*,RIGHT,NTIE +S 47,136,47,226,3,*,UP,NTIE +S 53,141,53,220,3,*,UP,PDIF +S 53,249,53,282,3,*,UP,NDIF +S 49,134,49,227,8,*,UP,NWELL +S 143,16,143,233,3,*,UP,ALU1 +S 137,232,144,232,3,*,RIGHT,ALU1 +S 76,232,143,232,3,*,RIGHT,ALU2 +S 112,50,112,120,2,*,UP,ALU1 +S 88,51,97,51,3,*,RIGHT,ALU1 +S 118,50,118,121,3,*,UP,ALU1 +S 86,40,119,40,3,*,RIGHT,ALU1 +S 103,51,119,51,3,*,RIGHT,ALU1 +S 70,50,70,121,2,*,UP,ALU1 +S 106,58,106,129,2,*,UP,ALU1 +S 94,58,94,129,2,*,UP,ALU1 +S 94,6,94,33,2,*,UP,ALU1 +S 63,120,90,120,3,*,RIGHT,ALU1 +S 100,57,100,120,2,*,UP,ALU1 +S 82,46,99,46,2,*,RIGHT,ALU1 +S 88,50,88,121,2,*,UP,ALU1 +S 82,9,82,114,2,*,UP,ALU1 +S 76,9,76,114,2,*,UP,ALU1 +S 106,6,106,33,2,*,UP,ALU1 +S 66,50,66,121,7,*,UP,ALU1 +S 63,51,71,51,3,*,RIGHT,ALU1 +S 66,-3,66,41,7,*,UP,ALU1 +S 100,-3,100,32,2,*,UP,ALU1 +S 88,-3,88,41,2,*,UP,ALU1 +S 70,-3,70,41,2,*,UP,ALU1 +S 75,-7,75,3,2,*,UP,ALU1 +S 112,-3,112,41,2,*,UP,ALU1 +S 118,-3,118,41,3,*,UP,ALU1 +S 79,-2,119,-2,3,*,RIGHT,ALU1 +S 100,37,100,54,2,*,UP,POLY +S 91,54,109,54,1,*,RIGHT,POLY +S 91,37,109,37,1,*,RIGHT,POLY +S 78,53,85,53,3,*,RIGHT,POLY +S 85,37,85,54,1,*,UP,POLY +S 73,37,73,54,1,*,UP,POLY +S 73,2,73,4,1,*,UP,POLY +S 63,40,71,40,3,*,RIGHT,PTIE +S 87,40,97,40,3,*,RIGHT,PTIE +S 103,40,119,40,3,*,RIGHT,PTIE +S 64,-3,64,41,3,*,UP,PTIE +S 118,-3,118,41,3,*,UP,PTIE +S 63,-2,119,-2,3,*,RIGHT,PTIE +S 63,51,71,51,3,*,RIGHT,NTIE +S 64,50,64,121,3,*,UP,NTIE +S 87,51,97,51,3,*,RIGHT,NTIE +S 118,50,118,121,3,*,UP,NTIE +S 103,51,119,51,3,*,RIGHT,NTIE +S 63,120,118,120,3,*,RIGHT,NTIE +S 82,56,82,115,3,*,UP,PDIF +S 106,56,106,115,3,*,UP,PDIF +S 97,54,97,117,1,*,UP,PTRANS +S 76,56,76,115,3,*,UP,PDIF +S 73,54,73,117,1,*,UP,PTRANS +S 70,56,70,115,3,*,UP,PDIF +S 103,54,103,117,1,*,UP,PTRANS +S 91,54,91,117,1,*,UP,PTRANS +S 88,56,88,115,3,*,UP,PDIF +S 85,54,85,117,1,*,UP,PTRANS +S 94,56,94,115,3,*,UP,PDIF +S 112,56,112,115,3,*,UP,PDIF +S 100,56,100,115,3,*,UP,PDIF +S 109,54,109,117,1,*,UP,PTRANS +S 85,4,85,37,1,*,UP,NTRANS +S 82,6,82,35,3,*,UP,NDIF +S 76,6,76,35,3,*,UP,NDIF +S 73,4,73,37,1,*,UP,NTRANS +S 70,6,70,35,2,*,UP,NDIF +S 112,6,112,35,3,*,UP,NDIF +S 103,4,103,37,1,*,UP,NTRANS +S 97,4,97,37,1,*,UP,NTRANS +S 91,4,91,37,1,*,UP,NTRANS +S 88,6,88,35,2,*,UP,NDIF +S 70,6,70,35,3,*,UP,NDIF +S 106,6,106,35,3,*,UP,NDIF +S 94,6,94,35,3,*,UP,NDIF +S 112,6,112,35,2,*,UP,NDIF +S 100,6,100,35,2,*,UP,NDIF +S 109,4,109,37,1,*,UP,NTRANS +S 62,86,120,86,72,*,RIGHT,NWELL +S 62,51,120,51,4,*,RIGHT,NWELL +S 66,16,143,16,3,*,RIGHT,ALU2 +S 70,130,144,130,2,*,RIGHT,ALU1 +S 70,131,144,131,2,*,RIGHT,ALU1 +S 58,296,120,296,9,*,RIGHT,ALU1 +S 59,142,59,291,3,*,UP,ALU1 +S 71,142,71,291,3,*,UP,ALU1 +S 65,237,65,288,3,*,UP,ALU1 +S 77,242,77,288,3,*,UP,ALU1 +S 77,248,77,282,3,*,UP,NDIF +S 71,248,71,282,3,*,UP,NDIF +S 65,248,65,282,3,*,UP,NDIF +S 59,248,59,282,3,*,UP,NDIF +S 56,246,56,284,1,*,UP,NTRANS +S 62,246,62,284,1,*,UP,NTRANS +S 68,246,68,284,1,*,UP,NTRANS +S 74,246,74,284,1,*,UP,NTRANS +S 54,287,78,287,3,*,RIGHT,PTIE +S 77,141,77,220,3,*,UP,PDIF +S 71,141,71,220,2,*,UP,PDIF +S 65,141,65,220,2,*,UP,PDIF +S 59,141,59,220,2,*,UP,PDIF +S 56,139,56,222,1,*,UP,PTRANS +S 65,138,65,226,3,*,UP,ALU1 +S 62,139,62,222,1,*,UP,PTRANS +S 68,139,68,222,1,*,UP,PTRANS +S 74,139,74,222,1,*,UP,PTRANS +S 67,134,67,227,28,*,UP,NWELL +S 77,138,77,226,3,*,UP,ALU1 +S 54,136,68,136,3,*,RIGHT,NTIE +S 74,136,78,136,3,*,RIGHT,NTIE +S 71,133,71,139,2,*,UP,POLY +S 56,139,74,139,1,*,RIGHT,POLY +S 54,136,68,136,3,*,RIGHT,ALU1 +S 74,136,78,136,3,*,RIGHT,ALU1 +S 71,237,71,239,2,*,UP,POLY +S 54,243,68,243,3,*,RIGHT,PTIE +S 74,243,78,243,3,*,RIGHT,PTIE +S 56,246,74,246,1,*,RIGHT,POLY +S 71,238,71,246,2,*,UP,POLY +S 71,238,76,238,3,*,RIGHT,POLY +S 76,232,76,238,2,*,UP,ALU1 +S 54,225,78,225,3,*,RIGHT,NTIE +S 107,142,107,291,3,*,UP,ALU1 +S 119,142,119,291,3,*,UP,ALU1 +S 113,237,113,288,3,*,UP,ALU1 +S 125,242,125,288,3,*,UP,ALU1 +S 125,248,125,282,3,*,UP,NDIF +S 119,248,119,282,3,*,UP,NDIF +S 113,248,113,282,3,*,UP,NDIF +S 107,248,107,282,3,*,UP,NDIF +S 104,246,104,284,1,*,UP,NTRANS +S 110,246,110,284,1,*,UP,NTRANS +S 116,246,116,284,1,*,UP,NTRANS +S 122,246,122,284,1,*,UP,NTRANS +S 102,287,126,287,3,*,RIGHT,PTIE +S 125,141,125,220,3,*,UP,PDIF +S 119,141,119,220,2,*,UP,PDIF +S 113,141,113,220,2,*,UP,PDIF +S 107,141,107,220,2,*,UP,PDIF +S 104,139,104,222,1,*,UP,PTRANS +S 113,138,113,226,3,*,UP,ALU1 +S 110,139,110,222,1,*,UP,PTRANS +S 116,139,116,222,1,*,UP,PTRANS +S 122,139,122,222,1,*,UP,PTRANS +S 115,134,115,227,28,*,UP,NWELL +S 125,138,125,226,3,*,UP,ALU1 +S 102,136,116,136,3,*,RIGHT,NTIE +S 122,136,126,136,3,*,RIGHT,NTIE +S 119,133,119,139,2,*,UP,POLY +S 104,139,122,139,1,*,RIGHT,POLY +S 102,136,116,136,3,*,RIGHT,ALU1 +S 122,136,126,136,3,*,RIGHT,ALU1 +S 119,237,119,239,2,*,UP,POLY +S 102,243,116,243,3,*,RIGHT,PTIE +S 122,243,126,243,3,*,RIGHT,PTIE +S 104,246,122,246,1,*,RIGHT,POLY +S 119,238,119,246,2,*,UP,POLY +S 119,238,124,238,3,*,RIGHT,POLY +S 124,232,124,238,2,*,UP,ALU1 +S 102,225,126,225,3,*,RIGHT,NTIE +S 83,142,83,291,3,*,UP,ALU1 +S 95,142,95,291,3,*,UP,ALU1 +S 89,237,89,288,3,*,UP,ALU1 +S 101,242,101,288,3,*,UP,ALU1 +S 101,248,101,282,3,*,UP,NDIF +S 95,248,95,282,3,*,UP,NDIF +S 89,248,89,282,3,*,UP,NDIF +S 83,248,83,282,3,*,UP,NDIF +S 80,246,80,284,1,*,UP,NTRANS +S 86,246,86,284,1,*,UP,NTRANS +S 92,246,92,284,1,*,UP,NTRANS +S 98,246,98,284,1,*,UP,NTRANS +S 78,287,102,287,3,*,RIGHT,PTIE +S 101,141,101,220,3,*,UP,PDIF +S 95,141,95,220,2,*,UP,PDIF +S 89,141,89,220,2,*,UP,PDIF +S 83,141,83,220,2,*,UP,PDIF +S 80,139,80,222,1,*,UP,PTRANS +S 89,138,89,226,3,*,UP,ALU1 +S 86,139,86,222,1,*,UP,PTRANS +S 92,139,92,222,1,*,UP,PTRANS +S 98,139,98,222,1,*,UP,PTRANS +S 91,134,91,227,28,*,UP,NWELL +S 101,138,101,226,3,*,UP,ALU1 +S 78,136,92,136,3,*,RIGHT,NTIE +S 98,136,102,136,3,*,RIGHT,NTIE +S 95,133,95,139,2,*,UP,POLY +S 80,139,98,139,1,*,RIGHT,POLY +S 78,136,92,136,3,*,RIGHT,ALU1 +S 98,136,102,136,3,*,RIGHT,ALU1 +S 95,237,95,239,2,*,UP,POLY +S 78,243,92,243,3,*,RIGHT,PTIE +S 98,243,102,243,3,*,RIGHT,PTIE +S 80,246,98,246,1,*,RIGHT,POLY +S 95,238,95,246,2,*,UP,POLY +S 95,238,100,238,3,*,RIGHT,POLY +S 100,232,100,238,2,*,UP,ALU1 +S 78,225,102,225,3,*,RIGHT,NTIE +S 89,301,89,356,62,*,UP,ALU1 +V 135,16,CONT_VIA +V 139,16,CONT_VIA +V 125,292,CONT_VIA +V 131,292,CONT_VIA +V 128,225,CONT_VIA +V 131,279,CONT_VIA +V 128,243,CONT_VIA +V 131,259,CONT_VIA +V 128,219,CONT_VIA +V 128,203,CONT_VIA +V 128,207,CONT_VIA +V 128,215,CONT_VIA +V 128,195,CONT_VIA +V 128,191,CONT_VIA +V 128,147,CONT_VIA +V 128,167,CONT_VIA +V 128,139,CONT_VIA +V 128,143,CONT_VIA +V 128,159,CONT_VIA +V 128,155,CONT_VIA +V 128,183,CONT_VIA +V 128,171,CONT_VIA +V 128,179,CONT_VIA +V 131,247,CONT_BODY_P +V 131,251,CONT_BODY_P +V 131,255,CONT_BODY_P +V 131,243,CONT_BODY_P +V 131,287,CONT_BODY_P +V 131,283,CONT_BODY_P +V 131,275,CONT_BODY_P +V 131,271,CONT_BODY_P +V 131,267,CONT_BODY_P +V 131,263,CONT_BODY_P +V 131,216,CONT_BODY_N +V 131,212,CONT_BODY_N +V 131,208,CONT_BODY_N +V 131,204,CONT_BODY_N +V 131,225,CONT_BODY_N +V 131,200,CONT_BODY_N +V 131,220,CONT_BODY_N +V 131,184,CONT_BODY_N +V 131,180,CONT_BODY_N +V 131,176,CONT_BODY_N +V 131,196,CONT_BODY_N +V 131,192,CONT_BODY_N +V 131,188,CONT_BODY_N +V 127,136,CONT_BODY_N +V 131,136,CONT_BODY_N +V 131,156,CONT_BODY_N +V 131,152,CONT_BODY_N +V 131,148,CONT_BODY_N +V 131,144,CONT_BODY_N +V 131,140,CONT_BODY_N +V 131,164,CONT_BODY_N +V 131,160,CONT_BODY_N +V 131,168,CONT_BODY_N +V 131,172,CONT_BODY_N +V 50,208,CONT_VIA +V 50,204,CONT_VIA +V 50,200,CONT_VIA +V 52,292,CONT_VIA +V 50,279,CONT_VIA +V 50,275,CONT_VIA +V 50,271,CONT_VIA +V 50,267,CONT_VIA +V 50,220,CONT_VIA +V 50,216,CONT_VIA +V 50,212,CONT_VIA +V 50,225,CONT_VIA +V 50,259,CONT_VIA +V 50,247,CONT_VIA +V 50,251,CONT_VIA +V 50,255,CONT_VIA +V 50,263,CONT_VIA +V 50,283,CONT_VIA +V 47,292,CONT_VIA +V 50,156,CONT_VIA +V 50,152,CONT_VIA +V 50,148,CONT_VIA +V 50,144,CONT_VIA +V 50,168,CONT_VIA +V 50,160,CONT_VIA +V 50,164,CONT_VIA +V 50,140,CONT_VIA +V 50,176,CONT_VIA +V 50,172,CONT_VIA +V 50,188,CONT_VIA +V 50,184,CONT_VIA +V 50,196,CONT_VIA +V 50,192,CONT_VIA +V 50,180,CONT_VIA +V 51,287,CONT_BODY_P +V 51,243,CONT_BODY_P +V 47,271,CONT_BODY_P +V 47,267,CONT_BODY_P +V 47,263,CONT_BODY_P +V 47,259,CONT_BODY_P +V 47,287,CONT_BODY_P +V 47,247,CONT_BODY_P +V 47,251,CONT_BODY_P +V 47,255,CONT_BODY_P +V 47,243,CONT_BODY_P +V 47,283,CONT_BODY_P +V 47,279,CONT_BODY_P +V 47,275,CONT_BODY_P +V 53,225,CONT_BODY_N +V 47,225,CONT_BODY_N +V 47,200,CONT_BODY_N +V 47,204,CONT_BODY_N +V 47,208,CONT_BODY_N +V 47,212,CONT_BODY_N +V 47,216,CONT_BODY_N +V 47,220,CONT_BODY_N +V 52,136,CONT_BODY_N +V 47,168,CONT_BODY_N +V 47,136,CONT_BODY_N +V 47,140,CONT_BODY_N +V 47,144,CONT_BODY_N +V 47,148,CONT_BODY_N +V 47,152,CONT_BODY_N +V 47,156,CONT_BODY_N +V 47,192,CONT_BODY_N +V 47,196,CONT_BODY_N +V 47,184,CONT_BODY_N +V 47,176,CONT_BODY_N +V 47,180,CONT_BODY_N +V 47,160,CONT_BODY_N +V 47,164,CONT_BODY_N +V 47,172,CONT_BODY_N +V 47,188,CONT_BODY_N +V 53,219,CONT_DIF_P +V 53,215,CONT_DIF_P +V 53,211,CONT_DIF_P +V 53,207,CONT_DIF_P +V 53,203,CONT_DIF_P +V 53,199,CONT_DIF_P +V 53,163,CONT_DIF_P +V 53,167,CONT_DIF_P +V 53,171,CONT_DIF_P +V 53,187,CONT_DIF_P +V 53,191,CONT_DIF_P +V 53,195,CONT_DIF_P +V 53,143,CONT_DIF_P +V 53,147,CONT_DIF_P +V 53,151,CONT_DIF_P +V 53,155,CONT_DIF_P +V 53,159,CONT_DIF_P +V 53,179,CONT_DIF_P +V 53,175,CONT_DIF_P +V 53,183,CONT_DIF_P +V 53,257,CONT_DIF_N +V 53,253,CONT_DIF_N +V 53,249,CONT_DIF_N +V 53,261,CONT_DIF_N +V 53,273,CONT_DIF_N +V 53,281,CONT_DIF_N +V 53,277,CONT_DIF_N +V 53,269,CONT_DIF_N +V 53,265,CONT_DIF_N +V 138,232,CONT_VIA +V 143,232,CONT_VIA +V 118,36,CONT_VIA +V 118,24,CONT_VIA +V 118,100,CONT_VIA +V 118,75,CONT_VIA +V 118,87,CONT_VIA +V 118,67,CONT_VIA +V 94,16,CONT_VIA +V 106,16,CONT_VIA +V 70,35,CONT_VIA +V 70,102,CONT_VIA +V 70,90,CONT_VIA +V 70,74,CONT_VIA +V 70,66,CONT_VIA +V 70,23,CONT_VIA +V 88,66,CONT_VIA +V 88,74,CONT_VIA +V 88,90,CONT_VIA +V 88,102,CONT_VIA +V 88,35,CONT_VIA +V 88,23,CONT_VIA +V 100,23,CONT_VIA +V 100,74,CONT_VIA +V 100,90,CONT_VIA +V 100,102,CONT_VIA +V 100,66,CONT_VIA +V 112,23,CONT_VIA +V 112,66,CONT_VIA +V 112,102,CONT_VIA +V 112,90,CONT_VIA +V 112,74,CONT_VIA +V 112,35,CONT_VIA +V 64,66,CONT_VIA +V 64,35,CONT_VIA +V 64,23,CONT_VIA +V 75,-7,CONT_VIA +V 75,3,CONT_POLY +V 77,53,CONT_POLY +V 100,46,CONT_POLY +V 118,28,CONT_BODY_P +V 118,32,CONT_BODY_P +V 118,8,CONT_BODY_P +V 118,3,CONT_BODY_P +V 118,40,CONT_BODY_P +V 118,12,CONT_BODY_P +V 118,16,CONT_BODY_P +V 118,20,CONT_BODY_P +V 92,40,CONT_BODY_P +V 96,40,CONT_BODY_P +V 108,40,CONT_BODY_P +V 112,40,CONT_BODY_P +V 88,40,CONT_BODY_P +V 104,40,CONT_BODY_P +V 70,40,CONT_BODY_P +V 64,40,CONT_BODY_P +V 64,31,CONT_BODY_P +V 64,27,CONT_BODY_P +V 64,19,CONT_BODY_P +V 64,15,CONT_BODY_P +V 64,11,CONT_BODY_P +V 64,7,CONT_BODY_P +V 64,3,CONT_BODY_P +V 96,-2,CONT_BODY_P +V 92,-2,CONT_BODY_P +V 84,-2,CONT_BODY_P +V 80,-2,CONT_BODY_P +V 118,-2,CONT_BODY_P +V 64,-2,CONT_BODY_P +V 100,-2,CONT_BODY_P +V 88,-2,CONT_BODY_P +V 70,-2,CONT_BODY_P +V 112,-2,CONT_BODY_P +V 108,-2,CONT_BODY_P +V 104,-2,CONT_BODY_P +V 118,91,CONT_BODY_N +V 118,83,CONT_BODY_N +V 118,108,CONT_BODY_N +V 118,116,CONT_BODY_N +V 118,79,CONT_BODY_N +V 118,71,CONT_BODY_N +V 118,51,CONT_BODY_N +V 118,112,CONT_BODY_N +V 118,63,CONT_BODY_N +V 118,59,CONT_BODY_N +V 118,120,CONT_BODY_N +V 118,95,CONT_BODY_N +V 118,104,CONT_BODY_N +V 118,55,CONT_BODY_N +V 70,51,CONT_BODY_N +V 74,120,CONT_BODY_N +V 70,120,CONT_BODY_N +V 79,120,CONT_BODY_N +V 84,120,CONT_BODY_N +V 112,120,CONT_BODY_N +V 104,51,CONT_BODY_N +V 108,51,CONT_BODY_N +V 100,120,CONT_BODY_N +V 92,51,CONT_BODY_N +V 96,51,CONT_BODY_N +V 112,51,CONT_BODY_N +V 88,51,CONT_BODY_N +V 89,120,CONT_BODY_N +V 64,86,CONT_BODY_N +V 64,78,CONT_BODY_N +V 64,74,CONT_BODY_N +V 64,70,CONT_BODY_N +V 64,63,CONT_BODY_N +V 64,59,CONT_BODY_N +V 64,55,CONT_BODY_N +V 64,104,CONT_BODY_N +V 64,94,CONT_BODY_N +V 64,98,CONT_BODY_N +V 64,51,CONT_BODY_N +V 64,108,CONT_BODY_N +V 64,112,CONT_BODY_N +V 64,116,CONT_BODY_N +V 64,120,CONT_BODY_N +V 64,90,CONT_BODY_N +V 64,82,CONT_BODY_N +V 70,114,CONT_DIF_P +V 70,82,CONT_DIF_P +V 70,78,CONT_DIF_P +V 70,110,CONT_DIF_P +V 70,98,CONT_DIF_P +V 70,58,CONT_DIF_P +V 70,70,CONT_DIF_P +V 70,62,CONT_DIF_P +V 70,94,CONT_DIF_P +V 70,106,CONT_DIF_P +V 70,86,CONT_DIF_P +V 76,98,CONT_DIF_P +V 76,106,CONT_DIF_P +V 76,66,CONT_DIF_P +V 76,110,CONT_DIF_P +V 76,82,CONT_DIF_P +V 76,58,CONT_DIF_P +V 76,102,CONT_DIF_P +V 76,94,CONT_DIF_P +V 82,62,CONT_DIF_P +V 76,70,CONT_DIF_P +V 76,78,CONT_DIF_P +V 76,90,CONT_DIF_P +V 76,86,CONT_DIF_P +V 76,114,CONT_DIF_P +V 76,74,CONT_DIF_P +V 76,62,CONT_DIF_P +V 82,78,CONT_DIF_P +V 82,102,CONT_DIF_P +V 82,90,CONT_DIF_P +V 82,58,CONT_DIF_P +V 82,82,CONT_DIF_P +V 82,86,CONT_DIF_P +V 82,114,CONT_DIF_P +V 82,74,CONT_DIF_P +V 88,82,CONT_DIF_P +V 88,114,CONT_DIF_P +V 88,86,CONT_DIF_P +V 82,106,CONT_DIF_P +V 82,94,CONT_DIF_P +V 82,98,CONT_DIF_P +V 82,66,CONT_DIF_P +V 82,70,CONT_DIF_P +V 100,94,CONT_DIF_P +V 88,62,CONT_DIF_P +V 88,70,CONT_DIF_P +V 82,110,CONT_DIF_P +V 88,94,CONT_DIF_P +V 88,98,CONT_DIF_P +V 88,110,CONT_DIF_P +V 88,78,CONT_DIF_P +V 100,78,CONT_DIF_P +V 100,82,CONT_DIF_P +V 100,114,CONT_DIF_P +V 88,106,CONT_DIF_P +V 100,62,CONT_DIF_P +V 100,58,CONT_DIF_P +V 100,70,CONT_DIF_P +V 100,98,CONT_DIF_P +V 112,58,CONT_DIF_P +V 112,62,CONT_DIF_P +V 112,86,CONT_DIF_P +V 88,58,CONT_DIF_P +V 112,82,CONT_DIF_P +V 112,94,CONT_DIF_P +V 100,106,CONT_DIF_P +V 100,110,CONT_DIF_P +V 94,102,CONT_DIF_P +V 94,78,CONT_DIF_P +V 94,90,CONT_DIF_P +V 100,86,CONT_DIF_P +V 112,110,CONT_DIF_P +V 112,106,CONT_DIF_P +V 112,98,CONT_DIF_P +V 112,70,CONT_DIF_P +V 94,86,CONT_DIF_P +V 94,114,CONT_DIF_P +V 94,74,CONT_DIF_P +V 112,114,CONT_DIF_P +V 94,94,CONT_DIF_P +V 94,98,CONT_DIF_P +V 94,66,CONT_DIF_P +V 94,70,CONT_DIF_P +V 106,70,CONT_DIF_P +V 106,102,CONT_DIF_P +V 106,78,CONT_DIF_P +V 112,78,CONT_DIF_P +V 94,106,CONT_DIF_P +V 94,110,CONT_DIF_P +V 94,58,CONT_DIF_P +V 94,82,CONT_DIF_P +V 106,86,CONT_DIF_P +V 106,114,CONT_DIF_P +V 106,74,CONT_DIF_P +V 94,62,CONT_DIF_P +V 106,62,CONT_DIF_P +V 106,94,CONT_DIF_P +V 106,98,CONT_DIF_P +V 106,66,CONT_DIF_P +V 106,90,CONT_DIF_P +V 106,106,CONT_DIF_P +V 106,110,CONT_DIF_P +V 106,58,CONT_DIF_P +V 106,82,CONT_DIF_P +V 94,12,CONT_DIF_N +V 94,7,CONT_DIF_N +V 76,29,CONT_DIF_N +V 70,11,CONT_DIF_N +V 70,15,CONT_DIF_N +V 70,19,CONT_DIF_N +V 70,27,CONT_DIF_N +V 70,31,CONT_DIF_N +V 70,7,CONT_DIF_N +V 106,12,CONT_DIF_N +V 82,21,CONT_DIF_N +V 106,7,CONT_DIF_N +V 76,21,CONT_DIF_N +V 76,25,CONT_DIF_N +V 76,9,CONT_DIF_N +V 76,13,CONT_DIF_N +V 76,17,CONT_DIF_N +V 76,33,CONT_DIF_N +V 88,19,CONT_DIF_N +V 88,15,CONT_DIF_N +V 88,11,CONT_DIF_N +V 82,33,CONT_DIF_N +V 82,29,CONT_DIF_N +V 82,9,CONT_DIF_N +V 82,13,CONT_DIF_N +V 82,17,CONT_DIF_N +V 112,27,CONT_DIF_N +V 112,19,CONT_DIF_N +V 100,19,CONT_DIF_N +V 82,25,CONT_DIF_N +V 100,11,CONT_DIF_N +V 100,15,CONT_DIF_N +V 88,31,CONT_DIF_N +V 88,27,CONT_DIF_N +V 94,25,CONT_DIF_N +V 94,21,CONT_DIF_N +V 94,33,CONT_DIF_N +V 88,7,CONT_DIF_N +V 112,15,CONT_DIF_N +V 112,11,CONT_DIF_N +V 112,7,CONT_DIF_N +V 112,31,CONT_DIF_N +V 106,21,CONT_DIF_N +V 94,29,CONT_DIF_N +V 100,28,CONT_DIF_N +V 100,33,CONT_DIF_N +V 106,25,CONT_DIF_N +V 100,7,CONT_DIF_N +V 106,33,CONT_DIF_N +V 106,29,CONT_DIF_N +V 143,16,CONT_VIA +V 77,277,CONT_DIF_N +V 77,261,CONT_DIF_N +V 77,257,CONT_DIF_N +V 77,273,CONT_DIF_N +V 77,269,CONT_DIF_N +V 77,253,CONT_DIF_N +V 77,265,CONT_VIA +V 77,249,CONT_VIA +V 77,281,CONT_VIA +V 65,249,CONT_VIA +V 65,253,CONT_DIF_N +V 65,269,CONT_DIF_N +V 65,273,CONT_DIF_N +V 65,265,CONT_DIF_N +V 65,281,CONT_DIF_N +V 65,257,CONT_DIF_N +V 65,277,CONT_VIA +V 65,261,CONT_VIA +V 77,287,CONT_BODY_P +V 65,287,CONT_BODY_P +V 56,136,CONT_BODY_N +V 67,136,CONT_BODY_N +V 61,136,CONT_BODY_N +V 75,136,CONT_BODY_N +V 71,131,CONT_POLY +V 64,136,CONT_VIA +V 59,250,CONT_DIF_N +V 59,274,CONT_DIF_N +V 59,278,CONT_DIF_N +V 59,254,CONT_DIF_N +V 59,258,CONT_DIF_N +V 59,262,CONT_DIF_N +V 59,266,CONT_DIF_N +V 59,270,CONT_DIF_N +V 71,258,CONT_DIF_N +V 71,262,CONT_DIF_N +V 71,254,CONT_DIF_N +V 71,250,CONT_DIF_N +V 71,278,CONT_DIF_N +V 71,266,CONT_DIF_N +V 71,270,CONT_DIF_N +V 71,274,CONT_DIF_N +V 65,143,CONT_DIF_P +V 59,147,CONT_DIF_P +V 65,147,CONT_DIF_P +V 59,151,CONT_DIF_P +V 59,143,CONT_DIF_P +V 71,143,CONT_DIF_P +V 77,143,CONT_DIF_P +V 71,147,CONT_DIF_P +V 77,147,CONT_DIF_P +V 71,151,CONT_DIF_P +V 65,155,CONT_DIF_P +V 59,155,CONT_DIF_P +V 59,195,CONT_DIF_P +V 59,179,CONT_DIF_P +V 65,179,CONT_DIF_P +V 59,183,CONT_DIF_P +V 65,183,CONT_DIF_P +V 59,187,CONT_DIF_P +V 59,191,CONT_DIF_P +V 65,191,CONT_DIF_P +V 65,195,CONT_DIF_P +V 59,163,CONT_DIF_P +V 59,159,CONT_DIF_P +V 65,159,CONT_DIF_P +V 59,175,CONT_DIF_P +V 59,171,CONT_DIF_P +V 59,167,CONT_DIF_P +V 65,167,CONT_DIF_P +V 65,171,CONT_DIF_P +V 71,155,CONT_DIF_P +V 77,155,CONT_DIF_P +V 77,195,CONT_DIF_P +V 71,183,CONT_DIF_P +V 71,187,CONT_DIF_P +V 71,191,CONT_DIF_P +V 77,191,CONT_DIF_P +V 71,195,CONT_DIF_P +V 71,175,CONT_DIF_P +V 71,171,CONT_DIF_P +V 71,179,CONT_DIF_P +V 77,179,CONT_DIF_P +V 77,183,CONT_DIF_P +V 71,163,CONT_DIF_P +V 71,159,CONT_DIF_P +V 77,159,CONT_DIF_P +V 77,171,CONT_DIF_P +V 77,167,CONT_DIF_P +V 71,167,CONT_DIF_P +V 65,151,CONT_VIA +V 77,151,CONT_VIA +V 65,175,CONT_VIA +V 65,187,CONT_VIA +V 65,163,CONT_VIA +V 77,187,CONT_VIA +V 77,175,CONT_VIA +V 77,163,CONT_VIA +V 59,199,CONT_DIF_P +V 71,199,CONT_DIF_P +V 65,199,CONT_VIA +V 77,199,CONT_VIA +V 59,203,CONT_DIF_P +V 71,203,CONT_DIF_P +V 65,203,CONT_DIF_P +V 77,203,CONT_DIF_P +V 65,207,CONT_DIF_P +V 77,207,CONT_DIF_P +V 71,207,CONT_DIF_P +V 59,207,CONT_DIF_P +V 59,211,CONT_DIF_P +V 71,211,CONT_DIF_P +V 77,211,CONT_VIA +V 65,211,CONT_VIA +V 59,215,CONT_DIF_P +V 65,215,CONT_DIF_P +V 71,215,CONT_DIF_P +V 77,215,CONT_DIF_P +V 65,243,CONT_BODY_P +V 77,243,CONT_BODY_P +V 76,238,CONT_POLY +V 65,238,CONT_VIA +V 76,232,CONT_VIA +V 77,225,CONT_BODY_N +V 65,225,CONT_BODY_N +V 77,219,CONT_DIF_P +V 71,219,CONT_DIF_P +V 65,219,CONT_DIF_P +V 59,219,CONT_DIF_P +V 125,277,CONT_DIF_N +V 125,261,CONT_DIF_N +V 125,257,CONT_DIF_N +V 125,273,CONT_DIF_N +V 125,269,CONT_DIF_N +V 125,253,CONT_DIF_N +V 125,265,CONT_VIA +V 125,249,CONT_VIA +V 125,281,CONT_VIA +V 113,249,CONT_VIA +V 113,253,CONT_DIF_N +V 113,269,CONT_DIF_N +V 113,273,CONT_DIF_N +V 113,265,CONT_DIF_N +V 113,281,CONT_DIF_N +V 113,257,CONT_DIF_N +V 113,277,CONT_VIA +V 113,261,CONT_VIA +V 125,287,CONT_BODY_P +V 113,287,CONT_BODY_P +V 104,136,CONT_BODY_N +V 115,136,CONT_BODY_N +V 109,136,CONT_BODY_N +V 123,136,CONT_BODY_N +V 119,131,CONT_POLY +V 112,136,CONT_VIA +V 107,250,CONT_DIF_N +V 107,274,CONT_DIF_N +V 107,278,CONT_DIF_N +V 107,254,CONT_DIF_N +V 107,258,CONT_DIF_N +V 107,262,CONT_DIF_N +V 107,266,CONT_DIF_N +V 107,270,CONT_DIF_N +V 119,258,CONT_DIF_N +V 119,262,CONT_DIF_N +V 119,254,CONT_DIF_N +V 119,250,CONT_DIF_N +V 119,278,CONT_DIF_N +V 119,266,CONT_DIF_N +V 119,270,CONT_DIF_N +V 119,274,CONT_DIF_N +V 113,143,CONT_DIF_P +V 107,147,CONT_DIF_P +V 113,147,CONT_DIF_P +V 107,151,CONT_DIF_P +V 107,143,CONT_DIF_P +V 119,143,CONT_DIF_P +V 125,143,CONT_DIF_P +V 119,147,CONT_DIF_P +V 125,147,CONT_DIF_P +V 119,151,CONT_DIF_P +V 113,155,CONT_DIF_P +V 107,155,CONT_DIF_P +V 107,195,CONT_DIF_P +V 107,179,CONT_DIF_P +V 113,179,CONT_DIF_P +V 107,183,CONT_DIF_P +V 113,183,CONT_DIF_P +V 107,187,CONT_DIF_P +V 107,191,CONT_DIF_P +V 113,191,CONT_DIF_P +V 113,195,CONT_DIF_P +V 107,163,CONT_DIF_P +V 107,159,CONT_DIF_P +V 113,159,CONT_DIF_P +V 107,175,CONT_DIF_P +V 107,171,CONT_DIF_P +V 107,167,CONT_DIF_P +V 113,167,CONT_DIF_P +V 113,171,CONT_DIF_P +V 119,155,CONT_DIF_P +V 125,155,CONT_DIF_P +V 125,195,CONT_DIF_P +V 119,183,CONT_DIF_P +V 119,187,CONT_DIF_P +V 119,191,CONT_DIF_P +V 125,191,CONT_DIF_P +V 119,195,CONT_DIF_P +V 119,175,CONT_DIF_P +V 119,171,CONT_DIF_P +V 119,179,CONT_DIF_P +V 125,179,CONT_DIF_P +V 125,183,CONT_DIF_P +V 119,163,CONT_DIF_P +V 119,159,CONT_DIF_P +V 125,159,CONT_DIF_P +V 125,171,CONT_DIF_P +V 125,167,CONT_DIF_P +V 119,167,CONT_DIF_P +V 113,151,CONT_VIA +V 125,151,CONT_VIA +V 113,175,CONT_VIA +V 113,187,CONT_VIA +V 113,163,CONT_VIA +V 125,187,CONT_VIA +V 125,175,CONT_VIA +V 125,163,CONT_VIA +V 107,199,CONT_DIF_P +V 119,199,CONT_DIF_P +V 113,199,CONT_VIA +V 125,199,CONT_VIA +V 107,203,CONT_DIF_P +V 119,203,CONT_DIF_P +V 113,203,CONT_DIF_P +V 125,203,CONT_DIF_P +V 113,207,CONT_DIF_P +V 125,207,CONT_DIF_P +V 119,207,CONT_DIF_P +V 107,207,CONT_DIF_P +V 107,211,CONT_DIF_P +V 119,211,CONT_DIF_P +V 125,211,CONT_VIA +V 113,211,CONT_VIA +V 107,215,CONT_DIF_P +V 113,215,CONT_DIF_P +V 119,215,CONT_DIF_P +V 125,215,CONT_DIF_P +V 113,243,CONT_BODY_P +V 125,243,CONT_BODY_P +V 124,238,CONT_POLY +V 113,238,CONT_VIA +V 124,232,CONT_VIA +V 125,225,CONT_BODY_N +V 113,225,CONT_BODY_N +V 125,219,CONT_DIF_P +V 119,219,CONT_DIF_P +V 113,219,CONT_DIF_P +V 107,219,CONT_DIF_P +V 101,277,CONT_DIF_N +V 101,261,CONT_DIF_N +V 101,257,CONT_DIF_N +V 101,273,CONT_DIF_N +V 101,269,CONT_DIF_N +V 101,253,CONT_DIF_N +V 101,265,CONT_VIA +V 101,249,CONT_VIA +V 101,281,CONT_VIA +V 89,249,CONT_VIA +V 89,253,CONT_DIF_N +V 89,269,CONT_DIF_N +V 89,273,CONT_DIF_N +V 89,265,CONT_DIF_N +V 89,281,CONT_DIF_N +V 89,257,CONT_DIF_N +V 89,277,CONT_VIA +V 89,261,CONT_VIA +V 101,287,CONT_BODY_P +V 89,287,CONT_BODY_P +V 80,136,CONT_BODY_N +V 91,136,CONT_BODY_N +V 85,136,CONT_BODY_N +V 99,136,CONT_BODY_N +V 95,131,CONT_POLY +V 88,136,CONT_VIA +V 83,250,CONT_DIF_N +V 83,274,CONT_DIF_N +V 83,278,CONT_DIF_N +V 83,254,CONT_DIF_N +V 83,258,CONT_DIF_N +V 83,262,CONT_DIF_N +V 83,266,CONT_DIF_N +V 83,270,CONT_DIF_N +V 95,258,CONT_DIF_N +V 95,262,CONT_DIF_N +V 95,254,CONT_DIF_N +V 95,250,CONT_DIF_N +V 95,278,CONT_DIF_N +V 95,266,CONT_DIF_N +V 95,270,CONT_DIF_N +V 95,274,CONT_DIF_N +V 89,143,CONT_DIF_P +V 83,147,CONT_DIF_P +V 89,147,CONT_DIF_P +V 83,151,CONT_DIF_P +V 83,143,CONT_DIF_P +V 95,143,CONT_DIF_P +V 101,143,CONT_DIF_P +V 95,147,CONT_DIF_P +V 101,147,CONT_DIF_P +V 95,151,CONT_DIF_P +V 89,155,CONT_DIF_P +V 83,155,CONT_DIF_P +V 83,195,CONT_DIF_P +V 83,179,CONT_DIF_P +V 89,179,CONT_DIF_P +V 83,183,CONT_DIF_P +V 89,183,CONT_DIF_P +V 83,187,CONT_DIF_P +V 83,191,CONT_DIF_P +V 89,191,CONT_DIF_P +V 89,195,CONT_DIF_P +V 83,163,CONT_DIF_P +V 83,159,CONT_DIF_P +V 89,159,CONT_DIF_P +V 83,175,CONT_DIF_P +V 83,171,CONT_DIF_P +V 83,167,CONT_DIF_P +V 89,167,CONT_DIF_P +V 89,171,CONT_DIF_P +V 95,155,CONT_DIF_P +V 101,155,CONT_DIF_P +V 101,195,CONT_DIF_P +V 95,183,CONT_DIF_P +V 95,187,CONT_DIF_P +V 95,191,CONT_DIF_P +V 101,191,CONT_DIF_P +V 95,195,CONT_DIF_P +V 95,175,CONT_DIF_P +V 95,171,CONT_DIF_P +V 95,179,CONT_DIF_P +V 101,179,CONT_DIF_P +V 101,183,CONT_DIF_P +V 95,163,CONT_DIF_P +V 95,159,CONT_DIF_P +V 101,159,CONT_DIF_P +V 101,171,CONT_DIF_P +V 101,167,CONT_DIF_P +V 95,167,CONT_DIF_P +V 89,151,CONT_VIA +V 101,151,CONT_VIA +V 89,175,CONT_VIA +V 89,187,CONT_VIA +V 89,163,CONT_VIA +V 101,187,CONT_VIA +V 101,175,CONT_VIA +V 101,163,CONT_VIA +V 83,199,CONT_DIF_P +V 95,199,CONT_DIF_P +V 89,199,CONT_VIA +V 101,199,CONT_VIA +V 83,203,CONT_DIF_P +V 95,203,CONT_DIF_P +V 89,203,CONT_DIF_P +V 101,203,CONT_DIF_P +V 89,207,CONT_DIF_P +V 101,207,CONT_DIF_P +V 95,207,CONT_DIF_P +V 83,207,CONT_DIF_P +V 83,211,CONT_DIF_P +V 95,211,CONT_DIF_P +V 101,211,CONT_VIA +V 89,211,CONT_VIA +V 83,215,CONT_DIF_P +V 89,215,CONT_DIF_P +V 95,215,CONT_DIF_P +V 101,215,CONT_DIF_P +V 89,243,CONT_BODY_P +V 101,243,CONT_BODY_P +V 100,238,CONT_POLY +V 89,238,CONT_VIA +V 100,232,CONT_VIA +V 101,225,CONT_BODY_N +V 89,225,CONT_BODY_N +V 101,219,CONT_DIF_P +V 95,219,CONT_DIF_P +V 89,219,CONT_DIF_P +V 83,219,CONT_DIF_P +EOF diff --git a/alliance/src/cells/src/padlib/palvdde_sp.ap b/alliance/src/cells/src/padlib/palvdde_sp.ap new file mode 100644 index 00000000..f1e2af8c --- /dev/null +++ b/alliance/src/cells/src/padlib/palvdde_sp.ap @@ -0,0 +1,140 @@ +V ALLIANCE : 3 +H palvdde_sp,P,11/ 9/95 +A 0,-7,172,356 +C 172,168,120,vdde,1,EAST,ALU2 +C 0,168,120,vdde,0,WEST,ALU2 +C 172,84,40,vddi,1,EAST,ALU2 +C 0,84,40,vddi,0,WEST,ALU2 +C 172,40,40,vssi,1,EAST,ALU2 +C 0,40,40,vssi,0,WEST,ALU2 +C 172,6,12,ck,1,EAST,ALU2 +C 0,6,12,ck,0,WEST,ALU2 +C 172,296,120,vsse,1,EAST,ALU2 +C 0,296,120,vsse,0,WEST,ALU2 +S 0,40,172,40,40,vssi,RIGHT,ALU2 +S 0,84,172,84,40,vddi,RIGHT,ALU2 +S 0,168,172,168,120,vdde,RIGHT,ALU2 +S 0,6,172,6,12,ck,RIGHT,ALU2 +S 0,296,172,296,120,vsse,RIGHT,ALU2 +S 86,108,86,356,100,*,UP,ALU1 +V 42,110,CONT_VIA +V 62,110,CONT_VIA +V 82,110,CONT_VIA +V 102,110,CONT_VIA +V 122,110,CONT_VIA +V 132,115,CONT_VIA +V 132,125,CONT_VIA +V 132,145,CONT_VIA +V 132,175,CONT_VIA +V 132,185,CONT_VIA +V 132,195,CONT_VIA +V 122,150,CONT_VIA +V 122,180,CONT_VIA +V 122,190,CONT_VIA +V 122,120,CONT_VIA +V 132,135,CONT_VIA +V 112,155,CONT_VIA +V 112,145,CONT_VIA +V 132,155,CONT_VIA +V 132,165,CONT_VIA +V 112,125,CONT_VIA +V 112,115,CONT_VIA +V 122,130,CONT_VIA +V 122,140,CONT_VIA +V 92,115,CONT_VIA +V 112,135,CONT_VIA +V 122,160,CONT_VIA +V 122,170,CONT_VIA +V 112,195,CONT_VIA +V 112,185,CONT_VIA +V 112,175,CONT_VIA +V 112,165,CONT_VIA +V 92,195,CONT_VIA +V 92,185,CONT_VIA +V 92,175,CONT_VIA +V 102,180,CONT_VIA +V 102,190,CONT_VIA +V 102,120,CONT_VIA +V 92,125,CONT_VIA +V 82,190,CONT_VIA +V 82,180,CONT_VIA +V 102,130,CONT_VIA +V 102,140,CONT_VIA +V 102,150,CONT_VIA +V 102,160,CONT_VIA +V 102,170,CONT_VIA +V 82,130,CONT_VIA +V 72,115,CONT_VIA +V 72,125,CONT_VIA +V 92,165,CONT_VIA +V 92,155,CONT_VIA +V 92,145,CONT_VIA +V 92,135,CONT_VIA +V 82,120,CONT_VIA +V 72,165,CONT_VIA +V 72,175,CONT_VIA +V 72,185,CONT_VIA +V 72,195,CONT_VIA +V 82,170,CONT_VIA +V 82,160,CONT_VIA +V 82,150,CONT_VIA +V 82,140,CONT_VIA +V 52,125,CONT_VIA +V 62,120,CONT_VIA +V 62,190,CONT_VIA +V 62,180,CONT_VIA +V 72,135,CONT_VIA +V 72,145,CONT_VIA +V 72,155,CONT_VIA +V 52,185,CONT_VIA +V 52,195,CONT_VIA +V 62,170,CONT_VIA +V 62,160,CONT_VIA +V 62,150,CONT_VIA +V 62,140,CONT_VIA +V 62,130,CONT_VIA +V 52,115,CONT_VIA +V 42,190,CONT_VIA +V 42,120,CONT_VIA +V 52,135,CONT_VIA +V 52,145,CONT_VIA +V 52,155,CONT_VIA +V 52,165,CONT_VIA +V 52,175,CONT_VIA +V 42,130,CONT_VIA +V 42,140,CONT_VIA +V 42,150,CONT_VIA +V 42,160,CONT_VIA +V 42,170,CONT_VIA +V 42,180,CONT_VIA +V 122,200,CONT_VIA +V 132,205,CONT_VIA +V 132,215,CONT_VIA +V 132,225,CONT_VIA +V 112,225,CONT_VIA +V 112,215,CONT_VIA +V 92,205,CONT_VIA +V 82,200,CONT_VIA +V 102,200,CONT_VIA +V 112,205,CONT_VIA +V 122,210,CONT_VIA +V 122,220,CONT_VIA +V 102,220,CONT_VIA +V 82,220,CONT_VIA +V 82,210,CONT_VIA +V 72,205,CONT_VIA +V 72,215,CONT_VIA +V 72,225,CONT_VIA +V 92,225,CONT_VIA +V 92,215,CONT_VIA +V 62,220,CONT_VIA +V 62,210,CONT_VIA +V 52,205,CONT_VIA +V 52,215,CONT_VIA +V 52,225,CONT_VIA +V 62,200,CONT_VIA +V 102,210,CONT_VIA +V 42,200,CONT_VIA +V 42,210,CONT_VIA +V 42,220,CONT_VIA +EOF diff --git a/alliance/src/cells/src/padlib/palvddeck_sp.ap b/alliance/src/cells/src/padlib/palvddeck_sp.ap new file mode 100644 index 00000000..354c10e5 --- /dev/null +++ b/alliance/src/cells/src/padlib/palvddeck_sp.ap @@ -0,0 +1,290 @@ +V ALLIANCE : 6 +H palvddeck_sp,P,13/10/2000,100 +A 0,-700,17200,35600 +C 0,29600,12000,vsse,0,WEST,ALU2 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 0,600,1200,ck,0,WEST,ALU2 +C 17200,600,1200,ck,1,EAST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 0,8400,4000,vddi,0,WEST,ALU2 +C 17200,8400,4000,vddi,1,EAST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,16800,12000,vdde,1,EAST,ALU2 +C 6700,-700,200,cko,1,SOUTH,ALU2 +C 6700,-700,200,cko,0,SOUTH,ALU1 +C 7900,-700,200,cko,3,SOUTH,ALU2 +C 7900,-700,200,cko,2,SOUTH,ALU1 +C 9100,-700,200,cko,5,SOUTH,ALU2 +C 9100,-700,200,cko,4,SOUTH,ALU1 +S 8600,10900,8600,35600,10000,*,UP,ALU1 +S 8500,2100,8500,4900,200,*,UP,ALU1 +S 7300,2200,7300,4500,200,*,UP,ALU1 +S 4300,2100,6100,2100,300,*,RIGHT,ALU1 +S 4300,2000,4300,5100,200,*,UP,ALU1 +S 6100,10400,9700,10400,200,*,RIGHT,ALU1 +S 6700,6600,9100,6600,200,*,RIGHT,ALU1 +S 6200,6100,7200,6100,200,*,RIGHT,ALU1 +S 6200,6100,6200,6900,200,*,UP,ALU1 +S 4300,6100,4300,10400,300,*,UP,ALU1 +S 6200,5000,8500,5000,200,*,RIGHT,ALU1 +S 3800,100,3800,5600,200,*,UP,ALU1 +S 3800,5600,5200,5600,200,*,RIGHT,ALU1 +S 6200,4400,6200,5000,200,*,UP,ALU1 +S 9700,6000,9700,10400,200,*,UP,ALU1 +S 4200,6100,5000,6100,200,*,RIGHT,ALU1 +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 5700,4900,5700,6200,200,*,UP,ALU1 +S 5500,2800,5500,5100,200,*,UP,ALU1 +S 4100,8500,9900,8500,5200,*,RIGHT,NWELL +S 5800,5600,7600,5600,200,*,RIGHT,ALU1 +S 6100,6800,6100,10400,200,*,UP,ALU1 +S 7300,7100,7300,10400,200,*,UP,ALU1 +S 8500,7100,8500,10400,200,*,UP,ALU1 +S 6000,10400,9800,10400,300,*,RIGHT,NTIE +S 6100,10300,6100,11100,300,*,UP,NTIE +S 9700,6100,9700,10500,300,*,UP,NTIE +S 7900,6700,7900,9600,200,*,UP,ALU1 +S 6700,6700,6700,9600,200,*,UP,ALU1 +S 9100,6600,9100,9900,300,*,UP,PDIF +S 8500,6600,8500,9900,200,*,UP,PDIF +S 7900,6600,7900,9900,200,*,UP,PDIF +S 7300,6600,7300,9900,200,*,UP,PDIF +S 6100,6600,6100,9900,300,*,UP,PDIF +S 6700,6600,6700,9900,200,*,UP,PDIF +S 6400,6400,6400,10100,100,*,UP,PTRANS +S 7000,6400,7000,10100,100,*,UP,PTRANS +S 7600,6400,7600,10100,100,*,UP,PTRANS +S 8200,6400,8200,10100,100,*,UP,PTRANS +S 8800,6400,8800,10100,100,*,UP,PTRANS +S 4200,6100,5000,6100,300,*,RIGHT,NTIE +S 4300,6000,4300,11000,300,*,UP,NTIE +S 4900,6600,4900,10400,300,*,UP,PDIF +S 4900,6800,4900,10400,200,*,UP,ALU1 +S 6100,2000,6100,4500,200,*,UP,ALU1 +S 9700,2000,9700,5100,300,*,UP,PTIE +S 9700,2000,9700,5100,300,*,UP,ALU1 +S 4200,5000,5000,5000,300,*,RIGHT,PTIE +S 4200,2100,9800,2100,300,*,RIGHT,PTIE +S 9700,2000,9700,5100,300,*,UP,PTIE +S 4300,2000,4300,5100,300,*,UP,PTIE +S 8500,2600,8500,4500,200,*,UP,NDIF +S 7300,2600,7300,4400,200,*,UP,NDIF +S 4900,2600,4900,4400,300,*,UP,NDIF +S 6100,2600,6100,4400,300,*,UP,NDIF +S 7900,2600,7900,4400,300,*,UP,NDIF +S 5500,2600,5500,4500,300,*,UP,NDIF +S 9100,2600,9100,4500,300,*,UP,NDIF +S 5500,6600,5500,10500,300,*,UP,PDIF +S 6700,2600,6700,4500,200,*,UP,NDIF +S 4900,2000,4900,5100,200,*,UP,ALU1 +S 7600,2400,7600,4700,100,*,UP,NTRANS +S 8200,2400,8200,4700,100,*,UP,NTRANS +S 8800,2400,8800,4700,100,*,UP,NTRANS +S 5200,2400,5200,4700,100,*,UP,NTRANS +S 6400,2400,6400,4700,100,*,UP,NTRANS +S 7000,2400,7000,4700,100,*,UP,NTRANS +S 5200,6400,5200,10700,100,*,UP,PTRANS +S 5400,6100,7200,6100,300,*,RIGHT,NTIE +S 8000,6100,9800,6100,300,*,RIGHT,NTIE +S 8000,5000,9800,5000,300,*,RIGHT,PTIE +S 5400,5000,7200,5000,300,*,RIGHT,PTIE +S 6400,6400,8800,6400,100,*,RIGHT,POLY +S 5200,4700,5200,6400,100,*,UP,POLY +S 6400,4700,8800,4700,100,*,RIGHT,POLY +S 7600,4700,7600,6400,500,*,UP,POLY +S 5500,6100,5500,10400,200,*,UP,ALU1 +S 0,600,17200,600,1200,ck,RIGHT,ALU2 +S 6700,-700,6700,4400,200,*,UP,ALU1 +S 7900,-700,7900,4400,200,*,UP,ALU1 +S 9100,-700,9100,9600,200,*,UP,ALU1 +S 6700,1600,9100,1600,200,*,RIGHT,ALU1 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2 +B 8600,16800,10000,12000,CONT_VIA,* +B 3800,5600,200,200,CONT_TURN1,* +V 4300,10300,CONT_BODY_N,* +V 4300,9700,CONT_VIA,* +V 4300,9300,CONT_BODY_N,* +V 4300,8900,CONT_BODY_N,* +V 4300,8500,CONT_VIA,* +V 4300,8100,CONT_BODY_N,* +V 4300,7700,CONT_BODY_N,* +V 5200,5600,CONT_POLY,* +V 4300,7300,CONT_BODY_N,* +V 4300,6900,CONT_VIA,* +V 4300,6500,CONT_BODY_N,* +V 4300,6100,CONT_BODY_N,* +V 4900,6100,CONT_BODY_N,* +V 6700,6100,CONT_BODY_N,* +V 6200,6100,CONT_BODY_N,* +V 7100,6100,CONT_BODY_N,* +V 7600,5600,CONT_POLY,* +V 9700,9600,CONT_VIA,* +V 9700,7000,CONT_VIA,* +V 9700,6500,CONT_BODY_N,* +V 9700,6100,CONT_BODY_N,* +V 9700,7600,CONT_BODY_N,* +V 9700,8000,CONT_BODY_N,* +V 9700,8400,CONT_BODY_N,* +V 9700,8800,CONT_BODY_N,* +V 9700,9200,CONT_BODY_N,* +V 9700,10000,CONT_BODY_N,* +V 9700,10400,CONT_BODY_N,* +V 9300,10400,CONT_BODY_N,* +V 8900,10400,CONT_BODY_N,* +V 8500,10400,CONT_BODY_N,* +V 8100,10400,CONT_BODY_N,* +V 7700,10400,CONT_BODY_N,* +V 7300,10400,CONT_BODY_N,* +V 6900,10400,CONT_BODY_N,* +V 6500,10400,CONT_BODY_N,* +V 6100,10400,CONT_BODY_N,* +V 8500,7100,CONT_DIF_P,* +V 8500,9600,CONT_DIF_P,* +V 8500,9200,CONT_DIF_P,* +V 8500,8800,CONT_DIF_P,* +V 8500,8000,CONT_DIF_P,* +V 8500,7600,CONT_DIF_P,* +V 8500,10000,CONT_VIA,* +V 8500,8400,CONT_VIA,* +V 7300,7100,CONT_DIF_P,* +V 7300,7600,CONT_DIF_P,* +V 7300,8000,CONT_DIF_P,* +V 7300,8800,CONT_DIF_P,* +V 7300,9200,CONT_DIF_P,* +V 7300,9600,CONT_DIF_P,* +V 7300,8400,CONT_VIA,* +V 7300,10000,CONT_VIA,* +V 4900,6800,CONT_DIF_P,* +V 4900,10400,CONT_DIF_P,* +V 4900,9600,CONT_DIF_P,* +V 4900,9200,CONT_DIF_P,* +V 4900,8800,CONT_DIF_P,* +V 4900,8000,CONT_DIF_P,* +V 4900,7600,CONT_DIF_P,* +V 4900,7200,CONT_VIA,* +V 4900,10000,CONT_VIA,* +V 4900,8400,CONT_VIA,* +V 6100,7200,CONT_VIA,* +V 6100,8400,CONT_VIA,* +V 6100,10000,CONT_VIA,* +V 6100,6800,CONT_DIF_P,* +V 6100,7600,CONT_DIF_P,* +V 6100,8000,CONT_DIF_P,* +V 6100,8800,CONT_DIF_P,* +V 6100,9200,CONT_DIF_P,* +V 6100,9600,CONT_DIF_P,* +V 6200,5000,CONT_BODY_P,* +V 6600,5000,CONT_VIA,* +V 8100,5000,CONT_BODY_P,* +V 7100,5000,CONT_BODY_P,* +V 9700,2500,CONT_BODY_P,* +V 9700,3300,CONT_BODY_P,* +V 9700,3700,CONT_BODY_P,* +V 9700,4100,CONT_BODY_P,* +V 9700,5000,CONT_BODY_P,* +V 9700,2100,CONT_BODY_P,* +V 9700,4500,CONT_VIA,* +V 9700,2900,CONT_VIA,* +V 4300,5000,CONT_BODY_P,* +V 4300,4500,CONT_VIA,* +V 4300,4100,CONT_BODY_P,* +V 4300,3700,CONT_BODY_P,* +V 4300,3300,CONT_BODY_P,* +V 4300,2900,CONT_VIA,* +V 4300,2500,CONT_BODY_P,* +V 4300,2100,CONT_BODY_P,* +V 5300,2100,CONT_BODY_P,* +V 5700,2100,CONT_BODY_P,* +V 4900,5000,CONT_BODY_P,* +V 8500,5000,CONT_BODY_P,* +V 4900,2100,CONT_BODY_P,* +V 6100,2100,CONT_BODY_P,* +V 7300,2100,CONT_BODY_P,* +V 8500,2100,CONT_BODY_P,* +V 8500,2400,CONT_VIA,* +V 7300,2400,CONT_VIA,* +V 6100,2400,CONT_VIA,* +V 4900,2400,CONT_VIA,* +V 8500,2800,CONT_DIF_N,* +V 7300,2800,CONT_DIF_N,* +V 6100,2800,CONT_DIF_N,* +V 4900,2800,CONT_DIF_N,* +V 4900,3200,CONT_DIF_N,* +V 6100,3200,CONT_DIF_N,* +V 7300,3200,CONT_DIF_N,* +V 8500,3200,CONT_DIF_N,* +V 8500,3600,CONT_DIF_N,* +V 7300,3600,CONT_DIF_N,* +V 6100,3600,CONT_DIF_N,* +V 4900,3600,CONT_DIF_N,* +V 4900,4400,CONT_DIF_N,* +V 4900,4000,CONT_VIA,* +V 8500,4000,CONT_VIA,* +V 7300,4000,CONT_VIA,* +V 6100,4000,CONT_VIA,* +V 8500,4400,CONT_DIF_N,* +V 6100,4400,CONT_DIF_N,* +V 7300,4400,CONT_DIF_N,* +V 9100,3600,CONT_DIF_N,* +V 9100,4000,CONT_DIF_N,* +V 9100,4400,CONT_DIF_N,* +V 9100,2800,CONT_DIF_N,* +V 7900,3600,CONT_DIF_N,* +V 7900,3200,CONT_DIF_N,* +V 7900,4400,CONT_DIF_N,* +V 7900,4000,CONT_DIF_N,* +V 6700,4000,CONT_DIF_N,* +V 6700,4400,CONT_DIF_N,* +V 6700,2800,CONT_DIF_N,* +V 6700,3200,CONT_DIF_N,* +V 6700,3600,CONT_DIF_N,* +V 9100,3200,CONT_DIF_N,* +V 7900,2800,CONT_DIF_N,* +V 5500,4000,CONT_DIF_N,* +V 5500,4400,CONT_DIF_N,* +V 5500,2800,CONT_DIF_N,* +V 5500,3200,CONT_DIF_N,* +V 5500,3600,CONT_DIF_N,* +V 9100,9200,CONT_DIF_P,* +V 9100,9600,CONT_DIF_P,* +V 9100,6800,CONT_DIF_P,* +V 9100,7200,CONT_DIF_P,* +V 9100,7600,CONT_DIF_P,* +V 9100,8000,CONT_DIF_P,* +V 7900,8800,CONT_DIF_P,* +V 7900,8400,CONT_DIF_P,* +V 9100,8400,CONT_DIF_P,* +V 9100,8800,CONT_DIF_P,* +V 7900,7200,CONT_DIF_P,* +V 7900,6800,CONT_DIF_P,* +V 7900,9600,CONT_DIF_P,* +V 7900,9200,CONT_DIF_P,* +V 6700,6800,CONT_DIF_P,* +V 6700,7200,CONT_DIF_P,* +V 6700,7600,CONT_DIF_P,* +V 6700,8000,CONT_DIF_P,* +V 6700,8400,CONT_DIF_P,* +V 6700,8800,CONT_DIF_P,* +V 7900,8000,CONT_DIF_P,* +V 7900,7600,CONT_DIF_P,* +V 6700,9200,CONT_DIF_P,* +V 6700,9600,CONT_DIF_P,* +V 5500,10000,CONT_DIF_P,* +V 5500,10400,CONT_DIF_P,* +V 5500,6800,CONT_DIF_P,* +V 5500,7200,CONT_DIF_P,* +V 5500,7600,CONT_DIF_P,* +V 5500,8000,CONT_DIF_P,* +V 5500,8400,CONT_DIF_P,* +V 5500,8800,CONT_DIF_P,* +V 5500,9200,CONT_DIF_P,* +V 5500,9600,CONT_DIF_P,* +V 3800,200,CONT_VIA,* +V 3800,1000,CONT_VIA,* +V 6700,-700,CONT_VIA,* +V 7900,-700,CONT_VIA,* +V 9100,-700,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/padlib/palvddi_sp.ap b/alliance/src/cells/src/padlib/palvddi_sp.ap new file mode 100644 index 00000000..c488a147 --- /dev/null +++ b/alliance/src/cells/src/padlib/palvddi_sp.ap @@ -0,0 +1,44 @@ +V ALLIANCE : 6 +H palvddi_sp,P,13/10/2000,100 +A 0,-700,17200,35600 +C 8600,-700,10000,vddi,0,SOUTH,ALU1 +C 8600,-700,10000,vddi,2,SOUTH,ALU2 +C 17200,16800,12000,vdde,1,EAST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,8400,4000,vddi,4,EAST,ALU2 +C 0,8400,4000,vddi,3,WEST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 17200,600,1200,ck,1,EAST,ALU2 +C 0,600,1200,ck,0,WEST,ALU2 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 0,29600,12000,vsse,0,WEST,ALU2 +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +S 0,8400,17100,8400,4000,vddi,RIGHT,ALU2 +S 0,600,17200,600,1200,ck,RIGHT,ALU2 +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 8600,-700,8600,35600,10000,*,UP,ALU1 +V 5700,-400,CONT_VIA,* +V 5200,-400,CONT_VIA,* +V 4700,-400,CONT_VIA,* +V 4200,-400,CONT_VIA,* +V 3700,-400,CONT_VIA,* +V 9700,-400,CONT_VIA,* +V 10200,-400,CONT_VIA,* +V 7700,-400,CONT_VIA,* +V 8200,-400,CONT_VIA,* +V 8700,-400,CONT_VIA,* +V 9200,-400,CONT_VIA,* +V 6700,-400,CONT_VIA,* +V 7200,-400,CONT_VIA,* +V 6200,-400,CONT_VIA,* +V 10700,-400,CONT_VIA,* +V 11200,-400,CONT_VIA,* +V 11700,-400,CONT_VIA,* +V 12200,-400,CONT_VIA,* +V 13200,-400,CONT_VIA,* +V 12700,-400,CONT_VIA,* +B 8600,-500,10000,400,CONT_TURN2,* +B 8600,8400,10000,4000,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/padlib/palvddick_sp.ap b/alliance/src/cells/src/padlib/palvddick_sp.ap new file mode 100644 index 00000000..dba9f897 --- /dev/null +++ b/alliance/src/cells/src/padlib/palvddick_sp.ap @@ -0,0 +1,411 @@ +V ALLIANCE : 6 +H palvddick_sp,P,13/10/2000,100 +A 0,-700,17200,35600 +C 8600,-700,10000,vddi,0,SOUTH,ALU1 +C 17200,600,1200,ck,1,EAST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 17200,8400,4000,vddi,4,EAST,ALU2 +C 0,600,1200,ck,0,WEST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 0,8400,4000,vddi,3,WEST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,16800,12000,vdde,1,EAST,ALU2 +C 8600,-700,10000,vddi,1,SOUTH,ALU2 +C 15500,-700,200,cko,3,SOUTH,ALU2 +C 15500,-700,200,cko,2,SOUTH,ALU1 +C 1700,-700,200,cko,1,SOUTH,ALU2 +C 1700,-700,200,cko,0,SOUTH,ALU1 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 0,29600,12000,vsse,0,WEST,ALU2 +S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2 +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +S 15500,-700,15500,1500,200,*,UP,ALU1 +S 0,600,17200,600,1200,ck,RIGHT,ALU2 +S 1700,-700,1700,1600,200,*,DOWN,ALU1 +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 8600,-700,8600,35600,10000,*,UP,ALU1 +S 15200,5200,15800,5200,100,*,RIGHT,POLY +S 14900,7100,15500,7100,100,*,RIGHT,POLY +S 13600,5700,14100,5700,300,*,RIGHT,PTIE +S 14300,5200,14300,7100,100,*,DOWN,POLY +S 14300,5200,14600,5200,100,*,RIGHT,POLY +S 14200,2100,16800,2100,300,*,LEFT,PTIE +S 14300,2100,14300,3400,300,*,UP,PTIE +S 13300,6800,14100,6800,300,*,RIGHT,NTIE +S 14400,300,14400,3800,200,*,DOWN,ALU1 +S 13600,3300,14300,3300,300,*,LEFT,PTIE +S 14300,4400,14300,6300,200,*,DOWN,ALU1 +S 14600,3700,14600,3900,100,*,DOWN,POLY +S 13200,12700,16600,12700,400,*,RIGHT,NWELL +S 13200,9700,16600,9700,6200,*,RIGHT,NWELL +S 14300,7100,14300,9400,100,*,UP,PTRANS +S 14900,7100,14900,12400,100,*,UP,PTRANS +S 15500,7100,15500,12400,100,*,UP,PTRANS +S 13400,6700,13400,9800,300,*,UP,NTIE +S 13300,9700,14100,9700,300,*,RIGHT,NTIE +S 15200,7300,15200,12200,200,*,DOWN,PDIF +S 15800,7300,15800,12200,300,*,DOWN,PDIF +S 14600,7300,14600,12200,300,*,DOWN,PDIF +S 14000,7300,14000,9200,300,*,DOWN,PDIF +S 14000,9600,14000,12800,300,*,UP,NTIE +S 14000,12700,16500,12700,300,*,RIGHT,NTIE +S 16400,6700,16400,12800,300,*,UP,NTIE +S 14000,6300,14000,9100,200,*,DOWN,ALU1 +S 15200,6300,15200,11900,200,*,DOWN,ALU1 +S 16700,2100,16700,5800,300,*,DOWN,PTIE +S 15800,2400,15800,5200,100,*,DOWN,NTRANS +S 14600,3900,14600,5200,100,*,DOWN,NTRANS +S 15200,2400,15200,5200,100,*,DOWN,NTRANS +S 16100,2600,16100,5000,300,*,DOWN,NDIF +S 14300,4100,14300,5000,300,*,DOWN,NDIF +S 14900,2600,14900,5000,300,*,DOWN,NDIF +S 15500,2600,15500,5000,300,*,DOWN,NDIF +S 13700,3400,13700,5800,300,*,UP,PTIE +S 14900,2100,14900,5800,200,*,DOWN,ALU1 +S 15500,1500,15500,6300,200,*,DOWN,ALU1 +S 15400,5200,15400,7100,200,*,UP,POLY +S 14700,6300,15300,6300,300,*,LEFT,POLY +S 15700,5700,16700,5700,300,*,RIGHT,PTIE +S 14500,5700,15100,5700,300,*,RIGHT,PTIE +S 15700,6800,16400,6800,300,*,RIGHT,NTIE +S 14500,6800,15100,6800,300,*,RIGHT,NTIE +S 1400,5200,2000,5200,100,*,RIGHT,POLY +S 1700,7100,2300,7100,100,*,RIGHT,POLY +S 3100,5700,3600,5700,300,*,RIGHT,PTIE +S 2900,5200,2900,7100,100,*,UP,POLY +S 2600,5200,2900,5200,100,*,RIGHT,POLY +S 400,2100,3000,2100,300,*,LEFT,PTIE +S 2900,2100,2900,3400,300,*,DOWN,PTIE +S 3100,6800,3900,6800,300,*,RIGHT,NTIE +S 2800,300,2800,3800,200,*,UP,ALU1 +S 2900,3300,3600,3300,300,*,LEFT,PTIE +S 2900,4400,2900,6300,200,*,UP,ALU1 +S 2600,3700,2600,3900,100,*,UP,POLY +S 600,12700,4000,12700,400,*,RIGHT,NWELL +S 600,9700,4000,9700,6200,*,RIGHT,NWELL +S 2900,7100,2900,9400,100,*,DOWN,PTRANS +S 2300,7100,2300,12400,100,*,DOWN,PTRANS +S 1700,7100,1700,12400,100,*,DOWN,PTRANS +S 3800,6700,3800,9800,300,*,DOWN,NTIE +S 3100,9700,3900,9700,300,*,RIGHT,NTIE +S 2000,7300,2000,12200,200,*,UP,PDIF +S 1400,7300,1400,12200,300,*,UP,PDIF +S 2600,7300,2600,12200,300,*,UP,PDIF +S 3200,7300,3200,9200,300,*,UP,PDIF +S 3200,9600,3200,12800,300,*,DOWN,NTIE +S 700,12700,3200,12700,300,*,RIGHT,NTIE +S 800,6700,800,12800,300,*,DOWN,NTIE +S 3200,6300,3200,9100,200,*,UP,ALU1 +S 2000,6300,2000,11900,200,*,UP,ALU1 +S 500,2100,500,5800,300,*,UP,PTIE +S 1400,2400,1400,5200,100,*,UP,NTRANS +S 2600,3900,2600,5200,100,*,UP,NTRANS +S 2000,2400,2000,5200,100,*,UP,NTRANS +S 1100,2600,1100,5000,300,*,UP,NDIF +S 2900,4100,2900,5000,300,*,UP,NDIF +S 2300,2600,2300,5000,300,*,UP,NDIF +S 1700,2600,1700,5000,300,*,UP,NDIF +S 3500,3400,3500,5800,300,*,DOWN,PTIE +S 2300,2100,2300,5800,200,*,UP,ALU1 +S 1700,1500,1700,6300,200,*,UP,ALU1 +S 1800,5200,1800,7100,200,*,DOWN,POLY +S 1900,6300,2500,6300,300,*,LEFT,POLY +S 500,5700,1500,5700,300,*,RIGHT,PTIE +S 2100,5700,2700,5700,300,*,RIGHT,PTIE +S 800,6800,1500,6800,300,*,RIGHT,NTIE +S 2100,6800,2700,6800,300,*,RIGHT,NTIE +S 1700,1600,15700,1600,200,*,RIGHT,ALU2 +S 3200,9600,3200,12800,200,*,UP,ALU1 +S 14000,9600,14000,12800,200,*,DOWN,ALU1 +S 14000,12600,16500,12600,500,*,LEFT,ALU1 +S 700,12600,3200,12600,500,*,LEFT,ALU1 +S 2500,6300,3200,6300,200,*,RIGHT,ALU1 +S 14000,6300,14700,6300,200,*,RIGHT,ALU1 +S 15200,6300,15500,6300,200,*,RIGHT,ALU1 +S 1700,6300,2000,6300,200,*,RIGHT,ALU1 +S 2600,6800,2600,12800,200,*,UP,ALU1 +S 800,2100,800,5800,900,*,UP,ALU1 +S 400,2100,1200,2100,200,*,LEFT,ALU1 +S 14600,6800,14600,12800,200,*,DOWN,ALU1 +S 15800,6800,15800,12800,200,*,DOWN,ALU1 +S 16200,6800,16200,12800,700,*,UP,ALU1 +S 15800,6800,16500,6800,200,*,LEFT,ALU1 +S 1000,6800,1000,12800,700,*,DOWN,ALU1 +S 1400,6800,1400,12800,200,*,UP,ALU1 +S 700,6800,1400,6800,200,*,LEFT,ALU1 +S 16400,2100,16400,5800,900,*,DOWN,ALU1 +S 16000,2100,16800,2100,200,*,RIGHT,ALU1 +S 1500,1600,2100,1600,200,*,LEFT,ALU1 +S 15100,1600,15700,1600,200,*,LEFT,ALU1 +V 5700,-400,CONT_VIA,* +V 5200,-400,CONT_VIA,* +V 4700,-400,CONT_VIA,* +V 4200,-400,CONT_VIA,* +V 3700,-400,CONT_VIA,* +V 9700,-400,CONT_VIA,* +V 10200,-400,CONT_VIA,* +V 7700,-400,CONT_VIA,* +V 8200,-400,CONT_VIA,* +V 8700,-400,CONT_VIA,* +V 9200,-400,CONT_VIA,* +V 6700,-400,CONT_VIA,* +V 7200,-400,CONT_VIA,* +V 6200,-400,CONT_VIA,* +V 10700,-400,CONT_VIA,* +V 11200,-400,CONT_VIA,* +V 11700,-400,CONT_VIA,* +V 12200,-400,CONT_VIA,* +V 13200,-400,CONT_VIA,* +V 12700,-400,CONT_VIA,* +B 8600,-500,10000,400,CONT_TURN2,* +V 1500,1600,CONT_VIA,* +V 15700,1600,CONT_VIA,* +V 15500,-700,CONT_VIA,* +V 1700,-700,CONT_VIA,* +V 16400,9900,CONT_VIA,* +V 16400,10300,CONT_BODY_N,* +V 14700,6300,CONT_POLY,* +V 16700,5700,CONT_BODY_P,* +V 16700,5300,CONT_VIA,* +V 16700,4900,CONT_BODY_P,* +V 16700,4500,CONT_BODY_P,* +V 16700,4100,CONT_BODY_P,* +V 16700,3700,CONT_VIA,* +V 16700,3300,CONT_BODY_P,* +V 16700,2900,CONT_BODY_P,* +V 16700,2500,CONT_BODY_P,* +V 16700,2100,CONT_BODY_P,* +V 14900,2100,CONT_BODY_P,* +V 16100,2100,CONT_BODY_P,* +V 14900,2500,CONT_VIA,* +V 16100,2500,CONT_VIA,* +V 16100,5300,CONT_VIA,* +V 14900,5300,CONT_VIA,* +V 14900,5700,CONT_BODY_P,* +V 16100,5700,CONT_BODY_P,* +V 16400,9100,CONT_BODY_N,* +V 16400,9500,CONT_BODY_N,* +V 14000,12300,CONT_BODY_N,* +V 14000,11900,CONT_BODY_N,* +V 14000,11500,CONT_BODY_N,* +V 14000,11100,CONT_BODY_N,* +V 14000,10700,CONT_BODY_N,* +V 16400,10700,CONT_BODY_N,* +V 16400,11100,CONT_BODY_N,* +V 16400,11500,CONT_BODY_N,* +V 16400,11900,CONT_BODY_N,* +V 16400,12300,CONT_BODY_N,* +V 16400,12700,CONT_BODY_N,* +V 16000,12700,CONT_BODY_N,* +V 15600,12700,CONT_BODY_N,* +V 15200,12700,CONT_BODY_N,* +V 14800,12700,CONT_BODY_N,* +V 14400,12700,CONT_BODY_N,* +V 14000,12700,CONT_BODY_N,* +V 14000,9700,CONT_BODY_N,* +V 16400,8300,CONT_BODY_N,* +V 16400,7900,CONT_BODY_N,* +V 16400,7500,CONT_BODY_N,* +V 16400,7100,CONT_VIA,* +V 16400,8700,CONT_VIA,* +V 14300,4400,CONT_DIF_N,* +V 14400,3800,CONT_POLY,* +V 16400,6800,CONT_BODY_N,* +V 14000,8300,CONT_DIF_P,* +V 14000,8700,CONT_DIF_P,* +V 14000,9100,CONT_DIF_P,* +V 14000,7500,CONT_DIF_P,* +V 14000,7900,CONT_DIF_P,* +V 14600,7100,CONT_VIA,* +V 14600,8700,CONT_VIA,* +V 14600,6800,CONT_BODY_N,* +V 14600,7900,CONT_DIF_P,* +V 14600,8300,CONT_DIF_P,* +V 14600,9100,CONT_DIF_P,* +V 14600,9500,CONT_DIF_P,* +V 14600,9900,CONT_DIF_P,* +V 14600,7500,CONT_DIF_P,* +V 15200,11900,CONT_DIF_P,* +V 15200,7500,CONT_DIF_P,* +V 15200,11500,CONT_DIF_P,* +V 15200,9500,CONT_DIF_P,* +V 15200,9100,CONT_DIF_P,* +V 15200,8700,CONT_DIF_P,* +V 15200,8300,CONT_DIF_P,* +V 15200,7900,CONT_DIF_P,* +V 15200,11100,CONT_DIF_P,* +V 15200,10700,CONT_DIF_P,* +V 15200,10300,CONT_DIF_P,* +V 15200,9900,CONT_DIF_P,* +V 15800,8700,CONT_VIA,* +V 15800,7100,CONT_VIA,* +V 15800,6800,CONT_BODY_N,* +V 15800,7500,CONT_DIF_P,* +V 15800,7900,CONT_DIF_P,* +V 15800,8300,CONT_DIF_P,* +V 15800,9100,CONT_DIF_P,* +V 15800,9500,CONT_DIF_P,* +V 15800,9900,CONT_DIF_P,* +V 16100,2900,CONT_DIF_N,* +V 16100,3300,CONT_DIF_N,* +V 16100,3700,CONT_DIF_N,* +V 16100,4100,CONT_DIF_N,* +V 16100,4500,CONT_DIF_N,* +V 16100,4900,CONT_DIF_N,* +V 14900,3200,CONT_DIF_N,* +V 14900,2800,CONT_DIF_N,* +V 15500,4800,CONT_DIF_N,* +V 15500,4400,CONT_DIF_N,* +V 15500,4000,CONT_DIF_N,* +V 15500,3600,CONT_DIF_N,* +V 15500,3200,CONT_DIF_N,* +V 15500,2800,CONT_DIF_N,* +V 14300,4900,CONT_DIF_N,* +V 14900,4800,CONT_DIF_N,* +V 14900,4400,CONT_DIF_N,* +V 14900,4000,CONT_DIF_N,* +V 14900,3600,CONT_DIF_N,* +V 14400,200,CONT_VIA,* +V 14400,1000,CONT_VIA,* +V 14000,10200,CONT_VIA,* +V 14600,10200,CONT_VIA,* +V 15800,10200,CONT_VIA,* +V 14600,11700,CONT_DIF_P,* +V 14600,10500,CONT_DIF_P,* +V 14600,10900,CONT_DIF_P,* +V 14600,11300,CONT_DIF_P,* +V 15800,10500,CONT_DIF_P,* +V 15800,10900,CONT_DIF_P,* +V 15800,11300,CONT_DIF_P,* +V 15800,11700,CONT_DIF_P,* +V 15800,12100,CONT_DIF_P,* +V 14600,12100,CONT_DIF_P,* +V 800,9900,CONT_VIA,* +V 800,10300,CONT_BODY_N,* +V 2500,6300,CONT_POLY,* +V 500,5700,CONT_BODY_P,* +V 500,5300,CONT_VIA,* +V 500,4900,CONT_BODY_P,* +V 500,4500,CONT_BODY_P,* +V 500,4100,CONT_BODY_P,* +V 500,3700,CONT_VIA,* +V 500,3300,CONT_BODY_P,* +V 500,2900,CONT_BODY_P,* +V 500,2500,CONT_BODY_P,* +V 500,2100,CONT_BODY_P,* +V 2300,2100,CONT_BODY_P,* +V 1100,2100,CONT_BODY_P,* +V 2300,2500,CONT_VIA,* +V 1100,2500,CONT_VIA,* +V 1100,5300,CONT_VIA,* +V 2300,5300,CONT_VIA,* +V 2300,5700,CONT_BODY_P,* +V 1100,5700,CONT_BODY_P,* +V 800,9100,CONT_BODY_N,* +V 800,9500,CONT_BODY_N,* +V 3200,12300,CONT_BODY_N,* +V 3200,11900,CONT_BODY_N,* +V 3200,11500,CONT_BODY_N,* +V 3200,11100,CONT_BODY_N,* +V 3200,10700,CONT_BODY_N,* +V 800,10700,CONT_BODY_N,* +V 800,11100,CONT_BODY_N,* +V 800,11500,CONT_BODY_N,* +V 800,11900,CONT_BODY_N,* +V 800,12300,CONT_BODY_N,* +V 800,12700,CONT_BODY_N,* +V 1200,12700,CONT_BODY_N,* +V 1600,12700,CONT_BODY_N,* +V 2000,12700,CONT_BODY_N,* +V 2400,12700,CONT_BODY_N,* +V 2800,12700,CONT_BODY_N,* +V 3200,12700,CONT_BODY_N,* +V 3200,9700,CONT_BODY_N,* +V 800,8300,CONT_BODY_N,* +V 800,7900,CONT_BODY_N,* +V 800,7500,CONT_BODY_N,* +V 800,7100,CONT_VIA,* +V 800,8700,CONT_VIA,* +V 2900,4400,CONT_DIF_N,* +V 2800,3800,CONT_POLY,* +V 800,6800,CONT_BODY_N,* +V 3200,8300,CONT_DIF_P,* +V 3200,8700,CONT_DIF_P,* +V 3200,9100,CONT_DIF_P,* +V 3200,7500,CONT_DIF_P,* +V 3200,7900,CONT_DIF_P,* +V 2600,7100,CONT_VIA,* +V 2600,8700,CONT_VIA,* +V 2600,6800,CONT_BODY_N,* +V 2600,7900,CONT_DIF_P,* +V 2600,8300,CONT_DIF_P,* +V 2600,9100,CONT_DIF_P,* +V 2600,9500,CONT_DIF_P,* +V 2600,9900,CONT_DIF_P,* +V 2600,7500,CONT_DIF_P,* +V 2000,11900,CONT_DIF_P,* +V 2000,7500,CONT_DIF_P,* +V 2000,11500,CONT_DIF_P,* +V 2000,9500,CONT_DIF_P,* +V 2000,9100,CONT_DIF_P,* +V 2000,8700,CONT_DIF_P,* +V 2000,8300,CONT_DIF_P,* +V 2000,7900,CONT_DIF_P,* +V 2000,11100,CONT_DIF_P,* +V 2000,10700,CONT_DIF_P,* +V 2000,10300,CONT_DIF_P,* +V 2000,9900,CONT_DIF_P,* +V 1400,8700,CONT_VIA,* +V 1400,7100,CONT_VIA,* +V 1400,6800,CONT_BODY_N,* +V 1400,7500,CONT_DIF_P,* +V 1400,7900,CONT_DIF_P,* +V 1400,8300,CONT_DIF_P,* +V 1400,9100,CONT_DIF_P,* +V 1400,9500,CONT_DIF_P,* +V 1400,9900,CONT_DIF_P,* +V 1100,2900,CONT_DIF_N,* +V 1100,3300,CONT_DIF_N,* +V 1100,3700,CONT_DIF_N,* +V 1100,4100,CONT_DIF_N,* +V 1100,4500,CONT_DIF_N,* +V 1100,4900,CONT_DIF_N,* +V 2300,3200,CONT_DIF_N,* +V 2300,2800,CONT_DIF_N,* +V 1700,4800,CONT_DIF_N,* +V 1700,4400,CONT_DIF_N,* +V 1700,4000,CONT_DIF_N,* +V 1700,3600,CONT_DIF_N,* +V 1700,3200,CONT_DIF_N,* +V 1700,2800,CONT_DIF_N,* +V 2900,4900,CONT_DIF_N,* +V 2300,4800,CONT_DIF_N,* +V 2300,4400,CONT_DIF_N,* +V 2300,4000,CONT_DIF_N,* +V 2300,3600,CONT_DIF_N,* +V 2800,200,CONT_VIA,* +V 2800,1000,CONT_VIA,* +V 3200,10200,CONT_VIA,* +V 2600,10200,CONT_VIA,* +V 1400,10200,CONT_VIA,* +V 2600,11700,CONT_DIF_P,* +V 2600,10500,CONT_DIF_P,* +V 2600,10900,CONT_DIF_P,* +V 2600,11300,CONT_DIF_P,* +V 1400,10500,CONT_DIF_P,* +V 1400,10900,CONT_DIF_P,* +V 1400,11300,CONT_DIF_P,* +V 1400,11700,CONT_DIF_P,* +V 1400,12100,CONT_DIF_P,* +V 2600,12100,CONT_DIF_P,* +B 8600,8400,10000,4000,CONT_VIA,* +B 3200,6300,200,200,CONT_TURN1,* +B 2000,6300,200,200,CONT_TURN1,* +B 1700,6300,200,200,CONT_TURN1,* +B 15500,6300,200,200,CONT_TURN1,* +B 15200,6300,200,200,CONT_TURN1,* +B 14000,6300,200,200,CONT_TURN1,* +V 2100,1600,CONT_VIA,* +V 15100,1600,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/padlib/palvsse_sp.ap b/alliance/src/cells/src/padlib/palvsse_sp.ap new file mode 100644 index 00000000..dbf5496e --- /dev/null +++ b/alliance/src/cells/src/padlib/palvsse_sp.ap @@ -0,0 +1,21 @@ +V ALLIANCE : 6 +H palvsse_sp,P,13/10/2000,100 +A 0,-700,17200,35600 +C 0,29600,12000,vsse,0,WEST,ALU2 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 0,600,1200,ck,0,WEST,ALU2 +C 17200,600,1200,ck,1,EAST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 0,8400,4000,vddi,0,WEST,ALU2 +C 17200,8400,4000,vddi,1,EAST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,16800,12000,vdde,1,EAST,ALU2 +S 8600,23600,8600,35600,10000,*,UP,ALU1 +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 0,600,17200,600,1200,ck,RIGHT,ALU2 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2 +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +B 8600,29600,10000,12000,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/padlib/palvsseck_sp.ap b/alliance/src/cells/src/padlib/palvsseck_sp.ap new file mode 100644 index 00000000..2b805b4f --- /dev/null +++ b/alliance/src/cells/src/padlib/palvsseck_sp.ap @@ -0,0 +1,290 @@ +V ALLIANCE : 6 +H palvsseck_sp,P,13/10/2000,100 +A 0,-700,17200,35600 +C 9100,-700,200,cko,4,SOUTH,ALU1 +C 9100,-700,200,cko,5,SOUTH,ALU2 +C 7900,-700,200,cko,2,SOUTH,ALU1 +C 7900,-700,200,cko,3,SOUTH,ALU2 +C 6700,-700,200,cko,0,SOUTH,ALU1 +C 6700,-700,200,cko,1,SOUTH,ALU2 +C 17200,16800,12000,vdde,1,EAST,ALU2 +C 0,16800,12000,vdde,0,WEST,ALU2 +C 17200,8400,4000,vddi,1,EAST,ALU2 +C 0,8400,4000,vddi,0,WEST,ALU2 +C 17200,4000,4000,vssi,1,EAST,ALU2 +C 0,4000,4000,vssi,0,WEST,ALU2 +C 17200,600,1200,ck,1,EAST,ALU2 +C 0,600,1200,ck,0,WEST,ALU2 +C 17200,29600,12000,vsse,1,EAST,ALU2 +C 0,29600,12000,vsse,0,WEST,ALU2 +S 8600,23700,8600,35600,10000,*,UP,ALU1 +S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2 +S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2 +S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2 +S 6700,1600,9100,1600,200,*,RIGHT,ALU1 +S 9100,-700,9100,9600,200,*,UP,ALU1 +S 7900,-700,7900,4400,200,*,UP,ALU1 +S 6700,-700,6700,4400,200,*,UP,ALU1 +S 0,600,17200,600,1200,ck,RIGHT,ALU2 +S 5500,6100,5500,10400,200,*,UP,ALU1 +S 7600,4700,7600,6400,500,*,UP,POLY +S 6400,4700,8800,4700,100,*,RIGHT,POLY +S 5200,4700,5200,6400,100,*,UP,POLY +S 6400,6400,8800,6400,100,*,RIGHT,POLY +S 5400,5000,7200,5000,300,*,RIGHT,PTIE +S 8000,5000,9800,5000,300,*,RIGHT,PTIE +S 8000,6100,9800,6100,300,*,RIGHT,NTIE +S 5400,6100,7200,6100,300,*,RIGHT,NTIE +S 5200,6400,5200,10700,100,*,UP,PTRANS +S 7000,2400,7000,4700,100,*,UP,NTRANS +S 6400,2400,6400,4700,100,*,UP,NTRANS +S 5200,2400,5200,4700,100,*,UP,NTRANS +S 8800,2400,8800,4700,100,*,UP,NTRANS +S 8200,2400,8200,4700,100,*,UP,NTRANS +S 7600,2400,7600,4700,100,*,UP,NTRANS +S 4900,2000,4900,5100,200,*,UP,ALU1 +S 6700,2600,6700,4500,200,*,UP,NDIF +S 5500,6600,5500,10500,300,*,UP,PDIF +S 9100,2600,9100,4500,300,*,UP,NDIF +S 5500,2600,5500,4500,300,*,UP,NDIF +S 7900,2600,7900,4400,300,*,UP,NDIF +S 6100,2600,6100,4400,300,*,UP,NDIF +S 4900,2600,4900,4400,300,*,UP,NDIF +S 7300,2600,7300,4400,200,*,UP,NDIF +S 8500,2600,8500,4500,200,*,UP,NDIF +S 4300,2000,4300,5100,300,*,UP,PTIE +S 9700,2000,9700,5100,300,*,UP,PTIE +S 4200,2100,9800,2100,300,*,RIGHT,PTIE +S 4200,5000,5000,5000,300,*,RIGHT,PTIE +S 9700,2000,9700,5100,300,*,UP,ALU1 +S 9700,2000,9700,5100,300,*,UP,PTIE +S 6100,2000,6100,4500,200,*,UP,ALU1 +S 4900,6800,4900,10400,200,*,UP,ALU1 +S 4900,6600,4900,10400,300,*,UP,PDIF +S 4300,6000,4300,11000,300,*,UP,NTIE +S 4200,6100,5000,6100,300,*,RIGHT,NTIE +S 8800,6400,8800,10100,100,*,UP,PTRANS +S 8200,6400,8200,10100,100,*,UP,PTRANS +S 7600,6400,7600,10100,100,*,UP,PTRANS +S 7000,6400,7000,10100,100,*,UP,PTRANS +S 6400,6400,6400,10100,100,*,UP,PTRANS +S 6700,6600,6700,9900,200,*,UP,PDIF +S 6100,6600,6100,9900,300,*,UP,PDIF +S 7300,6600,7300,9900,200,*,UP,PDIF +S 7900,6600,7900,9900,200,*,UP,PDIF +S 8500,6600,8500,9900,200,*,UP,PDIF +S 9100,6600,9100,9900,300,*,UP,PDIF +S 6700,6700,6700,9600,200,*,UP,ALU1 +S 7900,6700,7900,9600,200,*,UP,ALU1 +S 9700,6100,9700,10500,300,*,UP,NTIE +S 6100,10300,6100,11100,300,*,UP,NTIE +S 6000,10400,9800,10400,300,*,RIGHT,NTIE +S 8500,7100,8500,10400,200,*,UP,ALU1 +S 7300,7100,7300,10400,200,*,UP,ALU1 +S 6100,6800,6100,10400,200,*,UP,ALU1 +S 5800,5600,7600,5600,200,*,RIGHT,ALU1 +S 4100,8500,9900,8500,5200,*,RIGHT,NWELL +S 5500,2800,5500,5100,200,*,UP,ALU1 +S 5700,4900,5700,6200,200,*,UP,ALU1 +S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2 +S 4200,6100,5000,6100,200,*,RIGHT,ALU1 +S 9700,6000,9700,10400,200,*,UP,ALU1 +S 6200,4400,6200,5000,200,*,UP,ALU1 +S 3800,5600,5200,5600,200,*,RIGHT,ALU1 +S 3800,100,3800,5600,200,*,UP,ALU1 +S 6200,5000,8500,5000,200,*,RIGHT,ALU1 +S 4300,6100,4300,10400,300,*,UP,ALU1 +S 6200,6100,6200,6900,200,*,UP,ALU1 +S 6200,6100,7200,6100,200,*,RIGHT,ALU1 +S 6700,6600,9100,6600,200,*,RIGHT,ALU1 +S 6100,10400,9700,10400,200,*,RIGHT,ALU1 +S 4300,2000,4300,5100,200,*,UP,ALU1 +S 4300,2100,6100,2100,300,*,RIGHT,ALU1 +S 7300,2200,7300,4500,200,*,UP,ALU1 +S 8500,2100,8500,4900,200,*,UP,ALU1 +B 8600,29600,10000,12000,CONT_VIA,* +V 9100,-700,CONT_VIA,* +V 7900,-700,CONT_VIA,* +V 6700,-700,CONT_VIA,* +V 3800,1000,CONT_VIA,* +V 3800,200,CONT_VIA,* +V 5500,9600,CONT_DIF_P,* +V 5500,9200,CONT_DIF_P,* +V 5500,8800,CONT_DIF_P,* +V 5500,8400,CONT_DIF_P,* +V 5500,8000,CONT_DIF_P,* +V 5500,7600,CONT_DIF_P,* +V 5500,7200,CONT_DIF_P,* +V 5500,6800,CONT_DIF_P,* +V 5500,10400,CONT_DIF_P,* +V 5500,10000,CONT_DIF_P,* +V 6700,9600,CONT_DIF_P,* +V 6700,9200,CONT_DIF_P,* +V 7900,7600,CONT_DIF_P,* +V 7900,8000,CONT_DIF_P,* +V 6700,8800,CONT_DIF_P,* +V 6700,8400,CONT_DIF_P,* +V 6700,8000,CONT_DIF_P,* +V 6700,7600,CONT_DIF_P,* +V 6700,7200,CONT_DIF_P,* +V 6700,6800,CONT_DIF_P,* +V 7900,9200,CONT_DIF_P,* +V 7900,9600,CONT_DIF_P,* +V 7900,6800,CONT_DIF_P,* +V 7900,7200,CONT_DIF_P,* +V 9100,8800,CONT_DIF_P,* +V 9100,8400,CONT_DIF_P,* +V 7900,8400,CONT_DIF_P,* +V 7900,8800,CONT_DIF_P,* +V 9100,8000,CONT_DIF_P,* +V 9100,7600,CONT_DIF_P,* +V 9100,7200,CONT_DIF_P,* +V 9100,6800,CONT_DIF_P,* +V 9100,9600,CONT_DIF_P,* +V 9100,9200,CONT_DIF_P,* +V 5500,3600,CONT_DIF_N,* +V 5500,3200,CONT_DIF_N,* +V 5500,2800,CONT_DIF_N,* +V 5500,4400,CONT_DIF_N,* +V 5500,4000,CONT_DIF_N,* +V 7900,2800,CONT_DIF_N,* +V 9100,3200,CONT_DIF_N,* +V 6700,3600,CONT_DIF_N,* +V 6700,3200,CONT_DIF_N,* +V 6700,2800,CONT_DIF_N,* +V 6700,4400,CONT_DIF_N,* +V 6700,4000,CONT_DIF_N,* +V 7900,4000,CONT_DIF_N,* +V 7900,4400,CONT_DIF_N,* +V 7900,3200,CONT_DIF_N,* +V 7900,3600,CONT_DIF_N,* +V 9100,2800,CONT_DIF_N,* +V 9100,4400,CONT_DIF_N,* +V 9100,4000,CONT_DIF_N,* +V 9100,3600,CONT_DIF_N,* +V 7300,4400,CONT_DIF_N,* +V 6100,4400,CONT_DIF_N,* +V 8500,4400,CONT_DIF_N,* +V 6100,4000,CONT_VIA,* +V 7300,4000,CONT_VIA,* +V 8500,4000,CONT_VIA,* +V 4900,4000,CONT_VIA,* +V 4900,4400,CONT_DIF_N,* +V 4900,3600,CONT_DIF_N,* +V 6100,3600,CONT_DIF_N,* +V 7300,3600,CONT_DIF_N,* +V 8500,3600,CONT_DIF_N,* +V 8500,3200,CONT_DIF_N,* +V 7300,3200,CONT_DIF_N,* +V 6100,3200,CONT_DIF_N,* +V 4900,3200,CONT_DIF_N,* +V 4900,2800,CONT_DIF_N,* +V 6100,2800,CONT_DIF_N,* +V 7300,2800,CONT_DIF_N,* +V 8500,2800,CONT_DIF_N,* +V 4900,2400,CONT_VIA,* +V 6100,2400,CONT_VIA,* +V 7300,2400,CONT_VIA,* +V 8500,2400,CONT_VIA,* +V 8500,2100,CONT_BODY_P,* +V 7300,2100,CONT_BODY_P,* +V 6100,2100,CONT_BODY_P,* +V 4900,2100,CONT_BODY_P,* +V 8500,5000,CONT_BODY_P,* +V 4900,5000,CONT_BODY_P,* +V 5700,2100,CONT_BODY_P,* +V 5300,2100,CONT_BODY_P,* +V 4300,2100,CONT_BODY_P,* +V 4300,2500,CONT_BODY_P,* +V 4300,2900,CONT_VIA,* +V 4300,3300,CONT_BODY_P,* +V 4300,3700,CONT_BODY_P,* +V 4300,4100,CONT_BODY_P,* +V 4300,4500,CONT_VIA,* +V 4300,5000,CONT_BODY_P,* +V 9700,2900,CONT_VIA,* +V 9700,4500,CONT_VIA,* +V 9700,2100,CONT_BODY_P,* +V 9700,5000,CONT_BODY_P,* +V 9700,4100,CONT_BODY_P,* +V 9700,3700,CONT_BODY_P,* +V 9700,3300,CONT_BODY_P,* +V 9700,2500,CONT_BODY_P,* +V 7100,5000,CONT_BODY_P,* +V 8100,5000,CONT_BODY_P,* +V 6600,5000,CONT_VIA,* +V 6200,5000,CONT_BODY_P,* +V 6100,9600,CONT_DIF_P,* +V 6100,9200,CONT_DIF_P,* +V 6100,8800,CONT_DIF_P,* +V 6100,8000,CONT_DIF_P,* +V 6100,7600,CONT_DIF_P,* +V 6100,6800,CONT_DIF_P,* +V 6100,10000,CONT_VIA,* +V 6100,8400,CONT_VIA,* +V 6100,7200,CONT_VIA,* +V 4900,8400,CONT_VIA,* +V 4900,10000,CONT_VIA,* +V 4900,7200,CONT_VIA,* +V 4900,7600,CONT_DIF_P,* +V 4900,8000,CONT_DIF_P,* +V 4900,8800,CONT_DIF_P,* +V 4900,9200,CONT_DIF_P,* +V 4900,9600,CONT_DIF_P,* +V 4900,10400,CONT_DIF_P,* +V 4900,6800,CONT_DIF_P,* +V 7300,10000,CONT_VIA,* +V 7300,8400,CONT_VIA,* +V 7300,9600,CONT_DIF_P,* +V 7300,9200,CONT_DIF_P,* +V 7300,8800,CONT_DIF_P,* +V 7300,8000,CONT_DIF_P,* +V 7300,7600,CONT_DIF_P,* +V 7300,7100,CONT_DIF_P,* +V 8500,8400,CONT_VIA,* +V 8500,10000,CONT_VIA,* +V 8500,7600,CONT_DIF_P,* +V 8500,8000,CONT_DIF_P,* +V 8500,8800,CONT_DIF_P,* +V 8500,9200,CONT_DIF_P,* +V 8500,9600,CONT_DIF_P,* +V 8500,7100,CONT_DIF_P,* +V 6100,10400,CONT_BODY_N,* +V 6500,10400,CONT_BODY_N,* +V 6900,10400,CONT_BODY_N,* +V 7300,10400,CONT_BODY_N,* +V 7700,10400,CONT_BODY_N,* +V 8100,10400,CONT_BODY_N,* +V 8500,10400,CONT_BODY_N,* +V 8900,10400,CONT_BODY_N,* +V 9300,10400,CONT_BODY_N,* +V 9700,10400,CONT_BODY_N,* +V 9700,10000,CONT_BODY_N,* +V 9700,9200,CONT_BODY_N,* +V 9700,8800,CONT_BODY_N,* +V 9700,8400,CONT_BODY_N,* +V 9700,8000,CONT_BODY_N,* +V 9700,7600,CONT_BODY_N,* +V 9700,6100,CONT_BODY_N,* +V 9700,6500,CONT_BODY_N,* +V 9700,7000,CONT_VIA,* +V 9700,9600,CONT_VIA,* +V 7600,5600,CONT_POLY,* +V 7100,6100,CONT_BODY_N,* +V 6200,6100,CONT_BODY_N,* +V 6700,6100,CONT_BODY_N,* +V 4900,6100,CONT_BODY_N,* +V 4300,6100,CONT_BODY_N,* +V 4300,6500,CONT_BODY_N,* +V 4300,6900,CONT_VIA,* +V 4300,7300,CONT_BODY_N,* +V 5200,5600,CONT_POLY,* +V 4300,7700,CONT_BODY_N,* +V 4300,8100,CONT_BODY_N,* +V 4300,8500,CONT_VIA,* +V 4300,8900,CONT_BODY_N,* +V 4300,9300,CONT_BODY_N,* +V 4300,9700,CONT_VIA,* +V 4300,10300,CONT_BODY_N,* +B 3800,5600,200,200,CONT_TURN1,* +EOF diff --git a/alliance/src/cells/src/padlib/palvssi_sp.ap b/alliance/src/cells/src/padlib/palvssi_sp.ap new file mode 100644 index 00000000..8cb75bab --- /dev/null +++ b/alliance/src/cells/src/padlib/palvssi_sp.ap @@ -0,0 +1,44 @@ +V ALLIANCE : 6 +H palvssi_sp,P,13/10/2000,100 +A 0,0,17200,36300 +C 8600,0,10000,vssi,2,SOUTH,ALU1 +C 17200,17500,12000,vdde,3,EAST,ALU2 +C 0,17500,12000,vdde,2,WEST,ALU2 +C 17200,9100,4000,vddi,3,EAST,ALU2 +C 0,9100,4000,vddi,2,WEST,ALU2 +C 17200,4700,4000,vssi,9,EAST,ALU2 +C 0,4700,4000,vssi,8,WEST,ALU2 +C 17200,1300,1200,ck,3,EAST,ALU2 +C 0,1300,1200,ck,2,WEST,ALU2 +C 17200,30300,12000,vsse,3,EAST,ALU2 +C 0,30300,12000,vsse,2,WEST,ALU2 +C 8600,0,10000,vssi,3,SOUTH,ALU2 +S 8600,0,8600,36300,10000,*,UP,ALU1 +S 0,4700,17200,4700,4000,vssi,RIGHT,ALU2 +S 0,9100,17200,9100,4000,vddi,RIGHT,ALU2 +S 0,17500,17200,17500,12000,vdde,RIGHT,ALU2 +S 0,1300,17200,1300,1200,ck,RIGHT,ALU2 +S 0,30300,17200,30300,12000,vsse,RIGHT,ALU2 +B 8600,200,10000,400,CONT_TURN2,* +V 10700,300,CONT_VIA,* +V 11200,300,CONT_VIA,* +V 11700,300,CONT_VIA,* +V 12200,300,CONT_VIA,* +V 13200,300,CONT_VIA,* +V 12700,300,CONT_VIA,* +V 9700,300,CONT_VIA,* +V 10200,300,CONT_VIA,* +V 7700,300,CONT_VIA,* +V 8200,300,CONT_VIA,* +V 8700,300,CONT_VIA,* +V 9200,300,CONT_VIA,* +V 6700,300,CONT_VIA,* +V 7200,300,CONT_VIA,* +V 6200,300,CONT_VIA,* +V 5700,300,CONT_VIA,* +V 5200,300,CONT_VIA,* +V 4700,300,CONT_VIA,* +V 4200,300,CONT_VIA,* +V 3700,300,CONT_VIA,* +B 8600,4700,10000,4000,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/padlib/palvssick_sp.ap b/alliance/src/cells/src/padlib/palvssick_sp.ap new file mode 100644 index 00000000..0b4aee73 --- /dev/null +++ b/alliance/src/cells/src/padlib/palvssick_sp.ap @@ -0,0 +1,411 @@ +V ALLIANCE : 6 +H palvssick_sp,P,13/10/2000,100 +A 0,0,17200,36300 +C 8600,0,10000,vssi,2,SOUTH,ALU1 +C 8600,0,10000,vssi,4,SOUTH,ALU2 +C 17200,1300,1200,ck,3,EAST,ALU2 +C 17200,4700,4000,vssi,8,EAST,ALU2 +C 17200,9100,4000,vddi,3,EAST,ALU2 +C 0,1300,1200,ck,2,WEST,ALU2 +C 0,4700,4000,vssi,7,WEST,ALU2 +C 0,9100,4000,vddi,2,WEST,ALU2 +C 0,17500,12000,vdde,2,WEST,ALU2 +C 17200,17500,12000,vdde,3,EAST,ALU2 +C 15500,0,200,cko,7,SOUTH,ALU2 +C 15500,0,200,cko,6,SOUTH,ALU1 +C 1700,0,200,cko,5,SOUTH,ALU2 +C 1700,0,200,cko,4,SOUTH,ALU1 +C 17200,30300,12000,vsse,3,EAST,ALU2 +C 0,30300,12000,vsse,2,WEST,ALU2 +S 800,7500,1500,7500,300,*,RIGHT,NTIE +S 2100,7500,2700,7500,300,*,RIGHT,NTIE +S 3100,10400,3900,10400,300,*,RIGHT,NTIE +S 2000,8000,2000,12900,200,*,UP,PDIF +S 1400,8000,1400,12900,300,*,UP,PDIF +S 2600,8000,2600,12900,300,*,UP,PDIF +S 3200,8000,3200,9900,300,*,UP,PDIF +S 3200,10300,3200,13500,300,*,DOWN,NTIE +S 700,13400,3200,13400,300,*,RIGHT,NTIE +S 800,7400,800,13500,300,*,DOWN,NTIE +S 14500,7500,15100,7500,300,*,RIGHT,NTIE +S 3100,7500,3900,7500,300,*,RIGHT,NTIE +S 600,13400,4000,13400,400,*,RIGHT,NWELL +S 600,10400,4000,10400,6200,*,RIGHT,NWELL +S 2900,7800,2900,10100,100,*,DOWN,PTRANS +S 2300,7800,2300,13100,100,*,DOWN,PTRANS +S 1700,7800,1700,13100,100,*,DOWN,PTRANS +S 3800,7400,3800,10500,300,*,DOWN,NTIE +S 15200,8000,15200,12900,200,*,DOWN,PDIF +S 15800,8000,15800,12900,300,*,DOWN,PDIF +S 14600,8000,14600,12900,300,*,DOWN,PDIF +S 14000,8000,14000,9900,300,*,DOWN,PDIF +S 14000,10300,14000,13500,300,*,UP,NTIE +S 14000,13400,16500,13400,300,*,RIGHT,NTIE +S 16400,7400,16400,13500,300,*,UP,NTIE +S 15700,7500,16400,7500,300,*,RIGHT,NTIE +S 13300,7500,14100,7500,300,*,RIGHT,NTIE +S 13200,13400,16600,13400,400,*,RIGHT,NWELL +S 13200,10400,16600,10400,6200,*,RIGHT,NWELL +S 14300,7800,14300,10100,100,*,UP,PTRANS +S 14900,7800,14900,13100,100,*,UP,PTRANS +S 15500,7800,15500,13100,100,*,UP,PTRANS +S 13400,7400,13400,10500,300,*,UP,NTIE +S 13300,10400,14100,10400,300,*,RIGHT,NTIE +S 15800,3100,15800,5900,100,*,DOWN,NTRANS +S 14600,4600,14600,5900,100,*,DOWN,NTRANS +S 15200,3100,15200,5900,100,*,DOWN,NTRANS +S 1400,3100,1400,5900,100,*,UP,NTRANS +S 2600,4600,2600,5900,100,*,UP,NTRANS +S 2000,3100,2000,5900,100,*,UP,NTRANS +S 1100,3300,1100,5700,300,*,UP,NDIF +S 2900,4800,2900,5700,300,*,UP,NDIF +S 2300,3300,2300,5700,300,*,UP,NDIF +S 1700,3300,1700,5700,300,*,UP,NDIF +S 14900,3300,14900,5700,300,*,DOWN,NDIF +S 15500,3300,15500,5700,300,*,DOWN,NDIF +S 16100,3300,16100,5700,300,*,DOWN,NDIF +S 14300,4800,14300,5700,300,*,DOWN,NDIF +S 400,2800,3000,2800,300,*,LEFT,PTIE +S 500,2800,500,6500,300,*,UP,PTIE +S 500,6400,1500,6400,300,*,RIGHT,PTIE +S 3100,6400,3600,6400,300,*,RIGHT,PTIE +S 2900,2800,2900,4100,300,*,DOWN,PTIE +S 2900,4000,3600,4000,300,*,LEFT,PTIE +S 3500,4100,3500,6500,300,*,DOWN,PTIE +S 2100,6400,2700,6400,300,*,RIGHT,PTIE +S 13600,6400,14100,6400,300,*,RIGHT,PTIE +S 14200,2800,16800,2800,300,*,LEFT,PTIE +S 14300,2800,14300,4100,300,*,UP,PTIE +S 13600,4000,14300,4000,300,*,LEFT,PTIE +S 16700,2800,16700,6500,300,*,DOWN,PTIE +S 13700,4100,13700,6500,300,*,UP,PTIE +S 15700,6400,16700,6400,300,*,RIGHT,PTIE +S 14500,6400,15100,6400,300,*,RIGHT,PTIE +S 1800,5900,1800,7800,200,*,DOWN,POLY +S 1900,7000,2500,7000,300,*,LEFT,POLY +S 2600,5900,2900,5900,100,*,RIGHT,POLY +S 2600,4400,2600,4600,100,*,UP,POLY +S 15400,5900,15400,7800,200,*,UP,POLY +S 14700,7000,15300,7000,300,*,LEFT,POLY +S 1400,5900,2000,5900,100,*,RIGHT,POLY +S 1700,7800,2300,7800,100,*,RIGHT,POLY +S 2900,5900,2900,7800,100,*,UP,POLY +S 15200,5900,15800,5900,100,*,RIGHT,POLY +S 14900,7800,15500,7800,100,*,RIGHT,POLY +S 14300,5900,14300,7800,100,*,DOWN,POLY +S 14300,5900,14600,5900,100,*,RIGHT,POLY +S 14600,4400,14600,4600,100,*,DOWN,POLY +S 15500,0,15500,2200,200,*,UP,ALU1 +S 1700,0,1700,2300,200,*,DOWN,ALU1 +S 8600,0,8600,36300,10000,*,UP,ALU1 +S 800,2800,800,6500,900,*,UP,ALU1 +S 400,2800,1200,2800,200,*,LEFT,ALU1 +S 700,7500,1400,7500,200,*,LEFT,ALU1 +S 16400,2800,16400,6500,900,*,DOWN,ALU1 +S 16000,2800,16800,2800,200,*,RIGHT,ALU1 +S 1500,2300,2100,2300,200,*,LEFT,ALU1 +S 15100,2300,15700,2300,200,*,LEFT,ALU1 +S 14600,7500,14600,13500,200,*,DOWN,ALU1 +S 15800,7500,15800,13500,200,*,DOWN,ALU1 +S 16200,7500,16200,13500,700,*,UP,ALU1 +S 15800,7500,16500,7500,200,*,LEFT,ALU1 +S 1000,7500,1000,13500,700,*,DOWN,ALU1 +S 1400,7500,1400,13500,200,*,UP,ALU1 +S 14000,10300,14000,13500,200,*,DOWN,ALU1 +S 14000,13300,16500,13300,500,*,LEFT,ALU1 +S 700,13300,3200,13300,500,*,LEFT,ALU1 +S 2500,7000,3200,7000,200,*,RIGHT,ALU1 +S 14000,7000,14700,7000,200,*,RIGHT,ALU1 +S 15200,7000,15500,7000,200,*,RIGHT,ALU1 +S 1700,7000,2000,7000,200,*,RIGHT,ALU1 +S 2600,7500,2600,13500,200,*,UP,ALU1 +S 15500,2200,15500,7000,200,*,DOWN,ALU1 +S 2800,1000,2800,4500,200,*,UP,ALU1 +S 2900,5100,2900,7000,200,*,UP,ALU1 +S 3200,7000,3200,9800,200,*,UP,ALU1 +S 2000,7000,2000,12600,200,*,UP,ALU1 +S 2300,2800,2300,6500,200,*,UP,ALU1 +S 1700,2200,1700,7000,200,*,UP,ALU1 +S 3200,10300,3200,13500,200,*,UP,ALU1 +S 14400,1000,14400,4500,200,*,DOWN,ALU1 +S 14300,5100,14300,7000,200,*,DOWN,ALU1 +S 14000,7000,14000,9800,200,*,DOWN,ALU1 +S 15200,7000,15200,12600,200,*,DOWN,ALU1 +S 14900,2800,14900,6500,200,*,DOWN,ALU1 +S 0,9100,17200,9100,4000,vddi,RIGHT,ALU2 +S 0,4700,17200,4700,4000,vssi,RIGHT,ALU2 +S 0,17500,17200,17500,12000,vdde,RIGHT,ALU2 +S 0,1300,17200,1300,1200,ck,RIGHT,ALU2 +S 1700,2300,15700,2300,200,*,RIGHT,ALU2 +S 0,30300,17200,30300,12000,vsse,RIGHT,ALU2 +V 4000,300,CONT_VIA,* +V 4500,300,CONT_VIA,* +V 8500,300,CONT_VIA,* +V 8000,300,CONT_VIA,* +V 7500,300,CONT_VIA,* +V 7000,300,CONT_VIA,* +V 6500,300,CONT_VIA,* +V 6000,300,CONT_VIA,* +V 5500,300,CONT_VIA,* +V 5000,300,CONT_VIA,* +V 9000,300,CONT_VIA,* +V 9500,300,CONT_VIA,* +V 10000,300,CONT_VIA,* +V 10500,300,CONT_VIA,* +V 11000,300,CONT_VIA,* +V 11500,300,CONT_VIA,* +V 12000,300,CONT_VIA,* +V 12500,300,CONT_VIA,* +V 13000,300,CONT_VIA,* +V 13500,300,CONT_VIA,* +B 8600,200,10000,400,CONT_TURN2,* +V 1400,11200,CONT_DIF_P,* +V 1400,11600,CONT_DIF_P,* +V 1400,12000,CONT_DIF_P,* +V 1400,12400,CONT_DIF_P,* +V 1400,12800,CONT_DIF_P,* +V 2600,12800,CONT_DIF_P,* +V 1400,9000,CONT_DIF_P,* +V 1400,9800,CONT_DIF_P,* +V 1400,10200,CONT_DIF_P,* +V 1400,10600,CONT_DIF_P,* +V 2600,12400,CONT_DIF_P,* +V 2600,11200,CONT_DIF_P,* +V 2600,11600,CONT_DIF_P,* +V 2600,12000,CONT_DIF_P,* +V 2000,8600,CONT_DIF_P,* +V 2000,11800,CONT_DIF_P,* +V 2000,11400,CONT_DIF_P,* +V 2000,11000,CONT_DIF_P,* +V 2000,10600,CONT_DIF_P,* +V 1400,7500,CONT_BODY_N,* +V 1400,8200,CONT_DIF_P,* +V 1400,8600,CONT_DIF_P,* +V 2600,8200,CONT_DIF_P,* +V 2000,12600,CONT_DIF_P,* +V 2000,8200,CONT_DIF_P,* +V 2000,12200,CONT_DIF_P,* +V 2000,10200,CONT_DIF_P,* +V 2000,9800,CONT_DIF_P,* +V 2000,9400,CONT_DIF_P,* +V 2000,9000,CONT_DIF_P,* +V 3200,8200,CONT_DIF_P,* +V 3200,8600,CONT_DIF_P,* +V 2600,7500,CONT_BODY_N,* +V 2600,8600,CONT_DIF_P,* +V 2600,9000,CONT_DIF_P,* +V 2600,9800,CONT_DIF_P,* +V 2600,10200,CONT_DIF_P,* +V 2600,10600,CONT_DIF_P,* +V 3200,10400,CONT_BODY_N,* +V 800,9000,CONT_BODY_N,* +V 800,8600,CONT_BODY_N,* +V 800,8200,CONT_BODY_N,* +V 800,7500,CONT_BODY_N,* +V 3200,9000,CONT_DIF_P,* +V 3200,9400,CONT_DIF_P,* +V 3200,9800,CONT_DIF_P,* +V 800,13000,CONT_BODY_N,* +V 800,13400,CONT_BODY_N,* +V 1200,13400,CONT_BODY_N,* +V 1600,13400,CONT_BODY_N,* +V 2000,13400,CONT_BODY_N,* +V 2400,13400,CONT_BODY_N,* +V 2800,13400,CONT_BODY_N,* +V 3200,13400,CONT_BODY_N,* +V 3200,12600,CONT_BODY_N,* +V 3200,12200,CONT_BODY_N,* +V 3200,11800,CONT_BODY_N,* +V 3200,11400,CONT_BODY_N,* +V 800,11400,CONT_BODY_N,* +V 800,11800,CONT_BODY_N,* +V 800,12200,CONT_BODY_N,* +V 800,12600,CONT_BODY_N,* +V 15800,12000,CONT_DIF_P,* +V 15800,12400,CONT_DIF_P,* +V 15800,12800,CONT_DIF_P,* +V 14600,12800,CONT_DIF_P,* +V 800,11000,CONT_BODY_N,* +V 800,9800,CONT_BODY_N,* +V 800,10200,CONT_BODY_N,* +V 3200,13000,CONT_BODY_N,* +V 15800,10200,CONT_DIF_P,* +V 15800,10600,CONT_DIF_P,* +V 14600,12400,CONT_DIF_P,* +V 14600,11200,CONT_DIF_P,* +V 14600,11600,CONT_DIF_P,* +V 14600,12000,CONT_DIF_P,* +V 15800,11200,CONT_DIF_P,* +V 15800,11600,CONT_DIF_P,* +V 15200,11400,CONT_DIF_P,* +V 15200,11000,CONT_DIF_P,* +V 15200,10600,CONT_DIF_P,* +V 15800,7500,CONT_BODY_N,* +V 15800,8200,CONT_DIF_P,* +V 15800,8600,CONT_DIF_P,* +V 15800,9000,CONT_DIF_P,* +V 15800,9800,CONT_DIF_P,* +V 15200,8200,CONT_DIF_P,* +V 15200,12200,CONT_DIF_P,* +V 15200,10200,CONT_DIF_P,* +V 15200,9800,CONT_DIF_P,* +V 15200,9400,CONT_DIF_P,* +V 15200,9000,CONT_DIF_P,* +V 15200,8600,CONT_DIF_P,* +V 15200,11800,CONT_DIF_P,* +V 14600,7500,CONT_BODY_N,* +V 14600,8600,CONT_DIF_P,* +V 14600,9000,CONT_DIF_P,* +V 14600,9800,CONT_DIF_P,* +V 14600,10200,CONT_DIF_P,* +V 14600,10600,CONT_DIF_P,* +V 14600,8200,CONT_DIF_P,* +V 15200,12600,CONT_DIF_P,* +V 16400,8600,CONT_BODY_N,* +V 16400,8200,CONT_BODY_N,* +V 16400,7500,CONT_BODY_N,* +V 14000,9000,CONT_DIF_P,* +V 14000,9400,CONT_DIF_P,* +V 14000,9800,CONT_DIF_P,* +V 14000,8200,CONT_DIF_P,* +V 14000,8600,CONT_DIF_P,* +V 16000,13400,CONT_BODY_N,* +V 15600,13400,CONT_BODY_N,* +V 15200,13400,CONT_BODY_N,* +V 14800,13400,CONT_BODY_N,* +V 14400,13400,CONT_BODY_N,* +V 14000,13400,CONT_BODY_N,* +V 14000,10400,CONT_BODY_N,* +V 16400,9000,CONT_BODY_N,* +V 14000,11800,CONT_BODY_N,* +V 14000,11400,CONT_BODY_N,* +V 16400,11400,CONT_BODY_N,* +V 16400,11800,CONT_BODY_N,* +V 16400,12200,CONT_BODY_N,* +V 16400,12600,CONT_BODY_N,* +V 16400,13000,CONT_BODY_N,* +V 16400,13400,CONT_BODY_N,* +V 16400,11000,CONT_BODY_N,* +V 16400,9800,CONT_BODY_N,* +V 16400,10200,CONT_BODY_N,* +V 14000,13000,CONT_BODY_N,* +V 14000,12600,CONT_BODY_N,* +V 14000,12200,CONT_BODY_N,* +V 2300,5500,CONT_DIF_N,* +V 2300,5100,CONT_DIF_N,* +V 2300,4700,CONT_DIF_N,* +V 2300,4300,CONT_DIF_N,* +V 2300,3500,CONT_DIF_N,* +V 1700,5500,CONT_DIF_N,* +V 1700,5100,CONT_DIF_N,* +V 1700,4700,CONT_DIF_N,* +V 1700,4300,CONT_DIF_N,* +V 1700,3900,CONT_DIF_N,* +V 1700,3500,CONT_DIF_N,* +V 2900,5600,CONT_DIF_N,* +V 2900,5100,CONT_DIF_N,* +V 1100,3600,CONT_DIF_N,* +V 1100,4000,CONT_DIF_N,* +V 1100,4400,CONT_DIF_N,* +V 1100,4800,CONT_DIF_N,* +V 1100,5200,CONT_DIF_N,* +V 1100,5600,CONT_DIF_N,* +V 2300,3900,CONT_DIF_N,* +V 15500,4300,CONT_DIF_N,* +V 15500,3900,CONT_DIF_N,* +V 15500,3500,CONT_DIF_N,* +V 14300,5600,CONT_DIF_N,* +V 14900,5500,CONT_DIF_N,* +V 14900,5100,CONT_DIF_N,* +V 14900,4700,CONT_DIF_N,* +V 14900,4300,CONT_DIF_N,* +V 16100,4800,CONT_DIF_N,* +V 16100,5200,CONT_DIF_N,* +V 16100,5600,CONT_DIF_N,* +V 14900,3900,CONT_DIF_N,* +V 14900,3500,CONT_DIF_N,* +V 15500,5500,CONT_DIF_N,* +V 15500,5100,CONT_DIF_N,* +V 15500,4700,CONT_DIF_N,* +V 14300,5100,CONT_DIF_N,* +V 16100,3600,CONT_DIF_N,* +V 16100,4000,CONT_DIF_N,* +V 16100,4400,CONT_DIF_N,* +V 500,3600,CONT_BODY_P,* +V 500,3200,CONT_BODY_P,* +V 500,2800,CONT_BODY_P,* +V 500,6400,CONT_BODY_P,* +V 500,5600,CONT_BODY_P,* +V 500,5200,CONT_BODY_P,* +V 500,4800,CONT_BODY_P,* +V 500,4000,CONT_BODY_P,* +V 2300,2800,CONT_BODY_P,* +V 1100,2800,CONT_BODY_P,* +V 2300,6400,CONT_BODY_P,* +V 1100,6400,CONT_BODY_P,* +V 14900,2800,CONT_BODY_P,* +V 16100,2800,CONT_BODY_P,* +V 14900,6400,CONT_BODY_P,* +V 16100,6400,CONT_BODY_P,* +V 16700,6400,CONT_BODY_P,* +V 16700,5600,CONT_BODY_P,* +V 16700,5200,CONT_BODY_P,* +V 16700,4800,CONT_BODY_P,* +V 16700,4000,CONT_BODY_P,* +V 16700,3600,CONT_BODY_P,* +V 16700,3200,CONT_BODY_P,* +V 16700,2800,CONT_BODY_P,* +V 14700,7000,CONT_POLY,* +V 14400,4500,CONT_POLY,* +V 2500,7000,CONT_POLY,* +V 2800,4500,CONT_POLY,* +V 15500,0,CONT_VIA,* +V 1700,0,CONT_VIA,* +V 500,6000,CONT_VIA,* +V 500,4400,CONT_VIA,* +B 15200,7000,200,200,CONT_TURN1,* +B 14000,7000,200,200,CONT_TURN1,* +V 2100,2300,CONT_VIA,* +V 15100,2300,CONT_VIA,* +B 3200,7000,200,200,CONT_TURN1,* +B 2000,7000,200,200,CONT_TURN1,* +B 1700,7000,200,200,CONT_TURN1,* +B 15500,7000,200,200,CONT_TURN1,* +V 2600,10900,CONT_VIA,* +V 1400,10900,CONT_VIA,* +V 2800,900,CONT_VIA,* +V 2800,1700,CONT_VIA,* +V 3200,10900,CONT_VIA,* +V 1400,9400,CONT_VIA,* +V 1400,7800,CONT_VIA,* +V 2600,7800,CONT_VIA,* +V 2600,9400,CONT_VIA,* +V 800,7800,CONT_VIA,* +V 800,9400,CONT_VIA,* +V 2300,6000,CONT_VIA,* +V 2300,3200,CONT_VIA,* +V 1100,3200,CONT_VIA,* +V 1100,6000,CONT_VIA,* +V 800,10600,CONT_VIA,* +V 14400,1700,CONT_VIA,* +V 14000,10900,CONT_VIA,* +V 14600,10900,CONT_VIA,* +V 15800,10900,CONT_VIA,* +V 14400,900,CONT_VIA,* +V 15800,9400,CONT_VIA,* +V 15800,7800,CONT_VIA,* +V 14600,7800,CONT_VIA,* +V 14600,9400,CONT_VIA,* +V 16400,7800,CONT_VIA,* +V 16400,9400,CONT_VIA,* +V 16100,3200,CONT_VIA,* +V 16100,6000,CONT_VIA,* +V 14900,6000,CONT_VIA,* +V 16700,4400,CONT_VIA,* +V 14900,3200,CONT_VIA,* +V 16400,10600,CONT_VIA,* +V 16700,6000,CONT_VIA,* +B 8600,4700,10000,4000,CONT_VIA,* +V 1500,2300,CONT_VIA,* +V 15700,2300,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/padlib/pck_sp.al b/alliance/src/cells/src/padlib/pck_sp.al new file mode 100644 index 00000000..f2988375 --- /dev/null +++ b/alliance/src/cells/src/padlib/pck_sp.al @@ -0,0 +1,56 @@ +V ALLIANCE : 4 +H pck_sp,L,23/ 2/95 +C pad,UNKNOWN,EXTERNAL,2 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,3 +C vddi,UNKNOWN,EXTERNAL,4 +C vsse,UNKNOWN,EXTERNAL,5 +C vssi,UNKNOWN,EXTERNAL,6 +T N,1,27,6,2,7,0,0,0,0,147,29 +T N,1,27,7,2,6,0,0,0,0,141,29 +T N,1,27,7,2,6,0,0,0,0,153,29 +T N,1,27,7,2,6,0,0,0,0,129,29 +T N,1,27,6,2,7,0,0,0,0,123,29 +T N,1,27,6,2,7,0,0,0,0,135,29 +T N,1,27,6,2,7,0,0,0,0,111,29 +T N,1,27,7,2,6,0,0,0,0,117,29 +T N,1,27,7,2,6,0,0,0,0,105,29 +T N,1,27,6,2,7,0,0,0,0,99,29 +T N,1,27,7,2,6,0,0,0,0,93,29 +T N,1,27,6,2,7,0,0,0,0,87,29 +T N,1,27,1,7,6,0,0,0,0,52,29 +T N,1,27,6,7,1,0,0,0,0,46,29 +T N,1,27,1,7,6,0,0,0,0,28,29 +T N,1,27,1,7,6,0,0,0,0,40,29 +T N,1,27,6,7,1,0,0,0,0,34,29 +T N,1,27,6,7,1,0,0,0,0,70,29 +T N,1,27,1,7,6,0,0,0,0,64,29 +T N,1,27,6,7,1,0,0,0,0,58,29 +T N,1,35,2,5,5,0,0,0,0,73,273 +T N,1,35,5,5,2,0,0,0,0,79,273 +T N,1,35,2,5,5,0,0,0,0,85,273 +T N,1,35,5,5,2,0,0,0,0,91,273 +T P,1,27,7,2,4,0,0,0,0,105,80 +T P,1,27,4,2,7,0,0,0,0,99,80 +T P,1,27,7,2,4,0,0,0,0,93,80 +T P,1,27,4,2,7,0,0,0,0,87,80 +T P,1,57,4,7,1,0,0,0,0,70,95 +T P,1,57,4,7,1,0,0,0,0,46,95 +T P,1,57,1,7,4,0,0,0,0,52,95 +T P,1,57,4,7,1,0,0,0,0,58,95 +T P,1,57,1,7,4,0,0,0,0,64,95 +T P,1,57,1,7,4,0,0,0,0,28,95 +T P,1,57,4,7,1,0,0,0,0,34,95 +T P,1,57,1,7,4,0,0,0,0,40,95 +T P,1,80,2,3,3,0,0,0,0,73,188.5 +T P,1,80,3,3,2,0,0,0,0,79,188.5 +T P,1,80,2,3,3,0,0,0,0,85,188.5 +T P,1,80,3,3,2,0,0,0,0,91,188.5 +S 7,INTERNAL,0,mbk_sig3 +S 6,EXTERNAL,0,vssi +S 5,EXTERNAL,0,vsse +S 4,EXTERNAL,0,vddi +S 3,EXTERNAL,0,vdde +S 2,EXTERNAL,0,pad +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pck_sp.ap b/alliance/src/cells/src/padlib/pck_sp.ap new file mode 100644 index 00000000..a98320d6 --- /dev/null +++ b/alliance/src/cells/src/padlib/pck_sp.ap @@ -0,0 +1,17 @@ +V ALLIANCE : 3 +H pck_sp,P,30/ 0/95 +A 3,1,175,501 +C 3,48,40,vssi,0,WEST,ALU2 +C 3,92,40,vddi,0,WEST,ALU2 +C 3,14,12,ck,0,WEST,ALU2 +C 175,14,12,ck,1,EAST,ALU2 +C 175,48,40,vssi,1,EAST,ALU2 +C 175,92,40,vddi,1,EAST,ALU2 +C 175,176,120,vdde,1,EAST,ALU2 +C 175,304,120,vsse,1,EAST,ALU2 +C 3,304,120,vsse,0,WEST,ALU2 +C 3,176,120,vdde,0,WEST,ALU2 +C 91,501,1,pad,0,NORTH,ALU1 +I 3,1,palck_sp,log,NOSYM +I 3,364,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pck_sp.vbe b/alliance/src/cells/src/padlib/pck_sp.vbe new file mode 100644 index 00000000..f989fea0 --- /dev/null +++ b/alliance/src/cells/src/padlib/pck_sp.vbe @@ -0,0 +1,38 @@ +-- VHDL data flow description generated from `pck_sp` +-- date : Thu Feb 23 17:05:59 1995 + + +-- Entity Declaration + +ENTITY pck_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_pad : NATURAL := 1326; -- cin_pad + CONSTANT tpll_pad : NATURAL := 1443; -- tpll_pad + CONSTANT rdown_pad : NATURAL := 58; -- rdown_pad + CONSTANT tphh_pad : NATURAL := 228; -- tphh_pad + CONSTANT rup_pad : NATURAL := 68 -- rup_pad + ); + PORT ( + pad : in BIT; -- pad + ck : out BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pck_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pck_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pck_sp" + SEVERITY WARNING; + + +ck <= pad; +END; diff --git a/alliance/src/cells/src/padlib/pi_sp.al b/alliance/src/cells/src/padlib/pi_sp.al new file mode 100644 index 00000000..fff951fc --- /dev/null +++ b/alliance/src/cells/src/padlib/pi_sp.al @@ -0,0 +1,34 @@ +V ALLIANCE : 4 +H pi_sp,L,23/ 2/95 +C pad,UNKNOWN,EXTERNAL,2 +C t,UNKNOWN,EXTERNAL,3 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,4 +C vddi,UNKNOWN,EXTERNAL,5 +C vsse,UNKNOWN,EXTERNAL,6 +C vssi,UNKNOWN,EXTERNAL,7 +T N,1,27,3,8,7,0,0,0,0,88,29 +T N,1,27,7,8,3,0,0,0,0,94,29 +T N,1,27,7,2,8,0,0,0,0,111,29 +T N,1,27,8,2,7,0,0,0,0,117,29 +T N,1,27,7,2,8,0,0,0,0,123,29 +T N,1,35,6,6,2,0,0,0,0,97,273 +T N,1,35,2,6,6,0,0,0,0,91,273 +T N,1,35,6,6,2,0,0,0,0,85,273 +T N,1,35,2,6,6,0,0,0,0,79,273 +T P,1,57,5,8,3,0,0,0,0,94,95 +T P,1,57,3,8,5,0,0,0,0,88,95 +T P,1,27,5,2,8,0,0,0,0,111,80 +T P,1,80,4,4,2,0,0,0,0,97,188.5 +T P,1,80,2,4,4,0,0,0,0,91,188.5 +T P,1,80,4,4,2,0,0,0,0,85,188.5 +T P,1,80,2,4,4,0,0,0,0,79,188.5 +S 8,INTERNAL,0,mbk_sig4 +S 7,EXTERNAL,0,vssi +S 6,EXTERNAL,0,vsse +S 5,EXTERNAL,0,vddi +S 4,EXTERNAL,0,vdde +S 3,EXTERNAL,0,t +S 2,EXTERNAL,0,pad +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pi_sp.ap b/alliance/src/cells/src/padlib/pi_sp.ap new file mode 100644 index 00000000..5ed67aa0 --- /dev/null +++ b/alliance/src/cells/src/padlib/pi_sp.ap @@ -0,0 +1,19 @@ +V ALLIANCE : 3 +H pi_sp,P,30/ 0/95 +A 9,1,181,501 +C 91,1,2,t,1,SOUTH,ALU2 +C 91,1,2,t,0,SOUTH,ALU1 +C 9,14,12,ck,0,WEST,ALU2 +C 181,14,12,ck,1,EAST,ALU2 +C 181,48,40,vssi,1,EAST,ALU2 +C 181,92,40,vddi,1,EAST,ALU2 +C 181,176,120,vdde,1,EAST,ALU2 +C 9,304,120,vsse,0,WEST,ALU2 +C 181,304,120,vsse,1,EAST,ALU2 +C 9,176,120,vdde,0,WEST,ALU2 +C 9,92,40,vddi,0,WEST,ALU2 +C 9,48,40,vssi,0,WEST,ALU2 +C 97,501,1,pad,0,NORTH,ALU1 +I 9,364,padreal,pad,NOSYM +I 9,1,pali_sp,log,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pi_sp.vbe b/alliance/src/cells/src/padlib/pi_sp.vbe new file mode 100644 index 00000000..9791020d --- /dev/null +++ b/alliance/src/cells/src/padlib/pi_sp.vbe @@ -0,0 +1,39 @@ +-- VHDL data flow description generated from `pi_sp` +-- date : Thu Feb 23 17:06:23 1995 + + +-- Entity Declaration + +ENTITY pi_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_pad : NATURAL := 654; -- cin_pad + CONSTANT tpll_pad : NATURAL := 1487; -- tpll_pad + CONSTANT rdown_pad : NATURAL := 234; -- rdown_pad + CONSTANT tphh_pad : NATURAL := 233; -- tphh_pad + CONSTANT rup_pad : NATURAL := 273 -- rup_pad + ); + PORT ( + pad : in BIT; -- pad + t : out BIT; -- t + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pi_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pi_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pi_sp" + SEVERITY WARNING; + + +t <= pad; +END; diff --git a/alliance/src/cells/src/padlib/piot_sp.al b/alliance/src/cells/src/padlib/piot_sp.al new file mode 100644 index 00000000..b530e02c --- /dev/null +++ b/alliance/src/cells/src/padlib/piot_sp.al @@ -0,0 +1,118 @@ +V ALLIANCE : 4 +H piot_sp,L,23/ 2/95 +C i,UNKNOWN,EXTERNAL,3 +C b,UNKNOWN,EXTERNAL,1 +C t,UNKNOWN,EXTERNAL,5 +C pad,UNKNOWN,EXTERNAL,4 +C ck,UNKNOWN,EXTERNAL,2 +C vdde,UNKNOWN,EXTERNAL,6 +C vddi,UNKNOWN,EXTERNAL,7 +C vsse,UNKNOWN,EXTERNAL,8 +C vssi,UNKNOWN,EXTERNAL,9 +T N,1,10,9,17,16,0,0,0,0,149,30.5 +T N,1,10,17,1,9,0,0,0,0,155,30.5 +T N,1,29,14,16,15,0,0,0,0,119,20 +T N,1,29,15,16,14,0,0,0,0,125,20 +T N,1,29,14,16,15,0,0,0,0,131,20 +T N,1,29,15,16,14,0,0,0,0,137,20 +T N,1,30,9,13,15,0,0,0,0,83,20.5 +T N,1,30,15,13,9,0,0,0,0,77,20.5 +T N,1,30,9,13,15,0,0,0,0,71,20.5 +T N,1,30,15,13,9,0,0,0,0,65,20.5 +T N,1,30,9,12,13,0,0,0,0,59,20.5 +T N,1,30,15,17,9,0,0,0,0,89,20.5 +T N,1,30,9,17,15,0,0,0,0,107,20.5 +T N,1,30,12,3,9,0,0,0,0,47,20.5 +T N,1,30,15,17,9,0,0,0,0,101,20.5 +T N,1,30,9,17,15,0,0,0,0,95,20.5 +T N,1,30,9,4,11,0,0,0,0,29,20.5 +T N,1,30,5,11,9,0,0,0,0,35,20.5 +T N,1,30,9,11,5,0,0,0,0,41,20.5 +T N,1,30,9,4,11,0,0,0,0,17,20.5 +T N,1,30,11,4,9,0,0,0,0,23,20.5 +T N,1,35,4,15,8,0,0,0,0,137,265 +T N,1,35,8,15,4,0,0,0,0,143,265 +T N,1,35,4,15,8,0,0,0,0,149,265 +T N,1,35,8,15,4,0,0,0,0,155,265 +T N,1,35,4,15,8,0,0,0,0,113,265 +T N,1,35,8,15,4,0,0,0,0,119,265 +T N,1,35,4,15,8,0,0,0,0,125,265 +T N,1,35,8,15,4,0,0,0,0,131,265 +T N,1,35,4,15,8,0,0,0,0,89,265 +T N,1,35,8,15,4,0,0,0,0,95,265 +T N,1,35,4,15,8,0,0,0,0,101,265 +T N,1,35,8,15,4,0,0,0,0,107,265 +T N,1,35,4,15,8,0,0,0,0,65,265 +T N,1,35,8,15,4,0,0,0,0,71,265 +T N,1,35,4,15,8,0,0,0,0,77,265 +T N,1,35,8,15,4,0,0,0,0,83,265 +T N,1,35,4,15,8,0,0,0,0,41,265 +T N,1,35,8,15,4,0,0,0,0,47,265 +T N,1,35,4,15,8,0,0,0,0,53,265 +T N,1,35,8,15,4,0,0,0,0,59,265 +T N,1,35,8,15,4,0,0,0,0,35,265 +T N,1,35,4,15,8,0,0,0,0,29,265 +T N,1,35,8,15,4,0,0,0,0,23,265 +T N,1,35,4,15,8,0,0,0,0,17,265 +T P,1,59,15,17,14,0,0,0,0,131,86 +T P,1,59,14,17,15,0,0,0,0,137,86 +T P,1,60,14,13,7,0,0,0,0,77,85.5 +T P,1,59,15,17,14,0,0,0,0,119,86 +T P,1,59,14,17,15,0,0,0,0,125,86 +T P,1,60,7,13,14,0,0,0,0,83,85.5 +T P,1,60,7,13,14,0,0,0,0,71,85.5 +T P,1,60,14,13,7,0,0,0,0,65,85.5 +T P,1,60,7,12,13,0,0,0,0,59,85.5 +T P,1,60,14,16,7,0,0,0,0,101,85.5 +T P,1,60,7,16,14,0,0,0,0,95,85.5 +T P,1,60,14,16,7,0,0,0,0,89,85.5 +T P,1,60,7,11,5,0,0,0,0,41,85.5 +T P,1,60,12,3,7,0,0,0,0,47,85.5 +T P,1,60,7,16,14,0,0,0,0,107,85.5 +T P,40,3,7,9,4,0,0,0,0,14,91 +T P,1,30,7,4,11,0,0,0,0,29,70.5 +T P,1,60,5,11,7,0,0,0,0,35,85.5 +T P,1,20,7,17,16,0,0,0,0,149,66.5 +T P,1,20,17,1,7,0,0,0,0,155,66.5 +T P,1,80,4,14,6,0,0,0,0,137,180.5 +T P,1,80,6,14,4,0,0,0,0,143,180.5 +T P,1,80,4,14,6,0,0,0,0,149,180.5 +T P,1,80,6,14,4,0,0,0,0,155,180.5 +T P,1,80,4,14,6,0,0,0,0,113,180.5 +T P,1,80,6,14,4,0,0,0,0,119,180.5 +T P,1,80,4,14,6,0,0,0,0,125,180.5 +T P,1,80,6,14,4,0,0,0,0,131,180.5 +T P,1,80,4,14,6,0,0,0,0,89,180.5 +T P,1,80,6,14,4,0,0,0,0,95,180.5 +T P,1,80,4,14,6,0,0,0,0,101,180.5 +T P,1,80,6,14,4,0,0,0,0,107,180.5 +T P,1,80,4,14,6,0,0,0,0,65,180.5 +T P,1,80,6,14,4,0,0,0,0,71,180.5 +T P,1,80,4,14,6,0,0,0,0,77,180.5 +T P,1,80,6,14,4,0,0,0,0,83,180.5 +T P,1,80,4,14,6,0,0,0,0,41,180.5 +T P,1,80,6,14,4,0,0,0,0,47,180.5 +T P,1,80,4,14,6,0,0,0,0,53,180.5 +T P,1,80,6,14,4,0,0,0,0,59,180.5 +T P,1,80,6,14,4,0,0,0,0,35,180.5 +T P,1,80,4,14,6,0,0,0,0,29,180.5 +T P,1,80,6,14,4,0,0,0,0,23,180.5 +T P,1,80,4,14,6,0,0,0,0,17,180.5 +S 17,INTERNAL,0,mbk_sig10 +S 16,INTERNAL,0,mbk_sig12 +S 15,INTERNAL,0,mbk_sig9 +S 14,INTERNAL,0,mbk_sig11 +S 13,INTERNAL,0,mbk_sig6 +S 12,INTERNAL,0,mbk_sig7 +S 11,INTERNAL,0,mbk_sig2 +S 10,INTERNAL,0,mbk_sig15 +S 9,EXTERNAL,0,vssi +S 8,EXTERNAL,0,vsse +S 7,EXTERNAL,0,vddi +S 6,EXTERNAL,0,vdde +S 5,EXTERNAL,0,t +S 4,EXTERNAL,0,pad +S 3,EXTERNAL,0,i +S 2,EXTERNAL,0,ck +S 1,EXTERNAL,0,b +EOF diff --git a/alliance/src/cells/src/padlib/piot_sp.ap b/alliance/src/cells/src/padlib/piot_sp.ap new file mode 100644 index 00000000..9e1d31ee --- /dev/null +++ b/alliance/src/cells/src/padlib/piot_sp.ap @@ -0,0 +1,23 @@ +V ALLIANCE : 3 +H piot_sp,P,23/ 1/95 +A 0,-7,172,493 +C 157,-7,2,b,2,SOUTH,ALU1 +C 157,-7,2,b,3,SOUTH,ALU2 +C 49,-7,2,i,2,SOUTH,ALU1 +C 38,-7,2,t,2,SOUTH,ALU1 +C 49,-7,2,i,3,SOUTH,ALU2 +C 38,-7,2,t,3,SOUTH,ALU2 +C 88,493,1,pad,0,NORTH,ALU1 +C 0,296,120,vsse,0,WEST,ALU2 +C 172,296,120,vsse,1,EAST,ALU2 +C 172,6,12,ck,1,EAST,ALU2 +C 172,40,40,vssi,1,EAST,ALU2 +C 172,84,40,vddi,1,EAST,ALU2 +C 172,168,120,vdde,1,EAST,ALU2 +C 0,6,12,ck,0,WEST,ALU2 +C 0,40,40,vssi,0,WEST,ALU2 +C 0,84,40,vddi,0,WEST,ALU2 +C 0,168,120,vdde,0,WEST,ALU2 +I 0,356,padreal,pad,NOSYM +I 0,-7,paliot_sp,logic,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/piot_sp.vbe b/alliance/src/cells/src/padlib/piot_sp.vbe new file mode 100644 index 00000000..645ca029 --- /dev/null +++ b/alliance/src/cells/src/padlib/piot_sp.vbe @@ -0,0 +1,54 @@ +-- VHDL data flow description generated from `piot_sp` +-- date : Thu Feb 23 17:07:10 1995 + + +-- Entity Declaration + +ENTITY piot_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT rup : NATURAL := 402; -- rup + CONSTANT rdown : NATURAL := 0 -- rdown + ); + PORT ( + i : in BIT; -- i + b : in BIT; -- b + t : out BIT; -- t + pad : inout MUX_BIT BUS; -- pad + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END piot_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF piot_sp IS + SIGNAL b1 : BIT; -- b1 + SIGNAL b2 : BIT; -- b2 + SIGNAL b3 : BIT; -- b3 + SIGNAL b4 : BIT; -- b4 + SIGNAL b5 : BIT; -- b5 + SIGNAL b6 : BIT; -- b6 + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on piot_sp" + SEVERITY WARNING; + + b6 <= b5; + b5 <= b4; + b4 <= b3; + b3 <= b2; + b2 <= b1; + b1 <= b; + label0 : BLOCK (b6 = '1') + BEGIN + pad <= GUARDED i; + END BLOCK label0; + +t <= pad; +END; diff --git a/alliance/src/cells/src/padlib/piotw_sp.al b/alliance/src/cells/src/padlib/piotw_sp.al new file mode 100644 index 00000000..0e62cb08 --- /dev/null +++ b/alliance/src/cells/src/padlib/piotw_sp.al @@ -0,0 +1,94 @@ +V ALLIANCE : 4 +H piotw_sp,L,23/ 2/95 +C i,UNKNOWN,EXTERNAL,3 +C b,UNKNOWN,EXTERNAL,1 +C t,UNKNOWN,EXTERNAL,5 +C pad,UNKNOWN,EXTERNAL,4 +C ck,UNKNOWN,EXTERNAL,2 +C vdde,UNKNOWN,EXTERNAL,6 +C vddi,UNKNOWN,EXTERNAL,7 +C vsse,UNKNOWN,EXTERNAL,8 +C vssi,UNKNOWN,EXTERNAL,9 +T N,1,10,9,17,16,0,0,0,0,149,30.5 +T N,1,10,17,1,9,0,0,0,0,155,30.5 +T N,1,29,14,16,15,0,0,0,0,119,20 +T N,1,29,15,16,14,0,0,0,0,125,20 +T N,1,29,14,16,15,0,0,0,0,131,20 +T N,1,29,15,16,14,0,0,0,0,137,20 +T N,1,30,9,13,15,0,0,0,0,83,20.5 +T N,1,30,15,13,9,0,0,0,0,77,20.5 +T N,1,30,9,13,15,0,0,0,0,71,20.5 +T N,1,30,15,13,9,0,0,0,0,65,20.5 +T N,1,30,9,12,13,0,0,0,0,59,20.5 +T N,1,30,15,17,9,0,0,0,0,89,20.5 +T N,1,30,9,17,15,0,0,0,0,107,20.5 +T N,1,30,12,3,9,0,0,0,0,47,20.5 +T N,1,30,15,17,9,0,0,0,0,101,20.5 +T N,1,30,9,17,15,0,0,0,0,95,20.5 +T N,1,30,9,4,11,0,0,0,0,29,20.5 +T N,1,30,5,11,9,0,0,0,0,35,20.5 +T N,1,30,9,11,5,0,0,0,0,41,20.5 +T N,1,30,9,4,11,0,0,0,0,17,20.5 +T N,1,30,11,4,9,0,0,0,0,23,20.5 +T N,1,35,4,15,8,0,0,0,0,92,265 +T N,1,35,8,15,4,0,0,0,0,98,265 +T N,1,35,4,15,8,0,0,0,0,104,265 +T N,1,35,8,15,4,0,0,0,0,110,265 +T N,1,35,4,15,8,0,0,0,0,68,265 +T N,1,35,8,15,4,0,0,0,0,74,265 +T N,1,35,4,15,8,0,0,0,0,80,265 +T N,1,35,8,15,4,0,0,0,0,86,265 +T N,1,35,8,15,4,0,0,0,0,62,265 +T N,1,35,4,15,8,0,0,0,0,56,265 +T N,1,35,8,15,4,0,0,0,0,50,265 +T N,1,35,4,15,8,0,0,0,0,44,265 +T P,1,59,15,17,14,0,0,0,0,131,86 +T P,1,59,14,17,15,0,0,0,0,137,86 +T P,1,60,7,13,14,0,0,0,0,83,85.5 +T P,1,60,14,13,7,0,0,0,0,77,85.5 +T P,1,59,15,17,14,0,0,0,0,119,86 +T P,1,59,14,17,15,0,0,0,0,125,86 +T P,1,60,7,12,13,0,0,0,0,59,85.5 +T P,1,60,7,13,14,0,0,0,0,71,85.5 +T P,1,60,14,13,7,0,0,0,0,65,85.5 +T P,1,60,7,16,14,0,0,0,0,107,85.5 +T P,1,60,14,16,7,0,0,0,0,101,85.5 +T P,1,60,7,16,14,0,0,0,0,95,85.5 +T P,1,60,14,16,7,0,0,0,0,89,85.5 +T P,1,60,5,11,7,0,0,0,0,35,85.5 +T P,1,60,7,11,5,0,0,0,0,41,85.5 +T P,1,60,12,3,7,0,0,0,0,47,85.5 +T P,40,3,7,9,4,0,0,0,0,14,91 +T P,1,30,7,4,11,0,0,0,0,29,70.5 +T P,1,20,7,17,16,0,0,0,0,149,66.5 +T P,1,20,17,1,7,0,0,0,0,155,66.5 +T P,1,80,4,14,6,0,0,0,0,92,180.5 +T P,1,80,6,14,4,0,0,0,0,98,180.5 +T P,1,80,4,14,6,0,0,0,0,104,180.5 +T P,1,80,6,14,4,0,0,0,0,110,180.5 +T P,1,80,4,14,6,0,0,0,0,68,180.5 +T P,1,80,6,14,4,0,0,0,0,74,180.5 +T P,1,80,4,14,6,0,0,0,0,80,180.5 +T P,1,80,6,14,4,0,0,0,0,86,180.5 +T P,1,80,6,14,4,0,0,0,0,62,180.5 +T P,1,80,4,14,6,0,0,0,0,56,180.5 +T P,1,80,6,14,4,0,0,0,0,50,180.5 +T P,1,80,4,14,6,0,0,0,0,44,180.5 +S 17,INTERNAL,0,mbk_sig10 +S 16,INTERNAL,0,mbk_sig12 +S 15,INTERNAL,0,mbk_sig9 +S 14,INTERNAL,0,mbk_sig11 +S 13,INTERNAL,0,mbk_sig6 +S 12,INTERNAL,0,mbk_sig7 +S 11,INTERNAL,0,mbk_sig2 +S 10,INTERNAL,0,mbk_sig15 +S 9,EXTERNAL,0,vssi +S 8,EXTERNAL,0,vsse +S 7,EXTERNAL,0,vddi +S 6,EXTERNAL,0,vdde +S 5,EXTERNAL,0,t +S 4,EXTERNAL,0,pad +S 3,EXTERNAL,0,i +S 2,EXTERNAL,0,ck +S 1,EXTERNAL,0,b +EOF diff --git a/alliance/src/cells/src/padlib/piotw_sp.ap b/alliance/src/cells/src/padlib/piotw_sp.ap new file mode 100644 index 00000000..6ae120d9 --- /dev/null +++ b/alliance/src/cells/src/padlib/piotw_sp.ap @@ -0,0 +1,23 @@ +V ALLIANCE : 3 +H piotw_sp,P,23/ 1/95 +A 0,-7,172,493 +C 157,-7,2,b,2,SOUTH,ALU1 +C 157,-7,2,b,3,SOUTH,ALU2 +C 49,-7,2,i,2,SOUTH,ALU1 +C 49,-7,2,i,3,SOUTH,ALU2 +C 38,-7,2,t,2,SOUTH,ALU1 +C 38,-7,2,t,3,SOUTH,ALU2 +C 88,493,1,pad,0,NORTH,ALU1 +C 172,296,120,vsse,1,EAST,ALU2 +C 0,296,120,vsse,0,WEST,ALU2 +C 0,168,120,vdde,0,WEST,ALU2 +C 0,84,40,vddi,0,WEST,ALU2 +C 0,40,40,vssi,0,WEST,ALU2 +C 0,6,12,ck,0,WEST,ALU2 +C 172,168,120,vdde,1,EAST,ALU2 +C 172,84,40,vddi,1,EAST,ALU2 +C 172,40,40,vssi,1,EAST,ALU2 +C 172,6,12,ck,1,EAST,ALU2 +I 0,356,padreal,pad,NOSYM +I 0,-7,paliotw_sp,logic,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/piotw_sp.vbe b/alliance/src/cells/src/padlib/piotw_sp.vbe new file mode 100644 index 00000000..4dcd59df --- /dev/null +++ b/alliance/src/cells/src/padlib/piotw_sp.vbe @@ -0,0 +1,54 @@ +-- VHDL data flow description generated from `piotw_sp` +-- date : Thu Feb 23 17:07:47 1995 + + +-- Entity Declaration + +ENTITY piotw_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT rup : NATURAL := 402; -- rup + CONSTANT rdown : NATURAL := 0 -- rdown + ); + PORT ( + i : in BIT; -- i + b : in BIT; -- b + t : out BIT; -- t + pad : inout MUX_BIT BUS; -- pad + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END piotw_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF piotw_sp IS + SIGNAL b1 : BIT; -- b1 + SIGNAL b2 : BIT; -- b2 + SIGNAL b3 : BIT; -- b3 + SIGNAL b4 : BIT; -- b4 + SIGNAL b5 : BIT; -- b5 + SIGNAL b6 : BIT; -- b6 + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on piotw_sp" + SEVERITY WARNING; + + b6 <= b5; + b5 <= b4; + b4 <= b3; + b3 <= b2; + b2 <= b1; + b1 <= b; + label0 : BLOCK (b6 = '1') + BEGIN + pad <= GUARDED i; + END BLOCK label0; + +t <= pad; +END; diff --git a/alliance/src/cells/src/padlib/po_sp.al b/alliance/src/cells/src/padlib/po_sp.al new file mode 100644 index 00000000..dc58d26d --- /dev/null +++ b/alliance/src/cells/src/padlib/po_sp.al @@ -0,0 +1,80 @@ +V ALLIANCE : 4 +H po_sp,L,23/ 2/95 +C i,UNKNOWN,EXTERNAL,2 +C pad,UNKNOWN,EXTERNAL,3 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,4 +C vddi,UNKNOWN,EXTERNAL,5 +C vsse,UNKNOWN,EXTERNAL,6 +C vssi,UNKNOWN,EXTERNAL,7 +T N,1,30,10,2,7,0,0,0,0,45,20.5 +T N,1,30,7,10,9,0,0,0,0,57,20.5 +T N,1,30,8,9,7,0,0,0,0,63,20.5 +T N,1,30,7,9,8,0,0,0,0,69,20.5 +T N,1,30,8,9,7,0,0,0,0,75,20.5 +T N,1,30,7,9,8,0,0,0,0,81,20.5 +T N,1,35,3,8,6,0,0,0,0,17,265 +T N,1,35,6,8,3,0,0,0,0,23,265 +T N,1,35,3,8,6,0,0,0,0,29,265 +T N,1,35,6,8,3,0,0,0,0,35,265 +T N,1,35,3,8,6,0,0,0,0,41,265 +T N,1,35,6,8,3,0,0,0,0,47,265 +T N,1,35,3,8,6,0,0,0,0,53,265 +T N,1,35,6,8,3,0,0,0,0,59,265 +T N,1,35,3,8,6,0,0,0,0,65,265 +T N,1,35,6,8,3,0,0,0,0,71,265 +T N,1,35,3,8,6,0,0,0,0,77,265 +T N,1,35,6,8,3,0,0,0,0,83,265 +T N,1,35,3,8,6,0,0,0,0,89,265 +T N,1,35,6,8,3,0,0,0,0,95,265 +T N,1,35,3,8,6,0,0,0,0,101,265 +T N,1,35,6,8,3,0,0,0,0,107,265 +T N,1,35,3,8,6,0,0,0,0,113,265 +T N,1,35,6,8,3,0,0,0,0,119,265 +T N,1,35,3,8,6,0,0,0,0,125,265 +T N,1,35,6,8,3,0,0,0,0,131,265 +T N,1,35,3,8,6,0,0,0,0,137,265 +T N,1,35,6,8,3,0,0,0,0,143,265 +T N,1,35,3,8,6,0,0,0,0,149,265 +T N,1,35,6,8,3,0,0,0,0,155,265 +T P,1,60,10,2,5,0,0,0,0,45,85.5 +T P,1,60,5,9,8,0,0,0,0,69,85.5 +T P,1,60,5,10,9,0,0,0,0,57,85.5 +T P,1,60,8,9,5,0,0,0,0,63,85.5 +T P,1,60,8,9,5,0,0,0,0,75,85.5 +T P,1,60,5,9,8,0,0,0,0,81,85.5 +T P,1,80,3,8,4,0,0,0,0,17,180.5 +T P,1,80,4,8,3,0,0,0,0,23,180.5 +T P,1,80,3,8,4,0,0,0,0,29,180.5 +T P,1,80,4,8,3,0,0,0,0,35,180.5 +T P,1,80,3,8,4,0,0,0,0,41,180.5 +T P,1,80,4,8,3,0,0,0,0,47,180.5 +T P,1,80,3,8,4,0,0,0,0,53,180.5 +T P,1,80,4,8,3,0,0,0,0,59,180.5 +T P,1,80,3,8,4,0,0,0,0,65,180.5 +T P,1,80,4,8,3,0,0,0,0,71,180.5 +T P,1,80,3,8,4,0,0,0,0,77,180.5 +T P,1,80,4,8,3,0,0,0,0,83,180.5 +T P,1,80,3,8,4,0,0,0,0,89,180.5 +T P,1,80,4,8,3,0,0,0,0,95,180.5 +T P,1,80,3,8,4,0,0,0,0,101,180.5 +T P,1,80,4,8,3,0,0,0,0,107,180.5 +T P,1,80,3,8,4,0,0,0,0,113,180.5 +T P,1,80,4,8,3,0,0,0,0,119,180.5 +T P,1,80,3,8,4,0,0,0,0,125,180.5 +T P,1,80,4,8,3,0,0,0,0,131,180.5 +T P,1,80,3,8,4,0,0,0,0,137,180.5 +T P,1,80,4,8,3,0,0,0,0,143,180.5 +T P,1,80,3,8,4,0,0,0,0,149,180.5 +T P,1,80,4,8,3,0,0,0,0,155,180.5 +S 10,INTERNAL,0,mbk_sig3 +S 9,INTERNAL,0,mbk_sig4 +S 8,INTERNAL,0,mbk_sig6 +S 7,EXTERNAL,0,vssi +S 6,EXTERNAL,0,vsse +S 5,EXTERNAL,0,vddi +S 4,EXTERNAL,0,vdde +S 3,EXTERNAL,0,pad +S 2,EXTERNAL,0,i +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/po_sp.ap b/alliance/src/cells/src/padlib/po_sp.ap new file mode 100644 index 00000000..d6f6cc34 --- /dev/null +++ b/alliance/src/cells/src/padlib/po_sp.ap @@ -0,0 +1,19 @@ +V ALLIANCE : 3 +H po_sp,P,30/ 0/95 +A 0,-7,172,493 +C 172,6,12,ck,1,EAST,ALU2 +C 172,40,40,vssi,1,EAST,ALU2 +C 172,84,40,vddi,1,EAST,ALU2 +C 172,168,120,vdde,1,EAST,ALU2 +C 0,168,120,vdde,0,WEST,ALU2 +C 0,84,40,vddi,0,WEST,ALU2 +C 0,6,12,ck,0,WEST,ALU2 +C 0,40,40,vssi,0,WEST,ALU2 +C 47,-7,2,i,1,SOUTH,ALU2 +C 47,-7,2,i,0,SOUTH,ALU1 +C 88,493,1,pad,0,NORTH,ALU1 +C 172,296,120,vsse,1,EAST,ALU2 +C 0,296,120,vsse,0,WEST,ALU2 +I 0,-7,palo_sp,logic,NOSYM +I 0,356,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/po_sp.vbe b/alliance/src/cells/src/padlib/po_sp.vbe new file mode 100644 index 00000000..b646800d --- /dev/null +++ b/alliance/src/cells/src/padlib/po_sp.vbe @@ -0,0 +1,39 @@ +-- VHDL data flow description generated from `po_sp` +-- date : Thu Feb 23 17:08:20 1995 + + +-- Entity Declaration + +ENTITY po_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_i : NATURAL := 191; -- cin_i + CONSTANT tpll_i : NATURAL := 2176; -- tpll_i + CONSTANT rdown_i : NATURAL := 15; -- rdown_i + CONSTANT tphh_i : NATURAL := 2032; -- tphh_i + CONSTANT rup_i : NATURAL := 16 -- rup_i + ); + PORT ( + i : in BIT; -- i + pad : out BIT; -- pad + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END po_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF po_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on po_sp" + SEVERITY WARNING; + + +pad <= i; +END; diff --git a/alliance/src/cells/src/padlib/pot_sp.al b/alliance/src/cells/src/padlib/pot_sp.al new file mode 100644 index 00000000..814c64f8 --- /dev/null +++ b/alliance/src/cells/src/padlib/pot_sp.al @@ -0,0 +1,107 @@ +V ALLIANCE : 4 +H pot_sp,L,23/ 2/95 +C i,UNKNOWN,EXTERNAL,3 +C b,UNKNOWN,EXTERNAL,1 +C pad,UNKNOWN,EXTERNAL,4 +C ck,UNKNOWN,EXTERNAL,2 +C vdde,UNKNOWN,EXTERNAL,5 +C vddi,UNKNOWN,EXTERNAL,6 +C vsse,UNKNOWN,EXTERNAL,7 +C vssi,UNKNOWN,EXTERNAL,8 +T N,1,30,15,3,8,0,0,0,0,44,20.5 +T N,1,30,13,14,8,0,0,0,0,98,20.5 +T N,1,30,8,14,13,0,0,0,0,92,20.5 +T N,1,30,13,14,8,0,0,0,0,86,20.5 +T N,1,30,8,14,13,0,0,0,0,104,20.5 +T N,1,30,8,12,13,0,0,0,0,68,20.5 +T N,1,30,13,12,8,0,0,0,0,62,20.5 +T N,1,30,8,15,12,0,0,0,0,56,20.5 +T N,1,30,8,12,13,0,0,0,0,80,20.5 +T N,1,30,13,12,8,0,0,0,0,74,20.5 +T N,1,29,10,11,13,0,0,0,0,116,20 +T N,1,29,13,11,10,0,0,0,0,122,20 +T N,1,29,10,11,13,0,0,0,0,128,20 +T N,1,29,13,11,10,0,0,0,0,134,20 +T N,1,10,14,1,8,0,0,0,0,152,30.5 +T N,1,10,8,14,11,0,0,0,0,146,30.5 +T N,1,35,4,13,7,0,0,0,0,137,265 +T N,1,35,7,13,4,0,0,0,0,143,265 +T N,1,35,4,13,7,0,0,0,0,149,265 +T N,1,35,7,13,4,0,0,0,0,155,265 +T N,1,35,4,13,7,0,0,0,0,113,265 +T N,1,35,7,13,4,0,0,0,0,119,265 +T N,1,35,4,13,7,0,0,0,0,125,265 +T N,1,35,7,13,4,0,0,0,0,131,265 +T N,1,35,4,13,7,0,0,0,0,89,265 +T N,1,35,7,13,4,0,0,0,0,95,265 +T N,1,35,4,13,7,0,0,0,0,101,265 +T N,1,35,7,13,4,0,0,0,0,107,265 +T N,1,35,4,13,7,0,0,0,0,65,265 +T N,1,35,7,13,4,0,0,0,0,71,265 +T N,1,35,4,13,7,0,0,0,0,77,265 +T N,1,35,7,13,4,0,0,0,0,83,265 +T N,1,35,4,13,7,0,0,0,0,41,265 +T N,1,35,7,13,4,0,0,0,0,47,265 +T N,1,35,4,13,7,0,0,0,0,53,265 +T N,1,35,7,13,4,0,0,0,0,59,265 +T N,1,35,7,13,4,0,0,0,0,35,265 +T N,1,35,4,13,7,0,0,0,0,29,265 +T N,1,35,7,13,4,0,0,0,0,23,265 +T N,1,35,4,13,7,0,0,0,0,17,265 +T P,40,3,6,8,4,0,0,0,0,27,91 +T P,1,20,6,14,11,0,0,0,0,146,66.5 +T P,1,20,14,1,6,0,0,0,0,152,66.5 +T P,1,60,15,3,6,0,0,0,0,44,85.5 +T P,1,60,6,11,10,0,0,0,0,104,85.5 +T P,1,60,10,11,6,0,0,0,0,98,85.5 +T P,1,60,6,11,10,0,0,0,0,92,85.5 +T P,1,60,10,11,6,0,0,0,0,86,85.5 +T P,1,60,6,12,10,0,0,0,0,68,85.5 +T P,1,60,10,12,6,0,0,0,0,62,85.5 +T P,1,60,6,15,12,0,0,0,0,56,85.5 +T P,1,60,6,12,10,0,0,0,0,80,85.5 +T P,1,60,10,12,6,0,0,0,0,74,85.5 +T P,1,59,13,14,10,0,0,0,0,116,86 +T P,1,59,10,14,13,0,0,0,0,122,86 +T P,1,59,13,14,10,0,0,0,0,128,86 +T P,1,59,10,14,13,0,0,0,0,134,86 +T P,1,80,4,10,5,0,0,0,0,137,180.5 +T P,1,80,5,10,4,0,0,0,0,143,180.5 +T P,1,80,4,10,5,0,0,0,0,149,180.5 +T P,1,80,5,10,4,0,0,0,0,155,180.5 +T P,1,80,4,10,5,0,0,0,0,113,180.5 +T P,1,80,5,10,4,0,0,0,0,119,180.5 +T P,1,80,4,10,5,0,0,0,0,125,180.5 +T P,1,80,5,10,4,0,0,0,0,131,180.5 +T P,1,80,4,10,5,0,0,0,0,89,180.5 +T P,1,80,5,10,4,0,0,0,0,95,180.5 +T P,1,80,4,10,5,0,0,0,0,101,180.5 +T P,1,80,5,10,4,0,0,0,0,107,180.5 +T P,1,80,4,10,5,0,0,0,0,65,180.5 +T P,1,80,5,10,4,0,0,0,0,71,180.5 +T P,1,80,4,10,5,0,0,0,0,77,180.5 +T P,1,80,5,10,4,0,0,0,0,83,180.5 +T P,1,80,4,10,5,0,0,0,0,41,180.5 +T P,1,80,5,10,4,0,0,0,0,47,180.5 +T P,1,80,4,10,5,0,0,0,0,53,180.5 +T P,1,80,5,10,4,0,0,0,0,59,180.5 +T P,1,80,5,10,4,0,0,0,0,35,180.5 +T P,1,80,4,10,5,0,0,0,0,29,180.5 +T P,1,80,5,10,4,0,0,0,0,23,180.5 +T P,1,80,4,10,5,0,0,0,0,17,180.5 +S 15,INTERNAL,0,mbk_sig4 +S 14,INTERNAL,0,mbk_sig7 +S 13,INTERNAL,0,mbk_sig6 +S 12,INTERNAL,0,mbk_sig3 +S 11,INTERNAL,0,mbk_sig9 +S 10,INTERNAL,0,mbk_sig8 +S 9,INTERNAL,0,mbk_sig12 +S 8,EXTERNAL,0,vssi +S 7,EXTERNAL,0,vsse +S 6,EXTERNAL,0,vddi +S 5,EXTERNAL,0,vdde +S 4,EXTERNAL,0,pad +S 3,EXTERNAL,0,i +S 2,EXTERNAL,0,ck +S 1,EXTERNAL,0,b +EOF diff --git a/alliance/src/cells/src/padlib/pot_sp.ap b/alliance/src/cells/src/padlib/pot_sp.ap new file mode 100644 index 00000000..f43040f1 --- /dev/null +++ b/alliance/src/cells/src/padlib/pot_sp.ap @@ -0,0 +1,21 @@ +V ALLIANCE : 3 +H pot_sp,P,30/ 0/95 +A 0,-7,172,493 +C 154,-7,2,b,0,SOUTH,ALU1 +C 154,-7,2,b,1,SOUTH,ALU2 +C 46,-7,2,i,0,SOUTH,ALU1 +C 46,-7,2,i,1,SOUTH,ALU2 +C 0,168,120,vdde,0,WEST,ALU2 +C 0,84,40,vddi,0,WEST,ALU2 +C 0,40,40,vssi,0,WEST,ALU2 +C 0,6,12,ck,0,WEST,ALU2 +C 172,168,120,vdde,1,EAST,ALU2 +C 172,84,40,vddi,1,EAST,ALU2 +C 172,40,40,vssi,1,EAST,ALU2 +C 172,6,12,ck,1,EAST,ALU2 +C 172,296,120,vsse,1,EAST,ALU2 +C 0,296,120,vsse,0,WEST,ALU2 +C 88,493,1,pad,0,NORTH,ALU1 +I 0,-7,palot_sp,logic,NOSYM +I 0,356,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pot_sp.vbe b/alliance/src/cells/src/padlib/pot_sp.vbe new file mode 100644 index 00000000..578b57bc --- /dev/null +++ b/alliance/src/cells/src/padlib/pot_sp.vbe @@ -0,0 +1,51 @@ +-- VHDL data flow description generated from `pot_sp` +-- date : Thu Feb 23 17:09:25 1995 + + +-- Entity Declaration + +ENTITY pot_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT rup : NATURAL := 684404; -- rup + CONSTANT rdown : NATURAL := 24 -- rdown + ); + PORT ( + i : in BIT; -- i + b : in BIT; -- b + pad : out MUX_BIT BUS; -- pad + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pot_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pot_sp IS + SIGNAL b1 : BIT; -- b1 + SIGNAL b2 : BIT; -- b2 + SIGNAL b3 : BIT; -- b3 + SIGNAL b4 : BIT; -- b4 + SIGNAL b5 : BIT; -- b5 + SIGNAL b6 : BIT; -- b6 + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pot_sp" + SEVERITY WARNING; + + b6 <= b5; + b5 <= b4; + b4 <= b3; + b3 <= b2; + b2 <= b1; + b1 <= b; + label0 : BLOCK (b6 = '1') + BEGIN + pad <= GUARDED i; + END BLOCK label0; +END; diff --git a/alliance/src/cells/src/padlib/potw_sp.al b/alliance/src/cells/src/padlib/potw_sp.al new file mode 100644 index 00000000..4eb9a3ee --- /dev/null +++ b/alliance/src/cells/src/padlib/potw_sp.al @@ -0,0 +1,83 @@ +V ALLIANCE : 4 +H potw_sp,L,23/ 2/95 +C i,UNKNOWN,EXTERNAL,3 +C b,UNKNOWN,EXTERNAL,1 +C pad,UNKNOWN,EXTERNAL,4 +C ck,UNKNOWN,EXTERNAL,2 +C vdde,UNKNOWN,EXTERNAL,5 +C vddi,UNKNOWN,EXTERNAL,6 +C vsse,UNKNOWN,EXTERNAL,7 +C vssi,UNKNOWN,EXTERNAL,8 +T N,1,10,8,15,14,0,0,0,0,146,30.5 +T N,1,10,15,1,8,0,0,0,0,152,30.5 +T N,1,29,12,14,13,0,0,0,0,134,20 +T N,1,29,13,14,12,0,0,0,0,128,20 +T N,1,29,12,14,13,0,0,0,0,122,20 +T N,1,29,13,14,12,0,0,0,0,116,20 +T N,1,30,12,11,8,0,0,0,0,74,20.5 +T N,1,30,8,11,12,0,0,0,0,80,20.5 +T N,1,30,8,10,11,0,0,0,0,56,20.5 +T N,1,30,12,11,8,0,0,0,0,62,20.5 +T N,1,30,8,11,12,0,0,0,0,68,20.5 +T N,1,30,8,15,12,0,0,0,0,104,20.5 +T N,1,30,12,15,8,0,0,0,0,86,20.5 +T N,1,30,8,15,12,0,0,0,0,92,20.5 +T N,1,30,12,15,8,0,0,0,0,98,20.5 +T N,1,30,10,3,8,0,0,0,0,44,20.5 +T N,1,35,7,12,4,0,0,0,0,62,265 +T N,1,35,4,12,7,0,0,0,0,56,265 +T N,1,35,7,12,4,0,0,0,0,50,265 +T N,1,35,4,12,7,0,0,0,0,44,265 +T N,1,35,4,12,7,0,0,0,0,68,265 +T N,1,35,7,12,4,0,0,0,0,74,265 +T N,1,35,4,12,7,0,0,0,0,80,265 +T N,1,35,7,12,4,0,0,0,0,86,265 +T N,1,35,4,12,7,0,0,0,0,92,265 +T N,1,35,7,12,4,0,0,0,0,98,265 +T N,1,35,4,12,7,0,0,0,0,104,265 +T N,1,35,7,12,4,0,0,0,0,110,265 +T P,1,59,13,15,12,0,0,0,0,134,86 +T P,1,59,12,15,13,0,0,0,0,128,86 +T P,1,59,13,15,12,0,0,0,0,122,86 +T P,1,59,12,15,13,0,0,0,0,116,86 +T P,1,60,13,11,6,0,0,0,0,74,85.5 +T P,1,60,6,11,13,0,0,0,0,80,85.5 +T P,1,60,6,10,11,0,0,0,0,56,85.5 +T P,1,60,13,11,6,0,0,0,0,62,85.5 +T P,1,60,6,11,13,0,0,0,0,68,85.5 +T P,1,60,13,14,6,0,0,0,0,86,85.5 +T P,1,60,6,14,13,0,0,0,0,92,85.5 +T P,1,60,13,14,6,0,0,0,0,98,85.5 +T P,1,60,6,14,13,0,0,0,0,104,85.5 +T P,1,60,10,3,6,0,0,0,0,44,85.5 +T P,1,20,15,1,6,0,0,0,0,152,66.5 +T P,1,20,6,15,14,0,0,0,0,146,66.5 +T P,40,3,6,8,4,0,0,0,0,27,91 +T P,1,80,5,13,4,0,0,0,0,62,180.5 +T P,1,80,4,13,5,0,0,0,0,56,180.5 +T P,1,80,5,13,4,0,0,0,0,50,180.5 +T P,1,80,4,13,5,0,0,0,0,44,180.5 +T P,1,80,4,13,5,0,0,0,0,68,180.5 +T P,1,80,5,13,4,0,0,0,0,74,180.5 +T P,1,80,4,13,5,0,0,0,0,80,180.5 +T P,1,80,5,13,4,0,0,0,0,86,180.5 +T P,1,80,4,13,5,0,0,0,0,92,180.5 +T P,1,80,5,13,4,0,0,0,0,98,180.5 +T P,1,80,4,13,5,0,0,0,0,104,180.5 +T P,1,80,5,13,4,0,0,0,0,110,180.5 +S 15,INTERNAL,0,mbk_sig7 +S 14,INTERNAL,0,mbk_sig9 +S 13,INTERNAL,0,mbk_sig8 +S 12,INTERNAL,0,mbk_sig6 +S 11,INTERNAL,0,mbk_sig4 +S 10,INTERNAL,0,mbk_sig3 +S 9,INTERNAL,0,mbk_sig12 +S 8,EXTERNAL,0,vssi +S 7,EXTERNAL,0,vsse +S 6,EXTERNAL,0,vddi +S 5,EXTERNAL,0,vdde +S 4,EXTERNAL,0,pad +S 3,EXTERNAL,0,i +S 2,EXTERNAL,0,ck +S 1,EXTERNAL,0,b +EOF diff --git a/alliance/src/cells/src/padlib/potw_sp.ap b/alliance/src/cells/src/padlib/potw_sp.ap new file mode 100644 index 00000000..82e16248 --- /dev/null +++ b/alliance/src/cells/src/padlib/potw_sp.ap @@ -0,0 +1,21 @@ +V ALLIANCE : 3 +H potw_sp,P,30/ 0/95 +A 0,-7,172,493 +C 154,-7,2,b,0,SOUTH,ALU1 +C 154,-7,2,b,1,SOUTH,ALU2 +C 46,-7,2,i,1,SOUTH,ALU2 +C 46,-7,2,i,0,SOUTH,ALU1 +C 172,6,12,ck,1,EAST,ALU2 +C 172,40,40,vssi,1,EAST,ALU2 +C 172,84,40,vddi,1,EAST,ALU2 +C 172,168,120,vdde,1,EAST,ALU2 +C 0,6,12,ck,0,WEST,ALU2 +C 0,40,40,vssi,0,WEST,ALU2 +C 0,84,40,vddi,0,WEST,ALU2 +C 0,168,120,vdde,0,WEST,ALU2 +C 0,296,120,vsse,0,WEST,ALU2 +C 172,296,120,vsse,1,EAST,ALU2 +C 88,493,1,pad,0,NORTH,ALU1 +I 0,-7,palotw_sp,logic,NOSYM +I 0,356,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/potw_sp.vbe b/alliance/src/cells/src/padlib/potw_sp.vbe new file mode 100644 index 00000000..bd7513d3 --- /dev/null +++ b/alliance/src/cells/src/padlib/potw_sp.vbe @@ -0,0 +1,51 @@ +-- VHDL data flow description generated from `potw_sp` +-- date : Thu Feb 23 17:09:58 1995 + + +-- Entity Declaration + +ENTITY potw_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT rup : NATURAL := 684404; -- rup + CONSTANT rdown : NATURAL := 49 -- rdown + ); + PORT ( + i : in BIT; -- i + b : in BIT; -- b + pad : out MUX_BIT BUS; -- pad + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END potw_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF potw_sp IS + SIGNAL b1 : BIT; -- b1 + SIGNAL b2 : BIT; -- b2 + SIGNAL b3 : BIT; -- b3 + SIGNAL b4 : BIT; -- b4 + SIGNAL b5 : BIT; -- b5 + SIGNAL b6 : BIT; -- b6 + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on potw_sp" + SEVERITY WARNING; + + b6 <= b5; + b5 <= b4; + b4 <= b3; + b3 <= b2; + b2 <= b1; + b1 <= b; + label0 : BLOCK (b6 = '1') + BEGIN + pad <= GUARDED i; + END BLOCK label0; +END; diff --git a/alliance/src/cells/src/padlib/pow_sp.al b/alliance/src/cells/src/padlib/pow_sp.al new file mode 100644 index 00000000..50f28c09 --- /dev/null +++ b/alliance/src/cells/src/padlib/pow_sp.al @@ -0,0 +1,56 @@ +V ALLIANCE : 4 +H pow_sp,L,23/ 2/95 +C i,UNKNOWN,EXTERNAL,2 +C pad,UNKNOWN,EXTERNAL,3 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,4 +C vddi,UNKNOWN,EXTERNAL,5 +C vsse,UNKNOWN,EXTERNAL,6 +C vssi,UNKNOWN,EXTERNAL,7 +T N,1,30,7,10,9,0,0,0,0,85,20.5 +T N,1,30,10,2,7,0,0,0,0,73,20.5 +T N,1,30,8,9,7,0,0,0,0,103,20.5 +T N,1,30,7,9,8,0,0,0,0,97,20.5 +T N,1,30,8,9,7,0,0,0,0,91,20.5 +T N,1,30,7,9,8,0,0,0,0,109,20.5 +T N,1,35,3,8,6,0,0,0,0,56,265 +T N,1,35,6,8,3,0,0,0,0,62,265 +T N,1,35,3,8,6,0,0,0,0,68,265 +T N,1,35,6,8,3,0,0,0,0,74,265 +T N,1,35,3,8,6,0,0,0,0,104,265 +T N,1,35,6,8,3,0,0,0,0,110,265 +T N,1,35,3,8,6,0,0,0,0,116,265 +T N,1,35,6,8,3,0,0,0,0,122,265 +T N,1,35,3,8,6,0,0,0,0,80,265 +T N,1,35,6,8,3,0,0,0,0,86,265 +T N,1,35,3,8,6,0,0,0,0,92,265 +T N,1,35,6,8,3,0,0,0,0,98,265 +T P,1,60,5,9,8,0,0,0,0,97,85.5 +T P,1,60,10,2,5,0,0,0,0,73,85.5 +T P,1,60,8,9,5,0,0,0,0,103,85.5 +T P,1,60,8,9,5,0,0,0,0,91,85.5 +T P,1,60,5,10,9,0,0,0,0,85,85.5 +T P,1,60,5,9,8,0,0,0,0,109,85.5 +T P,1,80,3,8,4,0,0,0,0,56,180.5 +T P,1,80,4,8,3,0,0,0,0,62,180.5 +T P,1,80,3,8,4,0,0,0,0,68,180.5 +T P,1,80,4,8,3,0,0,0,0,74,180.5 +T P,1,80,3,8,4,0,0,0,0,104,180.5 +T P,1,80,4,8,3,0,0,0,0,110,180.5 +T P,1,80,3,8,4,0,0,0,0,116,180.5 +T P,1,80,4,8,3,0,0,0,0,122,180.5 +T P,1,80,3,8,4,0,0,0,0,80,180.5 +T P,1,80,4,8,3,0,0,0,0,86,180.5 +T P,1,80,3,8,4,0,0,0,0,92,180.5 +T P,1,80,4,8,3,0,0,0,0,98,180.5 +S 10,INTERNAL,0,mbk_sig5 +S 9,INTERNAL,0,mbk_sig4 +S 8,INTERNAL,0,mbk_sig3 +S 7,EXTERNAL,0,vssi +S 6,EXTERNAL,0,vsse +S 5,EXTERNAL,0,vddi +S 4,EXTERNAL,0,vdde +S 3,EXTERNAL,0,pad +S 2,EXTERNAL,0,i +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pow_sp.ap b/alliance/src/cells/src/padlib/pow_sp.ap new file mode 100644 index 00000000..e9c8e663 --- /dev/null +++ b/alliance/src/cells/src/padlib/pow_sp.ap @@ -0,0 +1,19 @@ +V ALLIANCE : 3 +H pow_sp,P,30/ 0/95 +A 0,-7,172,493 +C 75,-7,2,i,0,SOUTH,ALU1 +C 75,-7,2,i,1,SOUTH,ALU2 +C 172,6,12,ck,1,EAST,ALU2 +C 172,40,40,vssi,1,EAST,ALU2 +C 172,84,40,vddi,1,EAST,ALU2 +C 172,168,120,vdde,1,EAST,ALU2 +C 0,168,120,vdde,0,WEST,ALU2 +C 0,84,40,vddi,0,WEST,ALU2 +C 0,6,12,ck,0,WEST,ALU2 +C 0,40,40,vssi,0,WEST,ALU2 +C 0,296,120,vsse,0,WEST,ALU2 +C 172,296,120,vsse,1,EAST,ALU2 +C 88,493,1,pad,0,NORTH,ALU1 +I 0,-7,palow_sp,logic,NOSYM +I 0,356,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pow_sp.vbe b/alliance/src/cells/src/padlib/pow_sp.vbe new file mode 100644 index 00000000..ffbb6455 --- /dev/null +++ b/alliance/src/cells/src/padlib/pow_sp.vbe @@ -0,0 +1,39 @@ +-- VHDL data flow description generated from `pow_sp` +-- date : Thu Feb 23 17:08:48 1995 + + +-- Entity Declaration + +ENTITY pow_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_i : NATURAL := 191; -- cin_i + CONSTANT tpll_i : NATURAL := 1777; -- tpll_i + CONSTANT rdown_i : NATURAL := 30; -- rdown_i + CONSTANT tphh_i : NATURAL := 1608; -- tphh_i + CONSTANT rup_i : NATURAL := 32 -- rup_i + ); + PORT ( + i : in BIT; -- i + pad : out BIT; -- pad + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pow_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pow_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pow_sp" + SEVERITY WARNING; + + +pad <= i; +END; diff --git a/alliance/src/cells/src/padlib/pvdde_sp.al b/alliance/src/cells/src/padlib/pvdde_sp.al new file mode 100644 index 00000000..6d26778e --- /dev/null +++ b/alliance/src/cells/src/padlib/pvdde_sp.al @@ -0,0 +1,13 @@ +V ALLIANCE : 4 +H pvdde_sp,L,23/ 2/95 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,2 +C vddi,UNKNOWN,EXTERNAL,3 +C vsse,UNKNOWN,EXTERNAL,4 +C vssi,UNKNOWN,EXTERNAL,5 +S 5,EXTERNAL,0,vssi +S 4,EXTERNAL,0,vsse +S 3,EXTERNAL,0,vddi +S 2,EXTERNAL,0,vdde +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pvdde_sp.ap b/alliance/src/cells/src/padlib/pvdde_sp.ap new file mode 100644 index 00000000..7cc3206d --- /dev/null +++ b/alliance/src/cells/src/padlib/pvdde_sp.ap @@ -0,0 +1,17 @@ +V ALLIANCE : 3 +H pvdde_sp,P,30/ 0/95 +A 0,0,172,500 +C 172,13,12,ck,1,EAST,ALU2 +C 172,47,40,vssi,1,EAST,ALU2 +C 172,91,40,vddi,1,EAST,ALU2 +C 172,175,120,vdde,1,EAST,ALU2 +C 0,175,120,vdde,0,WEST,ALU2 +C 0,91,40,vddi,0,WEST,ALU2 +C 0,47,40,vssi,0,WEST,ALU2 +C 0,13,12,ck,0,WEST,ALU2 +C 0,303,120,vsse,0,WEST,ALU2 +C 172,303,120,vsse,1,EAST,ALU2 +C 88,500,1,vdde,2,NORTH,ALU1 +I 0,0,palvdde_sp,logic,NOSYM +I 0,363,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pvdde_sp.vbe b/alliance/src/cells/src/padlib/pvdde_sp.vbe new file mode 100644 index 00000000..7dbb223c --- /dev/null +++ b/alliance/src/cells/src/padlib/pvdde_sp.vbe @@ -0,0 +1,30 @@ +-- VHDL data flow description generated from `pvdde_sp` +-- date : Thu Feb 23 17:10:19 1995 + + +-- Entity Declaration + +ENTITY pvdde_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000 -- area + ); + PORT ( + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pvdde_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvdde_sp IS + +BEGIN + ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1') + REPORT "power supply is missing on pvdde_sp" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/padlib/pvddeck_sp.al b/alliance/src/cells/src/padlib/pvddeck_sp.al new file mode 100644 index 00000000..416456a2 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvddeck_sp.al @@ -0,0 +1,28 @@ +V ALLIANCE : 4 +H pvddeck_sp,L,23/ 2/95 +C cko,UNKNOWN,EXTERNAL,2 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,3 +C vddi,UNKNOWN,EXTERNAL,4 +C vsse,UNKNOWN,EXTERNAL,5 +C vssi,UNKNOWN,EXTERNAL,6 +T N,1,20,6,7,2,0,0,0,0,70,42.5 +T N,1,20,2,7,6,0,0,0,0,64,42.5 +T N,1,20,7,1,6,0,0,0,0,52,42.5 +T N,1,20,2,7,6,0,0,0,0,88,42.5 +T N,1,20,6,7,2,0,0,0,0,82,42.5 +T N,1,20,2,7,6,0,0,0,0,76,42.5 +T P,1,40,7,1,4,0,0,0,0,52,92.5 +T P,1,34,2,7,4,0,0,0,0,88,89.5 +T P,1,34,4,7,2,0,0,0,0,82,89.5 +T P,1,34,2,7,4,0,0,0,0,76,89.5 +T P,1,34,4,7,2,0,0,0,0,70,89.5 +T P,1,34,2,7,4,0,0,0,0,64,89.5 +S 7,INTERNAL,0,mbk_sig4 +S 6,EXTERNAL,0,vssi +S 5,EXTERNAL,0,vsse +S 4,EXTERNAL,0,vddi +S 3,EXTERNAL,0,vdde +S 2,EXTERNAL,0,cko +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pvddeck_sp.ap b/alliance/src/cells/src/padlib/pvddeck_sp.ap new file mode 100644 index 00000000..e7e0d2d7 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvddeck_sp.ap @@ -0,0 +1,23 @@ +V ALLIANCE : 3 +H pvddeck_sp,P,30/ 0/95 +A 0,0,172,500 +C 172,13,12,ck,1,EAST,ALU2 +C 172,47,40,vssi,1,EAST,ALU2 +C 172,91,40,vddi,1,EAST,ALU2 +C 172,175,120,vdde,1,EAST,ALU2 +C 0,175,120,vdde,0,WEST,ALU2 +C 0,91,40,vddi,0,WEST,ALU2 +C 0,47,40,vssi,0,WEST,ALU2 +C 0,13,12,ck,0,WEST,ALU2 +C 67,0,2,cko,1,SOUTH,ALU2 +C 67,0,2,cko,0,SOUTH,ALU1 +C 79,0,2,cko,3,SOUTH,ALU2 +C 79,0,2,cko,2,SOUTH,ALU1 +C 91,0,2,cko,5,SOUTH,ALU2 +C 91,0,2,cko,4,SOUTH,ALU1 +C 172,303,120,vsse,1,EAST,ALU2 +C 0,303,120,vsse,0,WEST,ALU2 +C 88,500,1,vdde,2,NORTH,ALU1 +I 0,0,palvddeck_sp,logic,NOSYM +I 0,363,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pvddeck_sp.vbe b/alliance/src/cells/src/padlib/pvddeck_sp.vbe new file mode 100644 index 00000000..6f0f899f --- /dev/null +++ b/alliance/src/cells/src/padlib/pvddeck_sp.vbe @@ -0,0 +1,40 @@ +-- VHDL data flow description generated from `pvddeck_sp` +-- date : Thu Feb 23 17:11:45 1995 + + +-- Entity Declaration + +ENTITY pvddeck_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1055; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 126; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 963; -- tphh_ck + CONSTANT rup_ck : NATURAL := 183 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pvddeck_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvddeck_sp IS + +BEGIN + ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1') + REPORT "power supply is missing on pvddeck_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/alliance/src/cells/src/padlib/pvddi_sp.al b/alliance/src/cells/src/padlib/pvddi_sp.al new file mode 100644 index 00000000..11982763 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvddi_sp.al @@ -0,0 +1,13 @@ +V ALLIANCE : 4 +H pvddi_sp,L,23/ 2/95 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,2 +C vddi,UNKNOWN,EXTERNAL,3 +C vsse,UNKNOWN,EXTERNAL,4 +C vssi,UNKNOWN,EXTERNAL,5 +S 5,EXTERNAL,0,vssi +S 4,EXTERNAL,0,vsse +S 3,EXTERNAL,0,vddi +S 2,EXTERNAL,0,vdde +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pvddi_sp.ap b/alliance/src/cells/src/padlib/pvddi_sp.ap new file mode 100644 index 00000000..7d1cdd1e --- /dev/null +++ b/alliance/src/cells/src/padlib/pvddi_sp.ap @@ -0,0 +1,19 @@ +V ALLIANCE : 3 +H pvddi_sp,P,30/ 0/95 +A 0,0,172,500 +C 86,0,100,vddi,0,SOUTH,ALU1 +C 86,0,100,vddi,1,SOUTH,ALU2 +C 0,47,40,vssi,0,WEST,ALU2 +C 0,175,120,vdde,0,WEST,ALU2 +C 0,91,40,vddi,2,WEST,ALU2 +C 0,13,12,ck,0,WEST,ALU2 +C 172,175,120,vdde,1,EAST,ALU2 +C 172,91,40,vddi,3,EAST,ALU2 +C 172,47,40,vssi,1,EAST,ALU2 +C 172,13,12,ck,1,EAST,ALU2 +C 0,303,120,vsse,0,WEST,ALU2 +C 172,303,120,vsse,1,EAST,ALU2 +C 88,500,1,vddi,4,NORTH,ALU1 +I 0,0,palvddi_sp,logic,NOSYM +I 0,363,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pvddi_sp.vbe b/alliance/src/cells/src/padlib/pvddi_sp.vbe new file mode 100644 index 00000000..94cec5b4 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvddi_sp.vbe @@ -0,0 +1,30 @@ +-- VHDL data flow description generated from `pvddi_sp` +-- date : Thu Feb 23 17:11:01 1995 + + +-- Entity Declaration + +ENTITY pvddi_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000 -- area + ); + PORT ( + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pvddi_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvddi_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvddi_sp" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/padlib/pvddick_sp.al b/alliance/src/cells/src/padlib/pvddick_sp.al new file mode 100644 index 00000000..e8205034 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvddick_sp.al @@ -0,0 +1,29 @@ +V ALLIANCE : 4 +H pvddick_sp,L,23/ 2/95 +C cko,UNKNOWN,EXTERNAL,2 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,3 +C vddi,UNKNOWN,EXTERNAL,4 +C vsse,UNKNOWN,EXTERNAL,5 +C vssi,UNKNOWN,EXTERNAL,6 +T N,1,25,2,8,6,0,0,0,0,158,45 +T N,1,10,8,1,6,0,0,0,0,146,52.5 +T N,1,25,6,8,2,0,0,0,0,152,45 +T N,1,25,2,7,6,0,0,0,0,14,45 +T N,1,10,7,1,6,0,0,0,0,26,52.5 +T N,1,25,6,7,2,0,0,0,0,20,45 +T P,1,20,4,1,8,0,0,0,0,143,89.5 +T P,1,50,2,8,4,0,0,0,0,149,104.5 +T P,1,50,4,8,2,0,0,0,0,155,104.5 +T P,1,20,4,1,7,0,0,0,0,29,89.5 +T P,1,50,2,7,4,0,0,0,0,23,104.5 +T P,1,50,4,7,2,0,0,0,0,17,104.5 +S 8,INTERNAL,0,mbk_sig6 +S 7,INTERNAL,0,mbk_sig5 +S 6,EXTERNAL,0,vssi +S 5,EXTERNAL,0,vsse +S 4,EXTERNAL,0,vddi +S 3,EXTERNAL,0,vdde +S 2,EXTERNAL,0,cko +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pvddick_sp.ap b/alliance/src/cells/src/padlib/pvddick_sp.ap new file mode 100644 index 00000000..f5178836 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvddick_sp.ap @@ -0,0 +1,23 @@ +V ALLIANCE : 3 +H pvddick_sp,P,30/ 0/95 +A 0,0,172,500 +C 86,0,100,vddi,1,SOUTH,ALU2 +C 86,0,100,vddi,0,SOUTH,ALU1 +C 17,0,2,cko,0,SOUTH,ALU1 +C 17,0,2,cko,1,SOUTH,ALU2 +C 172,13,12,ck,1,EAST,ALU2 +C 172,47,40,vssi,1,EAST,ALU2 +C 172,91,40,vddi,3,EAST,ALU2 +C 172,175,120,vdde,1,EAST,ALU2 +C 0,175,120,vdde,0,WEST,ALU2 +C 0,91,40,vddi,2,WEST,ALU2 +C 0,47,40,vssi,0,WEST,ALU2 +C 0,13,12,ck,0,WEST,ALU2 +C 155,0,1,cko,2,SOUTH,ALU1 +C 155,0,2,cko,2,SOUTH,ALU2 +C 172,303,120,vsse,1,EAST,ALU2 +C 0,303,120,vsse,0,WEST,ALU2 +C 88,500,1,vddi,4,NORTH,ALU1 +I 0,0,palvddick_sp,logic,NOSYM +I 0,363,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pvddick_sp.vbe b/alliance/src/cells/src/padlib/pvddick_sp.vbe new file mode 100644 index 00000000..37c44073 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvddick_sp.vbe @@ -0,0 +1,40 @@ +-- VHDL data flow description generated from `pvddick_sp` +-- date : Thu Feb 23 17:12:35 1995 + + +-- Entity Declaration + +ENTITY pvddick_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1235; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 253; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 1109; -- tphh_ck + CONSTANT rup_ck : NATURAL := 311 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pvddick_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvddick_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvddick_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/alliance/src/cells/src/padlib/pvsse_sp.al b/alliance/src/cells/src/padlib/pvsse_sp.al new file mode 100644 index 00000000..9d497fd4 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvsse_sp.al @@ -0,0 +1,13 @@ +V ALLIANCE : 4 +H pvsse_sp,L,23/ 2/95 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,2 +C vddi,UNKNOWN,EXTERNAL,3 +C vsse,UNKNOWN,EXTERNAL,4 +C vssi,UNKNOWN,EXTERNAL,5 +S 5,EXTERNAL,0,vssi +S 4,EXTERNAL,0,vsse +S 3,EXTERNAL,0,vddi +S 2,EXTERNAL,0,vdde +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pvsse_sp.ap b/alliance/src/cells/src/padlib/pvsse_sp.ap new file mode 100644 index 00000000..817bfe1e --- /dev/null +++ b/alliance/src/cells/src/padlib/pvsse_sp.ap @@ -0,0 +1,17 @@ +V ALLIANCE : 3 +H pvsse_sp,P,30/ 0/95 +A 0,0,172,500 +C 172,13,12,ck,1,EAST,ALU2 +C 172,47,40,vssi,1,EAST,ALU2 +C 172,91,40,vddi,1,EAST,ALU2 +C 172,175,120,vdde,1,EAST,ALU2 +C 0,175,120,vdde,0,WEST,ALU2 +C 0,91,40,vddi,0,WEST,ALU2 +C 0,47,40,vssi,0,WEST,ALU2 +C 0,13,12,ck,0,WEST,ALU2 +C 0,303,120,vsse,0,WEST,ALU2 +C 172,303,120,vsse,1,EAST,ALU2 +C 88,500,1,vsse,2,NORTH,ALU1 +I 0,0,palvsse_sp,logic,NOSYM +I 0,363,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pvsse_sp.vbe b/alliance/src/cells/src/padlib/pvsse_sp.vbe new file mode 100644 index 00000000..fd9208ee --- /dev/null +++ b/alliance/src/cells/src/padlib/pvsse_sp.vbe @@ -0,0 +1,30 @@ +-- VHDL data flow description generated from `pvsse_sp` +-- date : Thu Feb 23 17:10:40 1995 + + +-- Entity Declaration + +ENTITY pvsse_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000 -- area + ); + PORT ( + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pvsse_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvsse_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvsse_sp" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/padlib/pvsseck_sp.al b/alliance/src/cells/src/padlib/pvsseck_sp.al new file mode 100644 index 00000000..e3289211 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvsseck_sp.al @@ -0,0 +1,28 @@ +V ALLIANCE : 4 +H pvsseck_sp,L,23/ 2/95 +C cko,UNKNOWN,EXTERNAL,2 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,3 +C vddi,UNKNOWN,EXTERNAL,4 +C vsse,UNKNOWN,EXTERNAL,5 +C vssi,UNKNOWN,EXTERNAL,6 +T N,1,20,6,7,2,0,0,0,0,70,42.5 +T N,1,20,2,7,6,0,0,0,0,64,42.5 +T N,1,20,7,1,6,0,0,0,0,52,42.5 +T N,1,20,2,7,6,0,0,0,0,88,42.5 +T N,1,20,6,7,2,0,0,0,0,82,42.5 +T N,1,20,2,7,6,0,0,0,0,76,42.5 +T P,1,40,7,1,4,0,0,0,0,52,92.5 +T P,1,34,2,7,4,0,0,0,0,88,89.5 +T P,1,34,4,7,2,0,0,0,0,82,89.5 +T P,1,34,2,7,4,0,0,0,0,76,89.5 +T P,1,34,4,7,2,0,0,0,0,70,89.5 +T P,1,34,2,7,4,0,0,0,0,64,89.5 +S 7,INTERNAL,0,mbk_sig4 +S 6,EXTERNAL,0,vssi +S 5,EXTERNAL,0,vsse +S 4,EXTERNAL,0,vddi +S 3,EXTERNAL,0,vdde +S 2,EXTERNAL,0,cko +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pvsseck_sp.ap b/alliance/src/cells/src/padlib/pvsseck_sp.ap new file mode 100644 index 00000000..83240817 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvsseck_sp.ap @@ -0,0 +1,23 @@ +V ALLIANCE : 3 +H pvsseck_sp,P,30/ 0/95 +A 0,0,172,500 +C 172,13,12,ck,1,EAST,ALU2 +C 172,47,40,vssi,1,EAST,ALU2 +C 172,91,40,vddi,1,EAST,ALU2 +C 172,175,120,vdde,1,EAST,ALU2 +C 0,175,120,vdde,0,WEST,ALU2 +C 0,91,40,vddi,0,WEST,ALU2 +C 0,47,40,vssi,0,WEST,ALU2 +C 0,13,12,ck,0,WEST,ALU2 +C 67,0,2,cko,1,SOUTH,ALU2 +C 67,0,2,cko,0,SOUTH,ALU1 +C 79,0,2,cko,3,SOUTH,ALU2 +C 79,0,2,cko,2,SOUTH,ALU1 +C 91,0,2,cko,5,SOUTH,ALU2 +C 91,0,2,cko,4,SOUTH,ALU1 +C 0,303,120,vsse,0,WEST,ALU2 +C 172,303,120,vsse,1,EAST,ALU2 +C 88,500,1,vsse,2,NORTH,ALU1 +I 0,0,palvsseck_sp,logic,NOSYM +I 0,363,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pvsseck_sp.vbe b/alliance/src/cells/src/padlib/pvsseck_sp.vbe new file mode 100644 index 00000000..444ac41e --- /dev/null +++ b/alliance/src/cells/src/padlib/pvsseck_sp.vbe @@ -0,0 +1,40 @@ +-- VHDL data flow description generated from `pvsseck_sp` +-- date : Thu Feb 23 17:12:08 1995 + + +-- Entity Declaration + +ENTITY pvsseck_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1055; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 126; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 963; -- tphh_ck + CONSTANT rup_ck : NATURAL := 183 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pvsseck_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvsseck_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvsseck_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/alliance/src/cells/src/padlib/pvssi_sp.al b/alliance/src/cells/src/padlib/pvssi_sp.al new file mode 100644 index 00000000..466d2100 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvssi_sp.al @@ -0,0 +1,13 @@ +V ALLIANCE : 4 +H pvssi_sp,L,23/ 2/95 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,2 +C vddi,UNKNOWN,EXTERNAL,3 +C vsse,UNKNOWN,EXTERNAL,4 +C vssi,UNKNOWN,EXTERNAL,5 +S 5,EXTERNAL,0,vssi +S 4,EXTERNAL,0,vsse +S 3,EXTERNAL,0,vddi +S 2,EXTERNAL,0,vdde +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pvssi_sp.ap b/alliance/src/cells/src/padlib/pvssi_sp.ap new file mode 100644 index 00000000..a823dbff --- /dev/null +++ b/alliance/src/cells/src/padlib/pvssi_sp.ap @@ -0,0 +1,19 @@ +V ALLIANCE : 3 +H pvssi_sp,P,30/ 0/95 +A 0,0,172,500 +C 86,0,100,vssi,1,SOUTH,ALU2 +C 86,0,100,vssi,0,SOUTH,ALU1 +C 0,13,12,ck,0,WEST,ALU2 +C 0,47,40,vssi,2,WEST,ALU2 +C 0,91,40,vddi,0,WEST,ALU2 +C 0,175,120,vdde,0,WEST,ALU2 +C 172,175,120,vdde,1,EAST,ALU2 +C 172,91,40,vddi,1,EAST,ALU2 +C 172,47,40,vssi,3,EAST,ALU2 +C 172,13,12,ck,1,EAST,ALU2 +C 0,303,120,vsse,0,WEST,ALU2 +C 172,303,120,vsse,1,EAST,ALU2 +C 88,500,1,vssi,4,NORTH,ALU1 +I 0,0,palvssi_sp,logic,NOSYM +I 0,363,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pvssi_sp.vbe b/alliance/src/cells/src/padlib/pvssi_sp.vbe new file mode 100644 index 00000000..6f817126 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvssi_sp.vbe @@ -0,0 +1,30 @@ +-- VHDL data flow description generated from `pvssi_sp` +-- date : Thu Feb 23 17:11:22 1995 + + +-- Entity Declaration + +ENTITY pvssi_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000 -- area + ); + PORT ( + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pvssi_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvssi_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvssi_sp" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/padlib/pvssick_sp.al b/alliance/src/cells/src/padlib/pvssick_sp.al new file mode 100644 index 00000000..878902e0 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvssick_sp.al @@ -0,0 +1,29 @@ +V ALLIANCE : 4 +H pvssick_sp,L,23/ 2/95 +C cko,UNKNOWN,EXTERNAL,2 +C ck,UNKNOWN,EXTERNAL,1 +C vdde,UNKNOWN,EXTERNAL,3 +C vddi,UNKNOWN,EXTERNAL,4 +C vsse,UNKNOWN,EXTERNAL,5 +C vssi,UNKNOWN,EXTERNAL,6 +T N,1,25,2,8,6,0,0,0,0,158,45 +T N,1,10,8,1,6,0,0,0,0,146,52.5 +T N,1,25,6,8,2,0,0,0,0,152,45 +T N,1,25,2,7,6,0,0,0,0,14,45 +T N,1,10,7,1,6,0,0,0,0,26,52.5 +T N,1,25,6,7,2,0,0,0,0,20,45 +T P,1,20,4,1,8,0,0,0,0,143,89.5 +T P,1,50,2,8,4,0,0,0,0,149,104.5 +T P,1,50,4,8,2,0,0,0,0,155,104.5 +T P,1,20,4,1,7,0,0,0,0,29,89.5 +T P,1,50,2,7,4,0,0,0,0,23,104.5 +T P,1,50,4,7,2,0,0,0,0,17,104.5 +S 8,INTERNAL,0,mbk_sig5 +S 7,INTERNAL,0,mbk_sig4 +S 6,EXTERNAL,0,vssi +S 5,EXTERNAL,0,vsse +S 4,EXTERNAL,0,vddi +S 3,EXTERNAL,0,vdde +S 2,EXTERNAL,0,cko +S 1,EXTERNAL,0,ck +EOF diff --git a/alliance/src/cells/src/padlib/pvssick_sp.ap b/alliance/src/cells/src/padlib/pvssick_sp.ap new file mode 100644 index 00000000..77ea531d --- /dev/null +++ b/alliance/src/cells/src/padlib/pvssick_sp.ap @@ -0,0 +1,23 @@ +V ALLIANCE : 3 +H pvssick_sp,P,30/ 0/95 +A 0,0,172,500 +C 86,0,100,vssi,1,SOUTH,ALU2 +C 86,0,100,vssi,0,SOUTH,ALU1 +C 17,0,2,cko,0,SOUTH,ALU1 +C 17,0,2,cko,1,SOUTH,ALU2 +C 172,91,40,vddi,1,EAST,ALU2 +C 172,47,40,vssi,3,EAST,ALU2 +C 172,13,12,ck,1,EAST,ALU2 +C 172,175,120,vdde,1,EAST,ALU2 +C 0,175,120,vdde,0,WEST,ALU2 +C 0,91,40,vddi,0,WEST,ALU2 +C 0,47,40,vssi,2,WEST,ALU2 +C 0,13,12,ck,0,WEST,ALU2 +C 155,0,2,cko,2,SOUTH,ALU1 +C 155,0,2,cko,3,SOUTH,ALU2 +C 172,303,120,vsse,1,EAST,ALU2 +C 0,303,120,vsse,0,WEST,ALU2 +C 88,500,1,vssi,4,NORTH,ALU1 +I 0,0,palvssick_sp,logic,NOSYM +I 0,363,padreal,pad,NOSYM +EOF diff --git a/alliance/src/cells/src/padlib/pvssick_sp.vbe b/alliance/src/cells/src/padlib/pvssick_sp.vbe new file mode 100644 index 00000000..e780f4e6 --- /dev/null +++ b/alliance/src/cells/src/padlib/pvssick_sp.vbe @@ -0,0 +1,40 @@ +-- VHDL data flow description generated from `pvssick_sp` +-- date : Thu Feb 23 17:13:01 1995 + + +-- Entity Declaration + +ENTITY pvssick_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1235; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 253; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 1109; -- tphh_ck + CONSTANT rup_ck : NATURAL := 311 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END pvssick_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvssick_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvssick_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/alliance/src/cells/src/rflib/CATAL b/alliance/src/cells/src/rflib/CATAL new file mode 100644 index 00000000..a06325c8 --- /dev/null +++ b/alliance/src/cells/src/rflib/CATAL @@ -0,0 +1,32 @@ +rf_dec_bufad0 C +rf_dec_bufad1 C +rf_dec_bufad1r C +rf_dec_bufad2 C +rf_dec_bufad2r C +rf_dec_nand2 C +rf_dec_nand3 C +rf_dec_nand4 C +rf_dec_nao3 C +rf_dec_nbuf C +rf_dec_nor3 C +rf_fifo_buf C +rf_fifo_clock C +rf_fifo_empty C +rf_fifo_full C +rf_fifo_inc C +rf_fifo_nop C +rf_fifo_ok C +rf_fifo_orand4 C +rf_fifo_orand5 C +rf_fifo_ptreset C +rf_fifo_ptset C +rf_inmux_buf_2 C +rf_inmux_buf_4 C +rf_inmux_mem C +rf_mid_buf_2 C +rf_mid_buf_4 C +rf_mid_mem C +rf_mid_mem_r0 C +rf_out_buf_2 C +rf_out_buf_4 C +rf_out_mem C diff --git a/alliance/src/cells/src/rflib/Makefile.am b/alliance/src/cells/src/rflib/Makefile.am new file mode 100644 index 00000000..421ee905 --- /dev/null +++ b/alliance/src/cells/src/rflib/Makefile.am @@ -0,0 +1,6 @@ +# $Id: Makefile.am,v 1.1 2002/04/29 15:51:51 czo Exp $ + +rflib_DATA= CATAL rf_dec_bufad0.ap rf_dec_bufad0.vbe rf_dec_bufad1.ap rf_dec_bufad1.vbe rf_dec_bufad2.ap rf_dec_bufad2.vbe rf_dec_nand2.ap rf_dec_nand2.vbe rf_dec_nand3.ap rf_dec_nand3.vbe rf_dec_nand4.ap rf_dec_nand4.vbe rf_dec_nao3.ap rf_dec_nao3.vbe rf_dec_nbuf.ap rf_dec_nbuf.vbe rf_dec_nor3.ap rf_dec_nor3.vbe rf_fifo_buf.ap rf_fifo_buf.vbe rf_fifo_clock.ap rf_fifo_clock.vbe rf_fifo_empty.ap rf_fifo_empty.vbe rf_fifo_full.ap rf_fifo_full.vbe rf_fifo_inc.ap rf_fifo_inc.vbe rf_fifo_nop.ap rf_fifo_nop.vbe rf_fifo_ok.ap rf_fifo_ok.vbe rf_fifo_orand4.ap rf_fifo_orand4.vbe rf_fifo_orand5.ap rf_fifo_orand5.vbe rf_fifo_ptreset.ap rf_fifo_ptreset.vbe rf_fifo_ptset.ap rf_fifo_ptset.vbe rf_inmux_buf_2.ap rf_inmux_buf_2.vbe rf_inmux_buf_4.ap rf_inmux_buf_4.vbe rf_inmux_mem.ap rf_inmux_mem.vbe rf_mid_buf_2.ap rf_mid_buf_2.vbe rf_mid_buf_4.ap rf_mid_buf_4.vbe rf_mid_mem.ap rf_mid_mem.vbe rf_mid_mem_r0.ap rf_mid_mem_r0.vbe rf_out_buf_2.ap rf_out_buf_2.vbe rf_out_buf_4.ap rf_out_buf_4.vbe rf_out_mem.ap rf_out_mem.vbe rflib.lef + +EXTRA_DIST=$(rflib_DATA) + diff --git a/alliance/src/cells/src/rflib/rf_dec_bufad0.ap b/alliance/src/cells/src/rflib/rf_dec_bufad0.ap new file mode 100644 index 00000000..2af0ad41 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_bufad0.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H rf_dec_bufad0,P,15/ 3/2001,10 +A 0,0,450,500 +S 0,390,450,390,240,*,LEFT,NWELL +S 0,470,450,470,60,vdd,RIGHT,CALU1 +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 320,300,320,450,20,*,UP,ALU1 +S 320,50,320,100,20,*,DOWN,ALU1 +S 150,150,210,150,20,*,RIGHT,ALU1 +S 200,300,200,450,20,*,DOWN,ALU1 +S 200,50,200,100,20,*,UP,ALU1 +S 390,300,390,470,20,*,UP,ALU1 +S 390,30,390,150,20,*,DOWN,ALU1 +S 260,100,260,400,20,*,DOWN,ALU1 +S 110,140,110,260,10,*,UP,POLY +S 170,140,170,260,10,*,UP,POLY +S 230,140,230,260,10,*,UP,POLY +S 290,140,290,260,10,*,UP,POLY +S 210,150,290,150,30,*,RIGHT,POLY +S 390,20,390,160,30,*,DOWN,PTIE +S 200,30,200,120,30,*,UP,NDIF +S 260,30,260,120,30,*,UP,NDIF +S 80,30,80,120,30,*,UP,NDIF +S 140,30,140,120,30,*,UP,NDIF +S 320,30,320,120,30,*,UP,NDIF +S 230,10,230,140,10,*,DOWN,NTRANS +S 290,10,290,140,10,*,DOWN,NTRANS +S 110,10,110,140,10,*,DOWN,NTRANS +S 170,10,170,140,10,*,DOWN,NTRANS +S 80,280,80,470,30,*,DOWN,PDIF +S 230,260,230,490,10,*,UP,PTRANS +S 260,280,260,470,30,*,DOWN,PDIF +S 170,260,170,490,10,*,UP,PTRANS +S 110,260,110,490,10,*,UP,PTRANS +S 140,280,140,470,30,*,DOWN,PDIF +S 290,260,290,490,10,*,UP,PTRANS +S 320,280,320,470,30,*,DOWN,PDIF +S 390,290,390,480,30,*,UP,NTIE +S 200,280,200,470,30,*,DOWN,PDIF +S 50,200,170,200,30,*,RIGHT,POLY +S 140,100,140,400,20,*,DOWN,ALU1 +S 50,100,50,400,10,i,UP,CALU1 +S 150,250,150,250,20,nq,LEFT,CALU2 +S 250,300,250,300,20,q,LEFT,CALU2 +V 150,250,CONT_VIA,* +V 250,300,CONT_VIA,* +V 210,150,CONT_POLY,* +V 390,150,CONT_BODY_P,* +V 390,30,CONT_BODY_P,* +V 390,100,CONT_BODY_P,* +V 320,100,CONT_DIF_N,* +V 320,50,CONT_DIF_N,* +V 200,100,CONT_DIF_N,* +V 200,50,CONT_DIF_N,* +V 80,50,CONT_DIF_N,* +V 260,100,CONT_DIF_N,* +V 140,100,CONT_DIF_N,* +V 320,350,CONT_DIF_P,* +V 320,450,CONT_DIF_P,* +V 200,300,CONT_DIF_P,* +V 200,350,CONT_DIF_P,* +V 200,400,CONT_DIF_P,* +V 140,400,CONT_DIF_P,* +V 140,300,CONT_DIF_P,* +V 140,350,CONT_DIF_P,* +V 260,300,CONT_DIF_P,* +V 260,350,CONT_DIF_P,* +V 260,400,CONT_DIF_P,* +V 320,400,CONT_DIF_P,* +V 320,300,CONT_DIF_P,* +V 390,350,CONT_BODY_N,* +V 390,400,CONT_BODY_N,* +V 390,470,CONT_BODY_N,* +V 200,450,CONT_DIF_P,* +V 80,450,CONT_DIF_P,* +V 390,300,CONT_BODY_N,* +V 50,200,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_dec_bufad0.vbe b/alliance/src/cells/src/rflib/rf_dec_bufad0.vbe new file mode 100644 index 00000000..03c3741f --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_bufad0.vbe @@ -0,0 +1,21 @@ +ENTITY rf_dec_bufad0 IS +PORT ( + i : in BIT; + nq : inout BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_bufad0; + +ARCHITECTURE VBE OF rf_dec_bufad0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_bufad0" + SEVERITY WARNING; + + nq <= not i; + q <= not nq; + +END; diff --git a/alliance/src/cells/src/rflib/rf_dec_bufad1.ap b/alliance/src/cells/src/rflib/rf_dec_bufad1.ap new file mode 100644 index 00000000..052e0c81 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_bufad1.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H rf_dec_bufad1,P,15/ 3/2001,10 +A 0,0,500,500 +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,390,500,390,240,*,LEFT,NWELL +S 430,50,430,100,20,*,DOWN,ALU1 +S 430,300,430,450,20,*,UP,ALU1 +S 370,100,370,400,20,*,DOWN,ALU1 +S 190,300,190,450,20,*,UP,ALU1 +S 190,50,190,100,20,*,DOWN,ALU1 +S 310,50,310,100,20,*,UP,ALU1 +S 310,300,310,450,20,*,DOWN,ALU1 +S 320,150,400,150,30,*,RIGHT,POLY +S 400,140,400,260,10,*,UP,POLY +S 340,140,340,260,10,*,UP,POLY +S 280,140,280,260,10,*,UP,POLY +S 220,140,220,260,10,*,UP,POLY +S 430,30,430,120,30,*,UP,NDIF +S 250,30,250,120,30,*,UP,NDIF +S 190,30,190,120,30,*,UP,NDIF +S 370,30,370,120,30,*,UP,NDIF +S 310,30,310,120,30,*,UP,NDIF +S 280,10,280,140,10,*,DOWN,NTRANS +S 220,10,220,140,10,*,DOWN,NTRANS +S 400,10,400,140,10,*,DOWN,NTRANS +S 340,10,340,140,10,*,DOWN,NTRANS +S 250,280,250,470,30,*,DOWN,PDIF +S 220,260,220,490,10,*,UP,PTRANS +S 280,260,280,490,10,*,UP,PTRANS +S 370,280,370,470,30,*,DOWN,PDIF +S 340,260,340,490,10,*,UP,PTRANS +S 190,280,190,470,30,*,DOWN,PDIF +S 310,280,310,470,30,*,DOWN,PDIF +S 430,280,430,470,30,*,DOWN,PDIF +S 400,260,400,490,10,*,UP,PTRANS +S 100,300,100,470,20,*,UP,ALU1 +S 100,30,100,150,20,*,DOWN,ALU1 +S 100,20,100,160,30,*,DOWN,PTIE +S 100,290,100,480,30,*,UP,NTIE +S 300,200,300,200,20,q,LEFT,CALU3 +S 250,200,250,200,20,nq,LEFT,CALU3 +S 200,200,200,200,20,i,LEFT,CALU3 +S 200,200,300,200,20,*,RIGHT,TALU2 +S 250,100,250,400,20,*,DOWN,ALU1 +S 250,150,320,150,20,*,RIGHT,ALU1 +S 300,200,370,200,20,*,RIGHT,ALU1 +S 200,200,280,200,30,*,RIGHT,POLY +V 320,150,CONT_POLY,* +V 190,100,CONT_DIF_N,* +V 190,50,CONT_DIF_N,* +V 310,50,CONT_DIF_N,* +V 310,100,CONT_DIF_N,* +V 430,50,CONT_DIF_N,* +V 430,100,CONT_DIF_N,* +V 250,100,CONT_DIF_N,* +V 370,100,CONT_DIF_N,* +V 310,450,CONT_DIF_P,* +V 370,300,CONT_DIF_P,* +V 250,350,CONT_DIF_P,* +V 250,300,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 190,450,CONT_DIF_P,* +V 190,300,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 190,400,CONT_DIF_P,* +V 310,350,CONT_DIF_P,* +V 310,300,CONT_DIF_P,* +V 430,450,CONT_DIF_P,* +V 430,350,CONT_DIF_P,* +V 430,300,CONT_DIF_P,* +V 430,400,CONT_DIF_P,* +V 370,400,CONT_DIF_P,* +V 370,350,CONT_DIF_P,* +V 310,400,CONT_DIF_P,* +V 100,150,CONT_BODY_P,* +V 100,30,CONT_BODY_P,* +V 100,100,CONT_BODY_P,* +V 100,300,CONT_BODY_N,* +V 100,350,CONT_BODY_N,* +V 100,400,CONT_BODY_N,* +V 100,470,CONT_BODY_N,* +V 200,200,CONT_VIA2,* +V 250,200,CONT_VIA2,* +V 300,200,CONT_VIA2,* +V 200,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 300,200,CONT_VIA,* +V 200,200,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_dec_bufad1.vbe b/alliance/src/cells/src/rflib/rf_dec_bufad1.vbe new file mode 100644 index 00000000..af255e8d --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_bufad1.vbe @@ -0,0 +1,21 @@ +ENTITY rf_dec_bufad1 IS +PORT ( + i : in BIT; + nq : inout BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_bufad1; + +ARCHITECTURE VBE OF rf_dec_bufad1 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_bufad1" + SEVERITY WARNING; + + nq <= not i; + q <= not nq; + +END; diff --git a/alliance/src/cells/src/rflib/rf_dec_bufad2.ap b/alliance/src/cells/src/rflib/rf_dec_bufad2.ap new file mode 100644 index 00000000..75204720 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_bufad2.ap @@ -0,0 +1,135 @@ +V ALLIANCE : 6 +H rf_dec_bufad2,P,15/ 3/2001,10 +A 0,0,500,500 +S 200,200,450,200,20,*,LEFT,TALU2 +S 90,200,200,200,20,*,RIGHT,ALU1 +S 180,200,250,200,30,*,RIGHT,POLY +S 140,150,300,150,20,*,LEFT,ALU1 +S 140,250,300,250,20,*,RIGHT,ALU1 +S 60,150,140,150,30,*,RIGHT,POLY +S 60,250,140,250,30,*,RIGHT,POLY +S 90,100,90,400,20,*,DOWN,ALU1 +S 250,200,250,200,20,i0,LEFT,CALU3 +S 210,250,210,400,20,*,UP,ALU1 +S 210,100,210,150,20,*,DOWN,ALU1 +S 300,150,300,250,20,*,DOWN,ALU1 +S 350,150,400,150,20,*,RIGHT,ALU1 +S 350,250,400,250,20,*,RIGHT,ALU1 +S 330,100,350,100,20,*,RIGHT,ALU1 +S 330,300,350,300,20,*,RIGHT,ALU1 +S 330,350,350,350,20,*,RIGHT,ALU1 +S 330,400,350,400,20,*,RIGHT,ALU1 +S 350,100,350,400,20,*,UP,ALU1 +S 300,200,400,200,30,*,RIGHT,POLY +S 400,250,480,250,30,*,RIGHT,POLY +S 400,200,400,200,20,i1,LEFT,CALU3 +S 330,280,330,470,30,*,DOWN,PDIF +S 510,280,510,470,30,*,DOWN,PDIF +S 420,260,420,490,10,*,UP,PTRANS +S 390,280,390,470,30,*,DOWN,PDIF +S 480,260,480,490,10,*,UP,PTRANS +S 450,280,450,470,30,*,DOWN,PDIF +S 300,260,300,490,10,*,UP,PTRANS +S 270,280,270,470,30,*,DOWN,PDIF +S 360,260,360,490,10,*,UP,PTRANS +S 480,10,480,140,10,*,DOWN,NTRANS +S 420,10,420,140,10,*,DOWN,NTRANS +S 360,10,360,140,10,*,DOWN,NTRANS +S 300,10,300,140,10,*,DOWN,NTRANS +S 330,30,330,120,30,*,UP,NDIF +S 270,30,270,120,30,*,UP,NDIF +S 510,30,510,120,30,*,UP,NDIF +S 450,30,450,120,30,*,UP,NDIF +S 390,30,390,120,30,*,UP,NDIF +S 400,150,480,150,30,*,RIGHT,POLY +S 360,140,360,260,10,*,UP,POLY +S 300,140,300,260,10,*,UP,POLY +S 510,300,510,450,20,*,UP,ALU1 +S 510,50,510,100,20,*,DOWN,ALU1 +S 450,100,450,400,20,*,DOWN,ALU1 +S 270,50,270,100,20,*,DOWN,ALU1 +S 270,300,270,450,20,*,UP,ALU1 +S 0,390,500,390,240,*,LEFT,NWELL +S 240,140,240,260,10,*,UP,POLY +S 180,140,180,260,10,*,UP,POLY +S 240,260,240,490,10,*,UP,PTRANS +S 90,30,90,120,30,*,UP,NDIF +S 30,30,30,120,30,*,UP,NDIF +S 210,30,210,120,30,*,UP,NDIF +S 150,30,150,120,30,*,UP,NDIF +S 120,10,120,140,10,*,DOWN,NTRANS +S 60,10,60,140,10,*,DOWN,NTRANS +S 240,10,240,140,10,*,DOWN,NTRANS +S 180,10,180,140,10,*,DOWN,NTRANS +S 90,280,90,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 180,260,180,490,10,*,UP,PTRANS +S 30,300,30,450,20,*,UP,ALU1 +S 30,50,30,100,20,*,DOWN,ALU1 +S 30,280,30,470,30,*,DOWN,PDIF +S 150,280,150,470,30,*,DOWN,PDIF +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 200,200,200,200,20,q0,LEFT,CALU3 +S 300,200,300,200,20,nq0,LEFT,CALU3 +S 350,200,350,200,20,nq1,LEFT,CALU3 +S 450,200,450,200,20,q1,LEFT,CALU3 +V 140,150,CONT_POLY,* +V 140,250,CONT_POLY,* +V 200,200,CONT_VIA2,* +V 300,200,CONT_VIA2,* +V 250,200,CONT_VIA2,* +V 250,200,CONT_POLY,* +V 400,200,CONT_POLY,* +V 400,250,CONT_POLY,* +V 300,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 200,200,CONT_VIA,* +V 400,200,CONT_VIA,* +V 450,200,CONT_VIA,* +V 350,200,CONT_VIA,* +V 400,200,CONT_VIA2,* +V 450,200,CONT_VIA2,* +V 350,200,CONT_VIA2,* +V 270,450,CONT_DIF_P,* +V 510,300,CONT_DIF_P,* +V 510,350,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 330,300,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 450,300,CONT_DIF_P,* +V 390,450,CONT_DIF_P,* +V 510,450,CONT_DIF_P,* +V 510,400,CONT_DIF_P,* +V 450,100,CONT_DIF_N,* +V 390,50,CONT_DIF_N,* +V 510,100,CONT_DIF_N,* +V 510,50,CONT_DIF_N,* +V 330,100,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 400,150,CONT_POLY,* +V 90,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 30,300,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,50,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_dec_bufad2.vbe b/alliance/src/cells/src/rflib/rf_dec_bufad2.vbe new file mode 100644 index 00000000..10b7cb27 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_bufad2.vbe @@ -0,0 +1,26 @@ +ENTITY rf_dec_bufad2 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq0 : inout BIT; + q0 : out BIT; + nq1 : inout BIT; + q1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_bufad2; + +ARCHITECTURE VBE OF rf_dec_bufad2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_bufad2" + SEVERITY WARNING; + + nq0 <= not i0; + q0 <= not nq0; + nq1 <= not i1; + q1 <= not nq1; + +END; diff --git a/alliance/src/cells/src/rflib/rf_dec_nand2.ap b/alliance/src/cells/src/rflib/rf_dec_nand2.ap new file mode 100644 index 00000000..01b30116 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nand2.ap @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H rf_dec_nand2,P,21/ 8/2000,10 +A 0,0,500,500 +S 260,190,260,310,10,*,UP,POLY +S 240,140,240,210,10,*,UP,POLY +S 300,200,350,200,20,*,RIGHT,ALU1 +S 200,200,350,200,20,*,RIGHT,TALU2 +S 250,200,250,200,20,i1,LEFT,CALU3 +S 200,200,200,200,20,i0,LEFT,CALU3 +S 350,200,350,200,20,nq,LEFT,CALU3 +S 270,100,300,100,20,*,RIGHT,ALU1 +S 230,350,300,350,20,*,LEFT,ALU1 +S 300,100,300,350,20,*,UP,ALU1 +S 200,140,200,310,10,*,DOWN,POLY +S 170,330,170,460,30,*,DOWN,PDIF +S 290,330,290,460,30,*,DOWN,PDIF +S 260,310,260,440,10,*,UP,PTRANS +S 200,310,200,440,10,*,UP,PTRANS +S 230,330,230,420,30,*,DOWN,PDIF +S 290,400,290,450,20,*,DOWN,ALU1 +S 170,400,170,450,20,*,DOWN,ALU1 +S 240,10,240,140,10,*,DOWN,NTRANS +S 200,10,200,140,10,*,DOWN,NTRANS +S 270,30,270,120,30,*,DOWN,NDIF +S 170,30,170,120,30,*,DOWN,NDIF +S 170,50,170,100,20,*,DOWN,ALU1 +S 0,390,500,390,240,*,RIGHT,NWELL +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 70,300,70,470,20,*,UP,ALU1 +S 70,30,70,150,20,*,DOWN,ALU1 +S 70,20,70,160,30,*,DOWN,PTIE +S 70,290,70,480,30,*,UP,NTIE +S 430,30,430,150,20,*,DOWN,ALU1 +S 430,300,430,470,20,*,UP,ALU1 +S 430,20,430,160,30,*,DOWN,PTIE +S 430,290,430,480,30,*,UP,NTIE +V 200,200,CONT_POLY,* +V 250,200,CONT_POLY,* +V 350,200,CONT_VIA,* +V 200,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 250,200,CONT_VIA2,* +V 200,200,CONT_VIA2,* +V 350,200,CONT_VIA2,* +V 270,100,CONT_DIF_N,* +V 170,450,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 290,400,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 230,470,CONT_BODY_N,* +V 290,450,CONT_DIF_P,* +V 170,50,CONT_DIF_N,* +V 170,100,CONT_DIF_N,* +V 70,30,CONT_BODY_P,* +V 70,100,CONT_BODY_P,* +V 70,150,CONT_BODY_P,* +V 70,300,CONT_BODY_N,* +V 70,400,CONT_BODY_N,* +V 70,470,CONT_BODY_N,* +V 70,350,CONT_BODY_N,* +V 430,150,CONT_BODY_P,* +V 430,100,CONT_BODY_P,* +V 430,30,CONT_BODY_P,* +V 430,400,CONT_BODY_N,* +V 430,300,CONT_BODY_N,* +V 430,350,CONT_BODY_N,* +V 430,470,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_dec_nand2.vbe b/alliance/src/cells/src/rflib/rf_dec_nand2.vbe new file mode 100644 index 00000000..7c0132d8 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nand2.vbe @@ -0,0 +1,20 @@ +ENTITY rf_dec_nand2 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nand2; + +ARCHITECTURE VBE OF rf_dec_nand2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nand2" + SEVERITY WARNING; + + nq <= not(i0 and i1); + +END; diff --git a/alliance/src/cells/src/rflib/rf_dec_nand3.ap b/alliance/src/cells/src/rflib/rf_dec_nand3.ap new file mode 100644 index 00000000..0d495560 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nand3.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 6 +H rf_dec_nand3,P,22/ 8/2000,10 +A 0,0,500,500 +S 350,200,350,200,20,i0,LEFT,CALU3 +S 170,50,170,100,20,*,DOWN,ALU1 +S 170,30,170,120,30,*,DOWN,NDIF +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,390,500,390,240,*,RIGHT,NWELL +S 70,300,70,470,20,*,UP,ALU1 +S 70,30,70,150,20,*,DOWN,ALU1 +S 70,20,70,160,30,*,DOWN,PTIE +S 70,290,70,480,30,*,UP,NTIE +S 190,350,350,350,20,*,LEFT,ALU1 +S 350,100,350,350,20,*,UP,ALU1 +S 250,400,250,450,20,*,DOWN,ALU1 +S 370,400,370,450,20,*,DOWN,ALU1 +S 200,140,200,310,10,*,UP,POLY +S 200,310,220,310,10,*,RIGHT,POLY +S 310,30,310,120,30,*,DOWN,NDIF +S 200,10,200,140,10,*,DOWN,NTRANS +S 240,10,240,140,10,*,DOWN,NTRANS +S 280,10,280,140,10,*,DOWN,NTRANS +S 190,330,190,420,30,*,DOWN,PDIF +S 220,310,220,440,10,*,UP,PTRANS +S 280,310,280,440,10,*,UP,PTRANS +S 340,310,340,440,10,*,UP,PTRANS +S 370,330,370,460,30,*,DOWN,PDIF +S 250,330,250,460,30,*,DOWN,PDIF +S 310,330,310,420,30,*,DOWN,PDIF +S 430,30,430,150,20,*,DOWN,ALU1 +S 430,300,430,470,20,*,UP,ALU1 +S 430,20,430,160,30,*,DOWN,PTIE +S 430,290,430,480,30,*,UP,NTIE +S 260,310,280,310,10,*,RIGHT,POLY +S 310,310,340,310,10,*,RIGHT,POLY +S 310,100,350,100,20,*,RIGHT,ALU1 +S 200,200,200,200,20,i1,LEFT,CALU3 +S 250,200,250,200,20,i2,LEFT,CALU3 +S 400,200,400,200,20,nq,LEFT,CALU3 +S 200,200,400,200,20,*,RIGHT,TALU2 +S 300,200,350,200,20,*,RIGHT,ALU2 +S 350,200,400,200,20,*,RIGHT,ALU1 +S 240,140,240,210,10,*,UP,POLY +S 260,190,260,310,10,*,UP,POLY +S 310,140,310,310,10,*,DOWN,POLY +S 280,140,310,140,10,*,RIGHT,POLY +V 170,100,CONT_DIF_N,* +V 170,50,CONT_DIF_N,* +V 70,30,CONT_BODY_P,* +V 70,100,CONT_BODY_P,* +V 70,150,CONT_BODY_P,* +V 70,300,CONT_BODY_N,* +V 70,400,CONT_BODY_N,* +V 70,470,CONT_BODY_N,* +V 70,350,CONT_BODY_N,* +V 370,450,CONT_DIF_P,* +V 310,470,CONT_BODY_N,* +V 190,470,CONT_BODY_N,* +V 190,350,CONT_DIF_P,* +V 310,350,CONT_DIF_P,* +V 370,400,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 250,450,CONT_DIF_P,* +V 430,150,CONT_BODY_P,* +V 430,100,CONT_BODY_P,* +V 430,30,CONT_BODY_P,* +V 430,400,CONT_BODY_N,* +V 430,300,CONT_BODY_N,* +V 430,350,CONT_BODY_N,* +V 430,470,CONT_BODY_N,* +V 310,100,CONT_DIF_N,* +V 250,200,CONT_VIA2,* +V 400,200,CONT_VIA2,* +V 350,200,CONT_VIA2,* +V 200,200,CONT_VIA2,* +V 400,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 200,200,CONT_VIA,* +V 300,200,CONT_VIA,* +V 300,200,CONT_POLY,* +V 250,200,CONT_POLY,* +V 200,200,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_dec_nand3.vbe b/alliance/src/cells/src/rflib/rf_dec_nand3.vbe new file mode 100644 index 00000000..c1eec05c --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nand3.vbe @@ -0,0 +1,21 @@ +ENTITY rf_dec_nand3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nand3; + +ARCHITECTURE VBE OF rf_dec_nand3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nand3" + SEVERITY WARNING; + + nq <= not(i0 and i1 and i2); + +END; diff --git a/alliance/src/cells/src/rflib/rf_dec_nand4.ap b/alliance/src/cells/src/rflib/rf_dec_nand4.ap new file mode 100644 index 00000000..ce1a4f57 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nand4.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 6 +H rf_dec_nand4,P,21/ 8/2000,10 +A 0,0,500,500 +S 280,140,310,140,10,*,RIGHT,POLY +S 310,140,310,310,10,*,DOWN,POLY +S 240,140,240,210,10,*,UP,POLY +S 260,190,260,310,10,*,UP,POLY +S 350,200,400,200,20,*,RIGHT,ALU1 +S 300,200,350,200,20,*,RIGHT,ALU2 +S 150,200,400,200,20,*,RIGHT,TALU2 +S 250,200,250,200,20,i2,LEFT,CALU3 +S 200,200,200,200,20,i1,LEFT,CALU3 +S 150,200,150,200,20,i0,LEFT,CALU3 +S 350,200,350,200,20,i3,LEFT,CALU3 +S 400,200,400,200,20,nq,LEFT,CALU3 +S 430,290,430,480,30,*,UP,NTIE +S 430,20,430,160,30,*,DOWN,PTIE +S 430,300,430,470,20,*,UP,ALU1 +S 430,30,430,150,20,*,DOWN,ALU1 +S 310,330,310,420,30,*,DOWN,PDIF +S 130,330,130,460,30,*,DOWN,PDIF +S 250,330,250,460,30,*,DOWN,PDIF +S 370,330,370,460,30,*,DOWN,PDIF +S 160,310,160,440,10,*,UP,PTRANS +S 340,310,340,440,10,*,UP,PTRANS +S 280,310,280,440,10,*,UP,PTRANS +S 220,310,220,440,10,*,UP,PTRANS +S 190,330,190,420,30,*,DOWN,PDIF +S 280,10,280,140,10,*,DOWN,NTRANS +S 240,10,240,140,10,*,DOWN,NTRANS +S 200,10,200,140,10,*,DOWN,NTRANS +S 160,10,160,140,10,*,DOWN,NTRANS +S 130,30,130,120,30,*,DOWN,NDIF +S 310,30,310,120,30,*,DOWN,NDIF +S 160,140,160,310,10,*,DOWN,POLY +S 200,310,220,310,10,*,RIGHT,POLY +S 200,140,200,310,10,*,UP,POLY +S 130,50,130,100,20,*,DOWN,ALU1 +S 370,400,370,450,20,*,DOWN,ALU1 +S 250,400,250,450,20,*,DOWN,ALU1 +S 350,100,350,350,20,*,UP,ALU1 +S 190,350,350,350,20,*,LEFT,ALU1 +S 130,350,130,450,20,*,DOWN,ALU1 +S 70,290,70,480,30,*,UP,NTIE +S 70,20,70,160,30,*,DOWN,PTIE +S 70,30,70,150,20,*,DOWN,ALU1 +S 70,300,70,470,20,*,UP,ALU1 +S 0,390,500,390,240,*,RIGHT,NWELL +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 260,310,280,310,10,*,RIGHT,POLY +S 310,310,340,310,10,*,RIGHT,POLY +S 310,100,350,100,20,*,RIGHT,ALU1 +V 200,200,CONT_POLY,* +V 150,200,CONT_POLY,* +V 250,200,CONT_POLY,* +V 300,200,CONT_POLY,* +V 400,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 300,200,CONT_VIA,* +V 150,200,CONT_VIA,* +V 200,200,CONT_VIA,* +V 350,200,CONT_VIA2,* +V 400,200,CONT_VIA2,* +V 250,200,CONT_VIA2,* +V 150,200,CONT_VIA2,* +V 200,200,CONT_VIA2,* +V 430,470,CONT_BODY_N,* +V 430,350,CONT_BODY_N,* +V 430,300,CONT_BODY_N,* +V 430,400,CONT_BODY_N,* +V 430,30,CONT_BODY_P,* +V 430,100,CONT_BODY_P,* +V 430,150,CONT_BODY_P,* +V 250,450,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 370,400,CONT_DIF_P,* +V 310,350,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 130,350,CONT_DIF_P,* +V 130,400,CONT_DIF_P,* +V 190,470,CONT_BODY_N,* +V 310,470,CONT_BODY_N,* +V 130,450,CONT_DIF_P,* +V 370,450,CONT_DIF_P,* +V 130,100,CONT_DIF_N,* +V 130,50,CONT_DIF_N,* +V 70,350,CONT_BODY_N,* +V 70,470,CONT_BODY_N,* +V 70,400,CONT_BODY_N,* +V 70,300,CONT_BODY_N,* +V 70,150,CONT_BODY_P,* +V 70,100,CONT_BODY_P,* +V 70,30,CONT_BODY_P,* +V 310,100,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_dec_nand4.vbe b/alliance/src/cells/src/rflib/rf_dec_nand4.vbe new file mode 100644 index 00000000..b8fb199a --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nand4.vbe @@ -0,0 +1,22 @@ +ENTITY rf_dec_nand4 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nand4; + +ARCHITECTURE VBE OF rf_dec_nand4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nand4" + SEVERITY WARNING; + + nq <= not(i0 and i1 and i2 and i3); + +END; diff --git a/alliance/src/cells/src/rflib/rf_dec_nao3.ap b/alliance/src/cells/src/rflib/rf_dec_nao3.ap new file mode 100644 index 00000000..d11fca4c --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nao3.ap @@ -0,0 +1,62 @@ +V ALLIANCE : 6 +H rf_dec_nao3,P, 7/11/2000,10 +A 0,0,250,500 +S 200,350,200,350,20,i2,LEFT,CALU2 +S 200,200,200,350,20,*,DOWN,ALU1 +S 210,400,210,450,20,*,DOWN,ALU1 +S 100,400,100,400,20,i0,LEFT,CALU2 +S 100,200,120,200,30,*,RIGHT,POLY +S 120,260,120,490,10,*,UP,PTRANS +S 100,250,100,400,20,*,UP,ALU1 +S 50,200,100,200,20,*,RIGHT,ALU2 +S 0,470,250,470,60,vdd,RIGHT,CALU1 +S 0,30,250,30,60,vss,RIGHT,CALU1 +S 0,390,250,390,240,*,RIGHT,NWELL +S 180,260,180,490,10,*,UP,PTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 30,100,150,100,20,*,LEFT,ALU1 +S 150,150,150,400,20,*,DOWN,ALU1 +S 90,150,150,150,20,*,LEFT,ALU1 +S 60,60,60,190,10,*,DOWN,NTRANS +S 120,60,120,190,10,*,DOWN,NTRANS +S 150,80,150,170,30,*,UP,NDIF +S 30,80,30,170,30,*,UP,NDIF +S 90,80,90,170,30,*,UP,NDIF +S 180,200,210,200,30,*,RIGHT,POLY +S 180,60,180,190,10,*,DOWN,NTRANS +S 210,40,210,170,30,*,UP,NDIF +S 150,280,150,470,20,*,DOWN,PDIF +S 180,190,180,260,10,*,DOWN,POLY +S 120,190,120,260,10,*,DOWN,POLY +S 60,190,60,260,10,*,DOWN,POLY +S 70,250,100,250,20,*,RIGHT,ALU1 +S 60,260,60,490,10,*,UP,PTRANS +S 30,280,30,470,30,*,DOWN,PDIF +S 90,280,90,470,20,*,DOWN,PDIF +S 30,300,30,450,20,*,DOWN,ALU1 +S 220,40,220,170,30,*,UP,NDIF +S 50,200,50,200,20,i1,LEFT,CALU2 +S 100,150,100,150,20,nq,LEFT,CALU2 +V 200,350,CONT_VIA,* +V 30,300,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 100,400,CONT_VIA,* +V 210,450,CONT_DIF_P,* +V 150,100,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,30,CONT_BODY_P,* +V 150,30,CONT_BODY_P,* +V 210,50,CONT_DIF_N,* +V 100,200,CONT_VIA,* +V 100,200,CONT_POLY,* +V 90,150,CONT_DIF_N,* +V 200,200,CONT_POLY,* +V 100,150,CONT_VIA,* +V 150,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 70,250,CONT_POLY,* +V 30,450,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_dec_nao3.vbe b/alliance/src/cells/src/rflib/rf_dec_nao3.vbe new file mode 100644 index 00000000..6f76808b --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nao3.vbe @@ -0,0 +1,21 @@ +ENTITY rf_dec_nao3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nao3; + +ARCHITECTURE VBE OF rf_dec_nao3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nao3" + SEVERITY WARNING; + + nq <= not(i2 and (i1 or i0)); + +END; diff --git a/alliance/src/cells/src/rflib/rf_dec_nbuf.ap b/alliance/src/cells/src/rflib/rf_dec_nbuf.ap new file mode 100644 index 00000000..972ec4ca --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nbuf.ap @@ -0,0 +1,79 @@ +V ALLIANCE : 6 +H rf_dec_nbuf,P,15/ 3/2001,10 +A 0,0,550,500 +S 90,100,90,400,20,*,DOWN,ALU1 +S 100,250,210,250,20,*,RIGHT,ALU1 +S 0,390,550,390,240,*,LEFT,NWELL +S 0,470,550,470,60,vdd,RIGHT,CALU1 +S 0,30,550,30,60,vss,RIGHT,CALU1 +S 340,20,340,160,30,*,DOWN,PTIE +S 340,290,340,480,30,*,UP,NTIE +S 340,300,340,470,20,*,UP,ALU1 +S 340,30,340,150,20,*,DOWN,ALU1 +S 150,280,150,470,30,*,DOWN,PDIF +S 30,280,30,470,30,*,DOWN,PDIF +S 30,50,30,100,20,*,DOWN,ALU1 +S 30,300,30,450,20,*,UP,ALU1 +S 180,260,180,490,10,*,UP,PTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 120,260,120,490,10,*,UP,PTRANS +S 60,260,60,490,10,*,UP,PTRANS +S 90,280,90,470,30,*,DOWN,PDIF +S 180,10,180,140,10,*,DOWN,NTRANS +S 240,10,240,140,10,*,DOWN,NTRANS +S 60,10,60,140,10,*,DOWN,NTRANS +S 120,10,120,140,10,*,DOWN,NTRANS +S 150,30,150,120,30,*,UP,NDIF +S 210,30,210,120,30,*,UP,NDIF +S 30,30,30,120,30,*,UP,NDIF +S 90,30,90,120,30,*,UP,NDIF +S 240,260,240,490,10,*,UP,PTRANS +S 60,140,60,260,10,*,UP,POLY +S 120,140,120,260,10,*,UP,POLY +S 180,140,180,260,10,*,UP,POLY +S 240,140,240,260,10,*,UP,POLY +S 210,100,210,400,20,*,DOWN,ALU1 +S 270,300,270,450,20,*,UP,ALU1 +S 270,50,270,100,20,*,DOWN,ALU1 +S 270,30,270,120,30,*,UP,NDIF +S 270,280,270,470,30,*,DOWN,PDIF +S 150,300,150,450,20,*,DOWN,ALU1 +S 500,100,500,400,10,i,UP,CALU1 +S 60,200,500,200,30,*,RIGHT,POLY +S 100,100,200,100,20,nq,RIGHT,CALU2 +V 340,150,CONT_BODY_P,* +V 340,30,CONT_BODY_P,* +V 340,100,CONT_BODY_P,* +V 340,300,CONT_BODY_N,* +V 340,350,CONT_BODY_N,* +V 340,400,CONT_BODY_N,* +V 340,470,CONT_BODY_N,* +V 150,50,CONT_DIF_N,* +V 150,450,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 30,50,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,450,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,100,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 270,400,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,450,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 500,200,CONT_POLY,* +V 200,100,CONT_VIA,* +V 100,100,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_dec_nbuf.vbe b/alliance/src/cells/src/rflib/rf_dec_nbuf.vbe new file mode 100644 index 00000000..336421b0 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nbuf.vbe @@ -0,0 +1,19 @@ +ENTITY rf_dec_nbuf IS +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nbuf; + +ARCHITECTURE VBE OF rf_dec_nbuf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nbuf" + SEVERITY WARNING; + + nq <= not i; + +END; diff --git a/alliance/src/cells/src/rflib/rf_dec_nor3.ap b/alliance/src/cells/src/rflib/rf_dec_nor3.ap new file mode 100644 index 00000000..e15c13d4 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nor3.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H rf_dec_nor3,P,22/ 8/2000,10 +A 0,0,250,500 +S 50,200,50,200,20,i1,LEFT,CALU2 +S 50,200,100,200,20,*,RIGHT,ALU2 +S 100,150,100,150,20,nq,LEFT,CALU2 +S 220,40,220,120,30,*,UP,NDIF +S 200,100,200,100,20,i2,LEFT,CALU2 +S 200,100,200,150,20,*,UP,ALU1 +S 150,100,150,150,20,*,DOWN,ALU1 +S 50,150,150,150,20,*,RIGHT,ALU1 +S 180,150,210,150,30,*,RIGHT,POLY +S 100,250,100,400,20,*,UP,ALU1 +S 0,470,250,470,60,vdd,RIGHT,CALU1 +S 0,30,250,30,60,vss,RIGHT,CALU1 +S 210,300,210,450,20,*,DOWN,ALU1 +S 50,100,50,400,20,*,DOWN,ALU1 +S 0,390,250,390,240,*,RIGHT,NWELL +S 60,140,60,240,10,*,DOWN,POLY +S 60,240,110,240,10,*,LEFT,POLY +S 180,260,180,490,10,*,UP,PTRANS +S 50,280,50,420,30,*,DOWN,PDIF +S 100,260,100,490,10,*,UP,PTRANS +S 70,280,70,420,30,*,DOWN,PDIF +S 140,260,140,490,10,*,UP,PTRANS +S 120,60,120,140,10,*,DOWN,NTRANS +S 180,60,180,140,10,*,DOWN,NTRANS +S 60,60,60,140,10,*,DOWN,NTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 90,40,90,120,30,*,UP,NDIF +S 30,80,30,120,30,*,UP,NDIF +S 210,40,210,120,30,*,UP,NDIF +S 150,80,150,120,30,*,UP,NDIF +S 30,100,150,100,20,*,LEFT,ALU1 +S 120,140,120,210,10,*,DOWN,POLY +S 140,190,140,260,10,*,DOWN,POLY +S 100,200,140,200,30,*,RIGHT,POLY +S 180,140,180,260,10,*,UP,POLY +S 100,400,100,400,20,i0,LEFT,CALU2 +V 200,100,CONT_VIA,* +V 100,150,CONT_VIA,* +V 200,150,CONT_POLY,* +V 210,300,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,400,CONT_DIF_P,* +V 100,400,CONT_VIA,* +V 100,250,CONT_POLY,* +V 30,470,CONT_BODY_N,* +V 210,450,CONT_DIF_P,* +V 150,100,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 90,50,CONT_DIF_N,* +V 30,30,CONT_BODY_P,* +V 150,30,CONT_BODY_P,* +V 210,50,CONT_DIF_N,* +V 100,200,CONT_VIA,* +V 100,200,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_dec_nor3.vbe b/alliance/src/cells/src/rflib/rf_dec_nor3.vbe new file mode 100644 index 00000000..a13eb4b1 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_dec_nor3.vbe @@ -0,0 +1,21 @@ +ENTITY rf_dec_nor3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nor3; + +ARCHITECTURE VBE OF rf_dec_nor3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nor3" + SEVERITY WARNING; + + nq <= not(i0 or i1 or i2); + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_buf.ap b/alliance/src/cells/src/rflib/rf_fifo_buf.ap new file mode 100644 index 00000000..a7c73bb5 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_buf.ap @@ -0,0 +1,218 @@ +V ALLIANCE : 6 +H rf_fifo_buf,P,11/ 4/2002,10 +A 0,0,500,1000 +R 400,800,ref_ref,reset +S 300,750,350,750,20,*,RIGHT,ALU1 +S 350,800,400,800,20,*,LEFT,ALU1 +S 100,850,150,850,20,*,RIGHT,ALU1 +S 170,400,230,400,20,*,RIGHT,ALU1 +S 170,100,230,100,20,*,RIGHT,ALU1 +S 200,100,250,100,20,ckm,RIGHT,CALU2 +S 150,400,200,400,20,cks,LEFT,CALU2 +S 350,800,400,800,20,reset,RIGHT,CALU2 +S 100,850,150,850,20,r,RIGHT,CALU2 +S 300,750,350,750,20,w,RIGHT,CALU2 +S 0,530,500,530,60,vdd,RIGHT,CALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,610,540,610,240,*,RIGHT,NWELL +S 0,390,540,390,240,*,RIGHT,NWELL +S 50,100,50,400,20,xcks,DOWN,CALU1 +S 350,100,350,400,20,xckm,DOWN,CALU1 +S 250,600,250,900,20,nw,DOWN,CALU1 +S 280,750,300,750,30,*,RIGHT,POLY +S 80,850,100,850,30,*,RIGHT,POLY +S 110,880,110,970,30,*,DOWN,NDIF +S 110,900,110,950,20,*,DOWN,ALU1 +S 80,740,80,860,10,*,DOWN,POLY +S 80,860,80,990,10,*,DOWN,NTRANS +S 50,880,50,970,30,*,UP,NDIF +S 400,400,430,400,20,*,RIGHT,ALU1 +S 400,350,440,350,20,*,RIGHT,ALU1 +S 400,300,440,300,20,*,RIGHT,ALU1 +S 400,150,440,150,20,*,RIGHT,ALU1 +S 400,100,440,100,20,*,RIGHT,ALU1 +S 400,100,400,400,20,xreset,DOWN,CALU1 +S 450,250,470,250,30,*,RIGHT,POLY +S 470,190,470,260,10,*,DOWN,POLY +S 280,740,280,810,10,*,DOWN,POLY +S 140,390,200,390,10,*,RIGHT,POLY +S 200,110,260,110,10,*,RIGHT,POLY +S 300,200,320,200,30,*,RIGHT,POLY +S 80,200,100,200,30,*,RIGHT,POLY +S 230,200,300,200,20,*,RIGHT,ALU1 +S 320,190,320,260,10,*,DOWN,POLY +S 260,190,260,260,10,*,DOWN,POLY +S 230,150,230,350,20,*,DOWN,ALU1 +S 260,110,260,190,10,*,DOWN,NTRANS +S 230,130,230,170,30,*,UP,NDIF +S 230,280,230,370,30,*,DOWN,PDIF +S 260,260,260,390,10,*,UP,PTRANS +S 290,280,290,470,30,*,UP,PDIF +S 320,260,320,490,10,*,UP,PTRANS +S 350,280,350,470,30,*,DOWN,PDIF +S 320,60,320,190,10,*,DOWN,NTRANS +S 290,40,290,170,30,*,UP,NDIF +S 350,80,350,170,30,*,UP,NDIF +S 290,300,290,450,20,*,DOWN,ALU1 +S 290,50,290,150,20,*,DOWN,ALU1 +S 140,190,140,260,10,*,DOWN,POLY +S 170,150,170,350,20,*,DOWN,ALU1 +S 140,110,140,190,10,*,DOWN,NTRANS +S 170,130,170,170,30,*,UP,NDIF +S 80,190,80,260,10,*,DOWN,POLY +S 100,200,170,200,20,*,RIGHT,ALU1 +S 170,280,170,370,30,*,DOWN,PDIF +S 140,260,140,390,10,*,UP,PTRANS +S 110,40,110,170,30,*,UP,NDIF +S 110,50,110,150,20,*,DOWN,ALU1 +S 500,50,500,150,20,*,DOWN,ALU1 +S 500,40,500,170,30,*,UP,NDIF +S 80,60,80,190,10,*,DOWN,NTRANS +S 470,60,470,190,10,*,DOWN,NTRANS +S 50,80,50,170,30,*,UP,NDIF +S 440,80,440,170,30,*,UP,NDIF +S 80,260,80,490,10,*,UP,PTRANS +S 50,280,50,470,30,*,DOWN,PDIF +S 110,280,110,470,30,*,UP,PDIF +S 470,260,470,490,10,*,UP,PTRANS +S 500,280,500,470,30,*,UP,PDIF +S 440,280,440,470,30,*,DOWN,PDIF +S 110,300,110,450,20,*,DOWN,ALU1 +S 500,300,500,450,20,*,DOWN,ALU1 +S 280,510,280,740,10,*,UP,PTRANS +S 250,530,250,720,30,*,DOWN,PDIF +S 310,530,310,720,30,*,UP,PDIF +S 280,810,280,940,10,*,DOWN,NTRANS +S 310,830,310,960,30,*,DOWN,NDIF +S 250,830,250,920,30,*,UP,NDIF +S 310,850,310,950,20,*,DOWN,ALU1 +S 310,550,310,700,20,*,DOWN,ALU1 +S 50,530,50,720,30,*,DOWN,PDIF +S 80,510,80,740,10,*,UP,PTRANS +S 110,530,110,720,30,*,UP,PDIF +S 110,550,110,700,20,*,DOWN,ALU1 +S 500,550,500,700,20,*,DOWN,ALU1 +S 440,530,440,720,30,*,DOWN,PDIF +S 500,530,500,720,30,*,UP,PDIF +S 470,510,470,740,10,*,UP,PTRANS +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,970,500,970,60,vss,RIGHT,CALU1 +S 470,740,470,860,10,*,DOWN,POLY +S 400,800,470,800,30,*,RIGHT,POLY +S 440,830,440,920,30,*,UP,NDIF +S 470,810,470,940,10,*,DOWN,NTRANS +S 500,830,500,960,30,*,DOWN,NDIF +S 500,850,500,950,20,*,DOWN,ALU1 +S 450,250,500,250,20,*,RIGHT,TALU2 +S 450,250,450,600,20,nreset,DOWN,CALU3 +S 450,600,500,600,20,*,RIGHT,TALU2 +S 50,600,50,900,20,nr,DOWN,CALU1 +S 450,250,500,250,20,*,RIGHT,ALU2 +S 450,600,500,600,20,*,RIGHT,ALU2 +S 450,600,450,900,20,nreset,DOWN,CALU1 +V 200,100,CONT_VIA,* +V 200,400,CONT_VIA,* +V 100,850,CONT_VIA,* +V 400,800,CONT_VIA,* +V 300,750,CONT_VIA,* +V 250,970,CONT_BODY_P,* +V 370,970,CONT_BODY_P,* +V 300,750,CONT_POLY,* +V 100,850,CONT_POLY,* +V 110,950,CONT_DIF_N,* +V 110,900,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 450,600,CONT_VIA,* +V 450,600,CONT_VIA2,* +V 450,250,CONT_POLY,* +V 450,250,CONT_VIA,* +V 450,250,CONT_VIA2,* +V 440,30,CONT_BODY_P,* +V 350,30,CONT_BODY_P,* +V 230,30,CONT_BODY_P,* +V 170,30,CONT_BODY_P,* +V 30,30,CONT_BODY_P,* +V 230,470,CONT_BODY_N,* +V 170,470,CONT_BODY_N,* +V 200,100,CONT_POLY,* +V 200,400,CONT_POLY,* +V 300,200,CONT_POLY,* +V 230,150,CONT_DIF_N,* +V 230,350,CONT_DIF_P,* +V 290,450,CONT_DIF_P,* +V 290,400,CONT_DIF_P,* +V 290,350,CONT_DIF_P,* +V 350,400,CONT_DIF_P,* +V 230,300,CONT_DIF_P,* +V 350,350,CONT_DIF_P,* +V 290,300,CONT_DIF_P,* +V 290,50,CONT_DIF_N,* +V 290,100,CONT_DIF_N,* +V 290,150,CONT_DIF_N,* +V 350,150,CONT_DIF_N,* +V 350,100,CONT_DIF_N,* +V 290,50,CONT_DIF_N,* +V 170,150,CONT_DIF_N,* +V 100,200,CONT_POLY,* +V 170,300,CONT_DIF_P,* +V 110,50,CONT_DIF_N,* +V 110,50,CONT_DIF_N,* +V 110,150,CONT_DIF_N,* +V 110,100,CONT_DIF_N,* +V 50,150,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 440,150,CONT_DIF_N,* +V 440,100,CONT_DIF_N,* +V 500,150,CONT_DIF_N,* +V 110,400,CONT_DIF_P,* +V 110,450,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,400,CONT_DIF_P,* +V 110,300,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 500,450,CONT_DIF_P,* +V 500,400,CONT_DIF_P,* +V 500,350,CONT_DIF_P,* +V 500,300,CONT_DIF_P,* +V 440,300,CONT_DIF_P,* +V 440,350,CONT_DIF_P,* +V 440,400,CONT_DIF_P,* +V 310,600,CONT_DIF_P,* +V 310,650,CONT_DIF_P,* +V 310,700,CONT_DIF_P,* +V 250,600,CONT_DIF_P,* +V 250,650,CONT_DIF_P,* +V 250,700,CONT_DIF_P,* +V 310,550,CONT_DIF_P,* +V 250,900,CONT_DIF_N,* +V 250,850,CONT_DIF_N,* +V 310,900,CONT_DIF_N,* +V 310,950,CONT_DIF_N,* +V 310,850,CONT_DIF_N,* +V 50,700,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,600,CONT_DIF_P,* +V 110,700,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 110,550,CONT_DIF_P,* +V 110,950,CONT_DIF_N,* +V 500,550,CONT_DIF_P,* +V 500,600,CONT_DIF_P,* +V 500,650,CONT_DIF_P,* +V 500,700,CONT_DIF_P,* +V 440,600,CONT_DIF_P,* +V 500,50,CONT_DIF_N,* +V 500,100,CONT_DIF_N,* +V 400,800,CONT_POLY,* +V 440,650,CONT_DIF_P,* +V 440,700,CONT_DIF_P,* +V 500,850,CONT_DIF_N,* +V 500,900,CONT_DIF_N,* +V 440,850,CONT_DIF_N,* +V 440,900,CONT_DIF_N,* +V 500,950,CONT_DIF_N,* +V 440,970,CONT_BODY_P,* +V 180,970,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_buf.vbe b/alliance/src/cells/src/rflib/rf_fifo_buf.vbe new file mode 100644 index 00000000..2d64fed8 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_buf.vbe @@ -0,0 +1,33 @@ +ENTITY rf_fifo_buf IS +PORT ( + cks : in BIT; + ckm : in BIT; + r : in BIT; + w : in BIT; + reset : in BIT; + xcks : out BIT; + xckm : out BIT; + nr : out BIT; + nw : out BIT; + xreset : out BIT; + nreset : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_buf; + +ARCHITECTURE VBE OF rf_fifo_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_clock" + SEVERITY WARNING; + + xcks <= cks; + xckm <= ckm; + nr <= not r; + nw <= not w; + xreset <= reset; + nreset <= not reset; + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_clock.ap b/alliance/src/cells/src/rflib/rf_fifo_clock.ap new file mode 100644 index 00000000..b740ff85 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_clock.ap @@ -0,0 +1,266 @@ +V ALLIANCE : 6 +H rf_fifo_clock,P, 6/ 4/2002,10 +A 0,0,500,1000 +R 250,700,ref_ref,ck_25 +S 150,400,450,400,20,*,RIGHT,TALU2 +S 200,850,350,850,20,*,RIGHT,TALU2 +S 450,250,500,250,20,*,LEFT,ALU2 +S 400,400,450,400,20,*,LEFT,ALU2 +S 300,600,450,600,20,*,RIGHT,TALU2 +S 300,600,350,600,20,*,LEFT,ALU2 +S 400,600,450,600,20,*,RIGHT,ALU2 +S 320,150,320,200,20,*,DOWN,ALU1 +S 310,50,310,100,20,*,DOWN,ALU1 +S 500,200,500,250,20,*,DOWN,ALU1 +S 80,250,80,300,20,*,UP,ALU1 +S 60,140,60,310,10,*,UP,POLY +S 90,350,90,450,20,*,DOWN,ALU1 +S 30,100,30,400,20,*,DOWN,ALU1 +S 30,330,30,420,30,*,UP,PDIF +S 60,310,60,440,10,*,UP,PTRANS +S 150,700,200,700,20,*,LEFT,ALU1 +S 450,750,450,800,20,*,DOWN,ALU1 +S 300,800,350,800,20,*,RIGHT,ALU1 +S 300,850,350,850,20,*,LEFT,ALU1 +S 400,800,450,800,20,*,LEFT,ALU2 +S 300,800,350,800,20,*,RIGHT,ALU2 +S 380,900,380,950,20,*,DOWN,ALU1 +S 200,850,350,850,20,*,LEFT,ALU2 +S 150,400,200,400,20,*,RIGHT,ALU2 +S 200,400,200,850,20,ckm,UP,CALU3 +S 0,390,540,390,240,*,RIGHT,NWELL +S 0,610,540,610,240,*,RIGHT,NWELL +S 100,250,500,250,20,*,RIGHT,TALU2 +S 500,250,500,700,20,ck,DOWN,CALU3 +S 460,250,490,250,30,*,LEFT,POLY +S 480,250,500,250,20,*,RIGHT,ALU1 +S 430,400,450,400,20,*,RIGHT,ALU1 +S 430,330,430,420,30,*,UP,PDIF +S 460,60,460,140,10,*,DOWN,NTRANS +S 430,80,430,120,30,*,UP,NDIF +S 460,310,460,440,10,*,UP,PTRANS +S 460,140,460,310,10,*,DOWN,POLY +S 430,100,430,400,20,*,DOWN,ALU1 +S 100,600,100,900,20,ckok,UP,CALU1 +S 240,900,260,900,20,*,RIGHT,ALU1 +S 240,750,240,900,20,*,DOWN,ALU1 +S 130,750,190,750,30,*,RIGHT,POLY +S 250,400,300,400,20,*,RIGHT,ALU2 +S 400,200,400,600,20,*,DOWN,ALU3 +S 300,200,320,200,20,*,RIGHT,ALU1 +S 300,200,400,200,20,*,RIGHT,ALU2 +S 320,200,340,200,30,*,RIGHT,POLY +S 280,250,300,250,30,*,RIGHT,POLY +S 300,250,370,250,20,*,RIGHT,ALU1 +S 350,250,350,600,20,*,DOWN,ALU3 +S 100,250,350,250,20,*,RIGHT,ALU2 +S 80,250,100,250,20,*,RIGHT,ALU1 +S 100,200,120,200,30,*,LEFT,POLY +S 60,250,80,250,30,*,RIGHT,POLY +S 30,200,100,200,20,*,RIGHT,ALU1 +S 180,830,180,970,70,*,UP,NDIF +S 180,880,180,920,30,*,DOWN,NDIF +S 180,850,180,950,20,*,DOWN,ALU1 +S 40,900,100,900,20,*,RIGHT,ALU1 +S 40,850,100,850,20,*,RIGHT,ALU1 +S 100,530,100,670,30,*,UP,PDIF +S 130,810,130,990,10,*,DOWN,NTRANS +S 70,810,70,990,10,*,DOWN,NTRANS +S 40,830,40,970,30,*,DOWN,NDIF +S 100,830,100,970,30,*,DOWN,NDIF +S 130,510,130,690,10,*,UP,PTRANS +S 130,690,130,810,10,*,DOWN,POLY +S 70,690,70,810,10,*,DOWN,POLY +S 190,750,320,750,20,*,RIGHT,ALU1 +S 440,850,440,900,20,*,DOWN,ALU1 +S 250,100,250,400,20,*,UP,ALU1 +S 150,100,150,400,20,*,UP,ALU1 +S 370,100,370,350,20,*,DOWN,ALU1 +S 340,140,340,260,10,*,DOWN,POLY +S 370,280,370,370,30,*,UP,PDIF +S 340,260,340,390,10,*,UP,PTRANS +S 500,900,500,950,20,*,DOWN,ALU1 +S 320,900,320,950,20,*,DOWN,ALU1 +S 320,880,320,960,30,*,DOWN,NDIF +S 380,880,380,960,30,*,DOWN,NDIF +S 380,880,380,920,30,*,DOWN,NDIF +S 500,880,500,960,30,*,DOWN,NDIF +S 90,280,90,470,30,*,UP,PDIF +S 150,280,150,470,30,*,UP,PDIF +S 120,260,120,490,10,*,UP,PTRANS +S 120,60,120,190,10,*,DOWN,NTRANS +S 60,60,60,140,10,*,DOWN,NTRANS +S 30,80,30,120,30,*,UP,NDIF +S 150,80,150,170,30,*,UP,NDIF +S 90,40,90,170,30,*,UP,NDIF +S 120,190,120,260,10,*,DOWN,POLY +S 90,50,90,150,20,*,DOWN,ALU1 +S 500,50,500,100,20,*,DOWN,ALU1 +S 500,350,500,450,20,*,DOWN,ALU1 +S 310,300,310,450,20,*,DOWN,ALU1 +S 500,40,500,120,30,*,UP,NDIF +S 500,330,500,470,30,*,UP,PDIF +S 250,280,250,470,30,*,UP,PDIF +S 280,260,280,490,10,*,UP,PTRANS +S 310,280,310,470,30,*,UP,PDIF +S 340,60,340,140,10,*,DOWN,NTRANS +S 280,60,280,190,10,*,DOWN,NTRANS +S 310,40,310,170,30,*,UP,NDIF +S 250,80,250,170,30,*,UP,NDIF +S 370,80,370,120,30,*,UP,NDIF +S 280,190,280,260,10,*,DOWN,POLY +S 0,970,500,970,60,vss,RIGHT,CALU1 +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 440,880,440,910,30,*,DOWN,NDIF +S 410,860,410,930,10,*,DOWN,NTRANS +S 470,860,470,930,10,*,DOWN,NTRANS +S 260,880,260,910,30,*,DOWN,NDIF +S 290,860,290,930,10,*,DOWN,NTRANS +S 230,860,230,930,10,*,DOWN,NTRANS +S 470,510,470,690,10,*,UP,PTRANS +S 230,510,230,690,10,*,UP,PTRANS +S 440,530,440,670,30,*,UP,PDIF +S 410,510,410,690,10,*,UP,PTRANS +S 380,530,380,670,30,*,UP,PDIF +S 290,510,290,690,10,*,UP,PTRANS +S 260,530,260,670,30,*,UP,PDIF +S 320,530,320,670,30,*,UP,PDIF +S 500,530,500,670,30,*,UP,PDIF +S 180,550,180,650,20,*,UP,ALU1 +S 180,530,180,670,70,*,UP,PDIF +S 500,550,500,650,20,*,UP,ALU1 +S 470,690,470,860,10,*,UP,POLY +S 410,690,410,860,10,*,DOWN,POLY +S 380,650,400,650,20,*,RIGHT,ALU1 +S 320,600,320,750,20,*,DOWN,ALU1 +S 320,600,350,600,20,*,RIGHT,ALU1 +S 400,600,400,850,20,*,UP,ALU1 +S 230,690,230,860,10,*,DOWN,POLY +S 200,700,230,700,30,*,RIGHT,POLY +S 450,800,470,800,30,*,RIGHT,POLY +S 450,400,450,800,20,*,DOWN,ALU3 +S 290,690,290,860,10,*,UP,POLY +S 40,530,40,670,30,*,DOWN,PDIF +S 70,510,70,690,10,*,UP,PTRANS +S 400,850,440,850,20,*,RIGHT,ALU1 +S 50,650,50,800,20,wok,UP,CALU1 +S 40,550,40,600,20,*,UP,ALU1 +S 200,700,500,700,20,ck,RIGHT,CALU2 +S 300,400,300,800,20,cks,UP,CALU3 +S 350,850,410,850,30,*,RIGHT,POLY +S 300,800,450,800,20,*,RIGHT,TALU2 +S 450,400,450,800,20,*,DOWN,TALU3 +S 350,250,350,600,20,*,DOWN,TALU3 +S 400,200,400,600,20,*,DOWN,TALU3 +S 300,200,400,200,20,*,RIGHT,TALU2 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,530,500,530,60,vdd,RIGHT,CALU1 +V 30,400,CONT_DIF_P,* +V 200,850,CONT_VIA2,* +V 200,400,CONT_VIA2,* +V 480,250,CONT_POLY,* +V 500,250,CONT_VIA,* +V 500,250,CONT_VIA2,* +V 450,400,CONT_VIA,* +V 450,400,CONT_VIA2,* +V 430,350,CONT_DIF_P,* +V 430,400,CONT_DIF_P,* +V 430,100,CONT_DIF_N,* +V 30,350,CONT_DIF_P,* +V 150,400,CONT_VIA,* +V 300,400,CONT_VIA2,* +V 250,400,CONT_VIA,* +V 300,200,CONT_VIA,* +V 400,200,CONT_VIA2,* +V 320,200,CONT_POLY,* +V 300,250,CONT_POLY,* +V 350,250,CONT_VIA2,* +V 100,250,CONT_VIA,* +V 80,250,CONT_POLY,* +V 100,200,CONT_POLY,* +V 180,850,CONT_DIF_N,* +V 180,950,CONT_DIF_N,* +V 180,900,CONT_DIF_N,* +V 50,750,CONT_POLY,* +V 30,480,CONT_BODY_N,* +V 40,850,CONT_DIF_N,* +V 40,900,CONT_DIF_N,* +V 190,750,CONT_POLY,* +V 440,480,CONT_BODY_N,* +V 380,480,CONT_BODY_N,* +V 370,300,CONT_DIF_P,* +V 370,350,CONT_DIF_P,* +V 320,950,CONT_DIF_N,* +V 320,900,CONT_DIF_N,* +V 260,900,CONT_DIF_N,* +V 260,970,CONT_BODY_P,* +V 440,970,CONT_BODY_P,* +V 380,950,CONT_DIF_N,* +V 380,900,CONT_DIF_N,* +V 440,900,CONT_DIF_N,* +V 500,900,CONT_DIF_N,* +V 500,950,CONT_DIF_N,* +V 500,650,CONT_DIF_P,* +V 500,600,CONT_DIF_P,* +V 500,550,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,450,CONT_DIF_P,* +V 30,100,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 90,50,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 30,30,CONT_BODY_P,* +V 500,400,CONT_DIF_P,* +V 500,350,CONT_DIF_P,* +V 250,300,CONT_DIF_P,* +V 250,350,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 310,450,CONT_DIF_P,* +V 310,400,CONT_DIF_P,* +V 310,350,CONT_DIF_P,* +V 310,300,CONT_DIF_P,* +V 250,150,CONT_DIF_N,* +V 250,100,CONT_DIF_N,* +V 310,100,CONT_DIF_N,* +V 310,50,CONT_DIF_N,* +V 370,100,CONT_DIF_N,* +V 370,30,CONT_BODY_P,* +V 500,100,CONT_DIF_N,* +V 500,450,CONT_DIF_P,* +V 500,50,CONT_DIF_N,* +V 500,50,CONT_DIF_N,* +V 440,30,CONT_BODY_P,* +V 180,550,CONT_DIF_P,* +V 180,650,CONT_DIF_P,* +V 180,600,CONT_DIF_P,* +V 320,650,CONT_DIF_P,* +V 380,650,CONT_DIF_P,* +V 320,600,CONT_DIF_P,* +V 400,600,CONT_VIA2,* +V 400,600,CONT_VIA,* +V 350,600,CONT_VIA2,* +V 350,600,CONT_VIA,* +V 200,700,CONT_POLY,* +V 200,700,CONT_VIA,* +V 500,700,CONT_VIA2,* +V 450,800,CONT_VIA2,* +V 450,800,CONT_VIA,* +V 450,800,CONT_POLY,* +V 150,30,CONT_BODY_P,* +V 250,30,CONT_BODY_P,* +V 40,600,CONT_DIF_P,* +V 40,550,CONT_DIF_P,* +V 100,600,CONT_DIF_P,* +V 100,650,CONT_DIF_P,* +V 350,850,CONT_VIA,* +V 350,850,CONT_POLY,* +V 300,800,CONT_VIA2,* +V 300,800,CONT_VIA,* +V 300,800,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_clock.vbe b/alliance/src/cells/src/rflib/rf_fifo_clock.vbe new file mode 100644 index 00000000..27c0acf0 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_clock.vbe @@ -0,0 +1,39 @@ +ENTITY rf_fifo_clock IS +PORT ( + ck : in BIT; + wok : in BIT; + cks : inout BIT; + ckm : inout BIT; + ckok : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_clock; + +ARCHITECTURE VBE OF rf_fifo_clock IS + + SIGNAL nck : BIT; + SIGNAL sck : BIT; + SIGNAL mck : BIT; + SIGNAL nsck : BIT; + SIGNAL nmck : BIT; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_clock" + SEVERITY WARNING; + + nck <= not ck; + sck <= nck nor ckm; + mck <= ck nor cks; + nmck <= not mck; + nsck <= not sck; + cks <= not nsck; + ckm <= not nmck; + ckok <= mck nand wok; + +-- cks <= not(ck); +-- ckm <= ck; +-- ckok <= ckm nand wok; + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_empty.ap b/alliance/src/cells/src/rflib/rf_fifo_empty.ap new file mode 100644 index 00000000..c6fb47d8 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_empty.ap @@ -0,0 +1,99 @@ +V ALLIANCE : 6 +H rf_fifo_empty,P,13/ 4/2002,10 +A 0,0,500,500 +S 50,150,350,150,20,nreset,RIGHT,CALU2 +S 200,100,350,100,20,cks,LEFT,CALU2 +S 100,300,350,300,20,emptynext,RIGHT,CALU2 +S 150,200,350,200,20,ckm,LEFT,CALU2 +S 30,50,30,100,20,*,DOWN,ALU1 +S 150,80,150,170,30,*,DOWN,NDIF +S 90,80,90,170,30,*,DOWN,NDIF +S 120,60,120,190,10,*,UP,NTRANS +S 120,190,120,360,10,*,DOWN,POLY +S 30,30,30,170,30,*,DOWN,NDIF +S 60,60,60,190,10,*,UP,NTRANS +S 60,190,60,360,10,*,DOWN,POLY +S 40,250,40,400,20,*,DOWN,ALU1 +S 40,250,100,250,20,*,RIGHT,ALU1 +S 100,150,100,250,20,*,DOWN,ALU1 +S 40,400,90,400,20,*,LEFT,ALU1 +S 100,150,150,150,20,*,RIGHT,ALU1 +S 210,150,210,350,20,y,DOWN,ALU1 +S 330,150,330,350,20,z,DOWN,ALU1 +S 400,100,400,200,20,*,DOWN,ALU1 +S 270,100,400,100,20,*,LEFT,ALU1 +S 270,100,270,350,20,t,DOWN,ALU1 +S 310,400,450,400,20,*,RIGHT,ALU1 +S 300,110,300,190,10,*,UP,NTRANS +S 330,130,330,170,30,*,DOWN,NDIF +S 270,130,270,170,30,*,DOWN,NDIF +S 360,110,360,190,10,*,UP,NTRANS +S 330,330,330,370,30,*,DOWN,PDIF +S 360,310,360,390,10,*,DOWN,PTRANS +S 0,390,500,390,240,*,RIGHT,NWELL +S 180,250,320,250,10,*,RIGHT,POLY +S 180,250,180,420,10,*,DOWN,POLY +S 450,330,450,470,30,*,DOWN,PDIF +S 450,30,450,170,30,*,DOWN,NDIF +S 420,10,420,190,10,*,UP,NTRANS +S 420,310,420,490,10,*,DOWN,PTRANS +S 420,190,420,310,10,*,DOWN,POLY +S 210,300,360,300,10,*,RIGHT,POLY +S 250,400,300,400,50,*,RIGHT,PTRANS +S 180,400,230,400,50,*,RIGHT,PTRANS +S 390,330,390,470,30,*,DOWN,PDIF +S 390,30,390,170,30,*,DOWN,NDIF +S 360,190,360,310,10,*,DOWN,POLY +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 150,200,180,200,30,*,RIGHT,POLY +S 180,110,180,190,10,*,UP,NTRANS +S 150,380,150,470,30,*,DOWN,PDIF +S 30,380,30,470,30,*,DOWN,PDIF +S 60,360,60,490,10,*,DOWN,PTRANS +S 120,360,120,490,10,*,DOWN,PTRANS +S 90,380,90,470,30,*,DOWN,PDIF +S 210,130,210,170,30,*,DOWN,NDIF +S 220,110,300,110,10,*,RIGHT,POLY +S 90,300,120,300,30,*,RIGHT,POLY +S 100,300,100,350,20,*,DOWN,ALU1 +S 150,200,150,250,20,*,UP,ALU1 +S 50,150,50,200,20,*,DOWN,ALU1 +S 150,100,220,100,20,*,LEFT,ALU1 +S 450,100,450,400,20,empty,DOWN,CALU1 +V 30,100,CONT_DIF_N,* +V 50,200,CONT_POLY,* +V 330,470,CONT_BODY_N,* +V 310,400,CONT_POLY,* +V 220,300,CONT_POLY,* +V 320,250,CONT_POLY,* +V 270,150,CONT_DIF_N,* +V 400,200,CONT_POLY,* +V 450,150,CONT_DIF_N,* +V 450,350,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,450,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 390,450,CONT_DIF_P,* +V 330,150,CONT_DIF_N,* +V 390,50,CONT_DIF_N,* +V 160,200,CONT_POLY,* +V 100,300,CONT_POLY,* +V 210,450,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,50,CONT_DIF_N,* +V 210,150,CONT_DIF_N,* +V 220,100,CONT_POLY,* +V 150,150,CONT_DIF_N,* +V 90,400,CONT_DIF_P,* +V 210,30,CONT_BODY_P,* +V 330,30,CONT_BODY_P,* +V 200,100,CONT_VIA,* +V 50,150,CONT_VIA,* +V 150,200,CONT_VIA,* +V 100,300,CONT_VIA,* +V 450,400,CONT_DIF_P,* +V 450,100,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_empty.vbe b/alliance/src/cells/src/rflib/rf_fifo_empty.vbe new file mode 100644 index 00000000..f0cea2dd --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_empty.vbe @@ -0,0 +1,34 @@ +ENTITY rf_fifo_empty IS +PORT ( + ckm : in BIT; + nreset : in BIT; + emptynext : in BIT; + cks : in BIT; + empty : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_empty; + +ARCHITECTURE VBE OF rf_fifo_empty IS + SIGNAL latchm : REG_BIT REGISTER; + SIGNAL latchs : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_empty" + SEVERITY WARNING; + + label0 : BLOCK (ckm = '1') + BEGIN + latchm <= GUARDED (emptynext nand nreset); + END BLOCK label0; + + label1 : BLOCK (cks = '1') + BEGIN + latchs <= GUARDED (not latchm); + END BLOCK label1; + + empty <= (not latchs); + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_full.ap b/alliance/src/cells/src/rflib/rf_fifo_full.ap new file mode 100644 index 00000000..e8275509 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_full.ap @@ -0,0 +1,108 @@ +V ALLIANCE : 6 +H rf_fifo_full,P,13/ 4/2002,10 +A 0,0,500,500 +S 450,100,450,400,20,full,DOWN,CALU1 +S 200,100,350,100,20,cks,LEFT,CALU2 +S 50,150,350,150,20,reset,RIGHT,CALU2 +S 100,250,350,250,20,fullnext,RIGHT,CALU2 +S 150,200,350,200,20,ckm,LEFT,CALU2 +S 150,200,150,250,20,*,UP,ALU1 +S 150,100,220,100,20,*,LEFT,ALU1 +S 100,150,150,150,20,*,RIGHT,ALU1 +S 400,100,400,200,20,*,DOWN,ALU1 +S 270,100,400,100,20,*,LEFT,ALU1 +S 210,150,210,350,20,y,DOWN,ALU1 +S 270,100,270,350,20,t,DOWN,ALU1 +S 330,150,330,350,20,z,DOWN,ALU1 +S 310,400,450,400,20,*,RIGHT,ALU1 +S 300,110,300,190,10,*,UP,NTRANS +S 330,130,330,170,30,*,DOWN,NDIF +S 270,130,270,170,30,*,DOWN,NDIF +S 360,110,360,190,10,*,UP,NTRANS +S 330,330,330,370,30,*,DOWN,PDIF +S 360,310,360,390,10,*,DOWN,PTRANS +S 0,390,500,390,240,*,RIGHT,NWELL +S 180,250,320,250,10,*,RIGHT,POLY +S 180,250,180,420,10,*,DOWN,POLY +S 450,330,450,470,30,*,DOWN,PDIF +S 450,30,450,170,30,*,DOWN,NDIF +S 420,10,420,190,10,*,UP,NTRANS +S 420,310,420,490,10,*,DOWN,PTRANS +S 420,190,420,310,10,*,DOWN,POLY +S 210,300,360,300,10,*,RIGHT,POLY +S 250,400,300,400,50,*,RIGHT,PTRANS +S 180,400,230,400,50,*,RIGHT,PTRANS +S 390,330,390,470,30,*,DOWN,PDIF +S 390,30,390,170,30,*,DOWN,NDIF +S 360,190,360,310,10,*,DOWN,POLY +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 30,30,30,70,30,*,DOWN,NDIF +S 60,10,60,90,10,*,UP,NTRANS +S 120,10,120,90,10,*,UP,NTRANS +S 90,30,90,110,30,*,DOWN,NDIF +S 150,30,150,70,30,*,DOWN,NDIF +S 180,110,180,190,10,*,UP,NTRANS +S 150,130,150,170,30,*,DOWN,NDIF +S 210,130,210,170,30,*,DOWN,NDIF +S 220,110,300,110,10,*,RIGHT,POLY +S 160,200,180,200,30,*,RIGHT,POLY +S 390,200,420,200,30,*,RIGHT,POLY +S 30,100,30,150,20,*,DOWN,ALU1 +S 30,150,50,150,20,*,RIGHT,ALU1 +S 30,200,100,200,20,*,RIGHT,ALU1 +S 100,100,100,200,20,*,DOWN,ALU1 +S 60,260,60,490,10,*,DOWN,PTRANS +S 60,90,60,260,10,*,DOWN,POLY +S 120,90,120,260,10,*,UP,POLY +S 30,280,30,470,30,*,DOWN,PDIF +S 100,250,100,300,20,*,UP,ALU1 +S 100,250,120,250,30,*,RIGHT,POLY +S 90,280,90,470,30,*,DOWN,PDIF +S 120,260,120,490,10,*,DOWN,PTRANS +S 150,280,150,470,30,*,DOWN,PDIF +S 150,300,150,450,20,*,DOWN,ALU1 +S 30,200,30,400,20,*,DOWN,ALU1 +V 450,100,CONT_DIF_N,* +V 450,400,CONT_DIF_P,* +V 150,200,CONT_VIA,* +V 50,150,CONT_VIA,* +V 200,100,CONT_VIA,* +V 330,470,CONT_BODY_N,* +V 310,400,CONT_POLY,* +V 220,300,CONT_POLY,* +V 320,250,CONT_POLY,* +V 270,150,CONT_DIF_N,* +V 400,200,CONT_POLY,* +V 450,150,CONT_DIF_N,* +V 450,350,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,450,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 390,450,CONT_DIF_P,* +V 330,150,CONT_DIF_N,* +V 390,50,CONT_DIF_N,* +V 210,450,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 30,50,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 210,150,CONT_DIF_N,* +V 50,150,CONT_POLY,* +V 220,100,CONT_POLY,* +V 160,200,CONT_POLY,* +V 330,30,CONT_BODY_P,* +V 30,350,CONT_DIF_P,* +V 90,100,CONT_DIF_N,* +V 210,30,CONT_BODY_P,* +V 100,250,CONT_VIA,* +V 100,250,CONT_POLY,* +V 30,400,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 400,400,CONT_VIA,* +V 350,400,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_full.vbe b/alliance/src/cells/src/rflib/rf_fifo_full.vbe new file mode 100644 index 00000000..69a6c28c --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_full.vbe @@ -0,0 +1,34 @@ +ENTITY rf_fifo_full IS +PORT ( + ckm : in BIT; + reset : in BIT; + fullnext : in BIT; + cks : in BIT; + full : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_full; + +ARCHITECTURE VBE OF rf_fifo_full IS + SIGNAL latchm : REG_BIT REGISTER; + SIGNAL latchs : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_full" + SEVERITY WARNING; + + label0 : BLOCK (ckm = '1') + BEGIN + latchm <= GUARDED (fullnext nor reset); + END BLOCK label0; + + label1 : BLOCK (cks = '1') + BEGIN + latchs <= GUARDED (not latchm); + END BLOCK label1; + + full <= (not latchs); + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_inc.ap b/alliance/src/cells/src/rflib/rf_fifo_inc.ap new file mode 100644 index 00000000..d490d335 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_inc.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 6 +H rf_fifo_inc,P,13/ 4/2002,10 +A 0,0,500,500 +S 250,400,300,400,20,nval,LEFT,CALU2 +S 100,300,300,300,20,*,RIGHT,ALU1 +S 100,250,100,300,20,*,DOWN,ALU1 +S 50,100,50,400,20,inc,UP,CALU1 +S 300,400,360,400,20,*,RIGHT,ALU1 +S 340,190,410,190,20,*,RIGHT,ALU1 +S 410,100,410,400,20,*,UP,ALU1 +S 410,390,410,470,30,*,UP,PDIF +S 30,250,100,250,30,*,RIGHT,POLY +S 120,350,120,450,20,*,DOWN,ALU1 +S 240,350,240,470,20,*,UP,ALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 120,50,120,150,20,*,DOWN,ALU1 +S 0,50,0,150,20,*,UP,ALU1 +S 0,300,0,450,20,*,UP,ALU1 +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 30,190,30,260,10,*,DOWN,POLY +S 90,190,90,260,10,*,DOWN,POLY +S 270,190,270,260,10,*,DOWN,POLY +S 150,190,150,260,10,*,DOWN,POLY +S 230,190,340,190,10,*,RIGHT,POLY +S 190,190,190,260,10,*,DOWN,POLY +S 380,90,380,410,10,*,DOWN,POLY +S 120,80,120,170,30,*,DOWN,NDIF +S 60,80,60,170,30,*,DOWN,NDIF +S 0,30,0,170,30,*,DOWN,NDIF +S 260,80,260,170,30,*,DOWN,NDIF +S 230,60,230,190,10,*,UP,NTRANS +S 190,60,190,190,10,*,UP,NTRANS +S 380,10,380,90,10,*,UP,NTRANS +S 150,60,150,190,10,*,UP,NTRANS +S 30,60,30,190,10,*,UP,NTRANS +S 90,60,90,190,10,*,UP,NTRANS +S 210,260,210,390,10,*,UP,PTRANS +S 270,260,270,390,10,*,UP,PTRANS +S 180,280,180,370,30,*,DOWN,PDIF +S 150,260,150,390,10,*,UP,PTRANS +S 90,260,90,490,10,*,DOWN,PTRANS +S 60,280,60,470,30,*,DOWN,PDIF +S 120,280,120,470,30,*,DOWN,PDIF +S 30,260,30,490,10,*,DOWN,PTRANS +S 0,390,500,390,240,*,RIGHT,NWELL +S 350,430,350,470,30,*,UP,PDIF +S 380,410,380,490,10,*,UP,PTRANS +S 240,280,240,370,30,*,DOWN,PDIF +S 300,280,300,370,30,*,DOWN,PDIF +S 0,280,0,470,30,*,DOWN,PDIF +S 410,30,410,110,30,*,DOWN,NDIF +S 350,30,350,70,30,*,DOWN,NDIF +S 350,400,380,400,30,*,RIGHT,POLY +S 260,100,260,300,20,*,DOWN,ALU1 +S 100,200,150,200,20,ckm,LEFT,CALU2 +S 200,250,250,250,20,nreset,RIGHT,CALU2 +S 150,200,150,250,20,*,UP,ALU1 +S 200,200,200,250,20,*,DOWN,ALU1 +V 300,400,CONT_VIA,* +V 410,400,CONT_DIF_P,* +V 150,200,CONT_POLY,* +V 100,250,CONT_POLY,* +V 340,190,CONT_POLY,* +V 200,250,CONT_POLY,* +V 180,30,CONT_BODY_P,* +V 240,30,CONT_BODY_P,* +V 120,100,CONT_DIF_N,* +V 60,150,CONT_DIF_N,* +V 60,100,CONT_DIF_N,* +V 0,50,CONT_DIF_N,* +V 0,150,CONT_DIF_N,* +V 0,100,CONT_DIF_N,* +V 260,100,CONT_DIF_N,* +V 260,150,CONT_DIF_N,* +V 120,150,CONT_DIF_N,* +V 120,350,CONT_DIF_P,* +V 60,350,CONT_DIF_P,* +V 60,400,CONT_DIF_P,* +V 180,470,CONT_BODY_N,* +V 240,470,CONT_BODY_N,* +V 350,450,CONT_DIF_P,* +V 240,350,CONT_DIF_P,* +V 180,300,CONT_DIF_P,* +V 300,300,CONT_DIF_P,* +V 120,450,CONT_DIF_P,* +V 120,400,CONT_DIF_P,* +V 0,300,CONT_DIF_P,* +V 0,450,CONT_DIF_P,* +V 0,350,CONT_DIF_P,* +V 0,400,CONT_DIF_P,* +V 410,100,CONT_DIF_N,* +V 350,50,CONT_DIF_N,* +V 360,400,CONT_POLY,* +V 150,200,CONT_VIA,* +V 200,250,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_inc.vbe b/alliance/src/cells/src/rflib/rf_fifo_inc.vbe new file mode 100644 index 00000000..ee01d1c5 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_inc.vbe @@ -0,0 +1,21 @@ +ENTITY rf_fifo_inc IS +PORT ( + ckm : in BIT; + nreset : in BIT; + nval : in BIT; + inc : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_inc; + +ARCHITECTURE VBE OF rf_fifo_inc IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_inc" + SEVERITY WARNING; + + inc <= (not nval) and nreset and ckm; + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_nop.ap b/alliance/src/cells/src/rflib/rf_fifo_nop.ap new file mode 100644 index 00000000..1ea6a132 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_nop.ap @@ -0,0 +1,108 @@ +V ALLIANCE : 6 +H rf_fifo_nop,P,13/ 4/2002,10 +A 0,0,500,500 +S 250,150,400,150,20,rw,LEFT,CALU2 +S 200,250,250,250,20,nreset,LEFT,CALU2 +S 250,400,300,400,20,nval,RIGHT,CALU2 +S 100,300,300,300,20,*,RIGHT,ALU1 +S 100,250,100,300,20,*,DOWN,ALU1 +S 50,100,50,400,20,nop,UP,CALU1 +S 0,280,0,470,30,*,DOWN,PDIF +S 300,280,300,370,30,*,DOWN,PDIF +S 240,280,240,370,30,*,DOWN,PDIF +S 440,410,440,490,10,*,UP,PTRANS +S 380,410,380,490,10,*,UP,PTRANS +S 350,430,350,470,30,*,UP,PDIF +S 470,430,470,470,30,*,UP,PDIF +S 0,390,500,390,240,*,RIGHT,NWELL +S 30,260,30,490,10,*,DOWN,PTRANS +S 120,280,120,470,30,*,DOWN,PDIF +S 60,280,60,470,30,*,DOWN,PDIF +S 90,260,90,490,10,*,DOWN,PTRANS +S 150,260,150,390,10,*,UP,PTRANS +S 180,280,180,370,30,*,DOWN,PDIF +S 270,260,270,390,10,*,UP,PTRANS +S 210,260,210,390,10,*,UP,PTRANS +S 90,60,90,190,10,*,UP,NTRANS +S 30,60,30,190,10,*,UP,NTRANS +S 150,60,150,190,10,*,UP,NTRANS +S 440,10,440,90,10,*,UP,NTRANS +S 380,10,380,90,10,*,UP,NTRANS +S 190,60,190,190,10,*,UP,NTRANS +S 230,60,230,190,10,*,UP,NTRANS +S 260,80,260,170,30,*,DOWN,NDIF +S 350,30,350,110,30,*,DOWN,NDIF +S 0,30,0,170,30,*,DOWN,NDIF +S 410,30,410,70,30,*,DOWN,NDIF +S 470,30,470,70,30,*,DOWN,NDIF +S 60,80,60,170,30,*,DOWN,NDIF +S 120,80,120,170,30,*,DOWN,NDIF +S 380,90,380,410,10,*,DOWN,POLY +S 440,90,440,410,10,*,UP,POLY +S 190,190,190,260,10,*,DOWN,POLY +S 230,190,340,190,10,*,RIGHT,POLY +S 150,190,150,260,10,*,DOWN,POLY +S 270,190,270,260,10,*,DOWN,POLY +S 90,190,90,260,10,*,DOWN,POLY +S 30,190,30,260,10,*,DOWN,POLY +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,300,0,450,20,*,UP,ALU1 +S 0,50,0,150,20,*,UP,ALU1 +S 120,50,120,150,20,*,DOWN,ALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 240,350,240,470,20,*,UP,ALU1 +S 380,300,410,300,30,*,RIGHT,POLY +S 120,350,120,450,20,*,DOWN,ALU1 +S 30,250,100,250,30,*,RIGHT,POLY +S 410,390,410,470,30,*,UP,PDIF +S 260,100,260,300,20,*,DOWN,ALU1 +S 350,100,350,400,20,*,UP,ALU1 +S 350,400,410,400,20,*,RIGHT,ALU1 +S 100,200,150,200,20,ckm,LEFT,CALU2 +S 100,200,150,200,20,*,LEFT,ALU1 +S 150,250,200,250,20,*,LEFT,ALU1 +S 400,300,450,300,20,*,RIGHT,ALU1 +S 400,150,450,150,20,*,RIGHT,ALU1 +S 250,300,400,300,20,rwok,LEFT,CALU2 +V 300,400,CONT_VIA,* +V 0,400,CONT_DIF_P,* +V 0,350,CONT_DIF_P,* +V 0,450,CONT_DIF_P,* +V 0,300,CONT_DIF_P,* +V 120,400,CONT_DIF_P,* +V 120,450,CONT_DIF_P,* +V 300,300,CONT_DIF_P,* +V 180,300,CONT_DIF_P,* +V 240,350,CONT_DIF_P,* +V 350,450,CONT_DIF_P,* +V 470,450,CONT_DIF_P,* +V 240,470,CONT_BODY_N,* +V 180,470,CONT_BODY_N,* +V 60,400,CONT_DIF_P,* +V 60,350,CONT_DIF_P,* +V 120,350,CONT_DIF_P,* +V 120,150,CONT_DIF_N,* +V 260,150,CONT_DIF_N,* +V 260,100,CONT_DIF_N,* +V 350,100,CONT_DIF_N,* +V 470,50,CONT_DIF_N,* +V 0,100,CONT_DIF_N,* +V 0,150,CONT_DIF_N,* +V 0,50,CONT_DIF_N,* +V 60,100,CONT_DIF_N,* +V 60,150,CONT_DIF_N,* +V 120,100,CONT_DIF_N,* +V 240,30,CONT_BODY_P,* +V 180,30,CONT_BODY_P,* +V 200,250,CONT_POLY,* +V 340,190,CONT_POLY,* +V 400,300,CONT_POLY,* +V 450,150,CONT_POLY,* +V 100,250,CONT_POLY,* +V 150,200,CONT_POLY,* +V 410,400,CONT_DIF_P,* +V 150,200,CONT_VIA,* +V 200,250,CONT_VIA,* +V 400,300,CONT_VIA,* +V 400,150,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_nop.vbe b/alliance/src/cells/src/rflib/rf_fifo_nop.vbe new file mode 100644 index 00000000..b032c3a1 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_nop.vbe @@ -0,0 +1,24 @@ +ENTITY rf_fifo_nop IS +PORT ( + ckm : in BIT; + nreset : in BIT; + rw : in BIT; + rwok : in BIT; + nval : inout BIT; + nop : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_nop; + +ARCHITECTURE VBE OF rf_fifo_nop IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_nop" + SEVERITY WARNING; + + nval <= rw nand rwok; + nop <= nval and nreset and ckm; + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_ok.ap b/alliance/src/cells/src/rflib/rf_fifo_ok.ap new file mode 100644 index 00000000..95717d1b --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_ok.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H rf_fifo_ok,P,13/ 4/2002,10 +A 0,0,500,500 +S 150,300,150,450,20,*,UP,ALU1 +S 200,150,250,150,20,nrw,LEFT,CALU2 +S 200,300,250,300,20,nextval,RIGHT,CALU2 +S 50,200,50,250,20,*,DOWN,ALU1 +S 40,250,120,250,30,*,RIGHT,POLY +S 250,400,270,400,20,*,RIGHT,ALU1 +S 270,100,450,100,20,*,RIGHT,ALU1 +S 330,400,450,400,20,*,RIGHT,ALU1 +S 250,150,330,150,20,*,RIGHT,ALU1 +S 190,150,240,150,30,*,RIGHT,POLY +S 60,270,60,490,10,*,UP,PTRANS +S 30,290,30,470,30,*,DOWN,PDIF +S 150,290,150,470,30,*,DOWN,PDIF +S 120,270,120,490,10,*,UP,PTRANS +S 90,290,90,470,30,*,DOWN,PDIF +S 120,10,120,140,10,*,DOWN,NTRANS +S 60,10,60,140,10,*,DOWN,NTRANS +S 150,30,150,120,30,*,UP,NDIF +S 90,30,90,120,30,*,UP,NDIF +S 30,30,30,120,30,*,UP,NDIF +S 120,140,120,270,10,*,UP,POLY +S 60,140,60,270,10,*,UP,POLY +S 330,100,330,150,30,,UP,NDIF +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,390,500,390,240,,RIGHT,NWELL +S 450,30,450,120,30,*,UP,NDIF +S 450,290,450,470,30,*,DOWN,PDIF +S 420,10,420,140,10,*,DOWN,NTRANS +S 390,30,390,120,30,*,UP,NDIF +S 420,270,420,490,10,*,UP,PTRANS +S 420,140,420,270,10,*,UP,POLY +S 390,290,390,470,30,*,DOWN,PDIF +S 360,10,360,140,10,*,DOWN,NTRANS +S 330,30,330,120,30,*,UP,NDIF +S 360,270,360,490,10,*,UP,PTRANS +S 360,140,360,270,10,*,UP,POLY +S 330,290,330,470,30,*,DOWN,PDIF +S 300,10,300,140,10,*,DOWN,NTRANS +S 270,30,270,120,30,*,UP,NDIF +S 300,270,300,490,10,*,UP,PTRANS +S 300,140,300,270,10,*,UP,POLY +S 270,290,270,470,30,*,DOWN,PDIF +S 240,10,240,140,10,*,DOWN,NTRANS +S 210,30,210,120,30,*,UP,NDIF +S 240,270,240,490,10,*,UP,PTRANS +S 240,140,240,270,10,*,UP,POLY +S 210,290,210,470,30,*,DOWN,PDIF +S 420,250,460,250,30,*,RIGHT,POLY +S 30,300,30,450,20,*,DOWN,ALU1 +S 30,50,30,100,20,*,DOWN,ALU1 +S 150,50,150,100,20,*,DOWN,ALU1 +S 100,100,100,400,20,ok,DOWN,CALU1 +S 50,200,300,200,20,prev,RIGHT,CALU2 +S 300,250,350,250,20,rw,LEFT,CALU2 +S 400,350,450,350,20,ripple,LEFT,CALU2 +S 450,250,450,350,20,*,DOWN,ALU1 +S 300,200,350,200,20,*,RIGHT,ALU1 +S 150,150,200,150,20,*,LEFT,ALU1 +S 300,250,350,250,20,*,LEFT,ALU1 +S 250,150,250,400,20,*,UP,ALU1 +V 150,300,CONT_DIF_P,* +V 250,300,CONT_VIA,* +V 50,250,CONT_POLY,* +V 200,150,CONT_POLY,* +V 300,200,CONT_VIA,* +V 150,50,CONT_DIF_N,* +V 150,450,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,50,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 450,100,CONT_DIF_N,* +V 330,150,CONT_DIF_N,* +V 450,400,CONT_DIF_P,* +V 390,450,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 210,50,CONT_DIF_N,* +V 210,450,CONT_DIF_P,* +V 450,250,CONT_POLY,* +V 50,200,CONT_VIA,* +V 90,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 30,100,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 200,150,CONT_VIA,* +V 350,250,CONT_POLY,* +V 350,250,CONT_VIA,* +V 300,200,CONT_POLY,* +V 450,350,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_ok.vbe b/alliance/src/cells/src/rflib/rf_fifo_ok.vbe new file mode 100644 index 00000000..5537c904 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_ok.vbe @@ -0,0 +1,24 @@ +ENTITY rf_fifo_ok IS +PORT ( + rw : in BIT; + ripple : in BIT; + nrw : in BIT; + prev : in BIT; + nextval : out BIT; + ok : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_ok; + +ARCHITECTURE VBE OF rf_fifo_ok IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_ok" + SEVERITY WARNING; + + ok <= (not prev); + nextval <= not(((rw and ripple) or prev) and nrw); + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_orand4.ap b/alliance/src/cells/src/rflib/rf_fifo_orand4.ap new file mode 100644 index 00000000..49fc794f --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_orand4.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H rf_fifo_orand4,P, 6/ 4/2002,10 +A 0,0,500,500 +S 150,350,230,350,20,*,RIGHT,ALU1 +S 150,100,290,100,20,*,RIGHT,ALU1 +S 170,400,410,400,20,*,RIGHT,ALU1 +S 150,100,150,350,20,*,DOWN,ALU1 +S 100,100,100,400,20,rippleout,UP,CALU1 +S 200,150,200,300,20,a1,DOWN,CALU1 +S 250,150,250,300,20,b1,DOWN,CALU1 +S 350,100,350,350,20,a0,DOWN,CALU1 +S 400,100,400,350,20,b0,DOWN,CALU1 +S 70,270,70,440,10,*,DOWN,PTRANS +S 40,290,40,420,30,*,UP,PDIF +S 100,290,100,420,30,*,UP,PDIF +S 0,390,500,390,240,,RIGHT,NWELL +S 70,60,70,160,10,*,UP,NTRANS +S 40,80,40,140,30,*,DOWN,NDIF +S 100,80,100,140,30,*,DOWN,NDIF +S 70,200,150,200,30,*,RIGHT,POLY +S 70,160,70,270,10,*,DOWN,POLY +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 40,300,40,470,20,*,DOWN,ALU1 +S 40,30,40,100,20,*,DOWN,ALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 200,140,200,270,10,*,UP,POLY +S 260,140,260,270,10,*,UP,POLY +S 380,250,400,250,30,,RIGHT,POLY +S 380,140,380,270,10,*,UP,POLY +S 320,140,320,270,10,*,UP,POLY +S 320,250,340,250,30,,LEFT,POLY +S 170,30,170,120,30,*,UP,NDIF +S 230,30,230,120,30,*,UP,NDIF +S 290,30,290,120,30,*,UP,NDIF +S 410,30,410,120,30,*,UP,NDIF +S 350,30,350,120,30,*,UP,NDIF +S 290,30,290,120,30,*,UP,NDIF +S 380,10,380,140,10,*,DOWN,NTRANS +S 320,10,320,140,10,*,DOWN,NTRANS +S 200,10,200,140,10,*,DOWN,NTRANS +S 260,10,260,140,10,*,DOWN,NTRANS +S 170,290,170,470,30,*,DOWN,PDIF +S 200,270,200,490,10,*,UP,PTRANS +S 230,290,230,470,30,*,DOWN,PDIF +S 260,270,260,490,10,*,UP,PTRANS +S 290,290,290,470,30,*,DOWN,PDIF +S 350,290,350,470,30,*,DOWN,PDIF +S 320,270,320,490,10,*,UP,PTRANS +S 290,290,290,470,30,*,DOWN,PDIF +S 410,290,410,470,30,*,DOWN,PDIF +S 380,270,380,490,10,*,UP,PTRANS +V 100,400,CONT_DIF_P,* +V 100,350,CONT_DIF_P,* +V 100,300,CONT_DIF_P,* +V 40,400,CONT_DIF_P,* +V 40,300,CONT_DIF_P,* +V 100,470,CONT_BODY_N,* +V 40,470,CONT_BODY_N,* +V 40,350,CONT_DIF_P,* +V 40,100,CONT_DIF_N,* +V 100,100,CONT_DIF_N,* +V 100,30,CONT_BODY_P,* +V 40,30,CONT_BODY_P,* +V 260,250,CONT_POLY,* +V 400,250,CONT_POLY,* +V 170,50,CONT_DIF_N,* +V 290,100,CONT_DIF_N,* +V 410,50,CONT_DIF_N,* +V 170,400,CONT_DIF_P,* +V 290,400,CONT_DIF_P,* +V 350,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 290,400,CONT_DIF_P,* +V 410,400,CONT_DIF_P,* +V 340,250,CONT_POLY,* +V 200,250,CONT_POLY,* +V 150,200,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_orand4.vbe b/alliance/src/cells/src/rflib/rf_fifo_orand4.vbe new file mode 100644 index 00000000..fae9974d --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_orand4.vbe @@ -0,0 +1,22 @@ +ENTITY rf_fifo_orand4 IS +PORT ( + a0 : in BIT; + b0 : in BIT; + a1 : in BIT; + b1 : in BIT; + rippleout : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_orand4; + +ARCHITECTURE VBE OF rf_fifo_orand4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_orand4" + SEVERITY WARNING; + + rippleout <= (a0 and b0) or (a1 and b1); + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_orand5.ap b/alliance/src/cells/src/rflib/rf_fifo_orand5.ap new file mode 100644 index 00000000..e562a5d4 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_orand5.ap @@ -0,0 +1,85 @@ +V ALLIANCE : 6 +H rf_fifo_orand5,P, 6/ 4/2002,10 +A 0,0,500,500 +S 150,100,460,100,20,sor,RIGHT,ALU1 +S 150,350,400,350,20,*,RIGHT,ALU1 +S 340,400,460,400,20,*,RIGHT,ALU1 +S 160,400,280,400,20,*,RIGHT,ALU1 +S 450,150,450,300,20,b0,DOWN,CALU1 +S 350,150,350,300,20,a0,DOWN,CALU1 +S 300,150,300,300,20,ripplein,DOWN,CALU1 +S 250,150,250,300,20,b1,DOWN,CALU1 +S 200,150,200,300,20,a1,DOWN,CALU1 +S 150,100,150,350,20,*,DOWN,ALU1 +S 100,100,100,400,20,rippleout,UP,CALU1 +S 370,270,370,490,10,*,UP,PTRANS +S 400,290,400,470,30,*,DOWN,PDIF +S 430,270,430,490,10,*,UP,PTRANS +S 460,290,460,470,30,*,DOWN,PDIF +S 70,270,70,440,10,*,DOWN,PTRANS +S 40,290,40,420,30,*,UP,PDIF +S 100,290,100,420,30,*,UP,PDIF +S 0,390,500,390,240,,RIGHT,NWELL +S 160,290,160,470,30,*,DOWN,PDIF +S 190,270,190,490,10,*,UP,PTRANS +S 220,290,220,470,30,*,DOWN,PDIF +S 250,270,250,490,10,*,UP,PTRANS +S 280,290,280,470,30,*,DOWN,PDIF +S 310,270,310,490,10,*,UP,PTRANS +S 340,290,340,470,30,*,DOWN,PDIF +S 190,10,190,140,10,*,DOWN,NTRANS +S 250,10,250,140,10,*,DOWN,NTRANS +S 310,10,310,140,10,*,DOWN,NTRANS +S 370,10,370,140,10,*,DOWN,NTRANS +S 430,10,430,140,10,*,DOWN,NTRANS +S 70,60,70,160,10,*,UP,NTRANS +S 40,80,40,140,30,*,DOWN,NDIF +S 100,80,100,140,30,*,DOWN,NDIF +S 340,30,340,120,30,*,UP,NDIF +S 400,30,400,120,30,*,UP,NDIF +S 460,30,460,120,30,*,UP,NDIF +S 160,30,160,120,30,*,UP,NDIF +S 220,30,220,120,30,*,UP,NDIF +S 280,30,280,120,30,*,UP,NDIF +S 430,250,450,250,30,,RIGHT,POLY +S 70,200,150,200,30,*,RIGHT,POLY +S 70,160,70,270,10,*,DOWN,POLY +S 370,140,370,270,10,*,UP,POLY +S 430,140,430,270,10,*,UP,POLY +S 350,250,370,250,30,,LEFT,POLY +S 190,140,190,270,10,*,UP,POLY +S 250,140,250,270,10,*,UP,POLY +S 310,140,310,270,10,*,UP,POLY +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 40,300,40,470,20,*,DOWN,ALU1 +S 40,30,40,100,20,*,DOWN,ALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +V 340,400,CONT_DIF_P,* +V 400,350,CONT_DIF_P,* +V 100,400,CONT_DIF_P,* +V 100,350,CONT_DIF_P,* +V 100,300,CONT_DIF_P,* +V 40,400,CONT_DIF_P,* +V 40,300,CONT_DIF_P,* +V 220,450,CONT_DIF_P,* +V 100,470,CONT_BODY_N,* +V 40,470,CONT_BODY_N,* +V 460,400,CONT_DIF_P,* +V 160,400,CONT_DIF_P,* +V 280,400,CONT_DIF_P,* +V 40,350,CONT_DIF_P,* +V 40,100,CONT_DIF_N,* +V 100,100,CONT_DIF_N,* +V 160,50,CONT_DIF_N,* +V 280,100,CONT_DIF_N,* +V 340,50,CONT_DIF_N,* +V 460,100,CONT_DIF_N,* +V 100,30,CONT_BODY_P,* +V 40,30,CONT_BODY_P,* +V 350,250,CONT_POLY,* +V 450,250,CONT_POLY,* +V 150,200,CONT_POLY,* +V 200,250,CONT_POLY,* +V 250,250,CONT_POLY,* +V 300,250,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_orand5.vbe b/alliance/src/cells/src/rflib/rf_fifo_orand5.vbe new file mode 100644 index 00000000..6307f9c8 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_orand5.vbe @@ -0,0 +1,23 @@ +ENTITY rf_fifo_orand5 IS +PORT ( + a0 : in BIT; + b0 : in BIT; + a1 : in BIT; + b1 : in BIT; + ripplein : in BIT; + rippleout : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_orand5; + +ARCHITECTURE VBE OF rf_fifo_orand5 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_orand5" + SEVERITY WARNING; + + rippleout <= ripplein or (a0 and b0) or (a1 and b1); + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_ptreset.ap b/alliance/src/cells/src/rflib/rf_fifo_ptreset.ap new file mode 100644 index 00000000..e9de0464 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_ptreset.ap @@ -0,0 +1,114 @@ +V ALLIANCE : 6 +H rf_fifo_ptreset,P,13/ 4/2002,10 +A 0,0,500,500 +S 400,200,450,200,20,nop,RIGHT,CALU2 +S 100,200,450,200,20,*,RIGHT,TALU2 +S 300,200,300,250,20,*,UP,ALU1 +S 400,300,400,350,20,*,UP,ALU1 +S 400,200,400,250,20,*,UP,ALU1 +S 200,200,200,250,20,*,DOWN,ALU1 +S 100,200,100,250,20,*,DOWN,ALU1 +S 30,250,350,250,20,*,LEFT,POLY +S 150,300,470,300,20,*,RIGHT,POLY +S 50,350,400,350,20,*,RIGHT,TALU2 +S 120,80,120,170,30,*,DOWN,NDIF +S 90,60,90,190,10,*,UP,NTRANS +S 240,80,240,170,30,*,DOWN,NDIF +S 180,40,180,170,30,*,DOWN,NDIF +S 210,60,210,190,10,*,UP,NTRANS +S 370,80,370,170,50,*,DOWN,NDIF +S 410,60,410,190,10,*,UP,NTRANS +S 300,80,300,170,30,*,DOWN,NDIF +S 330,60,330,190,10,*,UP,NTRANS +S 400,350,400,420,30,*,UP,POLY +S 390,380,390,420,30,*,DOWN,POLY +S 180,380,180,420,30,*,DOWN,POLY +S 180,400,440,400,20,*,RIGHT,ALU1 +S 50,350,400,350,20,*,LEFT,ALU2 +S 120,400,170,400,50,*,RIGHT,PTRANS +S 330,400,380,400,50,*,RIGHT,PTRANS +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 470,10,470,190,10,*,UP,NTRANS +S 470,310,470,490,10,*,DOWN,PTRANS +S 440,30,440,170,30,*,DOWN,NDIF +S 440,330,440,470,30,*,DOWN,PDIF +S 500,30,500,170,30,*,DOWN,NDIF +S 500,330,500,470,30,*,DOWN,PDIF +S 60,30,60,170,30,*,DOWN,NDIF +S 0,30,0,170,30,*,DOWN,NDIF +S 30,10,30,190,10,*,UP,NTRANS +S 60,330,60,470,30,*,DOWN,PDIF +S 0,330,0,470,30,*,DOWN,PDIF +S 30,310,30,490,10,*,DOWN,PTRANS +S 30,190,30,310,10,*,DOWN,POLY +S 470,190,470,310,10,*,DOWN,POLY +S 290,190,330,190,10,*,RIGHT,POLY +S 500,350,500,450,20,*,UP,ALU1 +S 0,350,0,450,20,*,DOWN,ALU1 +S 240,150,360,150,20,*,LEFT,ALU1 +S 50,100,50,400,20,y,DOWN,ALU1 +S 150,100,150,350,20,z,UP,ALU1 +S 120,100,150,100,20,*,RIGHT,ALU1 +S 350,150,350,350,20,x,UP,ALU1 +S 370,100,370,150,20,*,DOWN,ALU1 +S 50,400,60,400,20,*,RIGHT,ALU1 +S 50,100,60,100,20,*,RIGHT,ALU1 +S 500,50,500,150,20,*,UP,ALU1 +S 0,50,0,150,20,*,DOWN,ALU1 +S 0,390,500,390,240,*,RIGHT,NWELL +S 250,100,300,100,20,ptm1,RIGHT,CALU2 +S 250,100,300,100,20,*,LEFT,ALU1 +S 450,100,450,400,20,*,DOWN,ALU1 +S 400,100,450,100,20,pt,LEFT,CALU2 +S 100,200,150,200,20,cks,LEFT,CALU2 +S 200,200,250,200,20,reset,RIGHT,CALU2 +S 300,200,350,200,20,inc,RIGHT,CALU2 +V 200,200,CONT_VIA,* +V 200,200,CONT_POLY,* +V 120,30,CONT_BODY_P,* +V 370,30,CONT_BODY_P,* +V 300,30,CONT_BODY_P,* +V 400,350,CONT_VIA,* +V 50,350,CONT_VIA,* +V 400,350,CONT_POLY,* +V 180,400,CONT_POLY,* +V 150,450,CONT_DIF_P,* +V 350,450,CONT_DIF_P,* +V 440,100,CONT_DIF_N,* +V 440,400,CONT_DIF_P,* +V 60,100,CONT_DIF_N,* +V 60,400,CONT_DIF_P,* +V 120,100,CONT_DIF_N,* +V 500,50,CONT_DIF_N,* +V 0,50,CONT_DIF_N,* +V 500,450,CONT_DIF_P,* +V 0,450,CONT_DIF_P,* +V 100,200,CONT_POLY,* +V 180,50,CONT_DIF_N,* +V 300,200,CONT_POLY,* +V 300,100,CONT_DIF_N,* +V 350,250,CONT_POLY,* +V 400,200,CONT_POLY,* +V 500,150,CONT_DIF_N,* +V 500,100,CONT_DIF_N,* +V 0,150,CONT_DIF_N,* +V 0,100,CONT_DIF_N,* +V 500,350,CONT_DIF_P,* +V 500,400,CONT_DIF_P,* +V 0,400,CONT_DIF_P,* +V 0,350,CONT_DIF_P,* +V 240,150,CONT_DIF_N,* +V 100,200,CONT_VIA,* +V 150,350,CONT_DIF_P,* +V 350,350,CONT_DIF_P,* +V 150,300,CONT_POLY,* +V 370,150,CONT_DIF_N,* +V 370,100,CONT_DIF_N,* +V 210,470,CONT_BODY_N,* +V 290,470,CONT_BODY_N,* +V 400,200,CONT_VIA,* +V 300,200,CONT_VIA,* +V 300,100,CONT_VIA,* +V 450,100,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_ptreset.vbe b/alliance/src/cells/src/rflib/rf_fifo_ptreset.vbe new file mode 100644 index 00000000..5be02916 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_ptreset.vbe @@ -0,0 +1,38 @@ +ENTITY rf_fifo_ptreset IS +PORT ( + nop : in BIT; + inc : in BIT; + cks : in BIT; + reset : in BIT; + ptm1 : in BIT; + pt : inout BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_ptreset; + +ARCHITECTURE VBE OF rf_fifo_ptreset IS + SIGNAL latchm : REG_BIT REGISTER; + SIGNAL latchs : REG_BIT REGISTER; + SIGNAL ckmux : BIT; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_ptreset" + SEVERITY WARNING; + + ckmux <= nop or inc or reset; + + label0 : BLOCK (ckmux = '1') + BEGIN + latchm <= GUARDED ((inc and ptm1) or (pt and nop)); + END BLOCK label0; + + label1 : BLOCK (cks = '1') + BEGIN + latchs <= GUARDED (not latchm); + END BLOCK label1; + + pt <= (not latchs); + +END; diff --git a/alliance/src/cells/src/rflib/rf_fifo_ptset.ap b/alliance/src/cells/src/rflib/rf_fifo_ptset.ap new file mode 100644 index 00000000..81646425 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_ptset.ap @@ -0,0 +1,113 @@ +V ALLIANCE : 6 +H rf_fifo_ptset,P,13/ 4/2002,10 +A 0,0,500,500 +S 400,200,450,200,20,nop,RIGHT,CALU2 +S 300,200,350,200,20,inc,RIGHT,CALU2 +S 200,200,250,200,20,nreset,LEFT,CALU2 +S 100,200,150,200,20,cks,LEFT,CALU2 +S 450,100,450,400,20,*,DOWN,ALU1 +S 400,100,450,100,20,pt,LEFT,CALU2 +S 250,100,300,100,20,*,LEFT,ALU1 +S 250,100,300,100,20,ptm1,LEFT,CALU2 +S 50,350,400,350,20,*,RIGHT,TALU2 +S 120,80,120,170,30,*,DOWN,NDIF +S 90,60,90,190,10,*,UP,NTRANS +S 300,80,300,170,30,*,DOWN,NDIF +S 370,80,370,170,50,*,DOWN,NDIF +S 410,60,410,190,10,*,UP,NTRANS +S 330,60,330,190,10,*,UP,NTRANS +S 180,400,440,400,20,*,RIGHT,ALU1 +S 200,150,200,300,20,*,DOWN,ALU1 +S 280,350,350,350,20,*,RIGHT,ALU1 +S 200,150,350,150,20,*,RIGHT,ALU1 +S 350,100,350,350,20,x,UP,ALU1 +S 350,100,370,100,20,*,RIGHT,ALU1 +S 180,380,180,420,30,*,DOWN,POLY +S 390,340,390,420,30,*,UP,POLY +S 50,400,60,400,20,*,RIGHT,ALU1 +S 50,100,60,100,20,*,RIGHT,ALU1 +S 440,100,450,100,20,*,RIGHT,ALU1 +S 440,400,450,400,20,*,RIGHT,ALU1 +S 50,350,400,350,20,*,RIGHT,ALU2 +S 330,400,380,400,50,*,RIGHT,PTRANS +S 120,400,170,400,50,*,RIGHT,PTRANS +S 30,300,200,300,10,*,RIGHT,POLY +S 150,250,470,250,10,*,RIGHT,POLY +S 220,330,220,470,30,*,DOWN,PDIF +S 280,330,280,470,30,*,DOWN,PDIF +S 250,310,250,490,10,*,DOWN,PTRANS +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 470,10,470,190,10,*,UP,NTRANS +S 470,310,470,490,10,*,DOWN,PTRANS +S 440,30,440,170,30,*,DOWN,NDIF +S 440,330,440,470,30,*,DOWN,PDIF +S 500,30,500,170,30,*,DOWN,NDIF +S 500,330,500,470,30,*,DOWN,PDIF +S 60,30,60,170,30,*,DOWN,NDIF +S 0,30,0,170,30,*,DOWN,NDIF +S 30,10,30,190,10,*,UP,NTRANS +S 60,330,60,470,30,*,DOWN,PDIF +S 0,330,0,470,30,*,DOWN,PDIF +S 30,310,30,490,10,*,DOWN,PTRANS +S 30,190,30,310,10,*,DOWN,POLY +S 470,190,470,310,10,*,DOWN,POLY +S 290,190,330,190,10,*,RIGHT,POLY +S 500,350,500,450,20,*,UP,ALU1 +S 0,350,0,450,20,*,DOWN,ALU1 +S 50,100,50,400,20,y,DOWN,ALU1 +S 150,100,150,350,20,z,UP,ALU1 +S 120,100,150,100,20,*,RIGHT,ALU1 +S 250,200,250,300,20,*,DOWN,ALU1 +S 500,50,500,150,20,*,UP,ALU1 +S 0,50,0,150,20,*,DOWN,ALU1 +S 0,390,500,390,240,*,RIGHT,NWELL +S 100,200,100,250,20,*,UP,ALU1 +S 100,200,450,200,20,*,RIGHT,TALU2 +S 400,200,400,250,20,*,UP,ALU1 +S 300,200,300,250,20,*,UP,ALU1 +S 400,300,400,350,20,*,DOWN,ALU1 +V 450,100,CONT_VIA,* +V 370,30,CONT_BODY_P,* +V 300,30,CONT_BODY_P,* +V 120,30,CONT_BODY_P,* +V 400,350,CONT_POLY,* +V 400,350,CONT_VIA,* +V 50,350,CONT_VIA,* +V 350,450,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 180,400,CONT_POLY,* +V 200,300,CONT_POLY,* +V 250,300,CONT_POLY,* +V 150,250,CONT_POLY,* +V 280,350,CONT_DIF_P,* +V 220,450,CONT_DIF_P,* +V 440,100,CONT_DIF_N,* +V 440,400,CONT_DIF_P,* +V 60,100,CONT_DIF_N,* +V 60,400,CONT_DIF_P,* +V 120,100,CONT_DIF_N,* +V 500,50,CONT_DIF_N,* +V 0,50,CONT_DIF_N,* +V 500,450,CONT_DIF_P,* +V 0,450,CONT_DIF_P,* +V 100,200,CONT_POLY,* +V 300,200,CONT_POLY,* +V 300,100,CONT_DIF_N,* +V 400,200,CONT_POLY,* +V 500,150,CONT_DIF_N,* +V 500,100,CONT_DIF_N,* +V 0,150,CONT_DIF_N,* +V 0,100,CONT_DIF_N,* +V 500,350,CONT_DIF_P,* +V 500,400,CONT_DIF_P,* +V 0,400,CONT_DIF_P,* +V 0,350,CONT_DIF_P,* +V 100,200,CONT_VIA,* +V 150,350,CONT_DIF_P,* +V 350,350,CONT_DIF_P,* +V 370,100,CONT_DIF_N,* +V 250,200,CONT_VIA,* +V 300,200,CONT_VIA,* +V 400,200,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_fifo_ptset.vbe b/alliance/src/cells/src/rflib/rf_fifo_ptset.vbe new file mode 100644 index 00000000..f6534bcf --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_fifo_ptset.vbe @@ -0,0 +1,38 @@ +ENTITY rf_fifo_ptset IS +PORT ( + nop : in BIT; + inc : in BIT; + cks : in BIT; + nreset : in BIT; + ptm1 : in BIT; + pt : inout BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_ptset; + +ARCHITECTURE VBE OF rf_fifo_ptset IS + SIGNAL latchm : REG_BIT REGISTER; + SIGNAL latchs : REG_BIT REGISTER; + SIGNAL ckmux : BIT; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_ptset" + SEVERITY WARNING; + + ckmux <= nop or inc or (not nreset); + + label0 : BLOCK (ckmux = '1') + BEGIN + latchm <= GUARDED ((inc and ptm1) or (pt and nop) or (not nreset)); + END BLOCK label0; + + label1 : BLOCK (cks = '1') + BEGIN + latchs <= GUARDED (not latchm); + END BLOCK label1; + + pt <= (not latchs); + +END; diff --git a/alliance/src/cells/src/rflib/rf_inmux_buf_2.ap b/alliance/src/cells/src/rflib/rf_inmux_buf_2.ap new file mode 100644 index 00000000..ef10ae52 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_inmux_buf_2.ap @@ -0,0 +1,214 @@ +V ALLIANCE : 6 +H rf_inmux_buf_2,P, 7/ 4/2002,10 +A 0,0,450,1000 +S 50,150,400,150,20,*,RIGHT,TALU2 +S 50,400,400,400,20,*,RIGHT,TALU2 +S 270,230,390,230,40,*,RIGHT,ALU1 +S 350,400,390,400,20,*,RIGHT,ALU2 +S 350,150,390,150,20,*,RIGHT,ALU2 +S 350,150,350,400,20,sel0,DOWN,CALU3 +S 90,400,250,400,20,*,RIGHT,ALU2 +S 250,150,250,400,20,sel1,UP,CALU3 +S 300,900,350,900,20,nck,LEFT,CALU2 +S 270,900,390,900,20,*,RIGHT,ALU1 +S 90,150,250,150,20,*,RIGHT,ALU2 +S 390,600,390,900,20,*,DOWN,ALU1 +S 200,700,200,900,20,ck,UP,CALU1 +S 450,900,450,950,20,vdd,DOWN,ALU1 +S 150,700,150,900,20,sel,UP,CALU1 +S 0,530,450,530,60,vdd,LEFT,CALU1 +S 0,470,450,470,60,vdd,LEFT,CALU1 +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 0,970,450,970,60,vss,RIGHT,CALU1 +S 450,50,450,100,20,*,DOWN,ALU1 +S 30,50,30,160,20,*,DOWN,ALU1 +S 330,50,330,160,20,*,DOWN,ALU1 +S 150,50,150,160,20,*,DOWN,ALU1 +S 60,240,180,240,30,*,LEFT,POLY +S 210,240,420,240,30,*,LEFT,POLY +S 150,300,150,450,20,*,DOWN,ALU1 +S 330,300,330,450,20,*,DOWN,ALU1 +S 420,130,420,310,10,*,DOWN,POLY +S 420,310,420,490,10,*,UP,PTRANS +S 450,330,450,470,30,*,DOWN,PDIF +S 190,750,420,750,30,*,LEFT,POLY +S 300,870,300,990,10,*,DOWN,NTRANS +S 360,870,360,990,10,*,DOWN,NTRANS +S 270,890,270,970,30,*,UP,NDIF +S 240,870,240,990,10,*,DOWN,NTRANS +S 390,890,390,970,30,*,UP,NDIF +S 210,890,210,970,30,*,UP,NDIF +S 330,890,330,970,30,*,UP,NDIF +S 420,870,420,990,10,*,DOWN,NTRANS +S 330,530,330,720,30,*,DOWN,PDIF +S 300,510,300,740,10,*,UP,PTRANS +S 360,510,360,740,10,*,UP,PTRANS +S 270,530,270,720,30,*,DOWN,PDIF +S 240,510,240,740,10,*,UP,PTRANS +S 390,530,390,720,30,*,DOWN,PDIF +S 420,510,420,740,10,*,UP,PTRANS +S 210,530,210,720,30,*,DOWN,PDIF +S 420,740,420,870,10,*,UP,POLY +S 240,740,240,870,10,*,UP,POLY +S 300,740,300,870,10,*,UP,POLY +S 360,740,360,870,10,*,UP,POLY +S 270,600,270,900,20,*,DOWN,ALU1 +S 330,550,330,790,20,*,UP,ALU1 +S 360,130,360,260,10,*,DOWN,POLY +S 300,130,300,260,10,*,DOWN,POLY +S 390,100,390,400,20,*,DOWN,ALU1 +S 270,100,270,400,20,*,DOWN,ALU1 +S 210,100,210,400,20,*,DOWN,ALU1 +S 90,100,90,400,20,*,DOWN,ALU1 +S 30,300,30,450,20,*,DOWN,ALU1 +S 30,280,30,470,30,*,DOWN,PDIF +S 90,280,90,470,30,*,DOWN,PDIF +S 150,280,150,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 180,260,180,490,10,*,UP,PTRANS +S 30,30,30,110,30,*,DOWN,NDIF +S 90,30,90,110,30,*,DOWN,NDIF +S 150,30,150,110,30,*,DOWN,NDIF +S 210,30,210,110,30,*,DOWN,NDIF +S 270,30,270,110,30,*,DOWN,NDIF +S 450,30,450,110,30,*,DOWN,NDIF +S 390,30,390,110,30,*,DOWN,NDIF +S 330,30,330,110,30,*,DOWN,NDIF +S 60,10,60,130,10,*,UP,NTRANS +S 330,280,330,470,30,*,DOWN,PDIF +S 300,260,300,490,10,*,UP,PTRANS +S 360,260,360,490,10,*,UP,PTRANS +S 270,280,270,470,30,*,DOWN,PDIF +S 390,280,390,470,30,*,DOWN,PDIF +S 210,280,210,470,30,*,DOWN,PDIF +S 450,530,450,720,30,*,DOWN,PDIF +S 450,890,450,970,30,*,UP,NDIF +S 0,390,470,390,240,*,RIGHT,NWELL +S 0,610,470,610,240,*,RIGHT,NWELL +S 420,10,420,130,10,*,UP,NTRANS +S 360,10,360,130,10,*,UP,NTRANS +S 300,10,300,130,10,*,UP,NTRANS +S 180,10,180,130,10,*,UP,NTRANS +S 120,10,120,130,10,*,UP,NTRANS +S 60,130,60,260,10,*,DOWN,POLY +S 120,130,120,260,10,*,DOWN,POLY +S 180,130,180,260,10,*,UP,POLY +S 450,550,450,700,20,*,DOWN,ALU1 +S 450,350,450,450,20,*,DOWN,ALU1 +S 30,550,30,700,20,*,DOWN,ALU1 +S 60,870,60,990,10,*,DOWN,NTRANS +S 30,840,30,950,20,*,UP,ALU1 +S 30,890,30,970,30,*,UP,NDIF +S 90,890,90,970,30,*,UP,NDIF +S 60,490,180,490,10,*,RIGHT,POLY +S 120,490,120,600,10,*,UP,POLY +S 180,490,180,600,10,*,UP,POLY +S 120,600,180,600,30,*,RIGHT,POLY +S 90,600,90,900,20,*,DOWN,ALU1 +S 90,600,150,600,20,*,RIGHT,ALU1 +S 150,650,210,650,20,*,RIGHT,ALU1 +S 60,740,60,870,10,*,DOWN,POLY +S 210,550,210,650,20,*,DOWN,ALU1 +S 60,800,150,800,10,*,RIGHT,POLY +S 300,750,470,750,120,*,LEFT,NWELL +S 60,520,60,740,10,*,UP,PTRANS +S 90,540,90,720,30,*,DOWN,PDIF +S 30,540,30,720,30,*,DOWN,PDIF +V 390,150,CONT_VIA,* +V 350,150,CONT_VIA2,* +V 210,400,CONT_VIA,* +V 250,400,CONT_VIA2,* +V 90,400,CONT_VIA,* +V 300,900,CONT_VIA,* +V 90,150,CONT_VIA,* +V 350,900,CONT_VIA,* +V 150,950,CONT_BODY_P,* +V 450,100,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,160,CONT_BODY_P,* +V 150,160,CONT_BODY_P,* +V 210,150,CONT_VIA,* +V 220,240,CONT_POLY,* +V 330,160,CONT_BODY_P,* +V 450,450,CONT_DIF_P,* +V 200,750,CONT_POLY,* +V 330,950,CONT_DIF_N,* +V 270,900,CONT_DIF_N,* +V 210,950,CONT_DIF_N,* +V 390,900,CONT_DIF_N,* +V 210,650,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 270,650,CONT_DIF_P,* +V 270,700,CONT_DIF_P,* +V 390,600,CONT_DIF_P,* +V 390,650,CONT_DIF_P,* +V 390,700,CONT_DIF_P,* +V 330,600,CONT_DIF_P,* +V 330,550,CONT_DIF_P,* +V 330,650,CONT_DIF_P,* +V 330,700,CONT_DIF_P,* +V 270,600,CONT_DIF_P,* +V 210,550,CONT_DIF_P,* +V 330,790,CONT_BODY_N,* +V 90,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 390,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 270,300,CONT_DIF_P,* +V 390,300,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 450,50,CONT_DIF_N,* +V 330,50,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 270,400,CONT_DIF_P,* +V 390,350,CONT_DIF_P,* +V 390,400,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 330,300,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 330,450,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 450,550,CONT_DIF_P,* +V 450,600,CONT_DIF_P,* +V 450,650,CONT_DIF_P,* +V 450,900,CONT_DIF_N,* +V 450,950,CONT_DIF_N,* +V 390,400,CONT_VIA,* +V 330,100,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 450,700,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,700,CONT_DIF_P,* +V 30,650,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 90,700,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,650,CONT_DIF_P,* +V 30,840,CONT_BODY_P,* +V 30,950,CONT_DIF_N,* +V 30,900,CONT_DIF_N,* +V 90,900,CONT_DIF_N,* +V 150,540,CONT_BODY_N,* +V 150,600,CONT_POLY,* +V 150,650,CONT_BODY_N,* +V 150,800,CONT_POLY,* +V 350,400,CONT_VIA2,* +V 250,150,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_inmux_buf_2.vbe b/alliance/src/cells/src/rflib/rf_inmux_buf_2.vbe new file mode 100644 index 00000000..29ceb42c --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_inmux_buf_2.vbe @@ -0,0 +1,24 @@ +ENTITY rf_inmux_buf_2 IS +PORT ( + ck : in BIT; + sel : in BIT; + nck : out BIT; + sel0 : out BIT; + sel1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_inmux_buf_2; + +ARCHITECTURE VBE OF rf_inmux_buf_2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_inmux_buf_2" + SEVERITY WARNING; + + nck <= not ck; + sel1 <= sel; + sel0 <= not sel; + +END; diff --git a/alliance/src/cells/src/rflib/rf_inmux_buf_4.ap b/alliance/src/cells/src/rflib/rf_inmux_buf_4.ap new file mode 100644 index 00000000..64935b6d --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_inmux_buf_4.ap @@ -0,0 +1,359 @@ +V ALLIANCE : 6 +H rf_inmux_buf_4,P,10/11/2000,10 +A 0,0,450,2000 +S 50,2000,150,2000,20,*,RIGHT,TALU2 +S 50,0,150,0,20,*,RIGHT,TALU2 +S 50,1000,150,1000,20,*,RIGHT,TALU2 +S 60,800,150,800,30,*,RIGHT,POLY +S 0,1390,470,1390,240,*,LEFT,NWELL +S 90,890,90,1110,30,*,UP,NDIF +S 30,1280,30,1460,30,*,DOWN,PDIF +S 90,1280,90,1460,30,*,DOWN,PDIF +S 60,1260,60,1480,10,*,UP,PTRANS +S 30,1030,30,1110,30,*,UP,NDIF +S 60,1010,60,1130,10,*,DOWN,NTRANS +S 120,1400,180,1400,30,*,LEFT,POLY +S 180,1400,180,1510,10,*,UP,POLY +S 120,1400,120,1510,10,*,UP,POLY +S 60,1130,60,1260,10,*,DOWN,POLY +S 30,1300,30,1450,20,*,DOWN,ALU1 +S 90,1400,150,1400,20,*,LEFT,ALU1 +S 90,1100,90,1400,20,*,DOWN,ALU1 +S 30,1050,30,1160,20,*,UP,ALU1 +S 450,1530,450,1670,30,*,DOWN,PDIF +S 420,1510,420,1690,10,*,UP,PTRANS +S 180,1510,180,1740,10,*,UP,PTRANS +S 120,1510,120,1740,10,*,UP,PTRANS +S 60,1510,60,1740,10,*,UP,PTRANS +S 150,1530,150,1720,30,*,DOWN,PDIF +S 90,1530,90,1720,30,*,DOWN,PDIF +S 30,1530,30,1720,30,*,DOWN,PDIF +S 0,1610,470,1610,240,*,LEFT,NWELL +S 210,1530,210,1720,30,*,DOWN,PDIF +S 390,1530,390,1720,30,*,DOWN,PDIF +S 270,1530,270,1720,30,*,DOWN,PDIF +S 360,1510,360,1740,10,*,UP,PTRANS +S 300,1510,300,1740,10,*,UP,PTRANS +S 330,1530,330,1720,30,*,DOWN,PDIF +S 210,1890,210,1970,30,*,DOWN,NDIF +S 150,1890,150,1970,30,*,DOWN,NDIF +S 90,1890,90,1970,30,*,DOWN,NDIF +S 30,1890,30,1970,30,*,DOWN,NDIF +S 420,1870,420,1990,10,*,UP,NTRANS +S 60,1870,60,1990,10,*,UP,NTRANS +S 330,1890,330,1970,30,*,DOWN,NDIF +S 390,1890,390,1970,30,*,DOWN,NDIF +S 450,1890,450,1970,30,*,DOWN,NDIF +S 270,1890,270,1970,30,*,DOWN,NDIF +S 120,1870,120,1990,10,*,UP,NTRANS +S 180,1870,180,1990,10,*,UP,NTRANS +S 300,1870,300,1990,10,*,UP,NTRANS +S 360,1870,360,1990,10,*,UP,NTRANS +S 420,1690,420,1870,10,*,DOWN,POLY +S 210,1760,420,1760,30,*,RIGHT,POLY +S 60,1760,180,1760,30,*,RIGHT,POLY +S 300,1740,300,1870,10,*,DOWN,POLY +S 360,1740,360,1870,10,*,DOWN,POLY +S 60,1510,180,1510,10,*,LEFT,POLY +S 180,1740,180,1870,10,*,UP,POLY +S 120,1740,120,1870,10,*,DOWN,POLY +S 60,1740,60,1870,10,*,DOWN,POLY +S 330,1550,330,1700,20,*,DOWN,ALU1 +S 150,1550,150,1700,20,*,DOWN,ALU1 +S 150,1840,150,1950,20,*,DOWN,ALU1 +S 330,1840,330,1950,20,*,DOWN,ALU1 +S 30,1840,30,1950,20,*,DOWN,ALU1 +S 450,1900,450,1950,20,*,DOWN,ALU1 +S 90,1600,90,1900,20,*,DOWN,ALU1 +S 210,1600,210,1900,20,*,DOWN,ALU1 +S 270,1600,270,1900,20,*,DOWN,ALU1 +S 390,1600,390,1900,20,*,DOWN,ALU1 +S 450,1550,450,1650,20,*,DOWN,ALU1 +S 30,1550,30,1700,20,*,DOWN,ALU1 +S 270,1600,390,1600,20,*,LEFT,ALU2 +S 90,1850,250,1850,20,*,LEFT,ALU2 +S 450,50,450,100,20,*,DOWN,ALU1 +S 30,50,30,160,20,*,DOWN,ALU1 +S 90,150,250,150,20,*,RIGHT,ALU2 +S 330,50,330,160,20,*,DOWN,ALU1 +S 150,50,150,160,20,*,DOWN,ALU1 +S 60,240,180,240,30,*,LEFT,POLY +S 210,240,420,240,30,*,LEFT,POLY +S 150,300,150,450,20,*,DOWN,ALU1 +S 330,300,330,450,20,*,DOWN,ALU1 +S 420,130,420,310,10,*,DOWN,POLY +S 420,310,420,490,10,*,UP,PTRANS +S 450,330,450,470,30,*,DOWN,PDIF +S 190,750,420,750,30,*,LEFT,POLY +S 300,870,300,990,10,*,DOWN,NTRANS +S 360,870,360,990,10,*,DOWN,NTRANS +S 270,890,270,970,30,*,UP,NDIF +S 240,870,240,990,10,*,DOWN,NTRANS +S 390,890,390,970,30,*,UP,NDIF +S 210,890,210,970,30,*,UP,NDIF +S 330,890,330,970,30,*,UP,NDIF +S 420,870,420,990,10,*,DOWN,NTRANS +S 330,530,330,720,30,*,DOWN,PDIF +S 300,510,300,740,10,*,UP,PTRANS +S 360,510,360,740,10,*,UP,PTRANS +S 270,530,270,720,30,*,DOWN,PDIF +S 240,510,240,740,10,*,UP,PTRANS +S 390,530,390,720,30,*,DOWN,PDIF +S 420,510,420,740,10,*,UP,PTRANS +S 210,530,210,720,30,*,DOWN,PDIF +S 420,740,420,870,10,*,UP,POLY +S 240,740,240,870,10,*,UP,POLY +S 300,740,300,870,10,*,UP,POLY +S 360,740,360,870,10,*,UP,POLY +S 390,600,390,900,20,*,DOWN,ALU1 +S 270,600,270,900,20,*,DOWN,ALU1 +S 330,550,330,790,20,*,UP,ALU1 +S 360,130,360,260,10,*,DOWN,POLY +S 300,130,300,260,10,*,DOWN,POLY +S 390,100,390,400,20,*,DOWN,ALU1 +S 270,100,270,400,20,*,DOWN,ALU1 +S 210,100,210,400,20,*,DOWN,ALU1 +S 90,100,90,400,20,*,DOWN,ALU1 +S 30,300,30,450,20,*,DOWN,ALU1 +S 30,280,30,470,30,*,DOWN,PDIF +S 90,280,90,470,30,*,DOWN,PDIF +S 150,280,150,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 180,260,180,490,10,*,UP,PTRANS +S 30,30,30,110,30,*,DOWN,NDIF +S 90,30,90,110,30,*,DOWN,NDIF +S 150,30,150,110,30,*,DOWN,NDIF +S 210,30,210,110,30,*,DOWN,NDIF +S 270,30,270,110,30,*,DOWN,NDIF +S 450,30,450,110,30,*,DOWN,NDIF +S 390,30,390,110,30,*,DOWN,NDIF +S 330,30,330,110,30,*,DOWN,NDIF +S 60,10,60,130,10,*,UP,NTRANS +S 330,280,330,470,30,*,DOWN,PDIF +S 300,260,300,490,10,*,UP,PTRANS +S 360,260,360,490,10,*,UP,PTRANS +S 270,280,270,470,30,*,DOWN,PDIF +S 390,280,390,470,30,*,DOWN,PDIF +S 210,280,210,470,30,*,DOWN,PDIF +S 450,530,450,720,30,*,DOWN,PDIF +S 450,890,450,970,30,*,UP,NDIF +S 0,390,470,390,240,*,RIGHT,NWELL +S 0,610,470,610,240,*,RIGHT,NWELL +S 420,10,420,130,10,*,UP,NTRANS +S 360,10,360,130,10,*,UP,NTRANS +S 300,10,300,130,10,*,UP,NTRANS +S 180,10,180,130,10,*,UP,NTRANS +S 120,10,120,130,10,*,UP,NTRANS +S 60,130,60,260,10,*,DOWN,POLY +S 120,130,120,260,10,*,DOWN,POLY +S 180,130,180,260,10,*,UP,POLY +S 270,400,390,400,20,*,RIGHT,ALU2 +S 450,550,450,700,20,*,DOWN,ALU1 +S 450,350,450,450,20,*,DOWN,ALU1 +S 30,550,30,700,20,*,DOWN,ALU1 +S 60,870,60,990,10,*,DOWN,NTRANS +S 30,840,30,950,20,*,UP,ALU1 +S 30,890,30,970,30,*,UP,NDIF +S 60,490,180,490,10,*,RIGHT,POLY +S 120,490,120,600,10,*,UP,POLY +S 180,490,180,600,10,*,UP,POLY +S 120,600,180,600,30,*,RIGHT,POLY +S 90,600,90,900,20,*,DOWN,ALU1 +S 90,600,150,600,20,*,RIGHT,ALU1 +S 150,650,210,650,20,*,RIGHT,ALU1 +S 60,740,60,870,10,*,DOWN,POLY +S 210,550,210,650,20,*,DOWN,ALU1 +S 300,750,470,750,120,*,LEFT,NWELL +S 60,520,60,740,10,*,UP,PTRANS +S 90,540,90,720,30,*,DOWN,PDIF +S 30,540,30,720,30,*,DOWN,PDIF +S 0,1470,450,1470,60,vdd,RIGHT,CALU1 +S 0,1530,450,1530,60,vdd,RIGHT,CALU1 +S 0,470,450,470,60,vdd,RIGHT,CALU1 +S 0,530,450,530,60,vdd,RIGHT,CALU1 +S 0,970,450,970,60,vss,RIGHT,CALU1 +S 0,1030,450,1030,60,vss,RIGHT,CALU1 +S 0,1970,450,1970,60,vss,LEFT,CALU1 +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 250,150,250,1850,20,sel1,DOWN,CALU3 +S 350,400,350,1600,20,sel0,UP,CALU3 +S 90,1850,250,1850,20,*,RIGHT,TALU2 +S 270,1600,390,1600,20,*,RIGHT,TALU2 +S 90,150,250,150,20,*,RIGHT,TALU2 +S 270,400,390,400,20,*,RIGHT,TALU2 +S 90,240,210,240,20,*,RIGHT,ALU1 +S 270,240,390,240,20,*,RIGHT,ALU1 +S 150,700,150,900,20,sel,UP,CALU1 +S 200,700,200,900,20,ck,UP,CALU1 +S 330,900,330,950,20,*,UP,ALU1 +S 450,900,450,950,20,*,DOWN,ALU1 +S 270,900,390,900,20,nck,RIGHT,CALU2 +S 100,0,100,2000,120,vss,UP,CALU3 +V 380,1040,CONT_BODY_P,* +V 380,1460,CONT_BODY_N,* +V 300,1040,CONT_BODY_P,* +V 200,1040,CONT_BODY_P,* +V 300,1460,CONT_BODY_N,* +V 210,1460,CONT_BODY_N,* +V 30,1450,CONT_DIF_P,* +V 150,1460,CONT_BODY_N,* +V 90,1350,CONT_DIF_P,* +V 90,1400,CONT_DIF_P,* +V 90,1300,CONT_DIF_P,* +V 30,1400,CONT_DIF_P,* +V 30,1350,CONT_DIF_P,* +V 30,1300,CONT_DIF_P,* +V 90,1100,CONT_DIF_N,* +V 30,1100,CONT_DIF_N,* +V 30,1050,CONT_DIF_N,* +V 30,1160,CONT_BODY_P,* +V 150,1400,CONT_POLY,* +V 450,1550,CONT_DIF_P,* +V 270,1700,CONT_DIF_P,* +V 210,1650,CONT_DIF_P,* +V 210,1600,CONT_DIF_P,* +V 210,1700,CONT_DIF_P,* +V 90,1600,CONT_DIF_P,* +V 90,1650,CONT_DIF_P,* +V 90,1700,CONT_DIF_P,* +V 30,1550,CONT_DIF_P,* +V 150,1550,CONT_DIF_P,* +V 150,1650,CONT_DIF_P,* +V 150,1600,CONT_DIF_P,* +V 150,1700,CONT_DIF_P,* +V 450,1600,CONT_DIF_P,* +V 450,1650,CONT_DIF_P,* +V 390,1700,CONT_DIF_P,* +V 330,1700,CONT_DIF_P,* +V 330,1650,CONT_DIF_P,* +V 390,1600,CONT_DIF_P,* +V 390,1650,CONT_DIF_P,* +V 270,1600,CONT_DIF_P,* +V 30,1700,CONT_DIF_P,* +V 30,1600,CONT_DIF_P,* +V 30,1650,CONT_DIF_P,* +V 270,1650,CONT_DIF_P,* +V 330,1550,CONT_DIF_P,* +V 330,1600,CONT_DIF_P,* +V 30,1900,CONT_DIF_N,* +V 450,1900,CONT_DIF_N,* +V 150,1950,CONT_DIF_N,* +V 330,1950,CONT_DIF_N,* +V 450,1950,CONT_DIF_N,* +V 90,1900,CONT_DIF_N,* +V 210,1900,CONT_DIF_N,* +V 270,1900,CONT_DIF_N,* +V 390,1900,CONT_DIF_N,* +V 150,1900,CONT_DIF_N,* +V 330,1900,CONT_DIF_N,* +V 30,1950,CONT_DIF_N,* +V 150,1840,CONT_BODY_P,* +V 30,1840,CONT_BODY_P,* +V 330,1840,CONT_BODY_P,* +V 220,1760,CONT_POLY,* +V 210,1850,CONT_VIA,* +V 390,1600,CONT_VIA,* +V 270,1600,CONT_VIA,* +V 90,1850,CONT_VIA,* +V 250,1850,CONT_VIA2,* +V 350,1600,CONT_VIA2,* +V 450,100,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,160,CONT_BODY_P,* +V 90,150,CONT_VIA,* +V 150,160,CONT_BODY_P,* +V 210,150,CONT_VIA,* +V 220,240,CONT_POLY,* +V 330,160,CONT_BODY_P,* +V 450,450,CONT_DIF_P,* +V 200,750,CONT_POLY,* +V 330,950,CONT_DIF_N,* +V 270,900,CONT_DIF_N,* +V 210,950,CONT_DIF_N,* +V 390,900,CONT_DIF_N,* +V 210,650,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 270,650,CONT_DIF_P,* +V 270,700,CONT_DIF_P,* +V 390,600,CONT_DIF_P,* +V 390,650,CONT_DIF_P,* +V 390,700,CONT_DIF_P,* +V 330,600,CONT_DIF_P,* +V 330,550,CONT_DIF_P,* +V 330,650,CONT_DIF_P,* +V 330,700,CONT_DIF_P,* +V 270,600,CONT_DIF_P,* +V 210,550,CONT_DIF_P,* +V 330,790,CONT_BODY_N,* +V 390,900,CONT_VIA,* +V 270,900,CONT_VIA,* +V 90,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 390,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 270,300,CONT_DIF_P,* +V 390,300,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 450,50,CONT_DIF_N,* +V 330,50,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 270,400,CONT_DIF_P,* +V 390,350,CONT_DIF_P,* +V 390,400,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 330,300,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 330,450,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 450,550,CONT_DIF_P,* +V 450,600,CONT_DIF_P,* +V 450,650,CONT_DIF_P,* +V 450,900,CONT_DIF_N,* +V 450,950,CONT_DIF_N,* +V 270,400,CONT_VIA,* +V 390,400,CONT_VIA,* +V 350,400,CONT_VIA2,* +V 330,100,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 450,700,CONT_DIF_P,* +V 250,150,CONT_VIA2,* +V 30,550,CONT_DIF_P,* +V 30,700,CONT_DIF_P,* +V 30,650,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 90,700,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,650,CONT_DIF_P,* +V 30,840,CONT_BODY_P,* +V 30,950,CONT_DIF_N,* +V 30,900,CONT_DIF_N,* +V 90,900,CONT_DIF_N,* +V 150,540,CONT_BODY_N,* +V 150,600,CONT_POLY,* +V 150,650,CONT_BODY_N,* +V 150,800,CONT_POLY,* +V 330,900,CONT_DIF_N,* +B 100,1000,120,20,CONT_VIA2,* +B 100,1000,120,20,CONT_VIA,* +B 100,0,120,20,CONT_VIA,* +B 100,0,120,20,CONT_VIA2,* +B 100,2000,120,20,CONT_VIA2,* +B 100,2000,120,20,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_inmux_buf_4.vbe b/alliance/src/cells/src/rflib/rf_inmux_buf_4.vbe new file mode 100644 index 00000000..e0512ca7 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_inmux_buf_4.vbe @@ -0,0 +1,24 @@ +ENTITY rf_inmux_buf_4 IS +PORT ( + ck : in BIT; + sel : in BIT; + nck : out BIT; + sel0 : out BIT; + sel1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_inmux_buf_4; + +ARCHITECTURE VBE OF rf_inmux_buf_4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_inmux_buf_4" + SEVERITY WARNING; + + nck <= not ck; + sel1 <= sel; + sel0 <= not sel; + +END; diff --git a/alliance/src/cells/src/rflib/rf_inmux_mem.ap b/alliance/src/cells/src/rflib/rf_inmux_mem.ap new file mode 100644 index 00000000..7cd4e79f --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_inmux_mem.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H rf_inmux_mem,P, 7/ 4/2002,10 +A 0,0,450,500 +R 200,150,ref_ref,datain0_15 +R 200,200,ref_ref,datain0_20 +R 200,250,ref_ref,datain0_25 +R 200,300,ref_ref,datain0_30 +R 200,350,ref_ref,datain0_35 +R 200,400,ref_ref,datain0_40 +R 400,150,ref_ref,datain1_15 +R 400,200,ref_ref,datain1_20 +R 400,250,ref_ref,datain1_25 +R 400,300,ref_ref,datain1_30 +R 400,350,ref_ref,datain1_35 +R 400,400,ref_ref,datain1_40 +S 200,300,400,300,20,*,RIGHT,TALU2 +S 200,300,250,300,20,*,LEFT,ALU2 +S 350,300,400,300,20,*,RIGHT,ALU2 +S 350,250,350,300,20,*,DOWN,ALU1 +S 100,100,150,100,20,dinx,RIGHT,CALU2 +S 250,100,340,100,20,*,RIGHT,ALU1 +S 250,100,250,300,20,*,DOWN,ALU1 +S 300,150,300,400,20,*,UP,ALU1 +S 400,150,400,400,20,datain1,UP,CALU1 +S 200,150,200,400,20,datain0,UP,CALU1 +S 350,300,350,300,20,sel0,LEFT,CALU3 +S 250,300,250,300,20,sel1,LEFT,CALU3 +S 30,50,30,170,20,*,UP,ALU1 +S 30,300,30,450,20,*,DOWN,ALU1 +S 30,30,30,120,30,*,UP,NDIF +S 60,10,60,140,10,*,DOWN,NTRANS +S 90,30,90,120,30,*,UP,NDIF +S 120,10,120,140,10,*,DOWN,NTRANS +S 170,30,170,120,70,*,UP,NDIF +S 150,300,150,450,20,*,DOWN,ALU1 +S 190,140,220,140,10,*,RIGHT,POLY +S 380,10,380,90,10,*,DOWN,NTRANS +S 340,10,340,90,10,*,DOWN,NTRANS +S 150,50,150,170,20,*,UP,ALU1 +S 410,30,410,70,30,*,DOWN,NDIF +S 260,10,260,90,10,*,DOWN,NTRANS +S 220,10,220,90,10,*,DOWN,NTRANS +S 260,90,260,200,10,*,UP,POLY +S 220,90,220,140,10,*,UP,POLY +S 300,30,300,160,30,*,UP,NDIF +S 380,140,400,140,10,*,LEFT,POLY +S 380,90,380,140,10,*,UP,POLY +S 300,30,300,70,50,*,UP,NDIF +S 290,30,290,160,30,*,UP,NDIF +S 60,140,60,260,10,*,UP,POLY +S 120,140,120,260,10,*,UP,POLY +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 30,280,30,470,30,*,DOWN,PDIF +S 150,280,150,330,30,*,UP,PDIF +S 90,280,90,470,30,*,DOWN,PDIF +S 380,340,380,470,10,*,UP,PTRANS +S 340,340,340,470,10,*,UP,PTRANS +S 220,340,220,470,10,*,UP,PTRANS +S 260,340,260,470,10,*,UP,PTRANS +S 300,360,300,450,50,*,UP,PDIF +S 410,360,410,460,30,*,UP,PDIF +S 170,360,170,470,70,*,DOWN,PDIF +S 190,340,220,340,10,*,RIGHT,POLY +S 260,290,260,340,10,*,UP,POLY +S 380,340,410,340,10,*,RIGHT,POLY +S 60,250,300,250,10,*,RIGHT,POLY +S 0,390,360,390,240,*,RIGHT,NWELL +S 0,430,450,430,160,*,LEFT,NWELL +S 340,200,340,340,10,*,DOWN,POLY +S 260,200,340,200,10,*,RIGHT,POLY +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 0,470,450,470,60,vdd,RIGHT,CALU1 +S 90,100,90,400,20,*,UP,ALU1 +V 100,100,CONT_VIA,* +V 30,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 30,170,CONT_BODY_P,* +V 30,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 200,150,CONT_POLY,* +V 410,50,CONT_DIF_N,* +V 410,450,CONT_DIF_P,* +V 400,150,CONT_POLY,* +V 300,150,CONT_DIF_N,* +V 300,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,100,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 150,450,CONT_DIF_P,* +V 150,100,CONT_DIF_N,* +V 150,300,CONT_DIF_P,* +V 150,170,CONT_BODY_P,* +V 340,100,CONT_POLY,* +V 300,500,CONT_BODY_N,* +V 250,300,CONT_POLY,* +V 200,330,CONT_POLY,* +V 400,330,CONT_POLY,* +V 300,250,CONT_POLY,* +V 250,300,CONT_VIA,* +V 350,300,CONT_VIA,* +V 350,300,CONT_POLY,* +V 350,300,CONT_VIA2,* +V 250,300,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_inmux_mem.vbe b/alliance/src/cells/src/rflib/rf_inmux_mem.vbe new file mode 100644 index 00000000..b0869fa9 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_inmux_mem.vbe @@ -0,0 +1,22 @@ +ENTITY rf_inmux_mem IS +PORT ( + datain0 : in BIT; + datain1 : in BIT; + sel0 : in BIT; + sel1 : in BIT; + dinx : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_inmux_mem; + +ARCHITECTURE VBE OF rf_inmux_mem IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1_x4" + SEVERITY WARNING; + + dinx <= (sel0 and datain0) or (sel1 and datain1); + +END; diff --git a/alliance/src/cells/src/rflib/rf_mid_buf_2.ap b/alliance/src/cells/src/rflib/rf_mid_buf_2.ap new file mode 100644 index 00000000..1c5410a8 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_mid_buf_2.ap @@ -0,0 +1,172 @@ +V ALLIANCE : 6 +H rf_mid_buf_2,P, 9/ 4/2002,10 +A 0,0,250,1000 +S 180,610,200,610,20,*,LEFT,ALU1 +S 50,610,70,610,20,*,RIGHT,ALU1 +S 180,600,200,600,20,*,LEFT,ALU1 +S 50,600,70,600,20,*,RIGHT,ALU1 +S 150,150,200,150,20,*,RIGHT,ALU2 +S 50,150,100,150,20,*,RIGHT,ALU2 +S 150,400,200,400,20,*,RIGHT,ALU2 +S 50,400,100,400,20,*,RIGHT,ALU2 +S 150,600,200,600,20,*,LEFT,ALU2 +S 50,600,100,600,20,*,RIGHT,ALU2 +S 200,900,250,900,20,nck,LEFT,CALU2 +S 150,890,150,970,30,*,DOWN,NDIF +S 60,890,60,970,30,*,DOWN,NDIF +S 50,150,50,600,20,read,UP,CALU3 +S 200,150,200,600,20,write,UP,CALU3 +S 0,470,250,470,60,vdd,RIGHT,CALU1 +S 0,530,250,530,60,vdd,RIGHT,CALU1 +S 0,970,250,970,60,vss,RIGHT,CALU1 +S 0,30,250,30,60,vss,RIGHT,CALU1 +S 0,50,0,150,20,*,UP,ALU1 +S 250,50,250,150,20,*,UP,ALU1 +S 120,50,120,150,20,*,UP,ALU1 +S 90,820,90,860,10,*,DOWN,POLY +S 30,850,100,850,30,*,RIGHT,POLY +S 30,820,30,870,10,*,DOWN,POLY +S 120,280,120,740,20,*,UP,ALU1 +S 50,660,50,900,20,*,UP,ALU1 +S 200,660,200,900,20,*,DOWN,ALU1 +S 30,210,90,210,10,*,RIGHT,POLY +S 160,210,220,210,10,*,RIGHT,POLY +S 30,870,30,990,10,*,UP,NTRANS +S 220,820,220,870,10,*,DOWN,POLY +S 220,850,260,850,30,*,RIGHT,POLY +S 220,870,220,990,10,*,UP,NTRANS +S 30,660,90,660,30,*,RIGHT,POLY +S 160,660,220,660,30,*,RIGHT,POLY +S 0,280,0,790,20,*,UP,ALU1 +S 0,720,0,800,30,*,UP,PDIF +S 60,720,60,800,30,*,UP,PDIF +S 90,700,90,820,10,*,DOWN,PTRANS +S 30,700,30,820,10,*,DOWN,PTRANS +S 0,890,0,970,30,*,UP,NDIF +S 30,200,30,310,10,*,UP,POLY +S 90,200,90,310,10,*,UP,POLY +S 160,200,160,310,10,*,UP,POLY +S 220,200,220,310,10,*,UP,POLY +S -20,390,270,390,260,*,LEFT,NWELL +S -20,650,270,650,320,*,LEFT,NWELL +S 250,890,250,970,30,*,UP,NDIF +S 130,720,130,800,30,*,UP,PDIF +S 220,700,220,820,10,*,UP,PTRANS +S 190,720,190,800,20,*,UP,PDIF +S 160,700,160,820,10,*,DOWN,PTRANS +S 250,720,250,800,30,*,UP,PDIF +S 250,850,250,900,20,*,UP,ALU1 +S 0,30,0,180,30,*,UP,NDIF +S 60,30,60,180,30,*,UP,NDIF +S 30,10,30,200,10,*,UP,NTRANS +S 220,10,220,200,10,*,DOWN,NTRANS +S 190,30,190,180,30,*,UP,NDIF +S 160,10,160,200,10,*,DOWN,NTRANS +S 120,30,120,180,30,*,UP,NDIF +S 130,30,130,180,30,*,UP,NDIF +S 90,10,90,200,10,*,DOWN,NTRANS +S 250,30,250,180,30,*,UP,NDIF +S 250,280,250,790,20,*,UP,ALU1 +S 190,100,190,400,20,*,UP,ALU1 +S 60,100,60,400,20,*,UP,ALU1 +S 60,330,60,620,30,*,UP,PDIF +S 220,310,220,640,10,*,DOWN,PTRANS +S 190,330,190,620,30,*,UP,PDIF +S 130,330,130,620,30,*,UP,PDIF +S 90,310,90,640,10,*,UP,PTRANS +S 0,330,0,620,30,*,UP,PDIF +S 30,310,30,640,10,*,UP,PTRANS +S 160,310,160,640,10,*,UP,PTRANS +S 120,330,120,620,30,*,UP,PDIF +S 250,330,250,620,30,*,DOWN,PDIF +S 220,640,220,670,10,*,UP,POLY +S 160,640,160,670,10,*,UP,POLY +S 90,640,90,670,10,*,UP,POLY +S 30,640,30,670,10,*,UP,POLY +S 180,870,180,990,10,*,UP,NTRANS +S 150,900,200,900,20,*,LEFT,ALU1 +S 160,820,160,860,10,*,UP,POLY +S 180,840,180,870,10,*,UP,POLY +S 140,850,180,850,30,*,RIGHT,POLY +S 0,900,0,950,20,*,UP,ALU1 +S 50,150,200,150,20,*,RIGHT,TALU2 +S 50,400,200,400,20,*,RIGHT,TALU2 +S 50,600,200,600,20,*,RIGHT,TALU2 +S 100,800,150,800,20,selr,RIGHT,CALU2 +S 100,850,150,850,20,selw,RIGHT,CALU2 +S 150,800,150,850,20,*,DOWN,ALU1 +S 100,800,100,850,20,*,UP,ALU1 +V 0,50,CONT_DIF_N,* +V 120,50,CONT_DIF_N,* +V 250,50,CONT_DIF_N,* +V 120,350,CONT_DIF_P,* +V 120,150,CONT_DIF_N,* +V 200,150,CONT_VIA,* +V 200,150,CONT_VIA2,* +V 200,400,CONT_VIA,* +V 200,400,CONT_VIA2,* +V 200,600,CONT_VIA,* +V 200,600,CONT_VIA2,* +V 120,670,CONT_BODY_N,* +V 50,660,CONT_POLY,* +V 250,790,CONT_DIF_P,* +V 0,790,CONT_DIF_P,* +V 100,850,CONT_POLY,* +V 200,660,CONT_POLY,* +V 150,850,CONT_POLY,* +V 60,900,CONT_DIF_N,* +V 250,740,CONT_DIF_P,* +V 60,740,CONT_DIF_P,* +V 0,740,CONT_DIF_P,* +V 190,740,CONT_DIF_P,* +V 250,900,CONT_VIA,* +V 0,950,CONT_DIF_N,* +V 120,280,CONT_BODY_N,* +V 0,350,CONT_DIF_P,* +V 60,350,CONT_DIF_P,* +V 60,400,CONT_DIF_P,* +V 0,400,CONT_DIF_P,* +V 0,150,CONT_DIF_N,* +V 60,150,CONT_DIF_N,* +V 60,100,CONT_DIF_N,* +V 0,100,CONT_DIF_N,* +V 190,400,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 250,350,CONT_DIF_P,* +V 190,100,CONT_DIF_N,* +V 250,100,CONT_DIF_N,* +V 190,150,CONT_DIF_N,* +V 250,150,CONT_DIF_N,* +V 0,450,CONT_DIF_P,* +V 250,450,CONT_DIF_P,* +V 0,500,CONT_DIF_P,* +V 0,550,CONT_DIF_P,* +V 250,500,CONT_DIF_P,* +V 250,550,CONT_DIF_P,* +V 0,600,CONT_DIF_P,* +V 60,600,CONT_DIF_P,* +V 190,600,CONT_DIF_P,* +V 250,600,CONT_DIF_P,* +V 250,950,CONT_DIF_N,* +V 250,850,CONT_POLY,* +V 120,100,CONT_DIF_N,* +V 120,400,CONT_DIF_P,* +V 120,550,CONT_DIF_P,* +V 120,450,CONT_DIF_P,* +V 120,500,CONT_DIF_P,* +V 250,280,CONT_BODY_N,* +V 0,280,CONT_BODY_N,* +V 120,740,CONT_DIF_P,* +V 50,600,CONT_VIA2,* +V 50,600,CONT_VIA,* +V 50,400,CONT_VIA2,* +V 50,400,CONT_VIA,* +V 50,150,CONT_VIA2,* +V 50,150,CONT_VIA,* +V 250,670,CONT_BODY_N,* +V 150,900,CONT_DIF_N,* +V 0,900,CONT_DIF_N,* +V 100,800,CONT_VIA,* +V 150,850,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_mid_buf_2.vbe b/alliance/src/cells/src/rflib/rf_mid_buf_2.vbe new file mode 100644 index 00000000..3545d57e --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_mid_buf_2.vbe @@ -0,0 +1,23 @@ +ENTITY rf_mid_buf_2 IS +PORT ( + selr : in BIT; + selw : in BIT; + nck : in BIT; + read : out BIT; + write : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_mid_buf_2; + +ARCHITECTURE VBE OF rf_mid_buf_2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_mid_buf_2" + SEVERITY WARNING; + + read <= selr; + write <= selw and nck; + +END; diff --git a/alliance/src/cells/src/rflib/rf_mid_buf_4.ap b/alliance/src/cells/src/rflib/rf_mid_buf_4.ap new file mode 100644 index 00000000..81942b9e --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_mid_buf_4.ap @@ -0,0 +1,306 @@ +V ALLIANCE : 6 +H rf_mid_buf_4,P,14/ 9/2000,10 +A 0,0,250,2000 +S 50,1400,50,1850,20,read,UP,CALU3 +S 200,150,200,600,20,write,UP,CALU3 +S 60,900,130,900,20,*,LEFT,ALU1 +S 90,820,90,870,10,*,DOWN,POLY +S 160,820,160,870,10,*,UP,POLY +S 90,850,160,850,30,*,RIGHT,POLY +S 120,890,120,970,30,*,DOWN,NDIF +S 90,870,90,990,10,*,DOWN,NTRANS +S 160,870,160,990,10,*,DOWN,NTRANS +S 130,890,130,970,30,*,DOWN,NDIF +S 220,640,220,670,10,*,DOWN,POLY +S 160,640,160,670,10,*,DOWN,POLY +S 90,640,90,670,10,*,DOWN,POLY +S 30,640,30,670,10,*,DOWN,POLY +S 0,330,0,620,30,*,UP,PDIF +S 130,330,130,620,30,*,DOWN,PDIF +S 90,310,90,640,10,*,DOWN,PTRANS +S 220,310,220,640,10,*,DOWN,PTRANS +S 250,330,250,620,30,*,DOWN,PDIF +S 160,310,160,640,10,*,DOWN,PTRANS +S 120,330,120,620,30,*,DOWN,PDIF +S 60,330,60,620,30,*,DOWN,PDIF +S 30,310,30,640,10,*,UP,PTRANS +S 190,330,190,620,30,*,DOWN,PDIF +S 130,40,130,100,20,*,DOWN,ALU1 +S 250,40,250,150,20,*,DOWN,ALU1 +S 0,40,0,150,20,*,DOWN,ALU1 +S 190,100,190,400,20,*,DOWN,ALU1 +S 60,100,60,400,20,*,DOWN,ALU1 +S 190,660,190,740,20,*,DOWN,ALU1 +S 130,740,130,790,20,*,UP,ALU1 +S 0,280,0,790,20,*,DOWN,ALU1 +S 60,660,60,900,20,*,UP,ALU1 +S 60,660,190,660,20,*,RIGHT,ALU1 +S 30,660,220,660,30,*,RIGHT,POLY +S 60,600,190,600,20,*,RIGHT,ALU1 +S 130,280,130,550,20,*,DOWN,ALU1 +S 0,30,0,180,30,*,DOWN,NDIF +S 160,10,160,200,10,*,UP,NTRANS +S 120,30,120,180,30,*,DOWN,NDIF +S 130,30,130,180,30,*,DOWN,NDIF +S 90,10,90,200,10,*,UP,NTRANS +S 60,30,60,180,30,*,DOWN,NDIF +S 30,10,30,200,10,*,UP,NTRANS +S 220,10,220,200,10,*,DOWN,NTRANS +S 190,30,190,180,30,*,DOWN,NDIF +S 250,30,250,180,30,*,DOWN,NDIF +S 0,850,0,900,20,*,DOWN,ALU1 +S 0,720,0,800,30,*,DOWN,PDIF +S 90,700,90,820,10,*,UP,PTRANS +S 60,720,60,800,20,*,DOWN,PDIF +S 30,700,30,820,10,*,DOWN,PTRANS +S 120,720,120,800,30,*,DOWN,PDIF +S 0,890,0,970,30,*,DOWN,NDIF +S 60,150,190,150,20,*,RIGHT,ALU1 +S -20,650,270,650,320,*,LEFT,NWELL +S -20,390,270,390,260,*,LEFT,NWELL +S 30,200,30,310,10,*,DOWN,POLY +S 90,200,90,310,10,*,DOWN,POLY +S 160,200,160,310,10,*,DOWN,POLY +S 220,200,220,310,10,*,DOWN,POLY +S 30,210,220,210,10,*,RIGHT,POLY +S 250,890,250,970,30,*,DOWN,NDIF +S 220,700,220,820,10,*,UP,PTRANS +S 160,700,160,820,10,*,UP,PTRANS +S 190,720,190,800,30,*,DOWN,PDIF +S 250,720,250,800,30,*,DOWN,PDIF +S 250,850,250,900,20,*,UP,ALU1 +S 250,280,250,790,20,*,DOWN,ALU1 +S 130,790,250,790,20,*,LEFT,ALU1 +S 220,870,220,990,10,*,DOWN,NTRANS +S 190,890,190,970,30,*,DOWN,NDIF +S 30,870,30,990,10,*,DOWN,NTRANS +S 60,890,60,970,30,*,DOWN,NDIF +S -10,850,30,850,30,*,RIGHT,POLY +S 30,820,30,870,10,*,UP,POLY +S 220,820,220,870,10,*,UP,POLY +S 220,850,260,850,30,*,RIGHT,POLY +S 130,1900,130,1960,20,*,DOWN,ALU1 +S 250,1850,250,1960,20,*,DOWN,ALU1 +S 0,1850,0,1960,20,*,DOWN,ALU1 +S 190,1600,190,1900,20,*,DOWN,ALU1 +S 60,1600,60,1900,20,*,DOWN,ALU1 +S 0,1210,0,1720,20,*,DOWN,ALU1 +S 30,1340,220,1340,30,*,LEFT,POLY +S 60,1400,190,1400,20,*,LEFT,ALU1 +S 130,1450,130,1720,20,*,DOWN,ALU1 +S 0,1820,0,1970,30,*,DOWN,NDIF +S 160,1800,160,1990,10,*,UP,NTRANS +S 120,1820,120,1970,30,*,DOWN,NDIF +S 130,1820,130,1970,30,*,DOWN,NDIF +S 90,1800,90,1990,10,*,UP,NTRANS +S 60,1820,60,1970,30,*,DOWN,NDIF +S 30,1800,30,1990,10,*,UP,NTRANS +S 220,1800,220,1990,10,*,DOWN,NTRANS +S 190,1820,190,1970,30,*,DOWN,NDIF +S 250,1820,250,1970,30,*,DOWN,NDIF +S 30,1130,30,1180,10,*,DOWN,POLY +S 0,1200,0,1280,30,*,DOWN,PDIF +S 90,1180,90,1300,10,*,UP,PTRANS +S 60,1200,60,1280,20,*,DOWN,PDIF +S 30,1180,30,1300,10,*,DOWN,PTRANS +S 120,1200,120,1280,30,*,DOWN,PDIF +S 60,1850,190,1850,20,*,LEFT,ALU1 +S -20,1350,270,1350,320,*,RIGHT,NWELL +S -20,1610,270,1610,260,*,RIGHT,NWELL +S 30,1690,30,1800,10,*,DOWN,POLY +S 90,1690,90,1800,10,*,DOWN,POLY +S 160,1690,160,1800,10,*,DOWN,POLY +S 220,1690,220,1800,10,*,DOWN,POLY +S 30,1790,220,1790,10,*,LEFT,POLY +S 250,1210,250,1720,20,*,DOWN,ALU1 +S 90,1130,90,1180,10,*,DOWN,POLY +S 160,1130,160,1180,10,*,DOWN,POLY +S 220,1130,220,1180,10,*,DOWN,POLY +S 30,1060,30,1130,10,*,DOWN,NTRANS +S 60,1080,60,1110,30,*,DOWN,NDIF +S 90,1060,90,1130,10,*,DOWN,NTRANS +S 220,1060,220,1130,10,*,DOWN,NTRANS +S 160,1060,160,1130,10,*,DOWN,NTRANS +S 190,1080,190,1110,30,*,DOWN,NDIF +S 250,1040,250,1110,30,*,DOWN,NDIF +S 0,1040,0,1110,30,*,DOWN,NDIF +S 120,1040,120,1110,30,*,DOWN,NDIF +S 130,1040,130,1110,30,*,DOWN,NDIF +S 30,1150,220,1150,30,*,LEFT,POLY +S 250,1200,250,1280,30,*,DOWN,PDIF +S 220,1180,220,1300,10,*,UP,PTRANS +S 190,1200,190,1280,20,*,DOWN,PDIF +S 160,1180,160,1300,10,*,DOWN,PTRANS +S 130,1200,130,1280,30,*,DOWN,PDIF +S 190,1100,190,1210,20,*,UP,ALU1 +S 130,1260,250,1260,20,*,LEFT,ALU1 +S 250,1050,250,1100,20,*,UP,ALU1 +S 0,1050,0,1100,20,*,DOWN,ALU1 +S 130,1380,130,1670,30,*,DOWN,PDIF +S 120,1380,120,1670,30,*,DOWN,PDIF +S 60,1380,60,1670,30,*,DOWN,PDIF +S 30,1360,30,1690,10,*,UP,PTRANS +S 190,1380,190,1670,30,*,DOWN,PDIF +S 220,1360,220,1690,10,*,DOWN,PTRANS +S 90,1360,90,1690,10,*,DOWN,PTRANS +S 250,1380,250,1670,30,*,DOWN,PDIF +S 160,1360,160,1690,10,*,DOWN,PTRANS +S 0,1380,0,1670,30,*,UP,PDIF +S 220,1330,220,1360,10,*,UP,POLY +S 160,1330,160,1360,10,*,UP,POLY +S 90,1330,90,1360,10,*,UP,POLY +S 30,1330,30,1360,10,*,UP,POLY +S 50,1340,190,1340,20,*,LEFT,ALU1 +S 60,1210,60,1340,20,*,UP,ALU1 +S 60,1100,190,1100,20,*,LEFT,ALU1 +S 60,1210,190,1210,20,*,LEFT,ALU1 +S 0,1850,250,1850,20,*,RIGHT,TALU2 +S 0,1600,250,1600,20,*,RIGHT,TALU2 +S 0,1400,250,1400,20,*,RIGHT,TALU2 +S 0,600,250,600,20,*,RIGHT,TALU2 +S 0,400,250,400,20,*,RIGHT,TALU2 +S 0,150,250,150,20,*,RIGHT,TALU2 +S 0,900,250,900,20,nck,RIGHT,CALU2 +S 150,850,150,850,20,selw,LEFT,CALU2 +S 100,1150,100,1150,20,selr,LEFT,CALU2 +S 0,1970,250,1970,60,vss,LEFT,CALU1 +S 0,1470,250,1470,60,vdd,LEFT,CALU1 +S 0,1530,250,1530,60,vdd,LEFT,CALU1 +S 0,970,250,970,60,vss,RIGHT,CALU1 +S 0,1030,250,1030,60,vss,RIGHT,CALU1 +S 0,470,250,470,60,vdd,RIGHT,CALU1 +S 0,530,250,530,60,vdd,RIGHT,CALU1 +S 0,30,250,30,60,vss,RIGHT,CALU1 +V 130,900,CONT_DIF_N,* +V 250,670,CONT_BODY_N,* +V 200,150,CONT_VIA,* +V 200,150,CONT_VIA2,* +V 200,400,CONT_VIA,* +V 200,400,CONT_VIA2,* +V 200,600,CONT_VIA,* +V 200,600,CONT_VIA2,* +V 130,660,CONT_POLY,* +V 60,790,CONT_DIF_P,* +V 130,740,CONT_DIF_P,* +V 0,790,CONT_DIF_P,* +V 190,660,CONT_POLY,* +V 60,660,CONT_POLY,* +V 250,280,CONT_BODY_N,* +V 0,280,CONT_BODY_N,* +V 130,500,CONT_DIF_P,* +V 130,450,CONT_DIF_P,* +V 130,550,CONT_DIF_P,* +V 130,400,CONT_DIF_P,* +V 150,850,CONT_POLY,* +V 130,40,CONT_DIF_N,* +V 130,100,CONT_DIF_N,* +V 0,850,CONT_POLY,* +V 0,950,CONT_DIF_N,* +V 0,600,CONT_DIF_P,* +V 60,600,CONT_DIF_P,* +V 190,600,CONT_DIF_P,* +V 250,600,CONT_DIF_P,* +V 0,550,CONT_DIF_P,* +V 0,500,CONT_DIF_P,* +V 250,550,CONT_DIF_P,* +V 250,500,CONT_DIF_P,* +V 0,450,CONT_DIF_P,* +V 250,450,CONT_DIF_P,* +V 0,150,CONT_DIF_N,* +V 60,150,CONT_DIF_N,* +V 0,40,CONT_DIF_N,* +V 0,100,CONT_DIF_N,* +V 60,100,CONT_DIF_N,* +V 0,350,CONT_DIF_P,* +V 60,350,CONT_DIF_P,* +V 0,400,CONT_DIF_P,* +V 60,400,CONT_DIF_P,* +V 250,100,CONT_DIF_N,* +V 190,100,CONT_DIF_N,* +V 250,40,CONT_DIF_N,* +V 190,150,CONT_DIF_N,* +V 250,150,CONT_DIF_N,* +V 250,400,CONT_DIF_P,* +V 190,400,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 250,350,CONT_DIF_P,* +V 130,280,CONT_BODY_N,* +V 250,950,CONT_DIF_N,* +V 250,850,CONT_POLY,* +V 250,900,CONT_VIA,* +V 150,850,CONT_VIA,* +V 0,900,CONT_VIA,* +V 130,790,CONT_DIF_P,* +V 250,790,CONT_DIF_P,* +V 60,740,CONT_DIF_P,* +V 250,740,CONT_DIF_P,* +V 190,740,CONT_DIF_P,* +V 0,740,CONT_DIF_P,* +V 60,1850,CONT_VIA2,* +V 50,1600,CONT_VIA2,* +V 50,1400,CONT_VIA2,* +V 60,1850,CONT_VIA,* +V 50,1600,CONT_VIA,* +V 50,1400,CONT_VIA,* +V 130,1340,CONT_POLY,* +V 60,1210,CONT_DIF_P,* +V 0,1210,CONT_DIF_P,* +V 190,1340,CONT_POLY,* +V 60,1340,CONT_POLY,* +V 250,1720,CONT_BODY_N,* +V 0,1720,CONT_BODY_N,* +V 130,1500,CONT_DIF_P,* +V 130,1550,CONT_DIF_P,* +V 130,1450,CONT_DIF_P,* +V 130,1600,CONT_DIF_P,* +V 130,1960,CONT_DIF_N,* +V 130,1900,CONT_DIF_N,* +V 0,1050,CONT_DIF_N,* +V 0,1400,CONT_DIF_P,* +V 60,1400,CONT_DIF_P,* +V 190,1400,CONT_DIF_P,* +V 250,1400,CONT_DIF_P,* +V 0,1450,CONT_DIF_P,* +V 0,1500,CONT_DIF_P,* +V 250,1450,CONT_DIF_P,* +V 250,1500,CONT_DIF_P,* +V 0,1550,CONT_DIF_P,* +V 250,1550,CONT_DIF_P,* +V 0,1850,CONT_DIF_N,* +V 60,1850,CONT_DIF_N,* +V 0,1960,CONT_DIF_N,* +V 0,1900,CONT_DIF_N,* +V 60,1900,CONT_DIF_N,* +V 0,1650,CONT_DIF_P,* +V 60,1650,CONT_DIF_P,* +V 0,1600,CONT_DIF_P,* +V 60,1600,CONT_DIF_P,* +V 250,1900,CONT_DIF_N,* +V 190,1900,CONT_DIF_N,* +V 250,1960,CONT_DIF_N,* +V 190,1850,CONT_DIF_N,* +V 250,1850,CONT_DIF_N,* +V 250,1600,CONT_DIF_P,* +V 190,1600,CONT_DIF_P,* +V 190,1650,CONT_DIF_P,* +V 250,1650,CONT_DIF_P,* +V 130,1720,CONT_BODY_N,* +V 60,1260,CONT_DIF_P,* +V 0,1260,CONT_DIF_P,* +V 100,1150,CONT_VIA,* +V 100,1150,CONT_POLY,* +V 60,1100,CONT_DIF_N,* +V 120,1050,CONT_DIF_N,* +V 250,1050,CONT_DIF_N,* +V 190,1030,CONT_BODY_P,* +V 60,1030,CONT_BODY_P,* +V 190,1210,CONT_DIF_P,* +V 130,1260,CONT_DIF_P,* +V 190,1100,CONT_DIF_N,* +V 250,1210,CONT_DIF_P,* +V 250,1260,CONT_DIF_P,* +V 250,1100,CONT_DIF_N,* +V 0,1100,CONT_DIF_N,* +V 250,1330,CONT_BODY_N,* +V 0,1330,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_mid_buf_4.vbe b/alliance/src/cells/src/rflib/rf_mid_buf_4.vbe new file mode 100644 index 00000000..18cc9b4d --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_mid_buf_4.vbe @@ -0,0 +1,23 @@ +ENTITY rf_mid_buf_4 IS +PORT ( + selr : in BIT; + selw : in BIT; + nck : in BIT; + read : out BIT; + write : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_mid_buf_4; + +ARCHITECTURE VBE OF rf_mid_buf_4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_mid_buf_4" + SEVERITY WARNING; + + read <= selr; + write <= selw and nck; + +END; diff --git a/alliance/src/cells/src/rflib/rf_mid_mem.ap b/alliance/src/cells/src/rflib/rf_mid_mem.ap new file mode 100644 index 00000000..b97be0b5 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_mid_mem.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H rf_mid_mem,P, 7/ 4/2002,10 +A 0,0,250,500 +S 160,150,210,150,20,*,RIGHT,ALU1 +S 150,150,200,150,20,*,RIGHT,ALU2 +S 150,150,200,150,20,*,RIGHT,TALU2 +S 110,200,200,200,20,latch,LEFT,ALU1 +S 110,100,110,200,20,latch,UP,ALU1 +S 100,250,100,280,20,*,DOWN,ALU1 +S 250,200,250,250,20,*,DOWN,ALU1 +S 150,300,150,340,20,*,UP,ALU1 +S 200,100,250,100,20,*,LEFT,ALU1 +S 30,280,100,280,20,*,RIGHT,ALU1 +S 100,250,150,250,20,*,RIGHT,ALU1 +S 200,200,200,400,20,latch,DOWN,ALU1 +S 80,390,150,390,20,*,RIGHT,ALU1 +S 80,330,80,390,20,*,DOWN,ALU1 +S 30,280,30,400,20,*,DOWN,ALU1 +S 200,100,250,100,20,dinx,LEFT,CALU2 +S 200,250,250,250,20,rbus,LEFT,CALU2 +S 50,300,50,300,20,read,LEFT,CALU3 +S 200,150,200,150,20,write,LEFT,CALU3 +S 190,150,220,150,30,*,RIGHT,POLY +S 220,50,220,140,10,*,UP,NTRANS +S 250,70,250,120,30,*,DOWN,NDIF +S 130,160,130,180,40,*,DOWN,NDIF +S 160,220,160,270,100,*,DOWN,NDIF +S 220,200,220,290,10,*,UP,NTRANS +S 0,230,50,230,20,*,RIGHT,ALU1 +S 30,220,30,270,80,*,DOWN,NDIF +S 90,290,90,340,10,*,DOWN,POLY +S 90,200,90,290,10,*,UP,NTRANS +S 60,330,90,330,30,*,RIGHT,POLY +S 50,200,90,200,10,*,RIGHT,POLY +S 0,30,0,230,20,*,UP,ALU1 +S 110,100,150,100,20,*,RIGHT,ALU1 +S 90,70,100,70,10,*,LEFT,POLY +S 100,70,100,110,10,*,DOWN,POLY +S 30,70,90,70,10,*,RIGHT,NTRANS +S 150,290,220,290,10,*,RIGHT,POLY +S 120,360,200,360,10,*,RIGHT,POLY +S 0,430,250,430,160,*,RIGHT,NWELL +S 250,220,250,270,30,*,UP,NDIF +S 60,100,60,140,20,*,DOWN,ALU1 +S 60,480,160,480,10,*,RIGHT,POLY +S 160,470,160,480,10,*,DOWN,POLY +S 100,450,140,450,30,*,RIGHT,PDIF +S 170,420,170,470,30,*,UP,PTRANS +S 200,420,220,420,70,*,RIGHT,PDIF +S 120,360,120,420,10,*,DOWN,PTRANS +S 30,360,30,460,30,*,UP,PDIF +S 90,360,90,460,30,*,UP,PDIF +S 60,340,60,480,10,*,UP,PTRANS +S 70,150,70,200,50,*,UP,NTRANS +S 50,300,150,300,20,*,RIGHT,ALU2 +S 150,80,150,180,30,*,DOWN,NDIF +S 160,80,160,180,30,*,DOWN,NDIF +S 180,80,180,120,50,*,DOWN,NDIF +S 190,70,190,120,30,*,UP,NDIF +S 0,30,250,30,60,vss,RIGHT,CALU1 +S 0,470,250,470,60,vdd,RIGHT,CALU1 +S 50,300,150,300,20,ck,RIGHT,TALU2 +S 0,170,0,270,30,*,UP,NDIF +S 20,170,20,270,20,*,DOWN,NDIF +V 200,150,CONT_VIA,* +V 200,150,CONT_VIA2,* +V 200,150,CONT_POLY,* +V 200,500,CONT_BODY_N,* +V 250,250,CONT_DIF_N,* +V 50,230,CONT_DIF_N,* +V 150,250,CONT_DIF_N,* +V 80,330,CONT_POLY,* +V 0,230,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 60,40,CONT_DIF_N,* +V 110,100,CONT_POLY,* +V 150,300,CONT_POLY,* +V 200,350,CONT_POLY,* +V 60,100,CONT_DIF_N,* +V 60,140,CONT_POLY,* +V 250,100,CONT_DIF_N,* +V 210,400,CONT_DIF_P,* +V 150,390,CONT_DIF_P,* +V 90,450,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 150,300,CONT_VIA,* +V 50,300,CONT_VIA2,* +V 250,100,CONT_VIA,* +V 250,250,CONT_VIA,* +V 120,30,CONT_BODY_P,* +V 0,180,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_mid_mem.vbe b/alliance/src/cells/src/rflib/rf_mid_mem.vbe new file mode 100644 index 00000000..abe96394 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_mid_mem.vbe @@ -0,0 +1,30 @@ +ENTITY rf_mid_mem IS +PORT ( + dinx : in BIT; + write : in BIT; + read : in BIT; + rbus : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rf_mid_mem; + +ARCHITECTURE VBE OF rf_mid_mem IS + SIGNAL latch : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_mid_mem" + SEVERITY WARNING; + + label0 : BLOCK (write = '1') + BEGIN + latch <= GUARDED dinx; + END BLOCK label0; + + label1 : BLOCK (read = '1') + BEGIN + rbus <= GUARDED latch; + END BLOCK label1; + +END; diff --git a/alliance/src/cells/src/rflib/rf_mid_mem_r0.ap b/alliance/src/cells/src/rflib/rf_mid_mem_r0.ap new file mode 100644 index 00000000..463afa2f --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_mid_mem_r0.ap @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H rf_mid_mem_r0,P, 7/ 4/2002,10 +A 0,0,250,500 +S 100,300,150,300,20,*,LEFT,ALU1 +S 250,200,250,250,20,*,DOWN,ALU1 +S 50,300,150,300,20,ck,RIGHT,TALU2 +S 0,470,250,470,60,vdd,RIGHT,CALU1 +S 0,30,250,30,60,vss,RIGHT,CALU1 +S 50,300,150,300,20,*,RIGHT,ALU2 +S 250,220,250,270,30,*,UP,NDIF +S 0,430,250,430,160,*,RIGHT,NWELL +S 150,290,220,290,10,*,RIGHT,POLY +S 0,160,0,270,30,*,UP,NDIF +S 0,30,0,230,20,*,UP,ALU1 +S 220,200,220,290,10,*,UP,NTRANS +S 200,150,200,150,20,write,LEFT,CALU3 +S 50,300,50,300,20,read,LEFT,CALU3 +S 190,220,190,270,30,*,UP,NDIF +S 0,230,190,230,20,*,RIGHT,ALU1 +S 200,100,250,100,20,dinx,LEFT,CALU2 +S 200,250,250,250,20,rbus,LEFT,CALU2 +V 250,250,CONT_VIA,* +V 50,300,CONT_VIA2,* +V 150,300,CONT_VIA,* +V 0,170,CONT_DIF_N,* +V 150,300,CONT_POLY,* +V 0,230,CONT_DIF_N,* +V 250,250,CONT_DIF_N,* +V 200,500,CONT_BODY_N,* +V 190,230,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_mid_mem_r0.vbe b/alliance/src/cells/src/rflib/rf_mid_mem_r0.vbe new file mode 100644 index 00000000..71c03d0e --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_mid_mem_r0.vbe @@ -0,0 +1,25 @@ +ENTITY rf_mid_mem_r0 IS +PORT ( + dinx : in BIT; + write : in BIT; + read : in BIT; + rbus : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rf_mid_mem_r0; + +ARCHITECTURE VBE OF rf_mid_mem_r0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_mid_mem_r0" + SEVERITY WARNING; + + label1 : BLOCK (read = '1') + BEGIN + rbus <= GUARDED '0'; + END BLOCK label1; + + +END; diff --git a/alliance/src/cells/src/rflib/rf_out_buf_2.ap b/alliance/src/cells/src/rflib/rf_out_buf_2.ap new file mode 100644 index 00000000..3215558d --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_out_buf_2.ap @@ -0,0 +1,85 @@ +V ALLIANCE : 6 +H rf_out_buf_2,P, 7/ 4/2002,10 +A 0,0,550,1000 +S 100,150,200,150,20,*,RIGHT,ALU2 +S 100,400,200,400,20,*,RIGHT,ALU2 +S 100,600,200,600,20,*,RIGHT,ALU2 +S 100,900,150,900,20,nck,LEFT,CALU2 +S 180,640,180,700,10,*,UP,POLY +S 120,640,120,700,10,*,UP,POLY +S 150,600,150,650,20,*,UP,ALU1 +S 150,700,150,900,20,*,DOWN,ALU1 +S 120,700,180,700,30,*,RIGHT,POLY +S 100,600,200,600,20,*,RIGHT,TALU2 +S 100,400,200,400,20,*,RIGHT,TALU2 +S 100,150,200,150,20,*,RIGHT,TALU2 +S 150,150,150,600,20,xcks,UP,CALU3 +S 210,330,210,620,30,*,UP,PDIF +S 90,330,90,620,30,*,UP,PDIF +S 180,310,180,640,10,*,UP,PTRANS +S 150,330,150,620,30,*,UP,PDIF +S 120,310,120,640,10,*,UP,PTRANS +S 120,10,120,200,10,*,UP,NTRANS +S 180,10,180,200,10,*,DOWN,NTRANS +S 90,30,90,180,30,*,UP,NDIF +S 150,30,150,180,30,*,UP,NDIF +S 210,30,210,180,30,*,UP,NDIF +S 120,200,120,310,10,*,UP,POLY +S 180,200,180,310,10,*,UP,POLY +S 120,210,180,210,30,*,RIGHT,POLY +S 210,40,210,150,20,*,UP,ALU1 +S 90,40,90,150,20,*,UP,ALU1 +S 150,100,150,400,20,*,UP,ALU1 +S 90,280,90,670,20,*,UP,ALU1 +S 210,280,210,670,20,*,UP,ALU1 +S 0,610,550,610,240,*,LEFT,NWELL +S 0,390,550,390,240,*,LEFT,NWELL +S -20,650,430,650,320,*,LEFT,NWELL +S -20,390,430,390,260,*,LEFT,NWELL +S 0,470,550,470,60,vdd,RIGHT,CALU1 +S 0,530,550,530,60,vdd,RIGHT,CALU1 +S 0,30,550,30,60,vss,RIGHT,CALU1 +S 0,970,550,970,60,vss,RIGHT,CALU1 +S 290,30,290,150,20,*,DOWN,ALU1 +V 150,700,CONT_POLY,* +V 290,530,CONT_BODY_N,* +V 290,470,CONT_BODY_N,* +V 150,150,CONT_VIA,* +V 150,150,CONT_VIA2,* +V 150,400,CONT_VIA,* +V 150,400,CONT_VIA2,* +V 150,600,CONT_VIA,* +V 150,600,CONT_VIA2,* +V 210,600,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,550,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,600,CONT_DIF_P,* +V 90,280,CONT_BODY_N,* +V 210,450,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,280,CONT_BODY_N,* +V 210,670,CONT_BODY_N,* +V 90,670,CONT_BODY_N,* +V 90,600,CONT_DIF_P,* +V 90,550,CONT_DIF_P,* +V 90,500,CONT_DIF_P,* +V 90,450,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,40,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 210,40,CONT_DIF_N,* +V 210,150,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 280,970,CONT_BODY_P,* +V 220,970,CONT_BODY_P,* +V 150,900,CONT_VIA,* +V 290,90,CONT_BODY_P,* +V 290,150,CONT_BODY_P,* +V 290,30,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_out_buf_2.vbe b/alliance/src/cells/src/rflib/rf_out_buf_2.vbe new file mode 100644 index 00000000..6262aed7 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_out_buf_2.vbe @@ -0,0 +1,19 @@ +ENTITY rf_out_buf_2 IS +PORT ( + nck : in BIT; + xcks : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_out_buf_2; + +ARCHITECTURE VBE OF rf_out_buf_2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_out_buf_2" + SEVERITY WARNING; + + xcks <= not nck; + +END; diff --git a/alliance/src/cells/src/rflib/rf_out_buf_4.ap b/alliance/src/cells/src/rflib/rf_out_buf_4.ap new file mode 100644 index 00000000..6287401e --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_out_buf_4.ap @@ -0,0 +1,156 @@ +V ALLIANCE : 6 +H rf_out_buf_4,P,14/11/2000,10 +A 0,0,550,2000 +S 100,1850,200,1850,20,*,RIGHT,TALU2 +S 100,1600,200,1600,20,*,RIGHT,TALU2 +S 100,1400,200,1400,20,*,RIGHT,TALU2 +S 100,600,200,600,20,*,RIGHT,TALU2 +S 100,400,200,400,20,*,RIGHT,TALU2 +S 100,150,200,150,20,*,RIGHT,TALU2 +S 450,0,450,2000,120,vdd,UP,CALU3 +S 0,30,550,30,60,vss,RIGHT,CALU1 +S 0,530,550,530,60,vdd,RIGHT,CALU1 +S 0,470,550,470,60,vdd,RIGHT,CALU1 +S 0,1530,550,1530,60,vdd,LEFT,CALU1 +S 0,1470,550,1470,60,vdd,LEFT,CALU1 +S 0,1970,550,1970,60,vss,LEFT,CALU1 +S 0,1030,550,1030,60,vss,LEFT,CALU1 +S 0,970,550,970,60,vss,LEFT,CALU1 +S 0,1390,550,1390,240,*,RIGHT,NWELL +S 0,1610,550,1610,240,*,RIGHT,NWELL +S -20,1350,430,1350,320,*,RIGHT,NWELL +S -20,1610,430,1610,260,*,RIGHT,NWELL +S 0,610,550,610,240,*,LEFT,NWELL +S 0,390,550,390,240,*,LEFT,NWELL +S -20,650,430,650,320,*,LEFT,NWELL +S -20,390,430,390,260,*,LEFT,NWELL +S 150,150,150,1850,20,xcks,DOWN,CALU3 +S 150,900,150,900,20,nck,LEFT,CALU2 +S 150,1600,150,1900,20,*,UP,ALU1 +S 90,1850,90,1960,20,*,UP,ALU1 +S 210,1330,210,1720,20,*,UP,ALU1 +S 90,1330,90,1720,20,*,UP,ALU1 +S 210,1850,210,1960,20,*,UP,ALU1 +S 120,1690,120,1800,10,*,UP,POLY +S 120,1790,180,1790,10,*,LEFT,POLY +S 180,1690,180,1800,10,*,UP,POLY +S 150,1820,150,1970,30,*,UP,NDIF +S 90,1820,90,1970,30,*,UP,NDIF +S 210,1820,210,1970,30,*,UP,NDIF +S 120,1800,120,1990,10,*,UP,NTRANS +S 180,1800,180,1990,10,*,DOWN,NTRANS +S 150,1380,150,1670,30,*,UP,PDIF +S 120,1360,120,1690,10,*,UP,PTRANS +S 90,1380,90,1670,30,*,UP,PDIF +S 180,1360,180,1690,10,*,UP,PTRANS +S 210,1380,210,1670,30,*,UP,PDIF +S 280,1850,280,1970,20,*,DOWN,ALU1 +S 120,640,120,1360,10,*,UP,POLY +S 180,640,180,1360,10,*,UP,POLY +S 120,900,180,900,30,*,RIGHT,POLY +S 90,40,90,150,20,*,UP,ALU1 +S 150,100,150,400,20,*,UP,ALU1 +S 210,280,210,670,20,*,UP,ALU1 +S 90,280,90,670,20,*,UP,ALU1 +S 180,200,180,310,10,*,UP,POLY +S 120,200,120,310,10,*,UP,POLY +S 120,210,180,210,10,*,RIGHT,POLY +S 90,30,90,180,30,*,UP,NDIF +S 150,30,150,180,30,*,UP,NDIF +S 120,10,120,200,10,*,UP,NTRANS +S 180,10,180,200,10,*,DOWN,NTRANS +S 90,330,90,620,30,*,UP,PDIF +S 180,310,180,640,10,*,UP,PTRANS +S 150,330,150,620,30,*,UP,PDIF +S 120,310,120,640,10,*,UP,PTRANS +S 210,330,210,620,30,*,UP,PDIF +S 270,30,270,150,20,*,DOWN,ALU1 +S 210,40,210,150,20,*,UP,ALU1 +S 210,30,210,180,30,*,UP,NDIF +S 400,500,500,500,20,*,RIGHT,TALU2 +S 400,1500,500,1500,20,*,RIGHT,TALU2 +B 450,1500,120,20,CONT_VIA,* +B 450,1500,120,20,CONT_VIA2,* +B 450,500,120,20,CONT_VIA2,* +B 450,500,120,20,CONT_VIA,* +V 460,1030,CONT_BODY_P,* +V 460,970,CONT_BODY_P,* +V 150,900,CONT_VIA,* +V 150,900,CONT_POLY,* +V 90,1900,CONT_DIF_N,* +V 90,1960,CONT_DIF_N,* +V 90,1850,CONT_DIF_N,* +V 150,1900,CONT_DIF_N,* +V 150,1850,CONT_DIF_N,* +V 210,1960,CONT_DIF_N,* +V 210,1900,CONT_DIF_N,* +V 210,1850,CONT_DIF_N,* +V 150,1600,CONT_DIF_P,* +V 150,1400,CONT_DIF_P,* +V 90,1720,CONT_BODY_N,* +V 90,1400,CONT_DIF_P,* +V 90,1450,CONT_DIF_P,* +V 90,1500,CONT_DIF_P,* +V 90,1550,CONT_DIF_P,* +V 90,1600,CONT_DIF_P,* +V 90,1650,CONT_DIF_P,* +V 150,1650,CONT_DIF_P,* +V 90,1330,CONT_BODY_N,* +V 210,1330,CONT_BODY_N,* +V 210,1650,CONT_DIF_P,* +V 210,1600,CONT_DIF_P,* +V 210,1550,CONT_DIF_P,* +V 210,1500,CONT_DIF_P,* +V 210,1450,CONT_DIF_P,* +V 210,1400,CONT_DIF_P,* +V 210,1720,CONT_BODY_N,* +V 280,1970,CONT_BODY_P,* +V 280,1850,CONT_BODY_P,* +V 280,1910,CONT_BODY_P,* +V 270,1530,CONT_BODY_N,* +V 270,1470,CONT_BODY_N,* +V 150,1850,CONT_VIA2,* +V 150,1850,CONT_VIA,* +V 150,1600,CONT_VIA2,* +V 150,1600,CONT_VIA,* +V 150,1400,CONT_VIA2,* +V 150,1400,CONT_VIA,* +V 90,100,CONT_DIF_N,* +V 90,40,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,600,CONT_DIF_P,* +V 90,280,CONT_BODY_N,* +V 90,600,CONT_DIF_P,* +V 90,550,CONT_DIF_P,* +V 90,500,CONT_DIF_P,* +V 90,450,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,670,CONT_BODY_N,* +V 210,280,CONT_BODY_N,* +V 210,670,CONT_BODY_N,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,450,CONT_DIF_P,* +V 210,500,CONT_DIF_P,* +V 210,550,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 270,530,CONT_BODY_N,* +V 270,470,CONT_BODY_N,* +V 270,90,CONT_BODY_P,* +V 270,150,CONT_BODY_P,* +V 270,30,CONT_BODY_P,* +V 210,150,CONT_DIF_N,* +V 210,40,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 150,600,CONT_VIA2,* +V 150,600,CONT_VIA,* +V 150,400,CONT_VIA2,* +V 150,400,CONT_VIA,* +V 150,150,CONT_VIA2,* +V 150,150,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_out_buf_4.vbe b/alliance/src/cells/src/rflib/rf_out_buf_4.vbe new file mode 100644 index 00000000..868f2527 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_out_buf_4.vbe @@ -0,0 +1,19 @@ +ENTITY rf_out_buf_4 IS +PORT ( + nck : in BIT; + xcks : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_out_buf_4; + +ARCHITECTURE VBE OF rf_out_buf_4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_out_buf_4" + SEVERITY WARNING; + + xcks <= not nck; + +END; diff --git a/alliance/src/cells/src/rflib/rf_out_mem.ap b/alliance/src/cells/src/rflib/rf_out_mem.ap new file mode 100644 index 00000000..9a3e35b5 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_out_mem.ap @@ -0,0 +1,138 @@ +V ALLIANCE : 6 +H rf_out_mem,P, 7/ 4/2002,10 +A 0,0,550,500 +R 450,100,ref_ref,dataout_10 +R 450,150,ref_ref,dataout_15 +R 450,200,ref_ref,dataout_20 +R 450,250,ref_ref,dataout_25 +R 450,300,ref_ref,dataout_30 +R 450,350,ref_ref,dataout_35 +R 450,400,ref_ref,dataout_40 +S 230,250,230,300,20,*,UP,ALU1 +S 0,250,50,250,20,rbus,LEFT,CALU2 +S 330,250,400,250,20,*,RIGHT,ALU1 +S 150,150,210,150,20,*,RIGHT,ALU1 +S 150,350,210,350,20,*,LEFT,ALU1 +S 210,350,210,400,20,*,UP,ALU1 +S 330,100,330,400,20,*,DOWN,ALU1 +S 280,150,280,350,20,*,DOWN,ALU1 +S 150,150,150,350,20,*,UP,ALU1 +S 100,150,100,400,20,*,UP,ALU1 +S 270,150,280,150,20,*,RIGHT,ALU1 +S 80,350,100,350,20,*,RIGHT,ALU1 +S 120,310,120,360,10,*,DOWN,POLY +S 50,310,120,310,10,*,RIGHT,POLY +S 90,100,90,190,30,*,UP,NDIF +S 120,80,120,210,10,*,UP,NTRANS +S 50,210,120,210,10,*,RIGHT,POLY +S 50,200,50,300,20,*,UP,ALU1 +S 100,260,180,260,10,*,RIGHT,POLY +S 150,50,150,100,20,*,DOWN,ALU1 +S 150,400,150,450,20,*,UP,ALU1 +S 150,250,150,250,20,xcks,LEFT,CALU3 +S 300,80,330,80,40,*,RIGHT,POLY +S 150,30,150,190,30,*,UP,NDIF +S 240,210,240,250,10,*,DOWN,POLY +S 150,250,230,250,20,*,RIGHT,ALU2 +S 180,120,180,210,10,*,UP,NTRANS +S 210,150,210,190,30,*,UP,NDIF +S 270,120,270,190,30,*,UP,NDIF +S 240,120,240,210,10,*,UP,NTRANS +S 250,80,300,80,40,*,RIGHT,NTRANS +S 30,300,30,370,20,*,UP,ALU1 +S 30,300,50,300,20,*,LEFT,ALU1 +S 250,400,300,400,30,*,RIGHT,PTRANS +S 300,400,330,400,30,*,RIGHT,POLY +S 390,40,390,190,30,*,UP,NDIF +S 330,130,330,190,30,*,UP,NDIF +S 360,110,360,210,10,*,UP,NTRANS +S 360,210,360,290,10,*,DOWN,POLY +S 270,230,360,230,10,*,RIGHT,POLY +S 330,310,330,370,30,*,UP,PDIF +S 360,290,360,390,10,*,UP,PTRANS +S 110,390,550,390,240,*,LEFT,NWELL +S 390,250,480,250,30,*,RIGHT,POLY +S 60,350,90,350,30,*,RIGHT,POLY +S 60,340,60,420,10,*,DOWN,POLY +S 0,430,550,430,160,*,RIGHT,NWELL +S 450,80,450,170,30,*,UP,NDIF +S 420,60,420,190,10,*,UP,NTRANS +S 510,40,510,170,30,*,UP,NDIF +S 480,60,480,190,10,*,UP,NTRANS +S 480,260,480,490,10,*,UP,PTRANS +S 120,360,120,490,10,*,UP,PTRANS +S 390,280,390,470,30,*,UP,PDIF +S 90,380,90,470,30,*,UP,PDIF +S 420,260,420,490,10,*,UP,PTRANS +S 450,280,450,470,30,*,UP,PDIF +S 10,410,60,410,30,*,RIGHT,PTRANS +S 510,280,510,470,30,*,UP,PDIF +S 480,190,480,260,10,*,DOWN,POLY +S 420,190,420,260,10,*,DOWN,POLY +S 510,50,510,150,20,*,UP,ALU1 +S 510,300,510,450,20,*,UP,ALU1 +S 390,50,390,150,20,*,UP,ALU1 +S 390,300,390,450,20,*,DOWN,ALU1 +S 0,30,550,30,60,vss,RIGHT,CALU1 +S 0,470,550,470,60,vdd,LEFT,CALU1 +S 450,100,450,400,20,dataout,DOWN,CALU1 +S 180,210,180,290,10,*,DOWN,POLY +S 180,290,180,440,10,*,UP,PTRANS +S 210,310,210,420,30,*,UP,PDIF +S 150,310,150,470,30,*,UP,PDIF +S 150,250,250,250,20,*,RIGHT,TALU2 +V 270,350,CONT_DIF_P,* +V 100,260,CONT_POLY,* +V 90,30,CONT_BODY_P,* +V 90,150,CONT_DIF_N,* +V 50,200,CONT_POLY,* +V 150,50,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 210,30,CONT_BODY_P,* +V 230,250,CONT_VIA,* +V 230,250,CONT_POLY,* +V 150,250,CONT_VIA2,* +V 320,100,CONT_POLY,* +V 210,150,CONT_DIF_N,* +V 280,230,CONT_POLY,* +V 270,150,CONT_DIF_N,* +V 270,30,CONT_DIF_N,* +V 50,300,CONT_POLY,* +V 50,250,CONT_VIA,* +V 320,400,CONT_POLY,* +V 400,250,CONT_POLY,* +V 330,470,CONT_BODY_N,* +V 80,350,CONT_POLY,* +V 510,100,CONT_DIF_N,* +V 390,50,CONT_DIF_N,* +V 450,150,CONT_DIF_N,* +V 450,100,CONT_DIF_N,* +V 390,100,CONT_DIF_N,* +V 510,50,CONT_DIF_N,* +V 330,150,CONT_DIF_N,* +V 510,150,CONT_DIF_N,* +V 390,150,CONT_DIF_N,* +V 150,400,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 450,300,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 510,450,CONT_DIF_P,* +V 390,450,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 510,300,CONT_DIF_P,* +V 30,370,CONT_DIF_P,* +V 390,400,CONT_DIF_P,* +V 390,350,CONT_DIF_P,* +V 510,400,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 510,350,CONT_DIF_P,* +V 390,300,CONT_DIF_P,* +V 210,470,CONT_BODY_N,* +V 450,30,CONT_BODY_P,* +V 330,30,CONT_BODY_P,* +V 270,440,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/rflib/rf_out_mem.vbe b/alliance/src/cells/src/rflib/rf_out_mem.vbe new file mode 100644 index 00000000..86cd1067 --- /dev/null +++ b/alliance/src/cells/src/rflib/rf_out_mem.vbe @@ -0,0 +1,26 @@ +ENTITY rf_out_mem IS +PORT ( + rbus : in BIT; + xcks : in BIT; + dataout : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_out_mem; + +ARCHITECTURE VBE OF rf_out_mem IS + SIGNAL latch : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_out_mem" + SEVERITY WARNING; + + label0 : BLOCK (xcks = '1') + BEGIN + latch <= GUARDED rbus; + END BLOCK label0; + + dataout <= latch; + +END; diff --git a/alliance/src/cells/src/rflib/rflib.lef b/alliance/src/cells/src/rflib/rflib.lef new file mode 100644 index 00000000..ced427fd --- /dev/null +++ b/alliance/src/cells/src/rflib/rflib.lef @@ -0,0 +1,2635 @@ + +MACRO rf_dec_bufad0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION INOUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END nq + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 29.00 26.00 31.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END rf_dec_bufad0 + + +MACRO rf_dec_bufad1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END nq + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 31.00 21.00 ; + END +END rf_dec_bufad1 + + +MACRO rf_dec_bufad2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq0 + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END nq0 + PIN nq1 + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END nq1 + PIN q0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END q0 + PIN q1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END q1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 46.00 21.00 ; + END +END rf_dec_bufad2 + + +MACRO rf_dec_nand2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 36.00 21.00 ; + END +END rf_dec_nand2 + + +MACRO rf_dec_nand3 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 29.00 19.00 36.00 21.00 ; + RECT 19.00 19.00 41.00 21.00 ; + END +END rf_dec_nand3 + + +MACRO rf_dec_nand4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i0 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 14.00 19.00 41.00 21.00 ; + RECT 29.00 19.00 36.00 21.00 ; + END +END rf_dec_nand4 + + +MACRO rf_dec_nao3 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 34.00 21.00 36.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 39.00 11.00 41.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 19.00 11.00 21.00 ; + END +END rf_dec_nao3 + + +MACRO rf_dec_nbuf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END rf_dec_nbuf + + +MACRO rf_dec_nor3 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 39.00 11.00 41.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 19.00 11.00 21.00 ; + END +END rf_dec_nor3 + + +MACRO rf_fifo_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN xcks + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END xcks + PIN xckm + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END xckm + PIN nw + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 24.00 79.00 26.00 81.00 ; + RECT 24.00 74.00 26.00 76.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 24.00 59.00 26.00 61.00 ; + END + END nw + PIN xreset + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END xreset + PIN nr + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + END + END nr + PIN nreset + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 44.00 79.00 46.00 81.00 ; + RECT 44.00 74.00 46.00 76.00 ; + RECT 44.00 69.00 46.00 71.00 ; + RECT 44.00 64.00 46.00 66.00 ; + RECT 44.00 59.00 46.00 61.00 ; + LAYER L_ALU3 ; + RECT 44.00 59.00 46.00 61.00 ; + RECT 44.00 54.00 46.00 56.00 ; + RECT 44.00 49.00 46.00 51.00 ; + RECT 44.00 44.00 46.00 46.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + END + END nreset + PIN ckm + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END ckm + PIN cks + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + END + END cks + PIN reset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 34.00 79.00 36.00 81.00 ; + END + END reset + PIN r + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + END + END r + PIN w + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 74.00 36.00 76.00 ; + RECT 29.00 74.00 31.00 76.00 ; + END + END w + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 47.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 47.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + RECT 1.50 59.00 48.50 91.00 ; + LAYER L_ALU2 ; + RECT 44.00 59.00 51.00 61.00 ; + RECT 44.00 24.00 51.00 26.00 ; + RECT 44.00 59.00 51.00 61.00 ; + RECT 44.00 24.00 51.00 26.00 ; + END +END rf_fifo_buf + + +MACRO rf_fifo_clock + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN ckm + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + END + END ckm + PIN cks + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + END + END cks + PIN ckok + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + END + END ckok + PIN wok + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + END + END wok + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 44.00 69.00 46.00 71.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 34.00 69.00 36.00 71.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 19.00 69.00 21.00 71.00 ; + LAYER L_ALU3 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + END + END ck + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 47.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 47.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + RECT 1.50 59.00 48.50 91.00 ; + LAYER L_ALU2 ; + RECT 29.00 19.00 41.00 21.00 ; + RECT 29.00 79.00 46.00 81.00 ; + RECT 9.00 24.00 36.00 26.00 ; + RECT 29.00 19.00 41.00 21.00 ; + RECT 24.00 39.00 31.00 41.00 ; + RECT 9.00 24.00 51.00 26.00 ; + RECT 14.00 39.00 21.00 41.00 ; + RECT 19.00 84.00 36.00 86.00 ; + RECT 29.00 79.00 36.00 81.00 ; + RECT 39.00 79.00 46.00 81.00 ; + RECT 39.00 59.00 46.00 61.00 ; + RECT 29.00 59.00 36.00 61.00 ; + RECT 29.00 59.00 46.00 61.00 ; + RECT 39.00 39.00 46.00 41.00 ; + RECT 44.00 24.00 51.00 26.00 ; + RECT 19.00 84.00 36.00 86.00 ; + RECT 14.00 39.00 46.00 41.00 ; + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 61.00 ; + RECT 34.00 24.00 36.00 61.00 ; + RECT 44.00 39.00 46.00 81.00 ; + RECT 44.00 39.00 46.00 81.00 ; + RECT 34.00 24.00 36.00 61.00 ; + RECT 39.00 19.00 41.00 61.00 ; + END +END rf_fifo_clock + + +MACRO rf_fifo_empty + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN empty + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END empty + PIN nreset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END nreset + PIN cks + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END cks + PIN emptynext + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + END + END emptynext + PIN ckm + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END ckm + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END rf_fifo_empty + + +MACRO rf_fifo_full + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN full + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END full + PIN cks + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END cks + PIN reset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END reset + PIN fullnext + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + END + END fullnext + PIN ckm + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END ckm + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END rf_fifo_full + + +MACRO rf_fifo_inc + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN inc + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END inc + PIN nval + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + END + END nval + PIN ckm + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END ckm + PIN nreset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + END + END nreset + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END rf_fifo_inc + + +MACRO rf_fifo_nop + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nval + DIRECTION INOUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + END + END nval + PIN nop + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nop + PIN rw + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END rw + PIN nreset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + END + END nreset + PIN ckm + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END ckm + PIN rwok + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + END + END rwok + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END rf_fifo_nop + + +MACRO rf_fifo_ok + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nextval + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + END + END nextval + PIN ok + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END ok + PIN nrw + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END nrw + PIN prev + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END prev + PIN rw + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + END + END rw + PIN ripple + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + END + END ripple + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END rf_fifo_ok + + +MACRO rf_fifo_orand4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN rippleout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END rippleout + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END a1 + PIN b1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END b1 + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END a0 + PIN b0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END b0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END rf_fifo_orand4 + + +MACRO rf_fifo_orand5 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN rippleout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END rippleout + PIN b0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END b0 + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END a0 + PIN ripplein + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END ripplein + PIN b1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END b1 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END a1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END rf_fifo_orand5 + + +MACRO rf_fifo_ptreset + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN pt + DIRECTION INOUT ; + PORT + LAYER L_ALU2 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END pt + PIN nop + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END nop + PIN ptm1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END ptm1 + PIN cks + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END cks + PIN reset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END reset + PIN inc + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END inc + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 34.00 41.00 36.00 ; + RECT 4.00 34.00 41.00 36.00 ; + RECT 9.00 19.00 46.00 21.00 ; + END +END rf_fifo_ptreset + + +MACRO rf_fifo_ptset + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN pt + DIRECTION INOUT ; + PORT + LAYER L_ALU2 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END pt + PIN nop + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END nop + PIN inc + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END inc + PIN nreset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END nreset + PIN cks + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END cks + PIN ptm1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END ptm1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 9.00 19.00 46.00 21.00 ; + RECT 4.00 34.00 41.00 36.00 ; + RECT 4.00 34.00 41.00 36.00 ; + END +END rf_fifo_ptset + + +MACRO rf_inmux_buf_2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN sel0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END sel0 + PIN sel1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END sel1 + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + END + END nck + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + END + END ck + PIN sel + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 14.00 79.00 16.00 81.00 ; + RECT 14.00 74.00 16.00 76.00 ; + RECT 14.00 69.00 16.00 71.00 ; + END + END sel + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 42.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 42.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + RECT 1.50 59.00 43.50 91.00 ; + LAYER L_ALU2 ; + RECT 8.00 14.00 26.00 16.00 ; + RECT 8.00 39.00 26.00 41.00 ; + RECT 34.00 14.00 40.00 16.00 ; + RECT 34.00 39.00 40.00 41.00 ; + RECT 4.00 39.00 41.00 41.00 ; + RECT 4.00 14.00 41.00 16.00 ; + END +END rf_inmux_buf_2 + + +MACRO rf_inmux_buf_4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 200.00 ; + SYMMETRY Y ; + SITE core ; + PIN sel1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 184.00 26.00 186.00 ; + RECT 24.00 179.00 26.00 181.00 ; + RECT 24.00 174.00 26.00 176.00 ; + RECT 24.00 169.00 26.00 171.00 ; + RECT 24.00 164.00 26.00 166.00 ; + RECT 24.00 159.00 26.00 161.00 ; + RECT 24.00 154.00 26.00 156.00 ; + RECT 24.00 149.00 26.00 151.00 ; + RECT 24.00 144.00 26.00 146.00 ; + RECT 24.00 139.00 26.00 141.00 ; + RECT 24.00 134.00 26.00 136.00 ; + RECT 24.00 129.00 26.00 131.00 ; + RECT 24.00 124.00 26.00 126.00 ; + RECT 24.00 119.00 26.00 121.00 ; + RECT 24.00 114.00 26.00 116.00 ; + RECT 24.00 109.00 26.00 111.00 ; + RECT 24.00 104.00 26.00 106.00 ; + RECT 24.00 99.00 26.00 101.00 ; + RECT 24.00 94.00 26.00 96.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 24.00 79.00 26.00 81.00 ; + RECT 24.00 74.00 26.00 76.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 24.00 54.00 26.00 56.00 ; + RECT 24.00 49.00 26.00 51.00 ; + RECT 24.00 44.00 26.00 46.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END sel1 + PIN sel0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 159.00 36.00 161.00 ; + RECT 34.00 154.00 36.00 156.00 ; + RECT 34.00 149.00 36.00 151.00 ; + RECT 34.00 144.00 36.00 146.00 ; + RECT 34.00 139.00 36.00 141.00 ; + RECT 34.00 134.00 36.00 136.00 ; + RECT 34.00 129.00 36.00 131.00 ; + RECT 34.00 124.00 36.00 126.00 ; + RECT 34.00 119.00 36.00 121.00 ; + RECT 34.00 114.00 36.00 116.00 ; + RECT 34.00 109.00 36.00 111.00 ; + RECT 34.00 104.00 36.00 106.00 ; + RECT 34.00 99.00 36.00 101.00 ; + RECT 34.00 94.00 36.00 96.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 34.00 79.00 36.00 81.00 ; + RECT 34.00 74.00 36.00 76.00 ; + RECT 34.00 69.00 36.00 71.00 ; + RECT 34.00 64.00 36.00 66.00 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 34.00 54.00 36.00 56.00 ; + RECT 34.00 49.00 36.00 51.00 ; + RECT 34.00 44.00 36.00 46.00 ; + RECT 34.00 39.00 36.00 41.00 ; + END + END sel0 + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + END + END nck + PIN sel + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 14.00 79.00 16.00 81.00 ; + RECT 14.00 74.00 16.00 76.00 ; + RECT 14.00 69.00 16.00 71.00 ; + END + END sel + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + END + END ck + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 42.00 53.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 147.00 42.00 147.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 153.00 42.00 153.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 42.00 97.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 103.00 42.00 103.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 197.00 42.00 197.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 194.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + RECT 1.50 59.00 43.50 91.00 ; + RECT 1.50 109.00 43.50 141.00 ; + RECT 1.50 159.00 43.50 191.00 ; + LAYER L_ALU2 ; + RECT 26.00 39.00 40.00 41.00 ; + RECT 8.00 14.00 26.00 16.00 ; + RECT 26.00 159.00 40.00 161.00 ; + RECT 8.00 184.00 26.00 186.00 ; + RECT 26.00 39.00 40.00 41.00 ; + RECT 8.00 14.00 26.00 16.00 ; + RECT 8.00 184.00 26.00 186.00 ; + RECT 26.00 159.00 40.00 161.00 ; + RECT 4.00 99.00 16.00 101.00 ; + RECT 4.00 -1.00 16.00 1.00 ; + RECT 4.00 199.00 16.00 201.00 ; + END +END rf_inmux_buf_4 + + +MACRO rf_inmux_mem + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN dinx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END dinx + PIN datain1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END datain1 + PIN datain0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END datain0 + PIN sel0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 29.00 36.00 31.00 ; + END + END sel0 + PIN sel1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 29.00 26.00 31.00 ; + END + END sel1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + LAYER L_ALU2 ; + RECT 34.00 29.00 41.00 31.00 ; + RECT 19.00 29.00 26.00 31.00 ; + RECT 19.00 29.00 41.00 31.00 ; + END +END rf_inmux_mem + + +MACRO rf_mid_buf_2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN read + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END read + PIN write + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END write + PIN nck + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + END + END nck + PIN selr + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 79.00 16.00 81.00 ; + RECT 9.00 79.00 11.00 81.00 ; + END + END selr + PIN selw + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + END + END selw + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 22.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 22.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + RECT 1.50 59.00 23.50 91.00 ; + LAYER L_ALU2 ; + RECT 4.00 59.00 21.00 61.00 ; + RECT 4.00 39.00 21.00 41.00 ; + RECT 4.00 14.00 21.00 16.00 ; + RECT 4.00 59.00 11.00 61.00 ; + RECT 14.00 59.00 21.00 61.00 ; + RECT 4.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 21.00 41.00 ; + RECT 4.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 21.00 16.00 ; + END +END rf_mid_buf_2 + + +MACRO rf_mid_buf_4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 200.00 ; + SYMMETRY Y ; + SITE core ; + PIN read + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 184.00 6.00 186.00 ; + RECT 4.00 179.00 6.00 181.00 ; + RECT 4.00 174.00 6.00 176.00 ; + RECT 4.00 169.00 6.00 171.00 ; + RECT 4.00 164.00 6.00 166.00 ; + RECT 4.00 159.00 6.00 161.00 ; + RECT 4.00 154.00 6.00 156.00 ; + RECT 4.00 149.00 6.00 151.00 ; + RECT 4.00 144.00 6.00 146.00 ; + RECT 4.00 139.00 6.00 141.00 ; + END + END read + PIN write + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END write + PIN nck + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT -1.00 89.00 1.00 91.00 ; + END + END nck + PIN selw + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 84.00 16.00 86.00 ; + END + END selw + PIN selr + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 114.00 11.00 116.00 ; + END + END selr + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 22.00 53.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 147.00 22.00 147.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 153.00 22.00 153.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 22.00 97.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 103.00 22.00 103.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 197.00 22.00 197.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + RECT 1.50 59.00 23.50 91.00 ; + RECT 1.50 109.00 23.50 141.00 ; + RECT 1.50 159.00 23.50 191.00 ; + LAYER L_ALU2 ; + RECT -1.00 14.00 26.00 16.00 ; + RECT -1.00 39.00 26.00 41.00 ; + RECT -1.00 59.00 26.00 61.00 ; + RECT -1.00 139.00 26.00 141.00 ; + RECT -1.00 159.00 26.00 161.00 ; + RECT -1.00 184.00 26.00 186.00 ; + END +END rf_mid_buf_4 + + +MACRO rf_mid_mem + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN rbus + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + END + END rbus + PIN dinx + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END dinx + PIN read + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 29.00 6.00 31.00 ; + END + END read + PIN write + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END write + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 29.00 16.00 31.00 ; + RECT 4.00 29.00 16.00 31.00 ; + RECT 14.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 21.00 16.00 ; + END +END rf_mid_mem + + +MACRO rf_mid_mem_r0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN rbus + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + END + END rbus + PIN write + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END write + PIN read + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 29.00 6.00 31.00 ; + END + END read + PIN dinx + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END dinx + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 29.00 16.00 31.00 ; + RECT 4.00 29.00 16.00 31.00 ; + END +END rf_mid_mem_r0 + + +MACRO rf_out_buf_2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN xcks + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 59.00 16.00 61.00 ; + RECT 14.00 54.00 16.00 56.00 ; + RECT 14.00 49.00 16.00 51.00 ; + RECT 14.00 44.00 16.00 46.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END xcks + PIN nck + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + END + END nck + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 52.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 52.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + RECT 1.50 59.00 53.50 91.00 ; + LAYER L_ALU2 ; + RECT 9.00 14.00 21.00 16.00 ; + RECT 9.00 39.00 21.00 41.00 ; + RECT 9.00 59.00 21.00 61.00 ; + RECT 9.00 59.00 21.00 61.00 ; + RECT 9.00 39.00 21.00 41.00 ; + RECT 9.00 14.00 21.00 16.00 ; + END +END rf_out_buf_2 + + +MACRO rf_out_buf_4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 200.00 ; + SYMMETRY Y ; + SITE core ; + PIN xcks + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 184.00 16.00 186.00 ; + RECT 14.00 179.00 16.00 181.00 ; + RECT 14.00 174.00 16.00 176.00 ; + RECT 14.00 169.00 16.00 171.00 ; + RECT 14.00 164.00 16.00 166.00 ; + RECT 14.00 159.00 16.00 161.00 ; + RECT 14.00 154.00 16.00 156.00 ; + RECT 14.00 149.00 16.00 151.00 ; + RECT 14.00 144.00 16.00 146.00 ; + RECT 14.00 139.00 16.00 141.00 ; + RECT 14.00 134.00 16.00 136.00 ; + RECT 14.00 129.00 16.00 131.00 ; + RECT 14.00 124.00 16.00 126.00 ; + RECT 14.00 119.00 16.00 121.00 ; + RECT 14.00 114.00 16.00 116.00 ; + RECT 14.00 109.00 16.00 111.00 ; + RECT 14.00 104.00 16.00 106.00 ; + RECT 14.00 99.00 16.00 101.00 ; + RECT 14.00 94.00 16.00 96.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 14.00 79.00 16.00 81.00 ; + RECT 14.00 74.00 16.00 76.00 ; + RECT 14.00 69.00 16.00 71.00 ; + RECT 14.00 64.00 16.00 66.00 ; + RECT 14.00 59.00 16.00 61.00 ; + RECT 14.00 54.00 16.00 56.00 ; + RECT 14.00 49.00 16.00 51.00 ; + RECT 14.00 44.00 16.00 46.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END xcks + PIN nck + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 89.00 16.00 91.00 ; + END + END nck + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 52.00 53.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 147.00 52.00 147.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 153.00 52.00 153.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 45.00 6.00 45.00 194.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 52.00 97.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 103.00 52.00 103.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 197.00 52.00 197.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + RECT 1.50 59.00 53.50 91.00 ; + RECT 1.50 109.00 53.50 141.00 ; + RECT 1.50 159.00 53.50 191.00 ; + LAYER L_ALU2 ; + RECT 39.00 149.00 51.00 151.00 ; + RECT 39.00 49.00 51.00 51.00 ; + RECT 9.00 14.00 21.00 16.00 ; + RECT 9.00 39.00 21.00 41.00 ; + RECT 9.00 59.00 21.00 61.00 ; + RECT 9.00 139.00 21.00 141.00 ; + RECT 9.00 159.00 21.00 161.00 ; + RECT 9.00 184.00 21.00 186.00 ; + END +END rf_out_buf_4 + + +MACRO rf_out_mem + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN dataout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END dataout + PIN rbus + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT -1.00 24.00 1.00 26.00 ; + END + END rbus + PIN xcks + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END xcks + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + LAYER L_ALU2 ; + RECT 14.00 24.00 26.00 26.00 ; + RECT 14.00 24.00 24.00 26.00 ; + END +END rf_out_mem + + +END LIBRARY diff --git a/alliance/src/cells/src/sxlib/000000002.dat b/alliance/src/cells/src/sxlib/000000002.dat new file mode 100644 index 00000000..8f5f6414 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000002.dat differ diff --git a/alliance/src/cells/src/sxlib/000000003.dat b/alliance/src/cells/src/sxlib/000000003.dat new file mode 100644 index 00000000..2cc0a6b6 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000003.dat differ diff --git a/alliance/src/cells/src/sxlib/000000004.dat b/alliance/src/cells/src/sxlib/000000004.dat new file mode 100644 index 00000000..bb0180ee Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000004.dat differ diff --git a/alliance/src/cells/src/sxlib/000000005.dat b/alliance/src/cells/src/sxlib/000000005.dat new file mode 100644 index 00000000..b9c01ea0 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000005.dat differ diff --git a/alliance/src/cells/src/sxlib/000000006.dat b/alliance/src/cells/src/sxlib/000000006.dat new file mode 100644 index 00000000..04eea4f5 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000006.dat differ diff --git a/alliance/src/cells/src/sxlib/000000007.dat b/alliance/src/cells/src/sxlib/000000007.dat new file mode 100644 index 00000000..cd8150e9 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000007.dat differ diff --git a/alliance/src/cells/src/sxlib/000000008.dat b/alliance/src/cells/src/sxlib/000000008.dat new file mode 100644 index 00000000..2bf65cac Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000008.dat differ diff --git a/alliance/src/cells/src/sxlib/000000009.dat b/alliance/src/cells/src/sxlib/000000009.dat new file mode 100644 index 00000000..639b813b Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000009.dat differ diff --git a/alliance/src/cells/src/sxlib/000000010.dat b/alliance/src/cells/src/sxlib/000000010.dat new file mode 100644 index 00000000..8ea6907b Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000010.dat differ diff --git a/alliance/src/cells/src/sxlib/000000011.dat b/alliance/src/cells/src/sxlib/000000011.dat new file mode 100644 index 00000000..e23d8aa5 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000011.dat differ diff --git a/alliance/src/cells/src/sxlib/000000012.dat b/alliance/src/cells/src/sxlib/000000012.dat new file mode 100644 index 00000000..68fee161 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000012.dat differ diff --git a/alliance/src/cells/src/sxlib/000000013.dat b/alliance/src/cells/src/sxlib/000000013.dat new file mode 100644 index 00000000..3647fbf3 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000013.dat differ diff --git a/alliance/src/cells/src/sxlib/000000014.dat b/alliance/src/cells/src/sxlib/000000014.dat new file mode 100644 index 00000000..5074e607 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000014.dat differ diff --git a/alliance/src/cells/src/sxlib/000000015.dat b/alliance/src/cells/src/sxlib/000000015.dat new file mode 100644 index 00000000..f0f207eb Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000015.dat differ diff --git a/alliance/src/cells/src/sxlib/000000016.dat b/alliance/src/cells/src/sxlib/000000016.dat new file mode 100644 index 00000000..027c98ea Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000016.dat differ diff --git a/alliance/src/cells/src/sxlib/000000017.dat b/alliance/src/cells/src/sxlib/000000017.dat new file mode 100644 index 00000000..1e0d8abb Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000017.dat differ diff --git a/alliance/src/cells/src/sxlib/000000018.dat b/alliance/src/cells/src/sxlib/000000018.dat new file mode 100644 index 00000000..215eb3a6 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000018.dat differ diff --git a/alliance/src/cells/src/sxlib/000000019.dat b/alliance/src/cells/src/sxlib/000000019.dat new file mode 100644 index 00000000..af54d08e Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000019.dat differ diff --git a/alliance/src/cells/src/sxlib/000000020.dat b/alliance/src/cells/src/sxlib/000000020.dat new file mode 100644 index 00000000..6a9d5fa2 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000020.dat differ diff --git a/alliance/src/cells/src/sxlib/000000021.dat b/alliance/src/cells/src/sxlib/000000021.dat new file mode 100644 index 00000000..ad82e746 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000021.dat differ diff --git a/alliance/src/cells/src/sxlib/000000022.dat b/alliance/src/cells/src/sxlib/000000022.dat new file mode 100644 index 00000000..eef3ed2c Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000022.dat differ diff --git a/alliance/src/cells/src/sxlib/000000023.dat b/alliance/src/cells/src/sxlib/000000023.dat new file mode 100644 index 00000000..ac7ee646 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000023.dat differ diff --git a/alliance/src/cells/src/sxlib/000000024.dat b/alliance/src/cells/src/sxlib/000000024.dat new file mode 100644 index 00000000..9040c905 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000024.dat differ diff --git a/alliance/src/cells/src/sxlib/000000025.dat b/alliance/src/cells/src/sxlib/000000025.dat new file mode 100644 index 00000000..2d48d57b Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000025.dat differ diff --git a/alliance/src/cells/src/sxlib/000000026.dat b/alliance/src/cells/src/sxlib/000000026.dat new file mode 100644 index 00000000..75cc1c86 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000026.dat differ diff --git a/alliance/src/cells/src/sxlib/000000027.dat b/alliance/src/cells/src/sxlib/000000027.dat new file mode 100644 index 00000000..6053abeb Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000027.dat differ diff --git a/alliance/src/cells/src/sxlib/000000028.dat b/alliance/src/cells/src/sxlib/000000028.dat new file mode 100644 index 00000000..98574bc3 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000028.dat differ diff --git a/alliance/src/cells/src/sxlib/000000029.dat b/alliance/src/cells/src/sxlib/000000029.dat new file mode 100644 index 00000000..1c502145 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000029.dat differ diff --git a/alliance/src/cells/src/sxlib/000000030.dat b/alliance/src/cells/src/sxlib/000000030.dat new file mode 100644 index 00000000..67091bb5 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000030.dat differ diff --git a/alliance/src/cells/src/sxlib/000000031.dat b/alliance/src/cells/src/sxlib/000000031.dat new file mode 100644 index 00000000..6f0b6367 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000031.dat differ diff --git a/alliance/src/cells/src/sxlib/000000032.dat b/alliance/src/cells/src/sxlib/000000032.dat new file mode 100644 index 00000000..5248383e Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000032.dat differ diff --git a/alliance/src/cells/src/sxlib/000000033.dat b/alliance/src/cells/src/sxlib/000000033.dat new file mode 100644 index 00000000..e1d1b458 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000033.dat differ diff --git a/alliance/src/cells/src/sxlib/000000034.dat b/alliance/src/cells/src/sxlib/000000034.dat new file mode 100644 index 00000000..f8045799 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000034.dat differ diff --git a/alliance/src/cells/src/sxlib/000000035.dat b/alliance/src/cells/src/sxlib/000000035.dat new file mode 100644 index 00000000..2dd9cfef Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000035.dat differ diff --git a/alliance/src/cells/src/sxlib/000000036.dat b/alliance/src/cells/src/sxlib/000000036.dat new file mode 100644 index 00000000..c75da1a8 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000036.dat differ diff --git a/alliance/src/cells/src/sxlib/000000037.dat b/alliance/src/cells/src/sxlib/000000037.dat new file mode 100644 index 00000000..601f914b Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000037.dat differ diff --git a/alliance/src/cells/src/sxlib/000000038.dat b/alliance/src/cells/src/sxlib/000000038.dat new file mode 100644 index 00000000..253753e3 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000038.dat differ diff --git a/alliance/src/cells/src/sxlib/000000039.dat b/alliance/src/cells/src/sxlib/000000039.dat new file mode 100644 index 00000000..1f7f0584 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000039.dat differ diff --git a/alliance/src/cells/src/sxlib/000000040.dat b/alliance/src/cells/src/sxlib/000000040.dat new file mode 100644 index 00000000..b209e767 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000040.dat differ diff --git a/alliance/src/cells/src/sxlib/000000041.dat b/alliance/src/cells/src/sxlib/000000041.dat new file mode 100644 index 00000000..8063dabc Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000041.dat differ diff --git a/alliance/src/cells/src/sxlib/000000042.dat b/alliance/src/cells/src/sxlib/000000042.dat new file mode 100644 index 00000000..2899495e Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000042.dat differ diff --git a/alliance/src/cells/src/sxlib/000000043.dat b/alliance/src/cells/src/sxlib/000000043.dat new file mode 100644 index 00000000..51d64a28 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000043.dat differ diff --git a/alliance/src/cells/src/sxlib/000000044.dat b/alliance/src/cells/src/sxlib/000000044.dat new file mode 100644 index 00000000..a52170f7 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000044.dat differ diff --git a/alliance/src/cells/src/sxlib/000000045.dat b/alliance/src/cells/src/sxlib/000000045.dat new file mode 100644 index 00000000..f50bf8b0 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000045.dat differ diff --git a/alliance/src/cells/src/sxlib/000000046.dat b/alliance/src/cells/src/sxlib/000000046.dat new file mode 100644 index 00000000..625737c4 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000046.dat differ diff --git a/alliance/src/cells/src/sxlib/000000047.dat b/alliance/src/cells/src/sxlib/000000047.dat new file mode 100644 index 00000000..59801cd7 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000047.dat differ diff --git a/alliance/src/cells/src/sxlib/000000048.dat b/alliance/src/cells/src/sxlib/000000048.dat new file mode 100644 index 00000000..ce817eb2 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000048.dat differ diff --git a/alliance/src/cells/src/sxlib/000000049.dat b/alliance/src/cells/src/sxlib/000000049.dat new file mode 100644 index 00000000..e2aa0f95 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000049.dat differ diff --git a/alliance/src/cells/src/sxlib/000000050.dat b/alliance/src/cells/src/sxlib/000000050.dat new file mode 100644 index 00000000..3d028628 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000050.dat differ diff --git a/alliance/src/cells/src/sxlib/000000051.dat b/alliance/src/cells/src/sxlib/000000051.dat new file mode 100644 index 00000000..dbe52418 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000051.dat differ diff --git a/alliance/src/cells/src/sxlib/000000052.dat b/alliance/src/cells/src/sxlib/000000052.dat new file mode 100644 index 00000000..12fcf5fb Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000052.dat differ diff --git a/alliance/src/cells/src/sxlib/000000053.dat b/alliance/src/cells/src/sxlib/000000053.dat new file mode 100644 index 00000000..28227e04 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000053.dat differ diff --git a/alliance/src/cells/src/sxlib/000000054.dat b/alliance/src/cells/src/sxlib/000000054.dat new file mode 100644 index 00000000..742b60bd Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000054.dat differ diff --git a/alliance/src/cells/src/sxlib/000000055.dat b/alliance/src/cells/src/sxlib/000000055.dat new file mode 100644 index 00000000..d4ddfa7b Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000055.dat differ diff --git a/alliance/src/cells/src/sxlib/000000056.dat b/alliance/src/cells/src/sxlib/000000056.dat new file mode 100644 index 00000000..075be6df Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000056.dat differ diff --git a/alliance/src/cells/src/sxlib/000000057.dat b/alliance/src/cells/src/sxlib/000000057.dat new file mode 100644 index 00000000..f1195e62 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000057.dat differ diff --git a/alliance/src/cells/src/sxlib/000000058.dat b/alliance/src/cells/src/sxlib/000000058.dat new file mode 100644 index 00000000..18e58bca Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000058.dat differ diff --git a/alliance/src/cells/src/sxlib/000000059.dat b/alliance/src/cells/src/sxlib/000000059.dat new file mode 100644 index 00000000..e21a27e7 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000059.dat differ diff --git a/alliance/src/cells/src/sxlib/000000060.dat b/alliance/src/cells/src/sxlib/000000060.dat new file mode 100644 index 00000000..94635540 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000060.dat differ diff --git a/alliance/src/cells/src/sxlib/000000061.dat b/alliance/src/cells/src/sxlib/000000061.dat new file mode 100644 index 00000000..e8d5b694 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000061.dat differ diff --git a/alliance/src/cells/src/sxlib/000000062.dat b/alliance/src/cells/src/sxlib/000000062.dat new file mode 100644 index 00000000..aa9dbdd4 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000062.dat differ diff --git a/alliance/src/cells/src/sxlib/000000063.dat b/alliance/src/cells/src/sxlib/000000063.dat new file mode 100644 index 00000000..b77116dd Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000063.dat differ diff --git a/alliance/src/cells/src/sxlib/000000064.dat b/alliance/src/cells/src/sxlib/000000064.dat new file mode 100644 index 00000000..cbd34d07 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000064.dat differ diff --git a/alliance/src/cells/src/sxlib/000000065.dat b/alliance/src/cells/src/sxlib/000000065.dat new file mode 100644 index 00000000..0b0fb736 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000065.dat differ diff --git a/alliance/src/cells/src/sxlib/000000066.dat b/alliance/src/cells/src/sxlib/000000066.dat new file mode 100644 index 00000000..0d4e876e Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000066.dat differ diff --git a/alliance/src/cells/src/sxlib/000000067.dat b/alliance/src/cells/src/sxlib/000000067.dat new file mode 100644 index 00000000..d2ebacfc Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000067.dat differ diff --git a/alliance/src/cells/src/sxlib/000000068.dat b/alliance/src/cells/src/sxlib/000000068.dat new file mode 100644 index 00000000..d81ad246 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000068.dat differ diff --git a/alliance/src/cells/src/sxlib/000000069.dat b/alliance/src/cells/src/sxlib/000000069.dat new file mode 100644 index 00000000..97c43878 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000069.dat differ diff --git a/alliance/src/cells/src/sxlib/000000070.dat b/alliance/src/cells/src/sxlib/000000070.dat new file mode 100644 index 00000000..7ebf61c4 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000070.dat differ diff --git a/alliance/src/cells/src/sxlib/000000071.dat b/alliance/src/cells/src/sxlib/000000071.dat new file mode 100644 index 00000000..1711230c Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000071.dat differ diff --git a/alliance/src/cells/src/sxlib/000000072.dat b/alliance/src/cells/src/sxlib/000000072.dat new file mode 100644 index 00000000..a3e4f3a4 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000072.dat differ diff --git a/alliance/src/cells/src/sxlib/000000073.dat b/alliance/src/cells/src/sxlib/000000073.dat new file mode 100644 index 00000000..33603c4a Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000073.dat differ diff --git a/alliance/src/cells/src/sxlib/000000074.dat b/alliance/src/cells/src/sxlib/000000074.dat new file mode 100644 index 00000000..b657aff8 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000074.dat differ diff --git a/alliance/src/cells/src/sxlib/000000075.dat b/alliance/src/cells/src/sxlib/000000075.dat new file mode 100644 index 00000000..41b13f03 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000075.dat differ diff --git a/alliance/src/cells/src/sxlib/000000076.dat b/alliance/src/cells/src/sxlib/000000076.dat new file mode 100644 index 00000000..17336d59 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000076.dat differ diff --git a/alliance/src/cells/src/sxlib/000000077.dat b/alliance/src/cells/src/sxlib/000000077.dat new file mode 100644 index 00000000..3fca3a3f Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000077.dat differ diff --git a/alliance/src/cells/src/sxlib/000000078.dat b/alliance/src/cells/src/sxlib/000000078.dat new file mode 100644 index 00000000..438b0179 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000078.dat differ diff --git a/alliance/src/cells/src/sxlib/000000079.dat b/alliance/src/cells/src/sxlib/000000079.dat new file mode 100644 index 00000000..08fb7959 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000079.dat differ diff --git a/alliance/src/cells/src/sxlib/000000080.dat b/alliance/src/cells/src/sxlib/000000080.dat new file mode 100644 index 00000000..079fa138 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000080.dat differ diff --git a/alliance/src/cells/src/sxlib/000000081.dat b/alliance/src/cells/src/sxlib/000000081.dat new file mode 100644 index 00000000..5acdb047 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000081.dat differ diff --git a/alliance/src/cells/src/sxlib/000000082.dat b/alliance/src/cells/src/sxlib/000000082.dat new file mode 100644 index 00000000..6e1b2a3c Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000082.dat differ diff --git a/alliance/src/cells/src/sxlib/000000083.dat b/alliance/src/cells/src/sxlib/000000083.dat new file mode 100644 index 00000000..c1d9db20 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000083.dat differ diff --git a/alliance/src/cells/src/sxlib/000000084.dat b/alliance/src/cells/src/sxlib/000000084.dat new file mode 100644 index 00000000..c25e6b5a Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000084.dat differ diff --git a/alliance/src/cells/src/sxlib/000000085.dat b/alliance/src/cells/src/sxlib/000000085.dat new file mode 100644 index 00000000..d6ca4e4b Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000085.dat differ diff --git a/alliance/src/cells/src/sxlib/000000086.dat b/alliance/src/cells/src/sxlib/000000086.dat new file mode 100644 index 00000000..0dd55540 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000086.dat differ diff --git a/alliance/src/cells/src/sxlib/000000087.dat b/alliance/src/cells/src/sxlib/000000087.dat new file mode 100644 index 00000000..a35939ef Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000087.dat differ diff --git a/alliance/src/cells/src/sxlib/000000088.dat b/alliance/src/cells/src/sxlib/000000088.dat new file mode 100644 index 00000000..72d4a443 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000088.dat differ diff --git a/alliance/src/cells/src/sxlib/000000089.dat b/alliance/src/cells/src/sxlib/000000089.dat new file mode 100644 index 00000000..98b81956 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000089.dat differ diff --git a/alliance/src/cells/src/sxlib/000000090.dat b/alliance/src/cells/src/sxlib/000000090.dat new file mode 100644 index 00000000..8087a990 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000090.dat differ diff --git a/alliance/src/cells/src/sxlib/000000091.dat b/alliance/src/cells/src/sxlib/000000091.dat new file mode 100644 index 00000000..8342b5bf Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000091.dat differ diff --git a/alliance/src/cells/src/sxlib/000000092.dat b/alliance/src/cells/src/sxlib/000000092.dat new file mode 100644 index 00000000..641fb488 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000092.dat differ diff --git a/alliance/src/cells/src/sxlib/000000093.dat b/alliance/src/cells/src/sxlib/000000093.dat new file mode 100644 index 00000000..6c0c4f2a Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000093.dat differ diff --git a/alliance/src/cells/src/sxlib/000000094.dat b/alliance/src/cells/src/sxlib/000000094.dat new file mode 100644 index 00000000..fa8213a0 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000094.dat differ diff --git a/alliance/src/cells/src/sxlib/000000095.dat b/alliance/src/cells/src/sxlib/000000095.dat new file mode 100644 index 00000000..e5e48067 Binary files /dev/null and b/alliance/src/cells/src/sxlib/000000095.dat differ diff --git a/alliance/src/cells/src/sxlib/CATAL b/alliance/src/cells/src/sxlib/CATAL new file mode 100644 index 00000000..8b40a929 --- /dev/null +++ b/alliance/src/cells/src/sxlib/CATAL @@ -0,0 +1,98 @@ +a2_x2 C +a2_x4 C +a3_x2 C +a3_x4 C +a4_x2 C +a4_x4 C +an12_x1 C +an12_x4 C +ao22_x2 C +ao22_x4 C +ao2o22_x2 C +ao2o22_x4 C +buf_x2 C +buf_x4 C +buf_x8 C +fulladder_x2 C +fulladder_x4 C +halfadder_x2 C +halfadder_x4 C +inv_x1 C +inv_x2 C +inv_x4 C +inv_x8 C +mx2_x2 C +mx2_x4 C +mx3_x2 C +mx3_x4 C +na2_x1 C +na2_x4 C +na3_x1 C +na3_x4 C +na4_x1 C +na4_x4 C +nao22_x1 C +nao22_x4 C +nao2o22_x1 C +nao2o22_x4 C +nmx2_x1 C +nmx2_x4 C +nmx3_x1 C +nmx3_x4 C +no2_x1 C +no2_x4 C +no3_x1 C +no3_x4 C +no4_x1 C +no4_x4 C +noa22_x1 C +noa22_x4 C +noa2a22_x1 C +noa2a22_x4 C +noa2a2a23_x1 C +noa2a2a23_x4 C +noa2a2a2a24_x1 C +noa2a2a2a24_x4 C +noa2ao222_x1 C +noa2ao222_x4 C +noa3ao322_x1 C +noa3ao322_x4 C +nts_x1 C +nts_x2 C +nxr2_x1 C +nxr2_x4 C +o2_x2 C +o2_x4 C +o3_x2 C +o3_x4 C +o4_x2 C +o4_x4 C +oa22_x2 C +oa22_x4 C +oa2a22_x2 C +oa2a22_x4 C +oa2a2a23_x2 C +oa2a2a23_x4 C +oa2a2a2a24_x2 C +oa2a2a2a24_x4 C +oa2ao222_x2 C +oa2ao222_x4 C +oa3ao322_x2 C +oa3ao322_x4 C +on12_x1 C +on12_x4 C +one_x0 C +powmid_x0 C +powmid_x0 F +rowend_x0 C +rowend_x0 F +sff1_x4 C +sff2_x4 C +sff3_x4 C +tie_x0 C +tie_x0 F +ts_x4 C +ts_x8 C +xr2_x1 C +xr2_x4 C +zero_x0 C diff --git a/alliance/src/cells/src/sxlib/CIRCUIT.IDX b/alliance/src/cells/src/sxlib/CIRCUIT.IDX new file mode 100644 index 00000000..c0fc8a91 --- /dev/null +++ b/alliance/src/cells/src/sxlib/CIRCUIT.IDX @@ -0,0 +1,97 @@ +SystemHILO +uQPTQCZ1ZEJLA7-WS +95 +3 A2_X2 2 +3 A2_X4 3 +3 A3_X2 4 +3 A3_X4 5 +3 A4_X2 6 +3 A4_X4 7 +3 AN12_X1 8 +3 AN12_X4 9 +3 AO22_X2 10 +3 AO22_X4 11 +3 AO2O22_X2 12 +3 AO2O22_X4 13 +3 BUF_X2 14 +3 BUF_X4 15 +3 BUF_X8 16 +3 FULLADDER_X2 17 +3 FULLADDER_X4 18 +3 HALFADDER_X2 19 +3 HALFADDER_X4 20 +3 INV_X1 21 +3 INV_X2 22 +3 INV_X4 23 +3 INV_X8 24 +3 MX2_X2 25 +3 MX2_X4 26 +3 MX3_X2 27 +3 MX3_X4 28 +3 NA2_X1 29 +3 NA2_X4 30 +3 NA3_X1 31 +3 NA3_X4 32 +3 NA4_X1 33 +3 NA4_X4 34 +3 NAO22_X1 35 +3 NAO22_X4 36 +3 NAO2O22_X1 37 +3 NAO2O22_X4 38 +3 NMX2_X1 39 +3 NMX2_X4 40 +3 NMX3_X1 41 +3 NMX3_X4 42 +3 NO2_X1 43 +3 NO2_X4 44 +3 NO3_X1 45 +3 NO3_X4 46 +3 NO4_X1 47 +3 NO4_X4 48 +3 NOA22_X1 49 +3 NOA22_X4 50 +3 NOA2A22_X1 51 +3 NOA2A22_X4 52 +3 NOA2A2A23_X1 53 +3 NOA2A2A23_X4 54 +3 NOA2A2A2A24_X1 55 +3 NOA2A2A2A24_X4 56 +3 NOA2AO222_X1 57 +3 NOA2AO222_X4 58 +3 NOA3AO322_X1 59 +3 NOA3AO322_X4 60 +3 NTS_X1 61 +3 NTS_X2 62 +3 NXR2_X1 63 +3 NXR2_X4 64 +3 O2_X2 65 +3 O2_X4 66 +3 O3_X2 67 +3 O3_X4 68 +3 O4_X2 69 +3 O4_X4 70 +3 OA22_X2 71 +3 OA22_X4 72 +3 OA2A22_X2 73 +3 OA2A22_X4 74 +3 OA2A2A23_X2 75 +3 OA2A2A23_X4 76 +3 OA2A2A2A24_X2 77 +3 OA2A2A2A24_X4 78 +3 OA2AO222_X2 79 +3 OA2AO222_X4 80 +3 OA3AO322_X2 81 +3 OA3AO322_X4 82 +3 ON12_X1 83 +3 ON12_X4 84 +3 ONE_X0 85 +3 ROWEND_X0 86 +3 SFF1_X4 87 +3 SFF2_X4 88 +3 SFF3_X4 89 +3 TIE_X0 90 +3 TS_X4 91 +3 TS_X8 92 +3 XR2_X1 93 +3 XR2_X4 94 +3 ZERO_X0 95 diff --git a/alliance/src/cells/src/sxlib/Makefile.am b/alliance/src/cells/src/sxlib/Makefile.am new file mode 100644 index 00000000..5a592060 --- /dev/null +++ b/alliance/src/cells/src/sxlib/Makefile.am @@ -0,0 +1,6 @@ +# $Id: Makefile.am,v 1.1 2002/04/29 15:51:52 czo Exp $ + +sxlib_DATA= 000000002.dat 000000003.dat 000000004.dat 000000005.dat 000000006.dat 000000007.dat 000000008.dat 000000009.dat 000000010.dat 000000011.dat 000000012.dat 000000013.dat 000000014.dat 000000015.dat 000000016.dat 000000017.dat 000000018.dat 000000019.dat 000000020.dat 000000021.dat 000000022.dat 000000023.dat 000000024.dat 000000025.dat 000000026.dat 000000027.dat 000000028.dat 000000029.dat 000000030.dat 000000031.dat 000000032.dat 000000033.dat 000000034.dat 000000035.dat 000000036.dat 000000037.dat 000000038.dat 000000039.dat 000000040.dat 000000041.dat 000000042.dat 000000043.dat 000000044.dat 000000045.dat 000000046.dat 000000047.dat 000000048.dat 000000049.dat 000000050.dat 000000051.dat 000000052.dat 000000053.dat 000000054.dat 000000055.dat 000000056.dat 000000057.dat 000000058.dat 000000059.dat 000000060.dat 000000061.dat 000000062.dat 000000063.dat 000000064.dat 000000065.dat 000000066.dat 000000067.dat 000000068.dat 000000069.dat 000000070.dat 000000071.dat 000000072.dat 000000073.dat 000000074.dat 000000075.dat 000000076.dat 000000077.dat 000000078.dat 000000079.dat 000000080.dat 000000081.dat 000000082.dat 000000083.dat 000000084.dat 000000085.dat 000000086.dat 000000087.dat 000000088.dat 000000089.dat 000000090.dat 000000091.dat 000000092.dat 000000093.dat 000000094.dat 000000095.dat CATAL CIRCUIT.IDX Makefile.am Makefile.liban a2_x2.al a2_x2.ap a2_x2.sym a2_x2.vbe a2_x2.vhd a2_x4.al a2_x4.ap a2_x4.sym a2_x4.vbe a2_x4.vhd a3_x2.al a3_x2.ap a3_x2.sym a3_x2.vbe a3_x2.vhd a3_x4.al a3_x4.ap a3_x4.sym a3_x4.vbe a3_x4.vhd a4_x2.al a4_x2.ap a4_x2.sym a4_x2.vbe a4_x2.vhd a4_x4.al a4_x4.ap a4_x4.sym a4_x4.vbe a4_x4.vhd an12_x1.al an12_x1.ap an12_x1.sym an12_x1.vbe an12_x1.vhd an12_x4.al an12_x4.ap an12_x4.sym an12_x4.vbe an12_x4.vhd ao22_x2.al ao22_x2.ap ao22_x2.sym ao22_x2.vbe ao22_x2.vhd ao22_x4.al ao22_x4.ap ao22_x4.sym ao22_x4.vbe ao22_x4.vhd ao2o22_x2.al ao2o22_x2.ap ao2o22_x2.sym ao2o22_x2.vbe ao2o22_x2.vhd ao2o22_x4.al ao2o22_x4.ap ao2o22_x4.sym ao2o22_x4.vbe ao2o22_x4.vhd buf_x2.al buf_x2.ap buf_x2.sym buf_x2.vbe buf_x2.vhd buf_x4.al buf_x4.ap buf_x4.sym buf_x4.vbe buf_x4.vhd buf_x8.al buf_x8.ap buf_x8.sym buf_x8.vbe buf_x8.vhd fulladder_x2.al fulladder_x2.ap fulladder_x2.vbe fulladder_x2.vhd fulladder_x4.al fulladder_x4.ap fulladder_x4.vbe fulladder_x4.vhd halfadder_x2.al halfadder_x2.ap halfadder_x2.vbe halfadder_x2.vhd halfadder_x4.al halfadder_x4.ap halfadder_x4.vbe halfadder_x4.vhd inv_x1.al inv_x1.ap inv_x1.sym inv_x1.vbe inv_x1.vhd inv_x2.al inv_x2.ap inv_x2.sym inv_x2.vbe inv_x2.vhd inv_x4.al inv_x4.ap inv_x4.sym inv_x4.vbe inv_x4.vhd inv_x8.al inv_x8.ap inv_x8.sym inv_x8.vbe inv_x8.vhd mx2_x2.al mx2_x2.ap mx2_x2.sym mx2_x2.vbe mx2_x2.vhd mx2_x4.al mx2_x4.ap mx2_x4.sym mx2_x4.vbe mx2_x4.vhd mx3_x2.al mx3_x2.ap mx3_x2.vbe mx3_x2.vhd mx3_x4.al mx3_x4.ap mx3_x4.vbe mx3_x4.vhd na2_x1.al na2_x1.ap na2_x1.sym na2_x1.vbe na2_x1.vhd na2_x4.al na2_x4.ap na2_x4.sym na2_x4.vbe na2_x4.vhd na3_x1.al na3_x1.ap na3_x1.sym na3_x1.vbe na3_x1.vhd na3_x4.al na3_x4.ap na3_x4.sym na3_x4.vbe na3_x4.vhd na4_x1.al na4_x1.ap na4_x1.sym na4_x1.vbe na4_x1.vhd na4_x4.al na4_x4.ap na4_x4.sym na4_x4.vbe na4_x4.vhd nao22_x1.al nao22_x1.ap nao22_x1.sym nao22_x1.vbe nao22_x1.vhd nao22_x4.al nao22_x4.ap nao22_x4.sym nao22_x4.vbe nao22_x4.vhd nao2o22_x1.al nao2o22_x1.ap nao2o22_x1.sym nao2o22_x1.vbe nao2o22_x1.vhd nao2o22_x4.al nao2o22_x4.ap nao2o22_x4.sym nao2o22_x4.vbe nao2o22_x4.vhd nmx2_x1.al nmx2_x1.ap nmx2_x1.sym nmx2_x1.vbe nmx2_x1.vhd nmx2_x4.al nmx2_x4.ap nmx2_x4.sym nmx2_x4.vbe nmx2_x4.vhd nmx3_x1.al nmx3_x1.ap nmx3_x1.vbe nmx3_x1.vhd nmx3_x4.al nmx3_x4.ap nmx3_x4.vbe nmx3_x4.vhd no2_x1.al no2_x1.ap no2_x1.sym no2_x1.vbe no2_x1.vhd no2_x4.al no2_x4.ap no2_x4.sym no2_x4.vbe no2_x4.vhd no3_x1.al no3_x1.ap no3_x1.sym no3_x1.vbe no3_x1.vhd no3_x4.al no3_x4.ap no3_x4.sym no3_x4.vbe no3_x4.vhd no4_x1.al no4_x1.ap no4_x1.sym no4_x1.vbe no4_x1.vhd no4_x4.al no4_x4.ap no4_x4.sym no4_x4.vbe no4_x4.vhd noa22_x1.al noa22_x1.ap noa22_x1.sym noa22_x1.vbe noa22_x1.vhd noa22_x4.al noa22_x4.ap noa22_x4.sym noa22_x4.vbe noa22_x4.vhd noa2a22_x1.al noa2a22_x1.ap noa2a22_x1.sym noa2a22_x1.vbe noa2a22_x1.vhd noa2a22_x4.al noa2a22_x4.ap noa2a22_x4.sym noa2a22_x4.vbe noa2a22_x4.vhd noa2a2a23_x1.al noa2a2a23_x1.ap noa2a2a23_x1.sym noa2a2a23_x1.vbe noa2a2a23_x1.vhd noa2a2a23_x4.al noa2a2a23_x4.ap noa2a2a23_x4.sym noa2a2a23_x4.vbe noa2a2a23_x4.vhd noa2a2a2a24_x1.al noa2a2a2a24_x1.ap noa2a2a2a24_x1.sym noa2a2a2a24_x1.vbe noa2a2a2a24_x1.vhd noa2a2a2a24_x4.al noa2a2a2a24_x4.ap noa2a2a2a24_x4.sym noa2a2a2a24_x4.vbe noa2a2a2a24_x4.vhd noa2ao222_x1.al noa2ao222_x1.ap noa2ao222_x1.vbe noa2ao222_x1.vhd noa2ao222_x2.sym noa2ao222_x4.al noa2ao222_x4.ap noa2ao222_x4.sym noa2ao222_x4.vbe noa2ao222_x4.vhd noa3ao322_x1.al noa3ao322_x1.ap noa3ao322_x1.vbe noa3ao322_x1.vhd noa3ao322_x4.al noa3ao322_x4.ap noa3ao322_x4.sym noa3ao322_x4.vbe noa3ao322_x4.vhd nts_x1.al nts_x1.ap nts_x1.sym nts_x1.vbe nts_x1.vhd nts_x2.al nts_x2.ap nts_x2.sym nts_x2.vbe nts_x2.vhd nxr2_x1.al nxr2_x1.ap nxr2_x1.sym nxr2_x1.vbe nxr2_x1.vhd nxr2_x4.al nxr2_x4.ap nxr2_x4.sym nxr2_x4.vbe nxr2_x4.vhd o2_x2.al o2_x2.ap o2_x2.sym o2_x2.vbe o2_x2.vhd o2_x4.al o2_x4.ap o2_x4.sym o2_x4.vbe o2_x4.vhd o3_x2.al o3_x2.ap o3_x2.sym o3_x2.vbe o3_x2.vhd o3_x4.al o3_x4.ap o3_x4.sym o3_x4.vbe o3_x4.vhd o4_x2.al o4_x2.ap o4_x2.sym o4_x2.vbe o4_x2.vhd o4_x4.al o4_x4.ap o4_x4.sym o4_x4.vbe o4_x4.vhd oa22_x2.al oa22_x2.ap oa22_x2.sym oa22_x2.vbe oa22_x2.vhd oa22_x4.al oa22_x4.ap oa22_x4.sym oa22_x4.vbe oa22_x4.vhd oa2a22_x2.al oa2a22_x2.ap oa2a22_x2.sym oa2a22_x2.vbe oa2a22_x2.vhd oa2a22_x4.al oa2a22_x4.ap oa2a22_x4.sym oa2a22_x4.vbe oa2a22_x4.vhd oa2a2a23_x2.al oa2a2a23_x2.ap oa2a2a23_x2.sym oa2a2a23_x2.vbe oa2a2a23_x2.vhd oa2a2a23_x4.al oa2a2a23_x4.ap oa2a2a23_x4.sym oa2a2a23_x4.vbe oa2a2a23_x4.vhd oa2a2a2a24_x2.al oa2a2a2a24_x2.ap oa2a2a2a24_x2.sym oa2a2a2a24_x2.vbe oa2a2a2a24_x2.vhd oa2a2a2a24_x4.al oa2a2a2a24_x4.ap oa2a2a2a24_x4.sym oa2a2a2a24_x4.vbe oa2a2a2a24_x4.vhd oa2ao222_x2.al oa2ao222_x2.ap oa2ao222_x2.sym oa2ao222_x2.vbe oa2ao222_x2.vhd oa2ao222_x4.al oa2ao222_x4.ap oa2ao222_x4.sym oa2ao222_x4.vbe oa2ao222_x4.vhd oa3ao322_x1.sym oa3ao322_x2.al oa3ao322_x2.ap oa3ao322_x2.sym oa3ao322_x2.vbe oa3ao322_x2.vhd oa3ao322_x4.al oa3ao322_x4.ap oa3ao322_x4.sym oa3ao322_x4.vbe oa3ao322_x4.vhd on12_x1.al on12_x1.ap on12_x1.sym on12_x1.vbe on12_x1.vhd on12_x4.al on12_x4.ap on12_x4.sym on12_x4.vbe on12_x4.vhd one_x0.al one_x0.ap one_x0.sym one_x0.vbe one_x0.vhd powmid_x0.ap powmid_x0.vbe powmid_x0.vhd rowend_x0.al rowend_x0.ap rowend_x0.vbe rowend_x0.vhd sff1_x4.al sff1_x4.ap sff1_x4.sym sff1_x4.vbe sff1_x4.vhd sff2_x4.al sff2_x4.ap sff2_x4.sym sff2_x4.vbe sff2_x4.vhd sff3_x4.al sff3_x4.ap sff3_x4.vbe sff3_x4.vhd sxlib.cct sxlib.db sxlib.lef sxlib.lib sxlib.sdb sxlib.slib sxlib_FTGS.vhd sxlib_FTSM.vhd sxlib_UDSM.vhd sxlib_VITAL.vhd sxlib_Vcomponents.vhd sxlib_Vtables.vhd sxlib_components.vhd tie_x0.al tie_x0.ap tie_x0.vbe tie_x0.vhd ts_x4.al ts_x4.ap ts_x4.sym ts_x4.vbe ts_x4.vhd ts_x8.al ts_x8.ap ts_x8.sym ts_x8.vbe ts_x8.vhd xr2_x1.al xr2_x1.ap xr2_x1.sym xr2_x1.vbe xr2_x1.vhd xr2_x4.al xr2_x4.ap xr2_x4.sym xr2_x4.vbe xr2_x4.vhd zero_x0.al zero_x0.ap zero_x0.sym zero_x0.vbe zero_x0.vhd + +EXTRA_DIST=$(rflib_DATA) + diff --git a/alliance/src/cells/src/sxlib/Makefile.liban b/alliance/src/cells/src/sxlib/Makefile.liban new file mode 100644 index 00000000..4cc01da1 --- /dev/null +++ b/alliance/src/cells/src/sxlib/Makefile.liban @@ -0,0 +1,2 @@ +sxlib.log : sxlib.db sxlib.sdb + liban -arch FTGS sxlib.db > sxlib.log diff --git a/alliance/src/cells/src/sxlib/a2_x2.al b/alliance/src/cells/src/sxlib/a2_x2.al new file mode 100644 index 00000000..56135369 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a2_x2.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H a2_x2,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,1,2,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,2.9,5,6,2,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00005 +T P,0.35,2.9,2,7,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00004 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00003 +T N,0.35,2.9,4,2,1,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00002 +T N,0.35,2.9,3,6,4,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00001 +S 7,EXTERNAL,i0 +Q 0.00214738 +S 6,EXTERNAL,i1 +Q 0.00400776 +S 5,EXTERNAL,vdd +Q 0.00374949 +S 4,EXTERNAL,vss +Q 0.00298567 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00463918 +S 1,EXTERNAL,q +Q 0.00258522 +EOF diff --git a/alliance/src/cells/src/sxlib/a2_x2.ap b/alliance/src/cells/src/sxlib/a2_x2.ap new file mode 100644 index 00000000..fa59a07f --- /dev/null +++ b/alliance/src/cells/src/sxlib/a2_x2.ap @@ -0,0 +1,73 @@ +V ALLIANCE : 6 +H a2_x2,P,30/ 8/2000,100 +A 0,0,2500,5000 +R 2000,2000,ref_ref,q_20 +R 2000,1500,ref_ref,q_15 +R 2000,1000,ref_ref,q_10 +R 2000,4000,ref_ref,q_40 +R 2000,3500,ref_ref,q_35 +R 2000,3000,ref_ref,q_30 +R 2000,2500,ref_ref,q_25 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 1500,1000,ref_ref,i1_10 +R 1500,1500,ref_ref,i1_15 +R 1500,2000,ref_ref,i1_20 +R 1500,2500,ref_ref,i1_25 +R 1500,3000,ref_ref,i1_30 +R 1500,3500,ref_ref,i1_35 +R 1500,4000,ref_ref,i1_40 +S 2000,1000,2000,4000,200,*,DOWN,ALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +S 300,1000,950,1000,100,*,RIGHT,ALU1 +S 950,1000,950,4000,100,*,DOWN,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1200,2400,1200,3100,100,*,DOWN,POLY +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,1000,1500,4000,100,*,DOWN,ALU1 +S 1800,1400,1800,2600,100,*,UP,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 0,300,2500,300,600,vss,RIGHT,ALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,ALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 1000,2000,1800,2000,100,*,RIGHT,POLY +S 600,600,600,1900,100,*,DOWN,NTRANS +S 300,800,300,1700,300,*,UP,NDIF +S 900,300,900,1700,300,*,UP,NDIF +S 2000,1000,2000,4000,200,q,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1500,1000,1500,4000,200,i1,DOWN,CALU1 +V 300,4000,CONT_DIF_P,* +V 500,3000,CONT_POLY,* +V 1500,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1400,1500,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 900,4700,CONT_BODY_N,* +V 2100,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1000,2000,CONT_POLY,* +V 1400,2500,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 300,300,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/a2_x2.sym b/alliance/src/cells/src/sxlib/a2_x2.sym new file mode 100644 index 00000000..4ef52f4a Binary files /dev/null and b/alliance/src/cells/src/sxlib/a2_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/a2_x2.vbe b/alliance/src/cells/src/sxlib/a2_x2.vbe new file mode 100644 index 00000000..8e6db7cd --- /dev/null +++ b/alliance/src/cells/src/sxlib/a2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i1_q : NATURAL := 203; + CONSTANT tphh_i0_q : NATURAL := 261; + CONSTANT tpll_i0_q : NATURAL := 388; + CONSTANT tpll_i1_q : NATURAL := 434; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x2; + +ARCHITECTURE behaviour_data_flow OF a2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x2" + SEVERITY WARNING; + q <= (i0 and i1) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/a2_x2.vhd b/alliance/src/cells/src/sxlib/a2_x2.vhd new file mode 100644 index 00000000..9c04bc77 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a2_x2.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a2_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a2_x2; + +ARCHITECTURE RTL OF a2_x2 IS +BEGIN + q <= (i0 AND i1); +END RTL; diff --git a/alliance/src/cells/src/sxlib/a2_x4.al b/alliance/src/cells/src/sxlib/a2_x4.al new file mode 100644 index 00000000..70f58873 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a2_x4.al @@ -0,0 +1,30 @@ +V ALLIANCE : 6 +H a2_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,4,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00008 +T P,0.35,5.9,5,4,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00007 +T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00006 +T P,0.35,2.9,4,7,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00005 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,3,6,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 7,EXTERNAL,i0 +Q 0.00214738 +S 6,EXTERNAL,i1 +Q 0.00400776 +S 5,EXTERNAL,vdd +Q 0.00579486 +S 4,INTERNAL +Q 0.00596944 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,q +Q 0.00258522 +S 1,EXTERNAL,vss +Q 0.00450225 +EOF diff --git a/alliance/src/cells/src/sxlib/a2_x4.ap b/alliance/src/cells/src/sxlib/a2_x4.ap new file mode 100644 index 00000000..80b16acc --- /dev/null +++ b/alliance/src/cells/src/sxlib/a2_x4.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 6 +H a2_x4,P,30/ 8/2000,100 +A 0,0,3000,5000 +R 2000,2000,ref_ref,q_20 +R 2000,1500,ref_ref,q_15 +R 2000,1000,ref_ref,q_10 +R 2000,4000,ref_ref,q_40 +R 2000,3500,ref_ref,q_35 +R 2000,3000,ref_ref,q_30 +R 2000,2500,ref_ref,q_25 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 1500,1000,ref_ref,i1_10 +R 1500,1500,ref_ref,i1_15 +R 1500,2000,ref_ref,i1_20 +R 1500,2500,ref_ref,i1_25 +R 1500,3000,ref_ref,i1_30 +R 1500,3500,ref_ref,i1_35 +R 1500,4000,ref_ref,i1_40 +S 2000,1000,2000,4000,200,*,DOWN,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1200,2400,1200,3100,100,*,DOWN,POLY +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 2700,500,2700,1700,200,*,DOWN,ALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,1000,1500,4000,100,*,DOWN,ALU1 +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 1800,1400,1800,2600,100,*,UP,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 2700,3000,2700,4500,200,*,DOWN,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 950,1000,950,4000,100,*,DOWN,ALU1 +S 300,1000,950,1000,100,*,RIGHT,ALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +S 2000,1000,2000,4000,200,q,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1500,1000,1500,4000,200,i1,DOWN,CALU1 +V 500,3000,CONT_POLY,* +V 2700,1700,CONT_BODY_P,* +V 2700,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1400,1500,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 900,4700,CONT_BODY_N,* +V 2100,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1000,2000,CONT_POLY,* +V 1400,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/a2_x4.sym b/alliance/src/cells/src/sxlib/a2_x4.sym new file mode 100644 index 00000000..db1efc87 Binary files /dev/null and b/alliance/src/cells/src/sxlib/a2_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/a2_x4.vbe b/alliance/src/cells/src/sxlib/a2_x4.vbe new file mode 100644 index 00000000..f6955d6e --- /dev/null +++ b/alliance/src/cells/src/sxlib/a2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphh_i0_q : NATURAL := 338; + CONSTANT tpll_i0_q : NATURAL := 476; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x4; + +ARCHITECTURE behaviour_data_flow OF a2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x4" + SEVERITY WARNING; + q <= (i0 and i1) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/a2_x4.vhd b/alliance/src/cells/src/sxlib/a2_x4.vhd new file mode 100644 index 00000000..577cea82 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a2_x4; + +ARCHITECTURE RTL OF a2_x4 IS +BEGIN + q <= (i0 AND i1); +END RTL; diff --git a/alliance/src/cells/src/sxlib/a3_x2.al b/alliance/src/cells/src/sxlib/a3_x2.al new file mode 100644 index 00000000..87820e7b --- /dev/null +++ b/alliance/src/cells/src/sxlib/a3_x2.al @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H a3_x2,L,30/10/99 +C i0,IN,EXTERNAL,9 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,5 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,4 +T P,0.35,2.9,3,8,6,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,2.9,6,9,3,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T P,0.35,5.9,5,3,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00006 +T P,0.35,2.9,6,7,3,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00005 +T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00004 +T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,3,3.75,tr_00003 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,4.2,3.75,tr_00002 +T N,0.35,2.9,4,3,5,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00001 +S 9,EXTERNAL,i0 +Q 0.00260759 +S 8,EXTERNAL,i1 +Q 0.00282737 +S 7,EXTERNAL,i2 +Q 0.00304715 +S 6,EXTERNAL,vdd +Q 0.00350341 +S 5,EXTERNAL,q +Q 0.00364281 +S 4,EXTERNAL,vss +Q 0.00332715 +S 3,INTERNAL +Q 0.00629467 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/a3_x2.ap b/alliance/src/cells/src/sxlib/a3_x2.ap new file mode 100644 index 00000000..f29b2379 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a3_x2.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H a3_x2,P, 6/ 9/2000,100 +A 0,0,3000,5000 +R 1500,2500,ref_ref,i2_25 +R 1500,2000,ref_ref,i2_20 +R 1500,1500,ref_ref,i2_15 +R 500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 2500,2000,ref_ref,q_20 +R 2500,2500,ref_ref,q_25 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +R 2500,1500,ref_ref,q_15 +R 2500,1000,ref_ref,q_10 +S 1900,2000,2400,2000,300,*,RIGHT,POLY +S 300,300,1100,300,300,*,RIGHT,PTIE +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +S 2500,3500,2700,3500,200,*,LEFT,ALU1 +S 1800,2600,1800,3100,100,*,UP,POLY +S 1400,1900,1400,2600,100,*,UP,POLY +S 1400,2600,1800,2600,100,*,RIGHT,POLY +S 1500,1500,1500,3500,100,*,DOWN,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 300,800,300,1700,300,*,UP,NDIF +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 1000,1900,1000,3100,100,*,UP,POLY +S 600,1900,600,3100,100,*,UP,POLY +S 1000,3100,1200,3100,100,*,LEFT,POLY +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1000,1500,1000,3500,100,*,DOWN,ALU1 +S 300,4000,2000,4000,100,*,RIGHT,ALU1 +S 2100,2800,2100,4700,300,*,UP,PDIF +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2400,1400,2400,2600,100,*,UP,POLY +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 2450,4000,2700,4000,200,*,LEFT,ALU1 +S 2450,1000,2700,1000,200,*,LEFT,ALU1 +S 1500,1500,1500,3500,200,i2,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 2000,300,2000,1200,400,*,UP,NDIF +S 1700,300,1700,1700,300,*,UP,NDIF +V 1500,4700,CONT_BODY_N,* +V 1100,300,CONT_BODY_P,* +V 700,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 2000,2000,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 1000,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 2700,3000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,1000,CONT_DIF_N,* +V 2100,4500,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 1700,500,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/a3_x2.sym b/alliance/src/cells/src/sxlib/a3_x2.sym new file mode 100644 index 00000000..64f0ad54 Binary files /dev/null and b/alliance/src/cells/src/sxlib/a3_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/a3_x2.vbe b/alliance/src/cells/src/sxlib/a3_x2.vbe new file mode 100644 index 00000000..7a7b521b --- /dev/null +++ b/alliance/src/cells/src/sxlib/a3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 290; + CONSTANT tphh_i1_q : NATURAL := 353; + CONSTANT tphh_i0_q : NATURAL := 395; + CONSTANT tpll_i0_q : NATURAL := 435; + CONSTANT tpll_i1_q : NATURAL := 479; + CONSTANT tpll_i2_q : NATURAL := 521; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x2; + +ARCHITECTURE behaviour_data_flow OF a3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x2" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/a3_x2.vhd b/alliance/src/cells/src/sxlib/a3_x2.vhd new file mode 100644 index 00000000..08ae6662 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a3_x2.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a3_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a3_x2; + +ARCHITECTURE RTL OF a3_x2 IS +BEGIN + q <= ((i0 AND i1) AND i2); +END RTL; diff --git a/alliance/src/cells/src/sxlib/a3_x4.al b/alliance/src/cells/src/sxlib/a3_x4.al new file mode 100644 index 00000000..a0b7376e --- /dev/null +++ b/alliance/src/cells/src/sxlib/a3_x4.al @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H a3_x4,L,30/10/99 +C i0,IN,EXTERNAL,9 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,6,4,3,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00010 +T P,0.35,5.9,3,4,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009 +T P,0.35,2.9,6,7,4,0,0.75,0.75,7.3,7.3,5.4,10.65,tr_00008 +T P,0.35,2.9,4,8,6,0,0.75,0.75,7.3,7.3,3.6,10.65,tr_00007 +T P,0.35,2.9,6,9,4,0,0.75,0.75,7.3,7.3,1.8,10.65,tr_00006 +T N,0.35,2.9,4,9,5,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00005 +T N,0.35,2.9,3,4,2,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00004 +T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00003 +T N,0.35,2.9,5,8,1,0,0.75,0.75,7.3,7.3,3,2.25,tr_00002 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,4.2,2.25,tr_00001 +S 9,EXTERNAL,i0 +Q 0.0028158 +S 8,EXTERNAL,i1 +Q 0.00331294 +S 7,EXTERNAL,i2 +Q 0.00325537 +S 6,EXTERNAL,vdd +Q 0.00554878 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00773401 +S 3,EXTERNAL,q +Q 0.00264397 +S 2,EXTERNAL,vss +Q 0.00484372 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/a3_x4.ap b/alliance/src/cells/src/sxlib/a3_x4.ap new file mode 100644 index 00000000..2f1c1791 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a3_x4.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 6 +H a3_x4,P,30/ 8/2000,100 +A 0,0,3500,5000 +R 2500,1500,ref_ref,q_15 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1500,2500,ref_ref,i2_25 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 2500,4000,ref_ref,q_40 +R 2500,3500,ref_ref,q_35 +R 2500,3000,ref_ref,q_30 +R 2500,2500,ref_ref,q_25 +R 2500,2000,ref_ref,q_20 +R 2500,1000,ref_ref,q_10 +S 2000,4500,2000,4700,300,*,UP,PDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 3200,300,3200,1200,300,*,UP,NDIF +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 2600,300,2600,1200,300,*,UP,NDIF +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 2900,1400,2900,2600,100,*,UP,POLY +S 2300,1400,2300,2600,100,*,UP,POLY +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1000,1500,1000,3500,100,*,DOWN,ALU1 +S 1500,1500,1500,3500,100,*,DOWN,ALU1 +S 1800,2900,1800,4200,100,*,UP,PTRANS +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,4000,2000,4000,100,*,RIGHT,ALU1 +S 1000,2500,1200,2500,300,*,RIGHT,POLY +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1000,1400,1000,2600,100,*,UP,POLY +S 1400,1400,1400,2100,100,*,UP,POLY +S 1600,2900,1800,2900,100,*,RIGHT,POLY +S 1600,1900,1600,2900,100,*,DOWN,POLY +S 1900,2000,2900,2000,300,*,RIGHT,POLY +S 2100,2800,2100,4700,300,*,UP,PDIF +S 300,3100,300,4000,300,*,DOWN,PDIF +S 1200,2900,1200,4200,100,*,UP,PTRANS +S 600,2900,600,4200,100,*,UP,PTRANS +S 1500,3100,1500,4000,300,*,DOWN,PDIF +S 900,3100,900,4600,300,*,DOWN,PDIF +S 1900,300,1900,1200,300,*,UP,NDIF +S 1700,300,1700,1200,300,*,UP,NDIF +S 3200,3000,3200,4500,200,*,DOWN,ALU1 +S 3200,500,3200,1700,200,*,DOWN,ALU1 +S 1200,2400,1200,2900,100,*,DOWN,POLY +S 600,1400,600,2900,100,*,UP,POLY +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i2,DOWN,CALU1 +V 2000,4600,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 3200,500,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2000,500,CONT_DIF_N,* +V 2600,1000,CONT_DIF_N,* +V 2600,3000,CONT_DIF_P,* +V 2600,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3200,4500,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 3200,1700,CONT_BODY_P,* +V 900,4500,CONT_DIF_P,* +V 1000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/a3_x4.sym b/alliance/src/cells/src/sxlib/a3_x4.sym new file mode 100644 index 00000000..3f536421 Binary files /dev/null and b/alliance/src/cells/src/sxlib/a3_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/a3_x4.vbe b/alliance/src/cells/src/sxlib/a3_x4.vbe new file mode 100644 index 00000000..556b6b0f --- /dev/null +++ b/alliance/src/cells/src/sxlib/a3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 356; + CONSTANT tphh_i1_q : NATURAL := 428; + CONSTANT tphh_i0_q : NATURAL := 478; + CONSTANT tpll_i0_q : NATURAL := 514; + CONSTANT tpll_i1_q : NATURAL := 554; + CONSTANT tpll_i2_q : NATURAL := 592; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x4; + +ARCHITECTURE behaviour_data_flow OF a3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x4" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/a3_x4.vhd b/alliance/src/cells/src/sxlib/a3_x4.vhd new file mode 100644 index 00000000..751f7ee5 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a3_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a3_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a3_x4; + +ARCHITECTURE RTL OF a3_x4 IS +BEGIN + q <= ((i0 AND i1) AND i2); +END RTL; diff --git a/alliance/src/cells/src/sxlib/a4_x2.al b/alliance/src/cells/src/sxlib/a4_x2.al new file mode 100644 index 00000000..bd8536a8 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a4_x2.al @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H a4_x2,L,30/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,11,1,6,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00010 +T P,0.35,2.9,1,10,6,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009 +T P,0.35,2.9,6,9,1,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,2.9,1,8,6,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00007 +T P,0.35,2.9,6,7,1,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00006 +T N,0.35,2.9,4,8,5,0,0.75,0.75,7.3,7.3,4.2,3.75,tr_00005 +T N,0.35,2.9,2,10,3,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00004 +T N,0.35,2.9,5,7,1,0,0.75,0.75,7.3,7.3,5.4,3.75,tr_00003 +T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,3,3.75,tr_00002 +T N,0.35,2.9,2,1,11,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00001 +S 11,EXTERNAL,q +Q 0.00364281 +S 10,EXTERNAL,i0 +Q 0.00288944 +S 9,EXTERNAL,i1 +Q 0.00310922 +S 8,EXTERNAL,i2 +Q 0.00332901 +S 7,EXTERNAL,i3 +Q 0.00318596 +S 6,EXTERNAL,vdd +Q 0.0046087 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.00402115 +S 1,INTERNAL +Q 0.00564944 +EOF diff --git a/alliance/src/cells/src/sxlib/a4_x2.ap b/alliance/src/cells/src/sxlib/a4_x2.ap new file mode 100644 index 00000000..cecffc5a --- /dev/null +++ b/alliance/src/cells/src/sxlib/a4_x2.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H a4_x2,P,30/ 8/2000,100 +A 0,0,3500,5000 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 1500,2500,ref_ref,i2_25 +R 1000,3000,ref_ref,i1_30 +R 2000,1500,ref_ref,i3_15 +R 2000,2000,ref_ref,i3_20 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2000,3500,ref_ref,i3_35 +R 1500,3500,ref_ref,i2_35 +R 1500,3000,ref_ref,i2_30 +R 1000,3500,ref_ref,i1_35 +R 1500,2000,ref_ref,i2_20 +R 1500,1500,ref_ref,i2_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 3000,3000,ref_ref,q_30 +R 3000,2500,ref_ref,q_25 +R 3000,2000,ref_ref,q_20 +R 3000,1500,ref_ref,q_15 +R 3000,1000,ref_ref,q_10 +R 500,1000,ref_ref,i0_10 +R 1000,1000,ref_ref,i1_10 +R 1500,1000,ref_ref,i2_10 +S 300,4000,300,4500,200,*,UP,ALU1 +S 2950,4000,3200,4000,200,*,RIGHT,ALU1 +S 2950,1000,3200,1000,200,*,LEFT,ALU1 +S 3000,950,3000,4050,200,*,DOWN,ALU1 +S 900,4000,2550,4000,100,*,RIGHT,ALU1 +S 2100,1000,2550,1000,100,*,RIGHT,ALU1 +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 900,3300,900,4200,300,*,DOWN,PDIF +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1500,3300,1500,4600,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 1600,3100,1800,3100,100,*,RIGHT,POLY +S 2100,3100,2400,3100,100,*,LEFT,POLY +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 2900,1400,2900,2600,100,*,UP,POLY +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2400,2500,2900,2500,300,*,RIGHT,POLY +S 3200,300,3200,1200,300,*,UP,NDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 1800,1900,2100,1900,100,*,RIGHT,POLY +S 1600,2400,1600,3100,100,*,UP,POLY +S 2100,1900,2100,3100,100,*,DOWN,POLY +S 1400,1900,1400,2600,100,*,UP,POLY +S 1000,1900,1000,3100,100,*,UP,POLY +S 600,1900,600,3100,100,*,DOWN,POLY +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 1800,600,1800,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 300,400,300,1700,300,*,UP,NDIF +S 2000,800,2000,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 3000,3500,3200,3500,200,*,RIGHT,ALU1 +S 3000,3000,3200,3000,200,*,RIGHT,ALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 2000,1500,2000,3500,200,i3,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +V 300,4000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 900,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 1000,2500,CONT_POLY,* +V 2600,4700,CONT_DIF_P,* +V 2500,2500,CONT_POLY,* +V 3200,4000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 2600,400,CONT_DIF_N,* +V 2000,2000,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 1000,300,CONT_BODY_P,* +V 1800,300,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/a4_x2.sym b/alliance/src/cells/src/sxlib/a4_x2.sym new file mode 100644 index 00000000..716d5421 Binary files /dev/null and b/alliance/src/cells/src/sxlib/a4_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/a4_x2.vbe b/alliance/src/cells/src/sxlib/a4_x2.vbe new file mode 100644 index 00000000..3a635396 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 374; + CONSTANT tphh_i1_q : NATURAL := 441; + CONSTANT tpll_i3_q : NATURAL := 455; + CONSTANT tphh_i2_q : NATURAL := 482; + CONSTANT tpll_i2_q : NATURAL := 498; + CONSTANT tphh_i3_q : NATURAL := 506; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x2; + +ARCHITECTURE behaviour_data_flow OF a4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/a4_x2.vhd b/alliance/src/cells/src/sxlib/a4_x2.vhd new file mode 100644 index 00000000..5819d66a --- /dev/null +++ b/alliance/src/cells/src/sxlib/a4_x2.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a4_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a4_x2; + +ARCHITECTURE RTL OF a4_x2 IS +BEGIN + q <= (((i0 AND i1) AND i2) AND i3); +END RTL; diff --git a/alliance/src/cells/src/sxlib/a4_x4.al b/alliance/src/cells/src/sxlib/a4_x4.al new file mode 100644 index 00000000..7ce75993 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a4_x4.al @@ -0,0 +1,45 @@ +V ALLIANCE : 6 +H a4_x4,L,30/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,5 +T P,0.35,5.9,11,3,6,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00013 +T P,0.35,5.9,11,3,6,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00012 +T P,0.35,2.9,6,7,3,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00011 +T P,0.35,2.9,3,8,6,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010 +T P,0.35,2.9,6,9,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00009 +T P,0.35,2.9,3,10,6,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00008 +T N,0.35,2.9,11,3,5,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00007 +T N,0.35,2.9,11,3,5,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00006 +T N,0.35,2.9,5,3,11,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00005 +T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,3,3.75,tr_00004 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,5.4,3.75,tr_00003 +T N,0.35,2.9,5,10,1,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00002 +T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,4.2,3.75,tr_00001 +S 11,EXTERNAL,q +Q 0.00264397 +S 10,EXTERNAL,i0 +Q 0.00288944 +S 9,EXTERNAL,i1 +Q 0.00310922 +S 8,EXTERNAL,i2 +Q 0.00332901 +S 7,EXTERNAL,i3 +Q 0.00318597 +S 6,EXTERNAL,vdd +Q 0.00665407 +S 5,EXTERNAL,vss +Q 0.00571399 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.0070012 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/a4_x4.ap b/alliance/src/cells/src/sxlib/a4_x4.ap new file mode 100644 index 00000000..08860dfc --- /dev/null +++ b/alliance/src/cells/src/sxlib/a4_x4.ap @@ -0,0 +1,116 @@ +V ALLIANCE : 6 +H a4_x4,P,30/ 8/2000,100 +A 0,0,4000,5000 +R 1500,1000,ref_ref,i2_10 +R 1000,1000,ref_ref,i1_10 +R 500,1000,ref_ref,i0_10 +R 3000,1000,ref_ref,q_10 +R 3000,1500,ref_ref,q_15 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1000,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 2000,3500,ref_ref,i3_35 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 1000,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i2_25 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 2000,1500,2000,3500,200,i3,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +S 3000,950,3000,4050,200,*,DOWN,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 2000,900,2000,1700,300,*,UP,NDIF +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 900,4000,2550,4000,100,*,RIGHT,ALU1 +S 2100,1000,2550,1000,100,*,RIGHT,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 300,400,300,1700,300,*,UP,NDIF +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1800,600,1800,1900,100,*,DOWN,NTRANS +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 600,1900,600,3100,100,*,DOWN,POLY +S 1000,1900,1000,3100,100,*,UP,POLY +S 1400,1900,1400,2600,100,*,UP,POLY +S 2100,1900,2100,3100,100,*,DOWN,POLY +S 1600,2400,1600,3100,100,*,UP,POLY +S 1800,1900,2100,1900,100,*,RIGHT,POLY +S 3200,300,3200,1200,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 900,3300,900,4200,300,*,DOWN,PDIF +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 2800,1400,2800,2600,100,*,UP,POLY +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 3400,2600,3400,4900,100,*,DOWN,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 3700,3000,3700,4500,200,*,UP,ALU1 +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2400,2500,3400,2500,300,*,RIGHT,POLY +S 3700,500,3700,1700,200,*,DOWN,ALU1 +S 1450,3300,1450,4600,200,*,DOWN,PDIF +S 1700,3100,1700,4400,100,*,UP,PTRANS +S 2300,3100,2300,4400,100,*,UP,PTRANS +S 2100,3100,2300,3100,100,*,LEFT,POLY +S 1600,3100,1700,3100,100,*,RIGHT,POLY +S 2550,2800,2550,4700,200,*,DOWN,PDIF +V 300,4000,CONT_DIF_P,* +V 1800,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 1500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 2500,2500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 2500,400,CONT_DIF_N,* +V 3100,1000,CONT_DIF_N,* +V 3100,4000,CONT_DIF_P,* +V 3100,3000,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 2500,4700,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 3700,500,CONT_DIF_N,* +V 3700,4500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 3700,1700,CONT_BODY_P,* +V 1500,4700,CONT_DIF_P,* +V 2000,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/a4_x4.sym b/alliance/src/cells/src/sxlib/a4_x4.sym new file mode 100644 index 00000000..d6f59e2b Binary files /dev/null and b/alliance/src/cells/src/sxlib/a4_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/a4_x4.vbe b/alliance/src/cells/src/sxlib/a4_x4.vbe new file mode 100644 index 00000000..4f96afa4 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 540; + CONSTANT rdown_i1_q : NATURAL := 540; + CONSTANT rdown_i2_q : NATURAL := 540; + CONSTANT rdown_i3_q : NATURAL := 540; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 505; + CONSTANT tpll_i3_q : NATURAL := 538; + CONSTANT tpll_i2_q : NATURAL := 576; + CONSTANT tphh_i1_q : NATURAL := 578; + CONSTANT tpll_i1_q : NATURAL := 614; + CONSTANT tphh_i2_q : NATURAL := 627; + CONSTANT tpll_i0_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 661; + CONSTANT transistors : NATURAL := 13 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x4; + +ARCHITECTURE behaviour_data_flow OF a4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/a4_x4.vhd b/alliance/src/cells/src/sxlib/a4_x4.vhd new file mode 100644 index 00000000..93ffcf82 --- /dev/null +++ b/alliance/src/cells/src/sxlib/a4_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a4_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a4_x4; + +ARCHITECTURE RTL OF a4_x4 IS +BEGIN + q <= (((i0 AND i1) AND i2) AND i3); +END RTL; diff --git a/alliance/src/cells/src/sxlib/an12_x1.al b/alliance/src/cells/src/sxlib/an12_x1.al new file mode 100644 index 00000000..fd469213 --- /dev/null +++ b/alliance/src/cells/src/sxlib/an12_x1.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H an12_x1,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,4,7,1,0,0.75,0.75,13.3,13.3,2.7,11.25,tr_00006 +T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00005 +T P,0.35,2.9,3,6,5,0,0.75,0.75,7.3,7.3,5.7,9.75,tr_00004 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00003 +T N,0.35,1.4,1,3,2,0,0.75,0.75,4.3,4.3,3.9,3,tr_00002 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,5.7,3,tr_00001 +S 7,EXTERNAL,i0 +Q 0.00319019 +S 6,EXTERNAL,i1 +Q 0.00362068 +S 5,EXTERNAL,vdd +Q 0.00298567 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00417012 +S 2,EXTERNAL,vss +Q 0.00351447 +S 1,EXTERNAL,q +Q 0.00384845 +EOF diff --git a/alliance/src/cells/src/sxlib/an12_x1.ap b/alliance/src/cells/src/sxlib/an12_x1.ap new file mode 100644 index 00000000..c77449fb --- /dev/null +++ b/alliance/src/cells/src/sxlib/an12_x1.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 6 +H an12_x1,P, 6/ 9/2000,100 +A 0,0,2500,5000 +R 1500,1000,ref_ref,i1_10 +R 500,1000,ref_ref,q_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2500,ref_ref,i0_25 +R 500,4000,ref_ref,q_40 +R 500,3500,ref_ref,q_35 +R 1500,2500,ref_ref,i1_25 +R 1500,3000,ref_ref,i1_30 +R 1500,3500,ref_ref,i1_35 +R 1500,4000,ref_ref,i1_40 +R 500,3000,ref_ref,q_30 +R 500,2500,ref_ref,q_25 +R 500,1500,ref_ref,q_15 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1500,1500,ref_ref,i1_15 +R 1500,2000,ref_ref,i1_20 +S 700,2000,900,2000,300,*,LEFT,POLY +S 1700,1500,1900,1500,300,*,RIGHT,POLY +S 1700,2500,1900,2500,300,*,RIGHT,POLY +S 500,1000,500,1550,200,*,DOWN,ALU1 +S 250,2500,400,2500,200,*,LEFT,ALU1 +S 250,1500,500,1500,200,*,RIGHT,ALU1 +S 300,1450,300,2550,200,*,DOWN,ALU1 +S 900,2000,900,2600,100,*,UP,POLY +S 700,2000,900,2000,100,*,RIGHT,POLY +S 700,1400,700,2000,100,*,UP,POLY +S 1900,2400,1900,2600,100,*,UP,POLY +S 1900,1400,1900,1600,100,*,UP,POLY +S 1500,1500,1700,1500,200,*,LEFT,ALU1 +S 1500,2500,1700,2500,200,*,LEFT,ALU1 +S 2200,1000,2200,3500,100,*,UP,ALU1 +S 1300,2000,2200,2000,100,*,RIGHT,POLY +S 2200,2800,2200,3700,300,*,UP,PDIF +S 2200,800,2200,1200,300,*,DOWN,NDIF +S 1300,2050,1300,2600,100,*,DOWN,POLY +S 400,2800,400,4200,300,*,DOWN,PDIF +S 1900,2600,1900,3900,100,*,UP,PTRANS +S 600,2800,600,4200,300,*,DOWN,PDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,UP,PDIF +S 900,2600,900,4900,100,*,UP,PTRANS +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1600,400,1600,1200,300,*,UP,NDIF +S 400,400,400,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 1300,1400,1300,2000,100,*,UP,POLY +S 450,1000,1000,1000,200,*,LEFT,ALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 1500,1000,1500,4000,200,i1,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 500,2500,500,4000,200,q,DOWN,CALU1 +S 500,1000,500,1500,200,q,DOWN,CALU1 +S 500,2450,500,4000,200,*,DOWN,ALU1 +V 900,2000,CONT_POLY,* +V 1000,300,CONT_BODY_P,* +V 2200,300,CONT_BODY_P,* +V 1700,1500,CONT_POLY,* +V 1700,2500,CONT_POLY,* +V 2200,2000,CONT_POLY,* +V 2200,1000,CONT_DIF_N,* +V 2200,3500,CONT_DIF_P,* +V 2200,4700,CONT_BODY_N,* +V 400,4000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 2200,3000,CONT_DIF_P,* +V 1600,500,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/an12_x1.sym b/alliance/src/cells/src/sxlib/an12_x1.sym new file mode 100644 index 00000000..eafa148f Binary files /dev/null and b/alliance/src/cells/src/sxlib/an12_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/an12_x1.vbe b/alliance/src/cells/src/sxlib/an12_x1.vbe new file mode 100644 index 00000000..10267b44 --- /dev/null +++ b/alliance/src/cells/src/sxlib/an12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 3640; + CONSTANT rdown_i1_q : NATURAL := 3640; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i0_q : NATURAL := 168; + CONSTANT tphl_i0_q : NATURAL := 200; + CONSTANT tphh_i1_q : NATURAL := 285; + CONSTANT tpll_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x1; + +ARCHITECTURE behaviour_data_flow OF an12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x1" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/an12_x1.vhd b/alliance/src/cells/src/sxlib/an12_x1.vhd new file mode 100644 index 00000000..6779ed37 --- /dev/null +++ b/alliance/src/cells/src/sxlib/an12_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY an12_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END an12_x1; + +ARCHITECTURE RTL OF an12_x1 IS +BEGIN + q <= (NOT(i0) AND i1); +END RTL; diff --git a/alliance/src/cells/src/sxlib/an12_x4.al b/alliance/src/cells/src/sxlib/an12_x4.al new file mode 100644 index 00000000..95b23dae --- /dev/null +++ b/alliance/src/cells/src/sxlib/an12_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H an12_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010 +T P,0.35,2.9,1,4,5,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00009 +T P,0.35,5.9,8,1,5,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00008 +T P,0.35,5.9,5,1,8,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00007 +T P,0.35,2.9,5,7,1,0,0.75,0.75,7.3,7.3,6.6,11.25,tr_00006 +T N,0.35,1.4,3,6,4,0,0.75,0.75,4.3,4.3,1.8,2.1,tr_00005 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,3,1,8,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002 +T N,0.35,2.9,8,1,3,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00001 +S 8,EXTERNAL,q +Q 0.00258522 +S 7,EXTERNAL,i1 +Q 0.00400776 +S 6,EXTERNAL,i0 +Q 0.00372902 +S 5,EXTERNAL,vdd +Q 0.00606652 +S 4,INTERNAL +Q 0.00525013 +S 3,EXTERNAL,vss +Q 0.00536146 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00603296 +EOF diff --git a/alliance/src/cells/src/sxlib/an12_x4.ap b/alliance/src/cells/src/sxlib/an12_x4.ap new file mode 100644 index 00000000..eaf81a9e --- /dev/null +++ b/alliance/src/cells/src/sxlib/an12_x4.ap @@ -0,0 +1,103 @@ +V ALLIANCE : 6 +H an12_x4,P,30/ 8/2000,100 +A 0,0,4000,5000 +R 2500,1500,ref_ref,i1_15 +R 2500,2000,ref_ref,i1_20 +R 2500,2500,ref_ref,i1_25 +R 2500,3000,ref_ref,i1_30 +R 2500,3500,ref_ref,i1_35 +R 2500,4000,ref_ref,i1_40 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 3000,3000,ref_ref,q_30 +R 3000,2500,ref_ref,q_25 +R 3000,2000,ref_ref,q_20 +R 3000,1500,ref_ref,q_15 +R 3000,1000,ref_ref,q_10 +R 2500,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i0_15 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,1000,ref_ref,i0_10 +R 1000,4000,ref_ref,i0_40 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3700,3000,3700,4500,200,*,DOWN,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 3700,500,3700,1700,200,*,DOWN,ALU1 +S 2500,1000,2500,4000,100,*,DOWN,ALU1 +S 1950,1000,1950,4000,100,*,DOWN,ALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 2000,2000,3400,2000,100,*,RIGHT,POLY +S 2800,1400,2800,2600,100,*,UP,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2200,2400,2200,3100,100,*,DOWN,POLY +S 3700,300,3700,1200,300,*,UP,NDIF +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 3100,300,3100,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 2200,100,2200,1400,100,*,DOWN,NTRANS +S 2200,3100,2200,4400,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,DOWN,PDIF +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 3700,2800,3700,4700,300,*,DOWN,PDIF +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 1900,3300,1900,4200,300,*,DOWN,PDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1600,3100,1600,4400,100,*,UP,PTRANS +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,1000,1950,1000,100,*,RIGHT,ALU1 +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 600,300,600,1100,100,*,UP,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1100,3300,1100,4600,700,*,DOWN,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,2500,1600,2500,100,*,RIGHT,POLY +S 1600,1400,1600,3100,100,*,DOWN,POLY +S 1600,1400,1800,1400,100,*,RIGHT,POLY +S 600,3100,1000,3100,100,*,RIGHT,POLY +S 1000,3000,1000,3100,100,*,DOWN,POLY +S 600,1100,1000,1100,100,*,RIGHT,POLY +S 1000,1100,1000,1200,100,*,UP,POLY +S 2500,1000,2500,4000,200,i1,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +V 1900,3500,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 2400,2500,CONT_POLY,* +V 2400,1500,CONT_POLY,* +V 3700,1700,CONT_BODY_P,* +V 2500,500,CONT_DIF_N,* +V 3100,1000,CONT_DIF_N,* +V 3700,500,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 2500,4500,CONT_DIF_P,* +V 3700,4500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 1900,4000,CONT_DIF_P,* +V 1900,4700,CONT_BODY_N,* +V 3100,3000,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 3100,4000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 1300,4500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 300,2500,CONT_POLY,* +V 1000,1200,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/an12_x4.sym b/alliance/src/cells/src/sxlib/an12_x4.sym new file mode 100644 index 00000000..4b6274ce Binary files /dev/null and b/alliance/src/cells/src/sxlib/an12_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/an12_x4.vbe b/alliance/src/cells/src/sxlib/an12_x4.vbe new file mode 100644 index 00000000..0d030a6c --- /dev/null +++ b/alliance/src/cells/src/sxlib/an12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphl_i0_q : NATURAL := 461; + CONSTANT tplh_i0_q : NATURAL := 471; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x4; + +ARCHITECTURE behaviour_data_flow OF an12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x4" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/an12_x4.vhd b/alliance/src/cells/src/sxlib/an12_x4.vhd new file mode 100644 index 00000000..cc1252a1 --- /dev/null +++ b/alliance/src/cells/src/sxlib/an12_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY an12_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END an12_x4; + +ARCHITECTURE RTL OF an12_x4 IS +BEGIN + q <= (NOT(i0) AND i1); +END RTL; diff --git a/alliance/src/cells/src/sxlib/ao22_x2.al b/alliance/src/cells/src/sxlib/ao22_x2.al new file mode 100644 index 00000000..7a3497ad --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao22_x2.al @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H ao22_x2,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,6 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,9,6,2,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,2.9,5,8,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T P,0.35,2.9,2,7,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006 +T P,0.35,5.9,5,2,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005 +T N,0.35,2.9,4,2,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,1.4,1,7,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003 +T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002 +T N,0.35,1.4,2,8,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 9,INTERNAL +Q 0 +S 8,EXTERNAL,i0 +Q 0.00295462 +S 7,EXTERNAL,i2 +Q 0.00371745 +S 6,EXTERNAL,i1 +Q 0.00344928 +S 5,EXTERNAL,vdd +Q 0.00367968 +S 4,EXTERNAL,q +Q 0.00358405 +S 3,INTERNAL +Q 0.00114171 +S 2,INTERNAL +Q 0.00464422 +S 1,EXTERNAL,vss +Q 0.00367968 +EOF diff --git a/alliance/src/cells/src/sxlib/ao22_x2.ap b/alliance/src/cells/src/sxlib/ao22_x2.ap new file mode 100644 index 00000000..9b7b6482 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao22_x2.ap @@ -0,0 +1,97 @@ +V ALLIANCE : 6 +H ao22_x2,P,30/ 8/2000,100 +A 0,0,3000,5000 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 500,4000,ref_ref,i0_40 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 2000,4000,ref_ref,i2_40 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 2500,4000,ref_ref,q_40 +R 2500,3500,ref_ref,q_35 +R 2500,3000,ref_ref,q_30 +R 2500,2500,ref_ref,q_25 +R 2500,2000,ref_ref,q_20 +R 2500,1500,ref_ref,q_15 +R 2500,1000,ref_ref,q_10 +R 2000,1000,ref_ref,i2_10 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 2100,2800,2100,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 300,3300,300,4600,300,*,UP,PDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 1500,3300,1500,4200,300,*,UP,PDIF +S 2400,2600,2400,4900,100,*,DOWN,PTRANS +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 900,800,900,1600,300,*,DOWN,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 300,800,300,1200,300,*,DOWN,NDIF +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 600,600,600,1400,100,*,UP,NTRANS +S 1400,2100,2400,2100,100,*,RIGHT,POLY +S 1000,1800,1000,2100,300,*,UP,POLY +S 1800,2600,2100,2600,100,*,LEFT,POLY +S 1800,2600,1800,3100,100,*,DOWN,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 900,1800,1200,1800,100,*,RIGHT,POLY +S 1200,1400,1200,1800,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,UP,POLY +S 2400,1400,2400,2600,100,*,UP,POLY +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2500,3500,2700,3500,200,*,RIGHT,ALU1 +S 2500,4000,2700,4000,200,*,RIGHT,ALU1 +S 2500,1000,2700,1000,200,*,RIGHT,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 1000,2000,1000,4000,100,*,UP,ALU1 +S 300,1000,1500,1000,100,*,RIGHT,ALU1 +S 1500,1500,1500,4000,100,*,DOWN,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2500,3000,2700,3000,200,*,RIGHT,ALU1 +S 2500,950,2500,4050,200,*,DOWN,ALU1 +V 2700,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 2100,4500,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 900,1500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 1500,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 1500,2200,CONT_POLY,* +V 1000,3000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/ao22_x2.sym b/alliance/src/cells/src/sxlib/ao22_x2.sym new file mode 100644 index 00000000..ce180b7b Binary files /dev/null and b/alliance/src/cells/src/sxlib/ao22_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/ao22_x2.vbe b/alliance/src/cells/src/sxlib/ao22_x2.vbe new file mode 100644 index 00000000..7cfca61f --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 420; + CONSTANT tpll_i2_q : NATURAL := 425; + CONSTANT tpll_i0_q : NATURAL := 447; + CONSTANT tphh_i1_q : NATURAL := 493; + CONSTANT tpll_i1_q : NATURAL := 526; + CONSTANT tphh_i0_q : NATURAL := 558; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x2; + +ARCHITECTURE behaviour_data_flow OF ao22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/ao22_x2.vhd b/alliance/src/cells/src/sxlib/ao22_x2.vhd new file mode 100644 index 00000000..e0a0dd3e --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao22_x2.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ao22_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ao22_x2; + +ARCHITECTURE RTL OF ao22_x2 IS +BEGIN + q <= ((i0 OR i1) AND i2); +END RTL; diff --git a/alliance/src/cells/src/sxlib/ao22_x4.al b/alliance/src/cells/src/sxlib/ao22_x4.al new file mode 100644 index 00000000..97b82f3d --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao22_x4.al @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H ao22_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,2.9,3,6,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010 +T P,0.35,2.9,5,8,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009 +T P,0.35,2.9,9,7,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,8.1,11.25,tr_00007 +T P,0.35,5.9,4,3,5,0,0.75,0.75,13.3,13.3,9.9,11.25,tr_00006 +T N,0.35,1.4,3,8,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005 +T N,0.35,1.4,1,7,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004 +T N,0.35,1.4,2,6,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003 +T N,0.35,2.9,2,3,4,0,0.75,0.75,7.3,7.3,9.9,2.25,tr_00002 +T N,0.35,2.9,4,3,2,0,0.75,0.75,7.3,7.3,8.1,2.25,tr_00001 +S 9,INTERNAL +Q 0 +S 8,EXTERNAL,i0 +Q 0.00295461 +S 7,EXTERNAL,i1 +Q 0.00344928 +S 6,EXTERNAL,i2 +Q 0.00371745 +S 5,EXTERNAL,vdd +Q 0.00606652 +S 4,EXTERNAL,q +Q 0.00258522 +S 3,INTERNAL +Q 0.00618269 +S 2,EXTERNAL,vss +Q 0.00512644 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/alliance/src/cells/src/sxlib/ao22_x4.ap b/alliance/src/cells/src/sxlib/ao22_x4.ap new file mode 100644 index 00000000..d4d655f2 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao22_x4.ap @@ -0,0 +1,108 @@ +V ALLIANCE : 6 +H ao22_x4,P,30/ 8/2000,100 +A 0,0,4000,5000 +R 2000,1000,ref_ref,i2_10 +R 3000,1500,ref_ref,q_15 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 3000,1000,ref_ref,q_10 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 1500,1500,1500,4000,100,*,DOWN,ALU1 +S 300,1000,1500,1000,100,*,RIGHT,ALU1 +S 1000,2000,1000,4000,100,*,UP,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 3600,500,3600,1000,200,*,DOWN,ALU1 +S 3600,3000,3600,4500,200,*,UP,ALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 600,1400,600,3100,100,*,UP,POLY +S 1200,1400,1200,1800,100,*,DOWN,POLY +S 900,1800,1200,1800,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 1800,2600,1800,3100,100,*,DOWN,POLY +S 1800,2600,2100,2600,100,*,LEFT,POLY +S 2700,1400,2700,2600,100,*,UP,POLY +S 1400,2100,3300,2100,100,*,RIGHT,POLY +S 1000,1800,1000,2100,300,*,UP,POLY +S 3300,1400,3300,2600,100,*,UP,POLY +S 600,600,600,1400,100,*,UP,NTRANS +S 1200,600,1200,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 300,800,300,1200,300,*,DOWN,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 3300,100,3300,1400,100,*,UP,NTRANS +S 900,800,900,1600,300,*,DOWN,NDIF +S 2700,100,2700,1400,100,*,UP,NTRANS +S 3000,300,3000,1200,300,*,DOWN,NDIF +S 3600,300,3600,1200,300,*,DOWN,NDIF +S 2400,300,2400,1200,300,*,DOWN,NDIF +S 2400,2800,2400,4700,300,*,UP,PDIF +S 1500,3300,1500,4200,300,*,UP,PDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 300,3300,300,4600,300,*,UP,PDIF +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 2700,2600,2700,4900,100,*,DOWN,PTRANS +S 3000,2800,3000,4700,300,*,UP,PDIF +S 3300,2600,3300,4900,100,*,DOWN,PTRANS +S 3600,2800,3600,4700,300,*,UP,PDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +V 1000,3000,CONT_POLY,* +V 1500,2200,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 3600,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 3000,1000,CONT_DIF_N,* +V 2300,500,CONT_DIF_N,* +V 3600,500,CONT_DIF_N,* +V 900,1500,CONT_DIF_N,* +V 3600,3000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 3000,4000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 3600,4500,CONT_DIF_P,* +V 2300,4500,CONT_DIF_P,* +V 3600,4000,CONT_DIF_P,* +V 3600,3500,CONT_DIF_P,* +V 3000,3000,CONT_DIF_P,* +V 3000,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/ao22_x4.sym b/alliance/src/cells/src/sxlib/ao22_x4.sym new file mode 100644 index 00000000..a74c5237 Binary files /dev/null and b/alliance/src/cells/src/sxlib/ao22_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/ao22_x4.vbe b/alliance/src/cells/src/sxlib/ao22_x4.vbe new file mode 100644 index 00000000..2995c9cc --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tpll_i2_q : NATURAL := 505; + CONSTANT tphh_i2_q : NATURAL := 526; + CONSTANT tpll_i0_q : NATURAL := 552; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 647; + CONSTANT tphh_i0_q : NATURAL := 674; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x4; + +ARCHITECTURE behaviour_data_flow OF ao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/ao22_x4.vhd b/alliance/src/cells/src/sxlib/ao22_x4.vhd new file mode 100644 index 00000000..9edee9dd --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao22_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ao22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ao22_x4; + +ARCHITECTURE RTL OF ao22_x4 IS +BEGIN + q <= ((i0 OR i1) AND i2); +END RTL; diff --git a/alliance/src/cells/src/sxlib/ao2o22_x2.al b/alliance/src/cells/src/sxlib/ao2o22_x2.al new file mode 100644 index 00000000..c9435003 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao2o22_x2.al @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H ao2o22_x2,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,4 +C i2,IN,EXTERNAL,5 +C i3,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,9 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,10,6,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010 +T P,0.35,2.9,11,5,3,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00009 +T P,0.35,2.9,9,7,11,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00008 +T P,0.35,2.9,3,4,10,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00007 +T P,0.35,5.9,8,3,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00006 +T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00005 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00004 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,3,4,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002 +T N,0.35,2.9,1,3,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00001 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,EXTERNAL,vdd +Q 0.00505663 +S 8,EXTERNAL,q +Q 0.00258522 +S 7,EXTERNAL,i3 +Q 0.00295462 +S 6,EXTERNAL,i0 +Q 0.00295462 +S 5,EXTERNAL,i2 +Q 0.00323197 +S 4,EXTERNAL,i1 +Q 0.00323197 +S 3,INTERNAL +Q 0.00640584 +S 2,INTERNAL +Q 0.00199441 +S 1,EXTERNAL,vss +Q 0.00564418 +EOF diff --git a/alliance/src/cells/src/sxlib/ao2o22_x2.ap b/alliance/src/cells/src/sxlib/ao2o22_x2.ap new file mode 100644 index 00000000..6d49c1c9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao2o22_x2.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H ao2o22_x2,P, 6/ 9/2000,100 +A 0,0,4500,5000 +R 4000,1000,ref_ref,q_10 +R 4000,1500,ref_ref,q_15 +R 4000,2500,ref_ref,q_25 +R 4000,3500,ref_ref,q_35 +R 4000,3000,ref_ref,q_30 +R 4000,2000,ref_ref,q_20 +R 4000,4000,ref_ref,q_40 +R 2500,3500,ref_ref,i3_35 +R 2000,3500,ref_ref,i2_35 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 500,4000,ref_ref,i0_40 +R 500,3500,ref_ref,i0_35 +R 2500,1500,ref_ref,i3_15 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +S 3500,2000,3700,2000,300,*,RIGHT,POLY +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 3000,2000,3500,2000,100,*,RIGHT,ALU1 +S 3000,2000,3000,4000,100,*,DOWN,ALU1 +S 1600,4000,3000,4000,100,*,LEFT,ALU1 +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 900,800,900,1600,300,*,UP,NDIF +S 300,1000,2700,1000,100,*,RIGHT,ALU1 +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2700,800,2700,1200,300,*,UP,NDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 600,1400,600,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 2500,1500,2500,3500,200,i3,DOWN,CALU1 +S 2000,1500,2000,3500,200,i2,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +V 4000,4000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 4000,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 3500,2000,CONT_POLY,* +V 300,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 2700,300,CONT_BODY_P,* +V 900,4700,CONT_BODY_N,* +V 2100,4700,CONT_BODY_N,* +V 900,1500,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 1500,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/ao2o22_x2.sym b/alliance/src/cells/src/sxlib/ao2o22_x2.sym new file mode 100644 index 00000000..e11d7a60 Binary files /dev/null and b/alliance/src/cells/src/sxlib/ao2o22_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/ao2o22_x2.vbe b/alliance/src/cells/src/sxlib/ao2o22_x2.vbe new file mode 100644 index 00000000..c503d1b9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao2o22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 432; + CONSTANT tpll_i0_q : NATURAL := 451; + CONSTANT tphh_i3_q : NATURAL := 488; + CONSTANT tphh_i1_q : NATURAL := 508; + CONSTANT tpll_i3_q : NATURAL := 526; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tphh_i0_q : NATURAL := 572; + CONSTANT tpll_i2_q : NATURAL := 627; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x2; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/ao2o22_x2.vhd b/alliance/src/cells/src/sxlib/ao2o22_x2.vhd new file mode 100644 index 00000000..1e6a58e7 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao2o22_x2.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ao2o22_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ao2o22_x2; + +ARCHITECTURE RTL OF ao2o22_x2 IS +BEGIN + q <= ((i0 OR i1) AND (i2 OR i3)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/ao2o22_x4.al b/alliance/src/cells/src/sxlib/ao2o22_x4.al new file mode 100644 index 00000000..b54bd5fc --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao2o22_x4.al @@ -0,0 +1,44 @@ +V ALLIANCE : 6 +H ao2o22_x4,L,30/10/99 +C i0,IN,EXTERNAL,5 +C i1,IN,EXTERNAL,4 +C i2,IN,EXTERNAL,6 +C i3,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,9 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,8,1,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00012 +T P,0.35,5.9,9,1,8,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00011 +T P,0.35,2.9,1,4,11,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00010 +T P,0.35,2.9,9,7,10,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00009 +T P,0.35,2.9,10,6,1,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00008 +T P,0.35,2.9,11,5,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T N,0.35,2.9,8,1,3,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00006 +T N,0.35,2.9,3,1,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00005 +T N,0.35,1.4,1,4,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004 +T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,3,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00002 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00001 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,EXTERNAL,vdd +Q 0.007102 +S 8,EXTERNAL,q +Q 0.00258522 +S 7,EXTERNAL,i3 +Q 0.00295462 +S 6,EXTERNAL,i2 +Q 0.00323197 +S 5,EXTERNAL,i0 +Q 0.00295461 +S 4,EXTERNAL,i1 +Q 0.00323197 +S 3,EXTERNAL,vss +Q 0.00674947 +S 2,INTERNAL +Q 0.00199441 +S 1,INTERNAL +Q 0.00812254 +EOF diff --git a/alliance/src/cells/src/sxlib/ao2o22_x4.ap b/alliance/src/cells/src/sxlib/ao2o22_x4.ap new file mode 100644 index 00000000..072ba9f6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao2o22_x4.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H ao2o22_x4,P,30/ 8/2000,100 +A 0,0,5000,5000 +R 4000,1000,ref_ref,q_10 +R 4000,1500,ref_ref,q_15 +R 4000,2500,ref_ref,q_25 +R 4000,3500,ref_ref,q_35 +R 4000,3000,ref_ref,q_30 +R 4000,2000,ref_ref,q_20 +R 4000,4000,ref_ref,q_40 +R 2500,3500,ref_ref,i3_35 +R 2000,3500,ref_ref,i2_35 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 500,4000,ref_ref,i0_40 +R 500,3500,ref_ref,i0_35 +R 2500,1500,ref_ref,i3_15 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 2500,1500,2500,3500,200,i3,DOWN,CALU1 +S 2000,1500,2000,3500,200,i2,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 3000,2000,3500,2000,100,*,RIGHT,ALU1 +S 3000,2000,3000,4000,100,*,DOWN,ALU1 +S 1600,4000,3000,4000,100,*,LEFT,ALU1 +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 4600,300,4600,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 3500,2000,4300,2000,300,*,RIGHT,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 900,800,900,1600,300,*,UP,NDIF +S 300,1000,2700,1000,100,*,RIGHT,ALU1 +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2700,800,2700,1200,300,*,UP,NDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 600,1400,600,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +V 4000,4000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 4600,500,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 3500,2000,CONT_POLY,* +V 300,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 2700,300,CONT_BODY_P,* +V 900,4700,CONT_BODY_N,* +V 2100,4700,CONT_BODY_N,* +V 900,1500,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 1500,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/ao2o22_x4.sym b/alliance/src/cells/src/sxlib/ao2o22_x4.sym new file mode 100644 index 00000000..b81d17b3 Binary files /dev/null and b/alliance/src/cells/src/sxlib/ao2o22_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/ao2o22_x4.vbe b/alliance/src/cells/src/sxlib/ao2o22_x4.vbe new file mode 100644 index 00000000..61a5bff6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 554; + CONSTANT tpll_i0_q : NATURAL := 569; + CONSTANT tphh_i3_q : NATURAL := 606; + CONSTANT tphh_i1_q : NATURAL := 637; + CONSTANT tpll_i3_q : NATURAL := 639; + CONSTANT tpll_i1_q : NATURAL := 666; + CONSTANT tphh_i0_q : NATURAL := 696; + CONSTANT tpll_i2_q : NATURAL := 744; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/ao2o22_x4.vhd b/alliance/src/cells/src/sxlib/ao2o22_x4.vhd new file mode 100644 index 00000000..e056132e --- /dev/null +++ b/alliance/src/cells/src/sxlib/ao2o22_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ao2o22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ao2o22_x4; + +ARCHITECTURE RTL OF ao2o22_x4 IS +BEGIN + q <= ((i0 OR i1) AND (i2 OR i3)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/buf_x2.al b/alliance/src/cells/src/sxlib/buf_x2.al new file mode 100644 index 00000000..1fcb2f7a --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x2.al @@ -0,0 +1,21 @@ +V ALLIANCE : 6 +H buf_x2,L,30/10/99 +C i,IN,EXTERNAL,5 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00004 +T P,0.35,1.7,4,5,3,0,0.75,0.75,4.9,4.9,1.8,9.15,tr_00003 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,0.8,3,5,1,0,0.75,0.75,3.1,3.1,1.8,3.3,tr_00001 +S 5,EXTERNAL,i +Q 0.00373582 +S 4,EXTERNAL,vdd +Q 0.00323175 +S 3,INTERNAL +Q 0.00370178 +S 2,EXTERNAL,q +Q 0.00258522 +S 1,EXTERNAL,vss +Q 0.0026442 +EOF diff --git a/alliance/src/cells/src/sxlib/buf_x2.ap b/alliance/src/cells/src/sxlib/buf_x2.ap new file mode 100644 index 00000000..6fb7cab2 --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x2.ap @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H buf_x2,P,30/ 8/2000,100 +A 0,0,2000,5000 +R 1000,1000,ref_ref,i_10 +R 1000,1500,ref_ref,i_15 +R 1500,1000,ref_ref,q_10 +R 1500,2500,ref_ref,q_25 +R 1500,1500,ref_ref,q_15 +R 1500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,q_35 +R 1500,3000,ref_ref,q_30 +R 1500,2000,ref_ref,q_20 +R 1000,4000,ref_ref,i_40 +R 1000,3500,ref_ref,i_35 +R 1000,3000,ref_ref,i_30 +R 1000,2500,ref_ref,i_25 +R 1000,2000,ref_ref,i_20 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 300,4200,300,4700,200,*,DOWN,ALU1 +S 600,2500,800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 300,4200,300,4700,300,*,DOWN,NTIE +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 600,800,600,1400,100,*,DOWN,NTRANS +S 600,2600,600,3500,100,*,UP,PTRANS +S 300,2800,300,3300,300,*,DOWN,PDIF +S 300,1000,300,1200,300,*,UP,NDIF +S 300,1100,300,3000,100,*,DOWN,ALU1 +S 300,2000,1200,2000,200,*,RIGHT,POLY +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 800,2500,CONT_POLY,* +V 300,300,CONT_BODY_P,* +V 300,4200,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 300,3000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1100,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/buf_x2.sym b/alliance/src/cells/src/sxlib/buf_x2.sym new file mode 100644 index 00000000..9fb82c89 Binary files /dev/null and b/alliance/src/cells/src/sxlib/buf_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/buf_x2.vbe b/alliance/src/cells/src/sxlib/buf_x2.vbe new file mode 100644 index 00000000..e2e4c344 --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x2.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 6; + CONSTANT rdown_i_q : NATURAL := 1620; + CONSTANT rup_i_q : NATURAL := 1790; + CONSTANT tpll_i_q : NATURAL := 391; + CONSTANT tphh_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x2; + +ARCHITECTURE behaviour_data_flow OF buf_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x2" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/buf_x2.vhd b/alliance/src/cells/src/sxlib/buf_x2.vhd new file mode 100644 index 00000000..e5c84422 --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x2.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY buf_x2 IS +PORT( + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END buf_x2; + +ARCHITECTURE RTL OF buf_x2 IS +BEGIN + q <= i; +END RTL; diff --git a/alliance/src/cells/src/sxlib/buf_x4.al b/alliance/src/cells/src/sxlib/buf_x4.al new file mode 100644 index 00000000..f72dee40 --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x4.al @@ -0,0 +1,23 @@ +V ALLIANCE : 6 +H buf_x4,L,30/10/99 +C i,IN,EXTERNAL,5 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00006 +T P,0.35,5.9,4,3,2,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00005 +T P,0.35,2.9,4,5,3,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00004 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,1.4,3,5,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 5,EXTERNAL,i +Q 0.00373582 +S 4,EXTERNAL,vdd +Q 0.00527712 +S 3,INTERNAL +Q 0.00574803 +S 2,EXTERNAL,q +Q 0.00258522 +S 1,EXTERNAL,vss +Q 0.00374949 +EOF diff --git a/alliance/src/cells/src/sxlib/buf_x4.ap b/alliance/src/cells/src/sxlib/buf_x4.ap new file mode 100644 index 00000000..9dbc6a6e --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x4.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H buf_x4,P,30/ 8/2000,100 +A 0,0,2500,5000 +R 1000,2000,ref_ref,i_20 +R 1000,2500,ref_ref,i_25 +R 1000,3000,ref_ref,i_30 +R 1000,3500,ref_ref,i_35 +R 1000,4000,ref_ref,i_40 +R 1500,2000,ref_ref,q_20 +R 1500,3000,ref_ref,q_30 +R 1500,3500,ref_ref,q_35 +R 1500,4000,ref_ref,q_40 +R 1500,1500,ref_ref,q_15 +R 1500,2500,ref_ref,q_25 +R 1500,1000,ref_ref,q_10 +R 1000,1500,ref_ref,i_15 +R 1000,1000,ref_ref,i_10 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 300,2800,300,3700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 600,2600,600,3900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 300,4200,300,4700,300,*,DOWN,NTIE +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 600,2500,800,2500,300,*,RIGHT,POLY +S 300,4200,300,4700,200,*,DOWN,ALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 2100,3000,2100,4500,200,*,DOWN,ALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 2100,500,2100,1000,200,*,DOWN,ALU1 +S 300,2000,1800,2000,300,*,RIGHT,POLY +S 600,1500,800,1500,300,*,RIGHT,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 300,1000,300,3500,100,*,DOWN,ALU1 +V 2100,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 2100,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 300,4200,CONT_BODY_N,* +V 300,300,CONT_BODY_P,* +V 800,2500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 800,1500,CONT_POLY,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/buf_x4.sym b/alliance/src/cells/src/sxlib/buf_x4.sym new file mode 100644 index 00000000..d4472e27 Binary files /dev/null and b/alliance/src/cells/src/sxlib/buf_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/buf_x4.vbe b/alliance/src/cells/src/sxlib/buf_x4.vbe new file mode 100644 index 00000000..0b7726ef --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x4.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i : NATURAL := 9; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphh_i_q : NATURAL := 379; + CONSTANT tpll_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x4; + +ARCHITECTURE behaviour_data_flow OF buf_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x4" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/buf_x4.vhd b/alliance/src/cells/src/sxlib/buf_x4.vhd new file mode 100644 index 00000000..208df74a --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x4.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY buf_x4 IS +PORT( + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END buf_x4; + +ARCHITECTURE RTL OF buf_x4 IS +BEGIN + q <= i; +END RTL; diff --git a/alliance/src/cells/src/sxlib/buf_x8.al b/alliance/src/cells/src/sxlib/buf_x8.al new file mode 100644 index 00000000..55ee04cf --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x8.al @@ -0,0 +1,27 @@ +V ALLIANCE : 6 +H buf_x8,L,30/10/99 +C i,IN,EXTERNAL,5 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T P,0.35,5.9,4,3,1,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,5.9,4,3,1,0,0.75,0.75,13.3,13.3,9,11.25,tr_00007 +T P,0.35,5.9,4,5,3,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00006 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00004 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,9,2.25,tr_00002 +T N,0.35,2.9,3,5,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 5,EXTERNAL,i +Q 0.00373582 +S 4,EXTERNAL,vdd +Q 0.00782917 +S 3,INTERNAL +Q 0.00908482 +S 2,EXTERNAL,vss +Q 0.00647781 +S 1,EXTERNAL,q +Q 0.00599301 +EOF diff --git a/alliance/src/cells/src/sxlib/buf_x8.ap b/alliance/src/cells/src/sxlib/buf_x8.ap new file mode 100644 index 00000000..4e80fba3 --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x8.ap @@ -0,0 +1,99 @@ +V ALLIANCE : 6 +H buf_x8,P,30/ 8/2000,100 +A 0,0,4000,5000 +R 1000,2000,ref_ref,i_20 +R 1000,2500,ref_ref,i_25 +R 1000,3000,ref_ref,i_30 +R 1000,3500,ref_ref,i_35 +R 1000,4000,ref_ref,i_40 +R 1000,1500,ref_ref,i_15 +R 1000,1000,ref_ref,i_10 +R 1500,1500,ref_ref,q_15 +R 1500,2500,ref_ref,q_25 +R 1500,1000,ref_ref,q_10 +R 1500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,q_35 +R 1500,3000,ref_ref,q_30 +R 1500,2000,ref_ref,q_20 +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 2700,1000,2700,4000,200,*,UP,ALU1 +S 1500,2000,2700,2000,200,*,RIGHT,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 2100,3000,2100,4500,200,*,DOWN,ALU1 +S 2100,500,2100,1000,200,*,DOWN,ALU1 +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 3300,4000,3300,4700,300,*,DOWN,PDIF +S 3700,2900,3700,3400,300,*,DOWN,NTIE +S 600,100,600,1400,100,*,DOWN,NTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 300,300,300,1200,300,*,UP,NDIF +S 3200,1700,3800,1700,300,*,RIGHT,PTIE +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,2000,3000,2000,300,*,RIGHT,POLY +S 600,2500,800,2500,300,*,RIGHT,POLY +S 600,1500,800,1500,300,*,RIGHT,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 3300,500,3300,1700,200,*,UP,ALU1 +S 3300,1700,3700,1700,200,*,RIGHT,ALU1 +S 3700,2900,3700,3400,200,*,DOWN,ALU1 +S 3250,3400,3700,3400,200,*,RIGHT,ALU1 +S 3300,3350,3300,4500,200,*,DOWN,ALU1 +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 2100,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 800,2500,CONT_POLY,* +V 3300,500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 3300,4000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 3700,2900,CONT_BODY_N,* +V 3700,3400,CONT_BODY_N,* +V 3300,1700,CONT_BODY_P,* +V 3700,1700,CONT_BODY_P,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 300,2000,CONT_POLY,* +V 800,1500,CONT_POLY,* +V 1500,1000,CONT_DIF_N,* +V 2700,3000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,1000,CONT_DIF_N,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/buf_x8.sym b/alliance/src/cells/src/sxlib/buf_x8.sym new file mode 100644 index 00000000..21c53cae Binary files /dev/null and b/alliance/src/cells/src/sxlib/buf_x8.sym differ diff --git a/alliance/src/cells/src/sxlib/buf_x8.vbe b/alliance/src/cells/src/sxlib/buf_x8.vbe new file mode 100644 index 00000000..3b2ecc3b --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x8.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i : NATURAL := 15; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphh_i_q : NATURAL := 343; + CONSTANT tpll_i_q : NATURAL := 396; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x8; + +ARCHITECTURE behaviour_data_flow OF buf_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x8" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/buf_x8.vhd b/alliance/src/cells/src/sxlib/buf_x8.vhd new file mode 100644 index 00000000..cf5f0e48 --- /dev/null +++ b/alliance/src/cells/src/sxlib/buf_x8.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY buf_x8 IS +PORT( + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END buf_x8; + +ARCHITECTURE RTL OF buf_x8 IS +BEGIN + q <= i; +END RTL; diff --git a/alliance/src/cells/src/sxlib/fulladder_x2.al b/alliance/src/cells/src/sxlib/fulladder_x2.al new file mode 100644 index 00000000..10a81b4e --- /dev/null +++ b/alliance/src/cells/src/sxlib/fulladder_x2.al @@ -0,0 +1,100 @@ +V ALLIANCE : 6 +H fulladder_x2,L,30/10/99 +C a1,UNKNOWN,EXTERNAL,9 +C a2,UNKNOWN,EXTERNAL,10 +C a3,UNKNOWN,EXTERNAL,16 +C a4,UNKNOWN,EXTERNAL,21 +C b1,UNKNOWN,EXTERNAL,7 +C b2,UNKNOWN,EXTERNAL,6 +C b3,UNKNOWN,EXTERNAL,23 +C b4,UNKNOWN,EXTERNAL,24 +C cin1,IN,EXTERNAL,8 +C cin2,IN,EXTERNAL,22 +C cin3,IN,EXTERNAL,20 +C cout,OUT,EXTERNAL,11 +C sout,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,1 +T P,0.35,2,27,24,25,0,0.75,0.75,5.5,5.5,28.2,10.8,tr_00028 +T P,0.35,2,25,21,26,0,0.75,0.75,5.5,5.5,26.7,10.8,tr_00027 +T P,0.35,2,26,20,15,0,0.75,0.75,5.5,5.5,25.2,10.8,tr_00026 +T P,0.35,2.6,15,2,27,0,0.75,0.75,6.7,6.7,23.4,11.1,tr_00025 +T P,0.35,2,27,22,14,0,0.75,0.75,5.5,5.5,21.6,11.4,tr_00024 +T P,0.35,2,14,23,27,0,0.75,0.75,5.5,5.5,20.1,11.4,tr_00023 +T P,0.35,2,27,16,14,0,0.75,0.75,5.5,5.5,18.3,11.4,tr_00022 +T P,0.35,2.6,14,9,13,0,0.75,0.75,6.7,6.7,1.8,11.1,tr_00021 +T P,0.35,3.8,13,6,5,0,0.75,0.75,9.1,9.1,8.7,10.5,tr_00020 +T P,0.35,3.8,5,10,2,0,0.75,0.75,9.1,9.1,7.2,10.5,tr_00019 +T P,0.35,2.6,2,8,13,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00018 +T P,0.35,2.6,13,7,14,0,0.75,0.75,6.7,6.7,3.6,11.1,tr_00017 +T P,0.35,5.9,14,2,11,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00016 +T P,0.35,5.9,12,15,14,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00015 +T N,0.35,1.4,17,2,15,0,0.75,0.75,4.3,4.3,23.1,3.3,tr_00014 +T N,0.35,1.1,1,24,17,0,0.75,0.75,3.7,3.7,28.2,3.15,tr_00013 +T N,0.35,1.1,1,20,17,0,0.75,0.75,3.7,3.7,24.9,3.15,tr_00012 +T N,0.35,1.1,17,21,1,0,0.75,0.75,3.7,3.7,26.4,3.15,tr_00011 +T N,0.35,1.1,18,23,19,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00010 +T N,0.35,1.1,19,16,1,0,0.75,0.75,3.7,3.7,18.3,3.15,tr_00009 +T N,0.35,1.1,15,22,18,0,0.75,0.75,3.7,3.7,21.3,3.15,tr_00008 +T N,0.35,1.7,2,7,3,0,0.75,0.75,4.9,4.9,3.3,3.45,tr_00007 +T N,0.35,1.4,3,9,1,0,0.75,0.75,4.3,4.3,1.8,3.3,tr_00006 +T N,0.35,1.1,4,8,2,0,0.75,0.75,3.7,3.7,5.1,3.15,tr_00005 +T N,0.35,1.1,1,10,4,0,0.75,0.75,3.7,3.7,6.9,3.15,tr_00004 +T N,0.35,1.1,4,6,1,0,0.75,0.75,3.7,3.7,8.7,3.15,tr_00003 +T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00002 +T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00001 +S 27,INTERNAL +Q 0.00250174 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0 +S 24,EXTERNAL,b4 +Q 0.00295462 +S 23,EXTERNAL,b3 +Q 0.00296195 +S 22,EXTERNAL,cin2 +Q 0.00296195 +S 21,EXTERNAL,a4 +Q 0.00310499 +S 20,EXTERNAL,cin3 +Q 0.00283471 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00108534 +S 16,EXTERNAL,a3 +Q 0.00281157 +S 15,INTERNAL +Q 0.00630209 +S 14,EXTERNAL,vdd +Q 0.0105755 +S 13,INTERNAL +Q 0.00227626 +S 12,EXTERNAL,sout +Q 0.00211518 +S 11,EXTERNAL,cout +Q 0.00276149 +S 10,EXTERNAL,a2 +Q 0.00262649 +S 9,EXTERNAL,a1 +Q 0.00316706 +S 8,EXTERNAL,cin1 +Q 0.00311233 +S 7,EXTERNAL,b1 +Q 0.00311656 +S 6,EXTERNAL,b2 +Q 0.00239514 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00114171 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.0112381 +S 1,EXTERNAL,vss +Q 0.0111043 +EOF diff --git a/alliance/src/cells/src/sxlib/fulladder_x2.ap b/alliance/src/cells/src/sxlib/fulladder_x2.ap new file mode 100644 index 00000000..95608e04 --- /dev/null +++ b/alliance/src/cells/src/sxlib/fulladder_x2.ap @@ -0,0 +1,275 @@ +V ALLIANCE : 6 +H fulladder_x2,P, 6/ 9/2000,100 +A 0,0,10000,5000 +R 9500,3500,ref_ref,b4_35 +R 9000,3500,ref_ref,a4_35 +R 1000,3500,ref_ref,b1_35 +R 500,3500,ref_ref,a1_35 +R 500,1000,ref_ref,a1_10 +R 9500,3000,ref_ref,b4_30 +R 9500,2500,ref_ref,b4_25 +R 9500,2000,ref_ref,b4_20 +R 9500,1500,ref_ref,b4_15 +R 9000,3000,ref_ref,a4_30 +R 9000,2500,ref_ref,a4_25 +R 9000,2000,ref_ref,a4_20 +R 9000,1500,ref_ref,a4_15 +R 8500,3000,ref_ref,cin3_30 +R 8500,2500,ref_ref,cin3_25 +R 8500,2000,ref_ref,cin3_20 +R 8500,1500,ref_ref,cin3_15 +R 7000,3000,ref_ref,cin2_30 +R 7000,2500,ref_ref,cin2_25 +R 7000,2000,ref_ref,cin2_20 +R 7000,1500,ref_ref,cin2_15 +R 6500,3000,ref_ref,b3_30 +R 6500,2500,ref_ref,b3_25 +R 6500,2000,ref_ref,b3_20 +R 6500,1500,ref_ref,b3_15 +R 6000,3000,ref_ref,a3_30 +R 6000,2500,ref_ref,a3_25 +R 6000,2000,ref_ref,a3_20 +R 6000,1500,ref_ref,a3_15 +R 5000,3500,ref_ref,sout_35 +R 5000,3000,ref_ref,sout_30 +R 5000,2500,ref_ref,sout_25 +R 5000,2000,ref_ref,sout_20 +R 5000,1500,ref_ref,sout_15 +R 5000,1000,ref_ref,sout_10 +R 4000,1000,ref_ref,cout_10 +R 3500,3000,ref_ref,cout_30 +R 3500,2500,ref_ref,cout_25 +R 3500,2000,ref_ref,cout_20 +R 3500,1500,ref_ref,cout_15 +R 3000,3000,ref_ref,b2_30 +R 3000,2500,ref_ref,b2_25 +R 3000,2000,ref_ref,b2_20 +R 3000,1500,ref_ref,b2_15 +R 2500,3000,ref_ref,a2_30 +R 2500,2500,ref_ref,a2_25 +R 2500,2000,ref_ref,a2_20 +R 2500,1500,ref_ref,a2_15 +R 2000,3000,ref_ref,cin1_30 +R 2000,2500,ref_ref,cin1_25 +R 2000,2000,ref_ref,cin1_20 +R 2000,1500,ref_ref,cin1_15 +R 1000,3000,ref_ref,b1_30 +R 1000,2500,ref_ref,b1_25 +R 1000,2000,ref_ref,b1_20 +R 1000,1500,ref_ref,b1_15 +R 500,3000,ref_ref,a1_30 +R 500,2500,ref_ref,a1_25 +R 500,2000,ref_ref,a1_20 +R 500,1500,ref_ref,a1_15 +S 9100,900,9100,1200,300,*,UP,NDIF +S 8000,900,8000,1200,300,*,UP,NDIF +S 6400,3500,6400,4100,300,*,UP,PDIF +S 300,3300,300,4100,300,*,UP,PDIF +S 1500,3300,1500,4100,300,*,UP,PDIF +S 6950,3600,6950,4650,200,*,UP,PDIF +S 8550,450,8550,1200,200,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 9000,1500,9000,3500,100,*,UP,ALU1 +S 9500,1500,9500,3500,100,*,DOWN,ALU1 +S 900,400,2000,400,300,*,RIGHT,PTIE +S 300,500,300,1300,300,*,UP,NDIF +S 7400,900,7400,1200,300,*,UP,NDIF +S 7700,700,7700,1500,100,*,UP,NTRANS +S 7700,1500,7700,3100,100,*,UP,POLY +S 0,3900,10000,3900,2400,*,RIGHT,NWELL +S 1600,4700,3200,4700,300,*,RIGHT,NTIE +S 7600,4700,9200,4700,300,*,RIGHT,NTIE +S 6400,400,7900,400,300,*,RIGHT,PTIE +S 8400,2500,8400,3100,100,*,DOWN,POLY +S 6100,1400,6100,3300,100,*,UP,POLY +S 6600,1400,6600,3300,100,*,UP,POLY +S 7100,1400,7100,3300,100,*,UP,POLY +S 8900,1400,8900,3100,100,*,UP,POLY +S 9400,1400,9400,3100,100,*,DOWN,POLY +S 6600,3300,6700,3300,100,*,RIGHT,POLY +S 7100,3300,7200,3300,100,*,RIGHT,POLY +S 7700,3100,7800,3100,100,*,RIGHT,POLY +S 9700,3300,9700,4000,300,*,UP,PDIF +S 7500,3300,7500,4100,300,*,UP,PDIF +S 8100,3300,8100,4100,200,*,UP,PDIF +S 8700,3300,8700,3900,200,*,UP,PDIF +S 9400,3100,9400,4100,100,*,UP,PTRANS +S 8900,3100,8900,4100,100,*,UP,PTRANS +S 8400,3100,8400,4100,100,*,UP,PTRANS +S 7800,3100,7800,4300,100,*,UP,PTRANS +S 5700,3500,5700,4600,400,*,UP,PDIF +S 7200,3300,7200,4300,100,*,UP,PTRANS +S 6700,3300,6700,4300,100,*,UP,PTRANS +S 6100,3300,6100,4300,100,*,UP,PTRANS +S 8300,1400,8300,2400,100,*,UP,POLY +S 5800,500,5800,1200,300,*,UP,NDIF +S 9700,1000,9700,1200,300,*,UP,NDIF +S 9400,700,9400,1400,100,*,UP,NTRANS +S 8300,700,8300,1400,100,*,UP,NTRANS +S 8800,700,8800,1400,100,*,UP,NTRANS +S 6600,700,6600,1400,100,*,UP,NTRANS +S 6100,700,6100,1400,100,*,UP,NTRANS +S 7100,700,7100,1400,100,*,UP,NTRANS +S 8800,1400,8900,1400,100,*,RIGHT,POLY +S 1100,700,1100,1600,100,*,UP,NTRANS +S 600,1500,600,3100,100,*,UP,POLY +S 1000,2000,1200,2000,100,*,LEFT,POLY +S 1700,2500,2000,2500,100,*,RIGHT,POLY +S 1700,1400,1700,2500,100,*,UP,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1100,1600,1100,2000,100,*,UP,POLY +S 1200,2000,1200,3100,100,*,UP,POLY +S 2100,2900,2100,4100,200,*,UP,PDIF +S 2900,1400,2900,2700,100,*,UP,POLY +S 2400,1900,2400,2700,100,*,UP,POLY +S 900,3300,900,4450,300,*,UP,PDIF +S 600,3100,600,4300,100,*,UP,PTRANS +S 3200,2900,3200,4100,300,*,UP,PDIF +S 2700,2900,2700,4100,200,*,UP,PDIF +S 2900,2700,2900,4300,100,*,UP,PTRANS +S 2400,2700,2400,4300,100,*,UP,PTRANS +S 1800,3100,1800,4300,100,*,UP,PTRANS +S 1200,3100,1200,4300,100,*,UP,PTRANS +S 2300,1400,2300,1900,100,*,UP,POLY +S 3200,900,3200,1200,300,*,UP,NDIF +S 2600,500,2600,1200,300,*,UP,NDIF +S 2000,900,2000,1200,300,*,UP,NDIF +S 1400,900,1400,1400,300,*,UP,NDIF +S 600,700,600,1500,100,*,UP,NTRANS +S 1700,700,1700,1400,100,*,UP,NTRANS +S 2300,700,2300,1400,100,*,UP,NTRANS +S 2900,700,2900,1400,100,*,UP,NTRANS +S 0,300,10000,300,600,vss,RIGHT,CALU1 +S 0,4700,10000,4700,600,vdd,RIGHT,CALU1 +S 8000,1500,8000,3550,100,*,UP,ALU1 +S 7500,950,7500,1500,100,*,UP,ALU1 +S 9200,400,9600,400,300,*,RIGHT,PTIE +S 8300,2400,8400,2400,100,*,RIGHT,POLY +S 9700,300,9700,1000,200,*,DOWN,ALU1 +S 7500,2000,7500,3500,100,*,UP,ALU1 +S 8000,1000,9100,1000,100,*,RIGHT,ALU1 +S 6400,4000,9700,4000,100,*,RIGHT,ALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,DOWN,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 7500,1500,8000,1500,100,*,RIGHT,ALU1 +S 3800,300,3800,1200,300,*,UP,NDIF +S 4400,300,4400,1200,300,*,UP,NDIF +S 4100,100,4100,1400,100,*,DOWN,NTRANS +S 4700,100,4700,1400,100,*,DOWN,NTRANS +S 5000,300,5000,1200,300,*,UP,NDIF +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 5500,1000,7400,1000,100,*,RIGHT,ALU1 +S 4100,1400,4100,2600,100,*,UP,POLY +S 4700,1400,4700,2600,100,*,UP,POLY +S 4700,2000,5500,2000,100,*,LEFT,POLY +S 3450,3000,3800,3000,200,*,LEFT,ALU1 +S 3500,1450,3500,3050,200,*,DOWN,ALU1 +S 3800,1000,4000,1000,200,*,LEFT,ALU1 +S 6000,1500,6000,3000,100,*,DOWN,ALU1 +S 6500,1500,6500,3000,100,*,DOWN,ALU1 +S 7000,1500,7000,3000,100,*,UP,ALU1 +S 8500,1500,8500,3000,100,*,UP,ALU1 +S 5500,1000,5500,2000,100,*,DOWN,ALU1 +S 4300,2500,4400,2500,100,*,RIGHT,ALU1 +S 4400,2500,4400,4000,100,*,UP,ALU1 +S 4400,4000,5600,4000,100,*,RIGHT,ALU1 +S 5600,3500,5600,4000,100,*,DOWN,ALU1 +S 5600,3500,7500,3500,100,*,RIGHT,ALU1 +S 1500,3500,4400,3500,100,*,LEFT,ALU1 +S 5000,1000,5000,3500,200,*,UP,ALU1 +S 9500,1500,9500,3500,200,b4,DOWN,CALU1 +S 9000,1500,9000,3500,200,a4,DOWN,CALU1 +S 1000,1500,1000,3500,200,b1,DOWN,CALU1 +S 500,1000,500,3500,200,a1,DOWN,CALU1 +S 8500,1500,8500,3000,200,cin3,DOWN,CALU1 +S 7000,1500,7000,3000,200,cin2,DOWN,CALU1 +S 6500,1500,6500,3000,200,b3,DOWN,CALU1 +S 6000,1500,6000,3000,200,a3,DOWN,CALU1 +S 5000,1000,5000,3500,200,sout,DOWN,CALU1 +S 3000,1500,3000,3000,200,b2,DOWN,CALU1 +S 2500,1500,2500,3000,200,a2,DOWN,CALU1 +S 2000,1500,2000,3000,200,cin1,DOWN,CALU1 +S 3500,1500,3500,3000,200,cout,DOWN,CALU1 +S 4000,1000,4000,1500,200,cout,DOWN,CALU1 +S 4000,1000,4000,1550,200,*,DOWN,ALU1 +S 3450,1500,4050,1500,200,*,RIGHT,ALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1700,2500,2000,2500,300,*,LEFT,POLY +S 4100,2500,4300,2500,300,*,LEFT,POLY +S 7500,2000,7700,2000,300,*,RIGHT,POLY +V 6950,4600,CONT_DIF_P,* +V 8550,400,CONT_DIF_N,* +V 1500,400,CONT_BODY_P,* +V 1000,400,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 1600,4700,CONT_BODY_N,* +V 2000,4700,CONT_BODY_N,* +V 2400,4700,CONT_BODY_N,* +V 2800,4700,CONT_BODY_N,* +V 3200,4700,CONT_BODY_N,* +V 9200,4700,CONT_BODY_N,* +V 8800,4700,CONT_BODY_N,* +V 8400,4700,CONT_BODY_N,* +V 8000,4700,CONT_BODY_N,* +V 7600,4700,CONT_BODY_N,* +V 3200,400,CONT_BODY_P,* +V 7400,400,CONT_BODY_P,* +V 6900,400,CONT_BODY_P,* +V 6400,400,CONT_BODY_P,* +V 3000,2500,CONT_POLY,* +V 7500,4000,CONT_DIF_P,* +V 6350,4700,CONT_BODY_N,* +V 6400,4000,CONT_DIF_P,* +V 9700,4000,CONT_DIF_P,* +V 8100,3500,CONT_DIF_P,* +V 5800,500,CONT_DIF_N,* +V 9700,1000,CONT_DIF_N,* +V 9100,1000,CONT_DIF_N,* +V 8000,1000,CONT_DIF_N,* +V 7400,1000,CONT_DIF_N,* +V 7950,400,CONT_BODY_P,* +V 9600,400,CONT_BODY_P,* +V 9200,400,CONT_BODY_P,* +V 8500,2500,CONT_POLY,* +V 6000,2000,CONT_POLY,* +V 6500,2000,CONT_POLY,* +V 7000,2000,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 9500,2000,CONT_POLY,* +V 9000,2500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2600,500,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 2000,400,CONT_BODY_P,* +V 2000,2500,CONT_POLY,* +V 1400,1000,CONT_DIF_N,* +V 3800,1000,CONT_DIF_N,* +V 5000,1000,CONT_DIF_N,* +V 4400,500,CONT_DIF_N,* +V 4400,4500,CONT_DIF_P,* +V 3800,3000,CONT_DIF_P,* +V 5000,3000,CONT_DIF_P,* +V 5500,2000,CONT_POLY,* +V 4300,2500,CONT_POLY,* +V 5000,3500,CONT_DIF_P,* +V 5700,4500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/fulladder_x2.vbe b/alliance/src/cells/src/sxlib/fulladder_x2.vbe new file mode 100644 index 00000000..1df49a55 --- /dev/null +++ b/alliance/src/cells/src/sxlib/fulladder_x2.vbe @@ -0,0 +1,121 @@ +ENTITY fulladder_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a1 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT cin_a3 : NATURAL := 6; + CONSTANT cin_a4 : NATURAL := 6; + CONSTANT cin_b1 : NATURAL := 8; + CONSTANT cin_b2 : NATURAL := 8; + CONSTANT cin_b3 : NATURAL := 6; + CONSTANT cin_b4 : NATURAL := 6; + CONSTANT cin_cin1 : NATURAL := 7; + CONSTANT cin_cin2 : NATURAL := 6; + CONSTANT cin_cin3 : NATURAL := 6; + CONSTANT rdown_a1_cout : NATURAL := 1620; + CONSTANT rdown_a1_sout : NATURAL := 1620; + CONSTANT rdown_a2_cout : NATURAL := 1620; + CONSTANT rdown_a2_sout : NATURAL := 1620; + CONSTANT rdown_a3_sout : NATURAL := 1620; + CONSTANT rdown_a4_sout : NATURAL := 1620; + CONSTANT rdown_b1_cout : NATURAL := 1620; + CONSTANT rdown_b1_sout : NATURAL := 1620; + CONSTANT rdown_b2_cout : NATURAL := 1620; + CONSTANT rdown_b2_sout : NATURAL := 1620; + CONSTANT rdown_b3_sout : NATURAL := 1620; + CONSTANT rdown_b4_sout : NATURAL := 1620; + CONSTANT rdown_cin1_cout : NATURAL := 1620; + CONSTANT rdown_cin1_sout : NATURAL := 1620; + CONSTANT rdown_cin2_sout : NATURAL := 1620; + CONSTANT rdown_cin3_sout : NATURAL := 1620; + CONSTANT rup_a1_cout : NATURAL := 1790; + CONSTANT rup_a1_sout : NATURAL := 1790; + CONSTANT rup_a2_cout : NATURAL := 1790; + CONSTANT rup_a2_sout : NATURAL := 1790; + CONSTANT rup_a3_sout : NATURAL := 1790; + CONSTANT rup_a4_sout : NATURAL := 1790; + CONSTANT rup_b1_cout : NATURAL := 1790; + CONSTANT rup_b1_sout : NATURAL := 1790; + CONSTANT rup_b2_cout : NATURAL := 1790; + CONSTANT rup_b2_sout : NATURAL := 1790; + CONSTANT rup_b3_sout : NATURAL := 1790; + CONSTANT rup_b4_sout : NATURAL := 1790; + CONSTANT rup_cin1_cout : NATURAL := 1790; + CONSTANT rup_cin1_sout : NATURAL := 1790; + CONSTANT rup_cin2_sout : NATURAL := 1790; + CONSTANT rup_cin3_sout : NATURAL := 1790; + CONSTANT tphh_cin3_sout : NATURAL := 489; + CONSTANT tphh_a4_sout : NATURAL := 536; + CONSTANT tphh_b4_sout : NATURAL := 581; + CONSTANT tphh_a2_cout : NATURAL := 658; + CONSTANT tpll_cin1_cout : NATURAL := 694; + CONSTANT tphh_a1_cout : NATURAL := 699; + CONSTANT tpll_b1_cout : NATURAL := 709; + CONSTANT tpll_a1_cout : NATURAL := 736; + CONSTANT tphh_cin1_cout : NATURAL := 742; + CONSTANT tpll_b2_cout : NATURAL := 748; + CONSTANT tphh_b2_cout : NATURAL := 751; + CONSTANT tphh_b1_cout : NATURAL := 777; + CONSTANT tpll_a2_cout : NATURAL := 782; + CONSTANT tpll_cin2_sout : NATURAL := 893; + CONSTANT tphh_a3_sout : NATURAL := 902; + CONSTANT tpll_b3_sout : NATURAL := 951; + CONSTANT tpll_a3_sout : NATURAL := 1008; + CONSTANT tphh_b3_sout : NATURAL := 1014; + CONSTANT tpll_b4_sout : NATURAL := 1071; + CONSTANT tpll_a4_sout : NATURAL := 1114; + CONSTANT tphh_cin2_sout : NATURAL := 1116; + CONSTANT tphl_a2_sout : NATURAL := 1128; + CONSTANT tpll_cin3_sout : NATURAL := 1149; + CONSTANT tplh_cin1_sout : NATURAL := 1163; + CONSTANT tphl_a1_sout : NATURAL := 1169; + CONSTANT tplh_b1_sout : NATURAL := 1178; + CONSTANT tplh_a1_sout : NATURAL := 1205; + CONSTANT tphl_cin1_sout : NATURAL := 1212; + CONSTANT tplh_b2_sout : NATURAL := 1217; + CONSTANT tphl_b2_sout : NATURAL := 1221; + CONSTANT tphl_b1_sout : NATURAL := 1247; + CONSTANT tplh_a2_sout : NATURAL := 1251; + CONSTANT transistors : NATURAL := 28 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + a4 : in BIT; + b1 : in BIT; + b2 : in BIT; + b3 : in BIT; + b4 : in BIT; + cin1 : in BIT; + cin2 : in BIT; + cin3 : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END fulladder_x2; + +ARCHITECTURE behaviour_data_flow OF fulladder_x2 IS + SIGNAL ncout : BIT; + +BEGIN + ASSERT ((((cin1 and cin2) and cin3) or not (((cin1 or cin2) or cin3))) = '1') + REPORT "cin1, cin2, cin3 must be connected together on fulladder_x2" + SEVERITY WARNING; + ASSERT (((((b1 and b2) and b3) and b4) or not ((((b1 or b2) or b3) or + b4))) = '1') + REPORT "b1, b2, b3, b4 must be connected together on fulladder_x2" + SEVERITY WARNING; + ASSERT (((((a1 and a2) and a3) and a4) or not ((((a1 or a2) or a3) or + a4))) = '1') + REPORT "a1, a2, a3, a4 must be connected together on fulladder_x2" + SEVERITY WARNING; + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on fulladder_x2" + SEVERITY WARNING; + ncout <= not (((a1 and b1) or ((a2 or b2) and cin1))); + sout <= (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) after 1900 ps; + cout <= not (ncout) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/fulladder_x2.vhd b/alliance/src/cells/src/sxlib/fulladder_x2.vhd new file mode 100644 index 00000000..d9d8f757 --- /dev/null +++ b/alliance/src/cells/src/sxlib/fulladder_x2.vhd @@ -0,0 +1,34 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY fulladder_x2 IS +PORT( + a1 : IN STD_LOGIC; + a2 : IN STD_LOGIC; + a3 : IN STD_LOGIC; + a4 : IN STD_LOGIC; + b1 : IN STD_LOGIC; + b2 : IN STD_LOGIC; + b3 : IN STD_LOGIC; + b4 : IN STD_LOGIC; + cin1 : IN STD_LOGIC; + cin2 : IN STD_LOGIC; + cin3 : IN STD_LOGIC; + cout : OUT STD_LOGIC; + sout : OUT STD_LOGIC +); +END fulladder_x2; + +ARCHITECTURE RTL OF fulladder_x2 IS + SIGNAL ncout : STD_LOGIC; + +BEGIN + cout <= NOT(ncout); + sout <= (((a3 AND b3) AND cin2) OR (((a4 OR b4) OR cin3) AND ncout)); + ncout <= NOT(((a1 AND b1) OR ((a2 OR b2) AND cin1))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/fulladder_x4.al b/alliance/src/cells/src/sxlib/fulladder_x4.al new file mode 100644 index 00000000..777242de --- /dev/null +++ b/alliance/src/cells/src/sxlib/fulladder_x4.al @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H fulladder_x4,L,30/10/99 +C a1,UNKNOWN,EXTERNAL,10 +C a2,UNKNOWN,EXTERNAL,9 +C a3,UNKNOWN,EXTERNAL,20 +C a4,UNKNOWN,EXTERNAL,24 +C b1,UNKNOWN,EXTERNAL,7 +C b2,UNKNOWN,EXTERNAL,8 +C b3,UNKNOWN,EXTERNAL,21 +C b4,UNKNOWN,EXTERNAL,23 +C cin1,IN,EXTERNAL,6 +C cin2,IN,EXTERNAL,22 +C cin3,IN,EXTERNAL,19 +C cout,OUT,EXTERNAL,11 +C sout,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,11,3,13,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00032 +T P,0.35,2.6,14,7,13,0,0.75,0.75,6.7,6.7,3.6,11.1,tr_00031 +T P,0.35,2.6,3,6,14,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00030 +T P,0.35,3.8,5,9,3,0,0.75,0.75,9.1,9.1,7.2,10.5,tr_00029 +T P,0.35,3.8,14,8,5,0,0.75,0.75,9.1,9.1,8.7,10.5,tr_00028 +T P,0.35,2.6,13,10,14,0,0.75,0.75,6.7,6.7,1.8,11.1,tr_00027 +T P,0.35,5.9,13,3,11,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00026 +T P,0.35,5.9,13,15,12,0,0.75,0.75,13.3,13.3,17.7,11.25,tr_00025 +T P,0.35,5.9,12,15,13,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00024 +T P,0.35,2,13,21,25,0,0.75,0.75,5.5,5.5,21.6,11.4,tr_00023 +T P,0.35,2,25,22,13,0,0.75,0.75,5.5,5.5,23.1,11.4,tr_00022 +T P,0.35,2,25,23,27,0,0.75,0.75,5.5,5.5,29.7,10.8,tr_00021 +T P,0.35,2,27,24,26,0,0.75,0.75,5.5,5.5,28.2,10.8,tr_00020 +T P,0.35,2,25,20,13,0,0.75,0.75,5.5,5.5,19.8,11.4,tr_00019 +T P,0.35,2.6,15,3,25,0,0.75,0.75,6.7,6.7,24.9,11.1,tr_00018 +T P,0.35,2,26,19,15,0,0.75,0.75,5.5,5.5,26.7,10.8,tr_00017 +T N,0.35,2.9,1,3,11,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00016 +T N,0.35,1.1,2,8,1,0,0.75,0.75,3.7,3.7,8.7,3.15,tr_00015 +T N,0.35,1.1,1,9,2,0,0.75,0.75,3.7,3.7,6.9,3.15,tr_00014 +T N,0.35,1.1,2,6,3,0,0.75,0.75,3.7,3.7,5.1,3.15,tr_00013 +T N,0.35,1.4,4,10,1,0,0.75,0.75,4.3,4.3,1.8,3.3,tr_00012 +T N,0.35,1.7,3,7,4,0,0.75,0.75,4.9,4.9,3.3,3.45,tr_00011 +T N,0.35,2.9,11,3,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00010 +T N,0.35,2.9,12,15,1,0,0.75,0.75,7.3,7.3,17.7,2.25,tr_00009 +T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00008 +T N,0.35,1.4,16,3,15,0,0.75,0.75,4.3,4.3,24.6,3.3,tr_00007 +T N,0.35,1.1,1,23,16,0,0.75,0.75,3.7,3.7,29.7,3.15,tr_00006 +T N,0.35,1.1,15,22,17,0,0.75,0.75,3.7,3.7,22.8,3.15,tr_00005 +T N,0.35,1.1,17,21,18,0,0.75,0.75,3.7,3.7,21.3,3.15,tr_00004 +T N,0.35,1.1,16,24,1,0,0.75,0.75,3.7,3.7,27.9,3.15,tr_00003 +T N,0.35,1.1,1,19,16,0,0.75,0.75,3.7,3.7,26.4,3.15,tr_00002 +T N,0.35,1.1,18,20,1,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00001 +S 27,INTERNAL +Q 0 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0.00250174 +S 24,EXTERNAL,a4 +Q 0.00310499 +S 23,EXTERNAL,b4 +Q 0.00295462 +S 22,EXTERNAL,cin2 +Q 0.00296195 +S 21,EXTERNAL,b3 +Q 0.00296195 +S 20,EXTERNAL,a3 +Q 0.00252972 +S 19,EXTERNAL,cin3 +Q 0.00283471 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0 +S 16,INTERNAL +Q 0.00108534 +S 15,INTERNAL +Q 0.00752047 +S 14,INTERNAL +Q 0.00227626 +S 13,EXTERNAL,vdd +Q 0.010917 +S 12,EXTERNAL,sout +Q 0.00217394 +S 11,EXTERNAL,cout +Q 0.00217394 +S 10,EXTERNAL,a1 +Q 0.00316706 +S 9,EXTERNAL,a2 +Q 0.00262649 +S 8,EXTERNAL,b2 +Q 0.00239514 +S 7,EXTERNAL,b1 +Q 0.00311656 +S 6,EXTERNAL,cin1 +Q 0.00311233 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.0135185 +S 2,INTERNAL +Q 0.00114171 +S 1,EXTERNAL,vss +Q 0.0122096 +EOF diff --git a/alliance/src/cells/src/sxlib/fulladder_x4.ap b/alliance/src/cells/src/sxlib/fulladder_x4.ap new file mode 100644 index 00000000..a896b73d --- /dev/null +++ b/alliance/src/cells/src/sxlib/fulladder_x4.ap @@ -0,0 +1,286 @@ +V ALLIANCE : 6 +H fulladder_x4,P, 6/ 9/2000,100 +A 0,0,10500,5000 +R 4500,3500,ref_ref,cout_35 +R 4500,1000,ref_ref,cout_10 +R 4500,3000,ref_ref,cout_30 +R 4500,2500,ref_ref,cout_25 +R 4500,2000,ref_ref,cout_20 +R 4500,1500,ref_ref,cout_15 +R 7000,2000,ref_ref,b3_20 +R 10000,1500,ref_ref,b4_15 +R 6500,3000,ref_ref,a3_30 +R 6500,2500,ref_ref,a3_25 +R 6500,2000,ref_ref,a3_20 +R 9000,1500,ref_ref,cin3_15 +R 7000,1500,ref_ref,b3_15 +R 9000,2000,ref_ref,cin3_20 +R 10000,3500,ref_ref,b4_35 +R 7500,3000,ref_ref,cin2_30 +R 7500,2500,ref_ref,cin2_25 +R 7500,2000,ref_ref,cin2_20 +R 7500,1500,ref_ref,cin2_15 +R 7000,3000,ref_ref,b3_30 +R 7000,2500,ref_ref,b3_25 +R 10000,2500,ref_ref,b4_25 +R 10000,2000,ref_ref,b4_20 +R 9500,3000,ref_ref,a4_30 +R 9500,2500,ref_ref,a4_25 +R 9500,2000,ref_ref,a4_20 +R 9500,1500,ref_ref,a4_15 +R 9000,3000,ref_ref,cin3_30 +R 9000,2500,ref_ref,cin3_25 +R 9500,3500,ref_ref,a4_35 +R 10000,3000,ref_ref,b4_30 +R 5500,2000,ref_ref,sout_20 +R 5500,2500,ref_ref,sout_25 +R 5500,3000,ref_ref,sout_30 +R 5500,3500,ref_ref,sout_35 +R 5500,1000,ref_ref,sout_10 +R 5500,1500,ref_ref,sout_15 +R 1000,3500,ref_ref,b1_35 +R 500,3500,ref_ref,a1_35 +R 500,1000,ref_ref,a1_10 +R 3000,3000,ref_ref,b2_30 +R 3000,2500,ref_ref,b2_25 +R 3000,2000,ref_ref,b2_20 +R 3000,1500,ref_ref,b2_15 +R 2500,3000,ref_ref,a2_30 +R 2500,2500,ref_ref,a2_25 +R 2500,2000,ref_ref,a2_20 +R 2500,1500,ref_ref,a2_15 +R 2000,3000,ref_ref,cin1_30 +R 2000,2500,ref_ref,cin1_25 +R 2000,2000,ref_ref,cin1_20 +R 2000,1500,ref_ref,cin1_15 +R 1000,3000,ref_ref,b1_30 +R 1000,2500,ref_ref,b1_25 +R 1000,2000,ref_ref,b1_20 +R 1000,1500,ref_ref,b1_15 +R 500,3000,ref_ref,a1_30 +R 500,2500,ref_ref,a1_25 +R 500,2000,ref_ref,a1_20 +R 500,1500,ref_ref,a1_15 +S 9600,900,9600,1200,300,*,UP,NDIF +S 8500,900,8500,1200,300,*,UP,NDIF +S 6900,3500,6900,4100,300,*,UP,PDIF +S 1500,3300,1500,4100,300,*,UP,PDIF +S 4500,1000,4500,3500,200,cout,DOWN,CALU1 +S 6500,2000,6500,3000,200,a3,DOWN,CALU1 +S 7500,1500,7500,3000,200,cin2,DOWN,CALU1 +S 7000,1500,7000,3000,200,b3,DOWN,CALU1 +S 9000,1500,9000,3000,200,cin3,DOWN,CALU1 +S 9500,1500,9500,3500,200,a4,DOWN,CALU1 +S 10000,1500,10000,3500,200,b4,DOWN,CALU1 +S 5500,1000,5500,3500,200,sout,DOWN,CALU1 +S 3000,1500,3000,3000,200,b2,DOWN,CALU1 +S 2500,1500,2500,3000,200,a2,DOWN,CALU1 +S 2000,1500,2000,3000,200,cin1,DOWN,CALU1 +S 1000,1500,1000,3500,200,b1,DOWN,CALU1 +S 500,1000,500,3500,200,a1,DOWN,CALU1 +S 5300,2000,6000,2000,300,*,LEFT,POLY +S 3900,2000,4700,2000,300,*,RIGHT,POLY +S 0,4700,10500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,10500,3900,2400,*,RIGHT,NWELL +S 0,300,10500,300,600,vss,RIGHT,CALU1 +S 3800,500,3800,1000,200,*,UP,ALU1 +S 3800,4000,6100,4000,100,*,RIGHT,ALU1 +S 4500,950,4500,3550,200,*,UP,ALU1 +S 3800,2000,3900,2000,100,*,RIGHT,ALU1 +S 3800,2000,3800,4000,100,*,UP,ALU1 +S 1500,3500,3800,3500,100,*,LEFT,ALU1 +S 5500,950,5500,3550,200,*,UP,ALU1 +S 6500,1000,6500,1500,100,*,DOWN,ALU1 +S 6000,1500,6500,1500,100,*,RIGHT,ALU1 +S 6500,1000,7900,1000,100,*,RIGHT,ALU1 +S 6000,1500,6000,2000,100,*,DOWN,ALU1 +S 6500,2000,6500,3000,100,*,DOWN,ALU1 +S 6300,3500,6300,4700,300,*,UP,PDIF +S 6300,300,6300,1200,300,*,UP,NDIF +S 8900,3100,8900,4100,100,*,UP,PTRANS +S 8300,3100,8300,4300,100,*,UP,PTRANS +S 8100,4700,9700,4700,300,*,RIGHT,NTIE +S 10200,3300,10200,4000,300,*,UP,PDIF +S 8000,3300,8000,4100,300,*,UP,PDIF +S 8600,3300,8600,4100,200,*,UP,PDIF +S 6600,3300,6600,4300,100,*,UP,PTRANS +S 9400,3100,9400,4100,100,*,UP,PTRANS +S 9200,3300,9200,3900,200,*,UP,PDIF +S 9900,3100,9900,4100,100,*,UP,PTRANS +S 7700,3300,7700,4300,100,*,UP,PTRANS +S 7200,3300,7200,4300,100,*,UP,PTRANS +S 6600,700,6600,1400,100,*,UP,NTRANS +S 8800,700,8800,1400,100,*,UP,NTRANS +S 9300,700,9300,1400,100,*,UP,NTRANS +S 7100,700,7100,1400,100,*,UP,NTRANS +S 10200,1000,10200,1200,300,*,UP,NDIF +S 7600,700,7600,1400,100,*,UP,NTRANS +S 9900,700,9900,1400,100,*,UP,NTRANS +S 7900,900,7900,1200,300,*,UP,NDIF +S 8200,700,8200,1500,100,*,UP,NTRANS +S 6900,400,8400,400,300,*,RIGHT,PTIE +S 9700,400,10100,400,300,*,RIGHT,PTIE +S 8800,2400,8900,2400,100,*,RIGHT,POLY +S 9300,1400,9400,1400,100,*,RIGHT,POLY +S 7600,3300,7700,3300,100,*,RIGHT,POLY +S 8200,3100,8300,3100,100,*,RIGHT,POLY +S 8200,1500,8200,3100,100,*,UP,POLY +S 8900,2500,8900,3100,100,*,DOWN,POLY +S 6600,1400,6600,3300,100,*,UP,POLY +S 7100,1400,7100,3300,100,*,UP,POLY +S 7600,1400,7600,3300,100,*,UP,POLY +S 9400,1400,9400,3100,100,*,UP,POLY +S 9900,1400,9900,3100,100,*,DOWN,POLY +S 8800,1400,8800,2400,100,*,UP,POLY +S 7100,3300,7200,3300,100,*,RIGHT,POLY +S 7000,1500,7000,3000,100,*,DOWN,ALU1 +S 7500,1500,7500,3000,100,*,UP,ALU1 +S 9000,1500,9000,3000,100,*,UP,ALU1 +S 8000,2000,8000,3500,100,*,UP,ALU1 +S 8500,1000,9600,1000,100,*,RIGHT,ALU1 +S 6900,4000,10200,4000,100,*,RIGHT,ALU1 +S 9500,1500,9500,3500,100,*,UP,ALU1 +S 10000,1500,10000,3500,100,*,DOWN,ALU1 +S 6100,3500,6100,4000,100,*,DOWN,ALU1 +S 6100,3500,8000,3500,100,*,RIGHT,ALU1 +S 8500,1500,8500,3550,100,*,UP,ALU1 +S 8000,950,8000,1500,100,*,UP,ALU1 +S 8000,1500,8500,1500,100,*,RIGHT,ALU1 +S 10200,300,10200,1000,200,*,DOWN,ALU1 +S 6200,2800,6200,4700,300,*,DOWN,PDIF +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 5600,2800,5600,4700,300,*,DOWN,PDIF +S 5900,2600,5900,4900,100,*,UP,PTRANS +S 6200,300,6200,1200,300,*,UP,NDIF +S 5300,100,5300,1400,100,*,DOWN,NTRANS +S 5600,300,5600,1200,300,*,UP,NDIF +S 5900,100,5900,1400,100,*,DOWN,NTRANS +S 5300,1400,5300,2600,100,*,UP,POLY +S 5900,1400,5900,2600,100,*,UP,POLY +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 5000,300,5000,1200,300,*,UP,NDIF +S 4700,100,4700,1400,100,*,DOWN,NTRANS +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4700,1400,4700,2600,100,*,UP,POLY +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 900,400,2000,400,300,*,RIGHT,PTIE +S 300,500,300,1300,300,*,UP,NDIF +S 1600,4700,3200,4700,300,*,RIGHT,NTIE +S 1100,700,1100,1600,100,*,UP,NTRANS +S 600,1500,600,3100,100,*,UP,POLY +S 1000,2000,1200,2000,100,*,LEFT,POLY +S 1700,2500,2000,2500,100,*,RIGHT,POLY +S 1700,1400,1700,2500,100,*,UP,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1100,1600,1100,2000,100,*,UP,POLY +S 1200,2000,1200,3100,100,*,UP,POLY +S 2100,2900,2100,4100,200,*,UP,PDIF +S 2900,1400,2900,2700,100,*,UP,POLY +S 2400,1900,2400,2700,100,*,UP,POLY +S 300,3300,300,4050,300,*,UP,PDIF +S 900,3300,900,4450,300,*,UP,PDIF +S 600,3100,600,4300,100,*,UP,PTRANS +S 3200,2900,3200,4100,300,*,UP,PDIF +S 2700,2900,2700,4100,200,*,UP,PDIF +S 2900,2700,2900,4300,100,*,UP,PTRANS +S 2400,2700,2400,4300,100,*,UP,PTRANS +S 1800,3100,1800,4300,100,*,UP,PTRANS +S 1200,3100,1200,4300,100,*,UP,PTRANS +S 2300,1400,2300,1900,100,*,UP,POLY +S 3200,900,3200,1200,300,*,UP,NDIF +S 2600,500,2600,1200,300,*,UP,NDIF +S 2000,900,2000,1200,300,*,UP,NDIF +S 1400,900,1400,1400,300,*,UP,NDIF +S 600,700,600,1500,100,*,UP,NTRANS +S 1700,700,1700,1400,100,*,UP,NTRANS +S 2300,700,2300,1400,100,*,UP,NTRANS +S 2900,700,2900,1400,100,*,UP,NTRANS +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,DOWN,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3800,300,3800,1200,300,*,UP,NDIF +S 4400,300,4400,1200,300,*,UP,NDIF +S 4100,100,4100,1400,100,*,DOWN,NTRANS +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 4100,1400,4100,2600,100,*,UP,POLY +S 7450,3600,7450,4650,200,*,UP,PDIF +S 9050,400,9050,1200,200,*,UP,NDIF +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1700,2500,2000,2500,300,*,LEFT,POLY +S 8000,2000,8200,2000,300,*,RIGHT,POLY +V 3800,1000,CONT_DIF_N,* +V 4400,3500,CONT_DIF_P,* +V 4400,3000,CONT_DIF_P,* +V 4400,1000,CONT_DIF_N,* +V 3900,2000,CONT_POLY,* +V 10200,4000,CONT_DIF_P,* +V 8600,3500,CONT_DIF_P,* +V 9300,4700,CONT_BODY_N,* +V 8900,4700,CONT_BODY_N,* +V 8500,4700,CONT_BODY_N,* +V 8100,4700,CONT_BODY_N,* +V 8000,4000,CONT_DIF_P,* +V 6900,4000,CONT_DIF_P,* +V 9700,4700,CONT_BODY_N,* +V 7900,1000,CONT_DIF_N,* +V 10200,1000,CONT_DIF_N,* +V 9600,1000,CONT_DIF_N,* +V 8500,1000,CONT_DIF_N,* +V 6900,400,CONT_BODY_P,* +V 8450,400,CONT_BODY_P,* +V 10100,400,CONT_BODY_P,* +V 9700,400,CONT_BODY_P,* +V 7900,400,CONT_BODY_P,* +V 7400,400,CONT_BODY_P,* +V 10000,2000,CONT_POLY,* +V 9500,2500,CONT_POLY,* +V 9000,2500,CONT_POLY,* +V 6500,2000,CONT_POLY,* +V 7000,2000,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 8000,2000,CONT_POLY,* +V 6000,2000,CONT_POLY,* +V 5600,3000,CONT_DIF_P,* +V 5600,3500,CONT_DIF_P,* +V 5600,1000,CONT_DIF_N,* +V 6200,500,CONT_DIF_N,* +V 5000,500,CONT_DIF_N,* +V 3800,500,CONT_DIF_N,* +V 6200,4500,CONT_DIF_P,* +V 5000,4500,CONT_DIF_P,* +V 3800,4500,CONT_DIF_P,* +V 1500,400,CONT_BODY_P,* +V 1000,400,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 1600,4700,CONT_BODY_N,* +V 2000,4700,CONT_BODY_N,* +V 2400,4700,CONT_BODY_N,* +V 2800,4700,CONT_BODY_N,* +V 3200,4700,CONT_BODY_N,* +V 3200,400,CONT_BODY_P,* +V 3000,2500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2600,500,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 2000,400,CONT_BODY_P,* +V 2000,2500,CONT_POLY,* +V 1400,1000,CONT_DIF_N,* +V 7450,4600,CONT_DIF_P,* +V 9050,400,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/fulladder_x4.vbe b/alliance/src/cells/src/sxlib/fulladder_x4.vbe new file mode 100644 index 00000000..8c5b5658 --- /dev/null +++ b/alliance/src/cells/src/sxlib/fulladder_x4.vbe @@ -0,0 +1,121 @@ +ENTITY fulladder_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 5250; + CONSTANT cin_a1 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT cin_a3 : NATURAL := 6; + CONSTANT cin_a4 : NATURAL := 6; + CONSTANT cin_b1 : NATURAL := 8; + CONSTANT cin_b2 : NATURAL := 8; + CONSTANT cin_b3 : NATURAL := 6; + CONSTANT cin_b4 : NATURAL := 6; + CONSTANT cin_cin1 : NATURAL := 7; + CONSTANT cin_cin2 : NATURAL := 6; + CONSTANT cin_cin3 : NATURAL := 6; + CONSTANT rdown_a1_cout : NATURAL := 810; + CONSTANT rdown_a1_sout : NATURAL := 810; + CONSTANT rdown_a2_cout : NATURAL := 810; + CONSTANT rdown_a2_sout : NATURAL := 810; + CONSTANT rdown_a3_sout : NATURAL := 810; + CONSTANT rdown_a4_sout : NATURAL := 810; + CONSTANT rdown_b1_cout : NATURAL := 810; + CONSTANT rdown_b1_sout : NATURAL := 810; + CONSTANT rdown_b2_cout : NATURAL := 810; + CONSTANT rdown_b2_sout : NATURAL := 810; + CONSTANT rdown_b3_sout : NATURAL := 810; + CONSTANT rdown_b4_sout : NATURAL := 810; + CONSTANT rdown_cin1_cout : NATURAL := 810; + CONSTANT rdown_cin1_sout : NATURAL := 810; + CONSTANT rdown_cin2_sout : NATURAL := 810; + CONSTANT rdown_cin3_sout : NATURAL := 810; + CONSTANT rup_a1_cout : NATURAL := 890; + CONSTANT rup_a1_sout : NATURAL := 890; + CONSTANT rup_a2_cout : NATURAL := 890; + CONSTANT rup_a2_sout : NATURAL := 890; + CONSTANT rup_a3_sout : NATURAL := 890; + CONSTANT rup_a4_sout : NATURAL := 890; + CONSTANT rup_b1_cout : NATURAL := 890; + CONSTANT rup_b1_sout : NATURAL := 890; + CONSTANT rup_b2_cout : NATURAL := 890; + CONSTANT rup_b2_sout : NATURAL := 890; + CONSTANT rup_b3_sout : NATURAL := 890; + CONSTANT rup_b4_sout : NATURAL := 890; + CONSTANT rup_cin1_cout : NATURAL := 890; + CONSTANT rup_cin1_sout : NATURAL := 890; + CONSTANT rup_cin2_sout : NATURAL := 890; + CONSTANT rup_cin3_sout : NATURAL := 890; + CONSTANT tphh_cin3_sout : NATURAL := 630; + CONSTANT tphh_a4_sout : NATURAL := 673; + CONSTANT tphh_b4_sout : NATURAL := 715; + CONSTANT tphh_a1_cout : NATURAL := 800; + CONSTANT tphh_a2_cout : NATURAL := 801; + CONSTANT tpll_cin1_cout : NATURAL := 830; + CONSTANT tpll_b1_cout : NATURAL := 839; + CONSTANT tpll_a1_cout : NATURAL := 866; + CONSTANT tpll_b2_cout : NATURAL := 883; + CONSTANT tphh_b1_cout : NATURAL := 884; + CONSTANT tphh_b2_cout : NATURAL := 892; + CONSTANT tphh_cin1_cout : NATURAL := 899; + CONSTANT tpll_a2_cout : NATURAL := 924; + CONSTANT tphh_a3_sout : NATURAL := 1086; + CONSTANT tpll_cin2_sout : NATURAL := 1150; + CONSTANT tphh_b3_sout : NATURAL := 1202; + CONSTANT tpll_b3_sout : NATURAL := 1208; + CONSTANT tpll_a3_sout : NATURAL := 1265; + CONSTANT tphh_cin2_sout : NATURAL := 1308; + CONSTANT tpll_b4_sout : NATURAL := 1329; + CONSTANT tpll_a4_sout : NATURAL := 1377; + CONSTANT tpll_cin3_sout : NATURAL := 1417; + CONSTANT tphl_a1_sout : NATURAL := 1471; + CONSTANT tphl_a2_sout : NATURAL := 1472; + CONSTANT tplh_cin1_sout : NATURAL := 1492; + CONSTANT tplh_b1_sout : NATURAL := 1501; + CONSTANT tplh_a1_sout : NATURAL := 1528; + CONSTANT tplh_b2_sout : NATURAL := 1545; + CONSTANT tphl_b1_sout : NATURAL := 1555; + CONSTANT tphl_b2_sout : NATURAL := 1563; + CONSTANT tphl_cin1_sout : NATURAL := 1570; + CONSTANT tplh_a2_sout : NATURAL := 1586; + CONSTANT transistors : NATURAL := 32 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + a4 : in BIT; + b1 : in BIT; + b2 : in BIT; + b3 : in BIT; + b4 : in BIT; + cin1 : in BIT; + cin2 : in BIT; + cin3 : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END fulladder_x4; + +ARCHITECTURE behaviour_data_flow OF fulladder_x4 IS + SIGNAL ncout : BIT; + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on fulladder_x4" + SEVERITY WARNING; + ASSERT (((((a1 and a2) and a3) and a4) or not ((((a1 or a2) or a3) or + a4))) = '1') + REPORT "a1, a2, a3, a4 must be connected together on fulladder_x4" + SEVERITY WARNING; + ASSERT (((((b1 and b2) and b3) and b4) or not ((((b1 or b2) or b3) or + b4))) = '1') + REPORT "b1, b2, b3, b4 must be connected together on fulladder_x4" + SEVERITY WARNING; + ASSERT ((((cin1 and cin2) and cin3) or not (((cin1 or cin2) or cin3))) = '1') + REPORT "cin1, cin2, cin3 must be connected together on fulladder_x4" + SEVERITY WARNING; + ncout <= not (((a1 and b1) or ((a2 or b2) and cin1))); + sout <= (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) after 2200 ps; + cout <= not (ncout) after 1500 ps; +END; diff --git a/alliance/src/cells/src/sxlib/fulladder_x4.vhd b/alliance/src/cells/src/sxlib/fulladder_x4.vhd new file mode 100644 index 00000000..73aa48a2 --- /dev/null +++ b/alliance/src/cells/src/sxlib/fulladder_x4.vhd @@ -0,0 +1,34 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY fulladder_x4 IS +PORT( + a1 : IN STD_LOGIC; + a2 : IN STD_LOGIC; + a3 : IN STD_LOGIC; + a4 : IN STD_LOGIC; + b1 : IN STD_LOGIC; + b2 : IN STD_LOGIC; + b3 : IN STD_LOGIC; + b4 : IN STD_LOGIC; + cin1 : IN STD_LOGIC; + cin2 : IN STD_LOGIC; + cin3 : IN STD_LOGIC; + cout : OUT STD_LOGIC; + sout : OUT STD_LOGIC +); +END fulladder_x4; + +ARCHITECTURE RTL OF fulladder_x4 IS + SIGNAL ncout : STD_LOGIC; + +BEGIN + cout <= NOT(ncout); + sout <= (((a3 AND b3) AND cin2) OR (((a4 OR b4) OR cin3) AND ncout)); + ncout <= NOT(((a1 AND b1) OR ((a2 OR b2) AND cin1))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/halfadder_x2.al b/alliance/src/cells/src/sxlib/halfadder_x2.al new file mode 100644 index 00000000..fab1b263 --- /dev/null +++ b/alliance/src/cells/src/sxlib/halfadder_x2.al @@ -0,0 +1,57 @@ +V ALLIANCE : 6 +H halfadder_x2,L,30/10/99 +C a,UNKNOWN,EXTERNAL,7 +C b,UNKNOWN,EXTERNAL,8 +C cout,OUT,EXTERNAL,4 +C sout,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,3 +T P,0.35,2.6,6,7,1,0,0.75,0.75,6.7,6.7,3.9,11.1,tr_00020 +T P,0.35,5.9,14,9,6,0,0.75,0.75,13.3,13.3,21.9,11.25,tr_00019 +T P,0.35,5.9,4,1,6,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00018 +T P,0.35,3.2,12,8,6,0,0.75,0.75,7.9,7.9,11.1,9.9,tr_00017 +T P,0.35,3.2,6,13,12,0,0.75,0.75,7.9,7.9,16.5,9.9,tr_00016 +T P,0.35,3.2,12,5,9,0,0.75,0.75,7.9,7.9,14.7,9.9,tr_00015 +T P,0.35,3.2,9,7,12,0,0.75,0.75,7.9,7.9,12.9,9.9,tr_00014 +T P,0.35,2.6,1,8,6,0,0.75,0.75,6.7,6.7,5.7,11.1,tr_00013 +T P,0.35,2.3,6,8,5,0,0.75,0.75,6.1,6.1,9.3,9.45,tr_00012 +T P,0.35,3.2,13,7,6,0,0.75,0.75,7.9,7.9,18.3,9.9,tr_00011 +T N,0.35,2.9,3,9,14,0,0.75,0.75,7.3,7.3,21.9,2.25,tr_00010 +T N,0.35,2.9,3,1,4,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00009 +T N,0.35,1.4,3,8,11,0,0.75,0.75,4.3,4.3,11.1,3,tr_00008 +T N,0.35,2,1,8,2,0,0.75,0.75,5.5,5.5,5.7,3.3,tr_00007 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,3.9,3,tr_00006 +T N,0.35,1.7,9,5,10,0,0.75,0.75,4.9,4.9,14.7,3.15,tr_00005 +T N,0.35,1.4,10,7,3,0,0.75,0.75,4.3,4.3,16.5,3,tr_00004 +T N,0.35,1.1,3,7,13,0,0.75,0.75,3.7,3.7,18.3,3.15,tr_00003 +T N,0.35,1.7,11,13,9,0,0.75,0.75,4.9,4.9,12.9,3.15,tr_00002 +T N,0.35,1.1,5,8,3,0,0.75,0.75,3.7,3.7,9.3,3.15,tr_00001 +S 14,EXTERNAL,sout +Q 0.00258522 +S 13,INTERNAL +Q 0.00530432 +S 12,INTERNAL +Q 0.00171257 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.0062563 +S 8,EXTERNAL,b +Q 0.0069823 +S 7,EXTERNAL,a +Q 0.0115667 +S 6,EXTERNAL,vdd +Q 0.00938587 +S 5,INTERNAL +Q 0.00442919 +S 4,EXTERNAL,cout +Q 0.00258522 +S 3,EXTERNAL,vss +Q 0.00832828 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00435733 +EOF diff --git a/alliance/src/cells/src/sxlib/halfadder_x2.ap b/alliance/src/cells/src/sxlib/halfadder_x2.ap new file mode 100644 index 00000000..76802044 --- /dev/null +++ b/alliance/src/cells/src/sxlib/halfadder_x2.ap @@ -0,0 +1,185 @@ +V ALLIANCE : 6 +H halfadder_x2,P,30/ 8/2000,100 +A 0,0,8000,5000 +R 7500,2500,ref_ref,sout_25 +R 7500,2000,ref_ref,sout_20 +R 7500,1500,ref_ref,sout_15 +R 3500,1500,ref_ref,b_15 +R 3500,2000,ref_ref,b_20 +R 3500,2500,ref_ref,b_25 +R 3500,3000,ref_ref,b_30 +R 7500,4000,ref_ref,sout_40 +R 7500,1000,ref_ref,sout_10 +R 7500,3000,ref_ref,sout_30 +R 7500,3500,ref_ref,sout_35 +R 1000,3500,ref_ref,a_35 +R 1000,4000,ref_ref,a_40 +R 1000,1000,ref_ref,a_10 +R 1000,1500,ref_ref,a_15 +R 1000,2500,ref_ref,a_25 +R 1000,2000,ref_ref,a_20 +R 3500,3500,ref_ref,b_35 +R 3500,1000,ref_ref,b_10 +R 500,4000,ref_ref,cout_40 +R 500,1000,ref_ref,cout_10 +R 500,3000,ref_ref,cout_30 +R 500,3500,ref_ref,cout_35 +R 500,2500,ref_ref,cout_25 +R 500,2000,ref_ref,cout_20 +R 500,1500,ref_ref,cout_15 +R 1000,3000,ref_ref,a_30 +S 7500,1000,7500,4000,200,*,DOWN,ALU1 +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 5200,2800,5200,3800,300,*,DOWN,PDIF +S 3400,2800,3400,4500,300,*,DOWN,PDIF +S 5800,2800,5800,4500,300,*,DOWN,PDIF +S 2800,2800,2800,3500,300,*,UP,PDIF +S 6400,2800,6400,3800,300,*,DOWN,PDIF +S 6100,2600,6100,4000,100,*,UP,PTRANS +S 3100,2600,3100,3700,100,*,UP,PTRANS +S 0,3900,8000,3900,2400,*,LEFT,NWELL +S 1900,3100,1900,4300,100,*,DOWN,PTRANS +S 1600,3300,1600,4100,300,*,UP,PDIF +S 4300,2600,4300,4000,100,*,UP,PTRANS +S 4900,2600,4900,4000,100,*,UP,PTRANS +S 5500,2600,5500,4000,100,*,UP,PTRANS +S 3700,2600,3700,4000,100,*,UP,PTRANS +S 4000,2800,4000,3800,300,*,DOWN,PDIF +S 4600,2800,4600,3800,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,DOWN,PTRANS +S 2200,3300,2200,4600,300,*,UP,PDIF +S 400,2800,400,4700,300,*,UP,PDIF +S 1000,2800,1000,4700,300,*,UP,PDIF +S 7000,3400,7000,4700,300,*,DOWN,PDIF +S 7600,2800,7600,4700,300,*,DOWN,PDIF +S 7300,2600,7300,4900,100,*,UP,PTRANS +S 1300,3100,1300,4300,100,*,DOWN,PTRANS +S 3100,700,3100,1400,100,*,DOWN,NTRANS +S 4300,600,4300,1500,100,*,DOWN,NTRANS +S 4600,800,4600,1300,300,*,UP,NDIF +S 4000,800,4000,1300,300,*,UP,NDIF +S 5200,800,5200,1300,300,*,UP,NDIF +S 6100,700,6100,1400,100,*,DOWN,NTRANS +S 6400,900,6400,1600,300,*,UP,NDIF +S 5500,600,5500,1400,100,*,DOWN,NTRANS +S 2800,1000,2800,1200,300,*,UP,NDIF +S 3400,400,3400,1200,300,*,UP,NDIF +S 5800,400,5800,1200,300,*,UP,NDIF +S 4900,600,4900,1500,100,*,DOWN,NTRANS +S 1300,600,1300,1400,100,*,UP,NTRANS +S 1900,600,1900,1600,100,*,UP,NTRANS +S 2200,800,2200,1400,300,*,DOWN,NDIF +S 1600,800,1600,1400,300,*,DOWN,NDIF +S 3700,600,3700,1400,100,*,DOWN,NTRANS +S 1000,300,1000,1200,300,*,DOWN,NDIF +S 400,300,400,1200,300,*,DOWN,NDIF +S 700,100,700,1400,100,*,UP,NTRANS +S 7000,300,7000,1000,300,*,UP,NDIF +S 7600,300,7600,1200,300,*,UP,NDIF +S 7300,100,7300,1400,100,*,DOWN,NTRANS +S 4900,1500,4900,2600,100,*,DOWN,POLY +S 7000,2000,7300,2000,300,*,RIGHT,POLY +S 4300,1500,4600,1500,100,*,RIGHT,POLY +S 7300,1400,7300,2600,100,*,DOWN,POLY +S 1900,2000,2000,2000,100,*,RIGHT,POLY +S 1900,1600,1900,2000,100,*,UP,POLY +S 1000,2500,1300,2500,300,*,RIGHT,POLY +S 3100,2600,3700,2600,100,*,RIGHT,POLY +S 3100,1400,3700,1400,100,*,RIGHT,POLY +S 2800,2000,4900,2000,100,*,RIGHT,POLY +S 5500,1400,6100,1400,100,*,RIGHT,POLY +S 5500,2000,5500,2600,100,*,DOWN,POLY +S 5500,2000,6500,2000,100,*,RIGHT,POLY +S 4300,2600,4600,2600,100,*,RIGHT,POLY +S 1000,1500,1300,1500,300,*,RIGHT,POLY +S 700,2000,1500,2000,100,*,RIGHT,POLY +S 1300,2400,1300,3100,100,*,UP,POLY +S 700,1400,700,2600,100,*,DOWN,POLY +S 0,300,8000,300,600,vss,RIGHT,CALU1 +S 5000,1600,5000,2000,100,*,DOWN,ALU1 +S 0,4700,8000,4700,600,vdd,RIGHT,CALU1 +S 7000,1000,7000,2000,100,*,DOWN,ALU1 +S 7000,3500,7000,4500,200,*,DOWN,ALU1 +S 6000,1500,6000,4000,100,*,DOWN,ALU1 +S 6500,1500,6500,2900,100,*,DOWN,ALU1 +S 2100,3500,3500,3500,100,*,RIGHT,ALU1 +S 2100,3000,2100,3500,100,*,DOWN,ALU1 +S 2000,3000,2100,3000,100,*,LEFT,ALU1 +S 4500,1600,5000,1600,100,*,RIGHT,ALU1 +S 5200,3000,5200,3500,100,*,DOWN,ALU1 +S 2800,1000,2800,3000,100,*,DOWN,ALU1 +S 4000,3000,4600,3000,100,*,LEFT,ALU1 +S 4000,1000,4000,3000,100,*,UP,ALU1 +S 5000,2000,5500,2000,100,*,RIGHT,ALU1 +S 4500,2500,6000,2500,100,*,RIGHT,ALU1 +S 4000,1000,7000,1000,100,*,RIGHT,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1550,1000,1550,3500,100,*,UP,ALU1 +S 1000,4000,6000,4000,100,*,RIGHT,ALU1 +S 1550,1000,2200,1000,100,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 3500,1000,3500,3500,100,*,UP,ALU1 +S 4000,3500,5200,3500,100,*,RIGHT,ALU1 +S 7500,1000,7500,4000,200,sout,DOWN,CALU1 +S 3500,1000,3500,3500,200,b,DOWN,CALU1 +S 1000,1000,1000,4000,200,a,DOWN,CALU1 +S 500,1000,500,4000,200,cout,DOWN,CALU1 +V 4000,4700,CONT_BODY_N,* +V 5200,4700,CONT_BODY_N,* +V 7000,3500,CONT_DIF_P,* +V 2800,3000,CONT_DIF_P,* +V 6500,2900,CONT_DIF_P,* +V 7600,3000,CONT_DIF_P,* +V 7600,3500,CONT_DIF_P,* +V 7600,4000,CONT_DIF_P,* +V 7000,4500,CONT_DIF_P,* +V 4600,4700,CONT_BODY_N,* +V 4600,3000,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 5800,4500,CONT_DIF_P,* +V 2800,4700,CONT_BODY_N,* +V 6400,4700,CONT_BODY_N,* +V 4000,3500,CONT_DIF_P,* +V 5200,3500,CONT_DIF_P,* +V 7000,4000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +V 2200,4500,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 400,4000,CONT_DIF_P,* +V 1600,4700,CONT_BODY_N,* +V 1000,4500,CONT_DIF_P,* +V 5200,3000,CONT_DIF_P,* +V 7600,1000,CONT_DIF_N,* +V 7000,500,CONT_DIF_N,* +V 4600,1100,CONT_DIF_N,* +V 1000,500,CONT_DIF_N,* +V 2200,1000,CONT_DIF_N,* +V 400,1000,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 5800,500,CONT_DIF_N,* +V 6500,1500,CONT_DIF_N,* +V 2200,300,CONT_BODY_P,* +V 2800,300,CONT_BODY_P,* +V 6400,300,CONT_BODY_P,* +V 4600,300,CONT_BODY_P,* +V 5200,300,CONT_BODY_P,* +V 4000,300,CONT_BODY_P,* +V 1600,300,CONT_BODY_P,* +V 7000,2000,CONT_POLY,* +V 5500,2000,CONT_POLY,* +V 6500,2000,CONT_POLY,* +V 6000,2500,CONT_POLY,* +V 4500,1600,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1100,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 6000,1500,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2800,2000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 1100,1500,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/halfadder_x2.vbe b/alliance/src/cells/src/sxlib/halfadder_x2.vbe new file mode 100644 index 00000000..13966fa6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/halfadder_x2.vbe @@ -0,0 +1,50 @@ +ENTITY halfadder_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 27; + CONSTANT cin_b : NATURAL := 22; + CONSTANT rdown_a_cout : NATURAL := 1620; + CONSTANT rdown_a_sout : NATURAL := 1620; + CONSTANT rdown_a_sout : NATURAL := 1620; + CONSTANT rdown_b_cout : NATURAL := 1620; + CONSTANT rdown_b_sout : NATURAL := 1620; + CONSTANT rdown_b_sout : NATURAL := 1620; + CONSTANT rup_a_cout : NATURAL := 1790; + CONSTANT rup_a_sout : NATURAL := 1790; + CONSTANT rup_a_sout : NATURAL := 1790; + CONSTANT rup_b_cout : NATURAL := 1790; + CONSTANT rup_b_sout : NATURAL := 1790; + CONSTANT rup_b_sout : NATURAL := 1790; + CONSTANT tphh_a_cout : NATURAL := 361; + CONSTANT tpll_b_cout : NATURAL := 383; + CONSTANT tphh_b_cout : NATURAL := 386; + CONSTANT tpll_a_cout : NATURAL := 398; + CONSTANT tphh_a_sout : NATURAL := 421; + CONSTANT tpll_b_sout : NATURAL := 497; + CONSTANT tphl_b_sout : NATURAL := 531; + CONSTANT tplh_b_sout : NATURAL := 556; + CONSTANT tphh_b_sout : NATURAL := 558; + CONSTANT tpll_a_sout : NATURAL := 562; + CONSTANT tphl_a_sout : NATURAL := 575; + CONSTANT tplh_a_sout : NATURAL := 607; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + a : in BIT; + b : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END halfadder_x2; + +ARCHITECTURE behaviour_data_flow OF halfadder_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on halfadder_x2" + SEVERITY WARNING; + sout <= (a xor b) after 1200 ps; + cout <= (a and b) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/halfadder_x2.vhd b/alliance/src/cells/src/sxlib/halfadder_x2.vhd new file mode 100644 index 00000000..9ca38530 --- /dev/null +++ b/alliance/src/cells/src/sxlib/halfadder_x2.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY halfadder_x2 IS +PORT( + a : IN STD_LOGIC; + b : IN STD_LOGIC; + cout : OUT STD_LOGIC; + sout : OUT STD_LOGIC +); +END halfadder_x2; + +ARCHITECTURE RTL OF halfadder_x2 IS +BEGIN + cout <= (a AND b); + sout <= (a XOR b); +END RTL; diff --git a/alliance/src/cells/src/sxlib/halfadder_x4.al b/alliance/src/cells/src/sxlib/halfadder_x4.al new file mode 100644 index 00000000..4d1b8f27 --- /dev/null +++ b/alliance/src/cells/src/sxlib/halfadder_x4.al @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H halfadder_x4,L,30/10/99 +C a,UNKNOWN,EXTERNAL,6 +C b,UNKNOWN,EXTERNAL,7 +C cout,OUT,EXTERNAL,1 +C sout,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,4,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00024 +T P,0.35,5.9,1,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00023 +T P,0.35,5.9,5,9,14,0,0.75,0.75,13.3,13.3,25.2,11.25,tr_00022 +T P,0.35,5.9,14,9,5,0,0.75,0.75,13.3,13.3,23.4,11.25,tr_00021 +T P,0.35,2.6,5,6,4,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00020 +T P,0.35,2.6,4,7,5,0,0.75,0.75,6.7,6.7,7.2,11.1,tr_00019 +T P,0.35,3.2,9,6,12,0,0.75,0.75,7.9,7.9,14.4,9.9,tr_00018 +T P,0.35,3.2,12,11,9,0,0.75,0.75,7.9,7.9,16.2,9.9,tr_00017 +T P,0.35,3.2,5,13,12,0,0.75,0.75,7.9,7.9,18,9.9,tr_00016 +T P,0.35,3.2,12,7,5,0,0.75,0.75,7.9,7.9,12.6,9.9,tr_00015 +T P,0.35,3.2,13,6,5,0,0.75,0.75,7.9,7.9,19.8,9.9,tr_00014 +T P,0.35,2.3,5,7,11,0,0.75,0.75,6.1,6.1,10.8,9.45,tr_00013 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00012 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00011 +T N,0.35,2.9,14,9,2,0,0.75,0.75,7.3,7.3,25.2,2.25,tr_00010 +T N,0.35,2.9,2,9,14,0,0.75,0.75,7.3,7.3,23.4,2.25,tr_00009 +T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00008 +T N,0.35,2,4,7,3,0,0.75,0.75,5.5,5.5,7.2,3.3,tr_00007 +T N,0.35,1.4,2,7,8,0,0.75,0.75,4.3,4.3,12.6,3,tr_00006 +T N,0.35,1.4,10,6,2,0,0.75,0.75,4.3,4.3,18,3,tr_00005 +T N,0.35,1.7,9,11,10,0,0.75,0.75,4.9,4.9,16.2,3.15,tr_00004 +T N,0.35,1.7,8,13,9,0,0.75,0.75,4.9,4.9,14.4,3.15,tr_00003 +T N,0.35,1.1,2,6,13,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00002 +T N,0.35,1.1,11,7,2,0,0.75,0.75,3.7,3.7,10.8,3.15,tr_00001 +S 14,EXTERNAL,sout +Q 0.00258522 +S 13,INTERNAL +Q 0.00530431 +S 12,INTERNAL +Q 0.00171257 +S 11,INTERNAL +Q 0.00442919 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.00752047 +S 8,INTERNAL +Q 0 +S 7,EXTERNAL,b +Q 0.0069823 +S 6,EXTERNAL,a +Q 0.0115667 +S 5,EXTERNAL,vdd +Q 0.0134766 +S 4,INTERNAL +Q 0.00589885 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.011949 +S 1,EXTERNAL,cout +Q 0.00258522 +EOF diff --git a/alliance/src/cells/src/sxlib/halfadder_x4.ap b/alliance/src/cells/src/sxlib/halfadder_x4.ap new file mode 100644 index 00000000..8a9ab130 --- /dev/null +++ b/alliance/src/cells/src/sxlib/halfadder_x4.ap @@ -0,0 +1,216 @@ +V ALLIANCE : 6 +H halfadder_x4,P, 6/ 9/2000,100 +A 0,0,9000,5000 +R 1000,4000,ref_ref,cout_40 +R 1000,1000,ref_ref,cout_10 +R 1000,3000,ref_ref,cout_30 +R 1000,3500,ref_ref,cout_35 +R 1000,2500,ref_ref,cout_25 +R 1000,2000,ref_ref,cout_20 +R 1000,1500,ref_ref,cout_15 +R 1500,3000,ref_ref,a_30 +R 1500,3500,ref_ref,a_35 +R 1500,4000,ref_ref,a_40 +R 1500,1000,ref_ref,a_10 +R 1500,1500,ref_ref,a_15 +R 1500,2500,ref_ref,a_25 +R 1500,2000,ref_ref,a_20 +R 4000,3500,ref_ref,b_35 +R 4000,1000,ref_ref,b_10 +R 4000,1500,ref_ref,b_15 +R 4000,2000,ref_ref,b_20 +R 4000,2500,ref_ref,b_25 +R 4000,3000,ref_ref,b_30 +R 8000,4000,ref_ref,sout_40 +R 8000,1000,ref_ref,sout_10 +R 8000,3000,ref_ref,sout_30 +R 8000,3500,ref_ref,sout_35 +R 8000,2500,ref_ref,sout_25 +R 8000,2000,ref_ref,sout_20 +R 8000,1500,ref_ref,sout_15 +S 7500,2000,8400,2000,300,*,RIGHT,POLY +S 1000,1000,1000,4000,200,cout,DOWN,CALU1 +S 1500,1000,1500,4000,200,a,DOWN,CALU1 +S 4000,1000,4000,3500,200,b,DOWN,CALU1 +S 8000,1000,8000,4000,200,sout,DOWN,CALU1 +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 2700,3300,2700,4600,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 8400,2600,8400,4900,100,*,UP,PTRANS +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 7500,3400,7500,4700,300,*,DOWN,PDIF +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 7800,2600,7800,4900,100,*,UP,PTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 7500,300,7500,1000,300,*,UP,NDIF +S 8700,300,8700,1200,300,*,UP,NDIF +S 8100,300,8100,1200,300,*,UP,NDIF +S 8400,100,8400,1400,100,*,DOWN,NTRANS +S 7800,100,7800,1400,100,*,DOWN,NTRANS +S 600,1400,600,2600,100,*,DOWN,POLY +S 1500,1500,1800,1500,300,*,RIGHT,POLY +S 1200,2000,2000,2000,100,*,RIGHT,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1500,2500,1800,2500,300,*,RIGHT,POLY +S 3600,2600,4200,2600,100,*,RIGHT,POLY +S 3600,1400,4200,1400,100,*,RIGHT,POLY +S 3300,2000,5400,2000,100,*,RIGHT,POLY +S 6000,1400,6600,1400,100,*,RIGHT,POLY +S 6000,2000,6000,2600,100,*,DOWN,POLY +S 6000,2000,7000,2000,100,*,RIGHT,POLY +S 4800,2600,5100,2600,100,*,RIGHT,POLY +S 7800,1400,7800,2600,100,*,DOWN,POLY +S 8400,1400,8400,2600,100,*,DOWN,POLY +S 0,300,9000,300,600,vss,RIGHT,CALU1 +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 300,1000,300,1700,200,*,UP,ALU1 +S 0,4700,9000,4700,600,vdd,RIGHT,CALU1 +S 2500,2000,2500,3000,100,*,UP,ALU1 +S 2050,1000,2050,3500,100,*,UP,ALU1 +S 1500,4000,6500,4000,100,*,RIGHT,ALU1 +S 2050,1000,2700,1000,100,*,RIGHT,ALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 4000,1000,4000,3500,100,*,UP,ALU1 +S 4500,3500,5700,3500,100,*,RIGHT,ALU1 +S 5700,3000,5700,3500,100,*,DOWN,ALU1 +S 3300,1000,3300,3000,100,*,DOWN,ALU1 +S 4500,3000,5100,3000,100,*,LEFT,ALU1 +S 4500,1000,4500,3000,100,*,UP,ALU1 +S 8700,1000,8700,1700,200,*,UP,ALU1 +S 5500,2000,6000,2000,100,*,RIGHT,ALU1 +S 5000,2500,6500,2500,100,*,RIGHT,ALU1 +S 4500,1000,7500,1000,100,*,RIGHT,ALU1 +S 7500,1000,7500,2000,100,*,DOWN,ALU1 +S 8700,500,8700,1000,200,*,DOWN,ALU1 +S 8700,3000,8700,4500,200,*,DOWN,ALU1 +S 7500,3500,7500,4500,200,*,DOWN,ALU1 +S 6500,1500,6500,4000,100,*,DOWN,ALU1 +S 7000,1500,7000,2900,100,*,DOWN,ALU1 +S 2600,3500,4000,3500,100,*,RIGHT,ALU1 +S 2600,3000,2600,3500,100,*,DOWN,ALU1 +S 2500,3000,2600,3000,100,*,LEFT,ALU1 +S 600,2000,1200,2000,300,*,LEFT,POLY +S 2400,2000,2500,2000,100,*,RIGHT,POLY +S 1800,600,1800,1400,100,*,UP,NTRANS +S 1800,3100,1800,4300,100,*,DOWN,PTRANS +S 2400,3100,2400,4300,100,*,DOWN,PTRANS +S 2100,3300,2100,4100,300,*,UP,PDIF +S 2400,1600,2400,2000,100,*,UP,POLY +S 2400,600,2400,1600,100,*,UP,NTRANS +S 2700,800,2700,1400,300,*,DOWN,NDIF +S 2100,800,2100,1400,300,*,DOWN,NDIF +S 4200,600,4200,1400,100,*,DOWN,NTRANS +S 6000,600,6000,1400,100,*,DOWN,NTRANS +S 4800,2600,4800,4000,100,*,UP,PTRANS +S 5400,2600,5400,4000,100,*,UP,PTRANS +S 6000,2600,6000,4000,100,*,UP,PTRANS +S 4200,2600,4200,4000,100,*,UP,PTRANS +S 3300,1000,3300,1200,300,*,UP,NDIF +S 3900,400,3900,1200,300,*,UP,NDIF +S 6300,400,6300,1200,300,*,UP,NDIF +S 5000,1600,5500,1600,100,*,RIGHT,ALU1 +S 4800,1500,5100,1500,100,*,RIGHT,POLY +S 5400,600,5400,1500,100,*,DOWN,NTRANS +S 4800,600,4800,1500,100,*,DOWN,NTRANS +S 5100,800,5100,1300,300,*,UP,NDIF +S 4500,800,4500,1300,300,*,UP,NDIF +S 5700,800,5700,1300,300,*,UP,NDIF +S 5500,1600,5500,2000,100,*,DOWN,ALU1 +S 4500,2800,4500,3800,300,*,DOWN,PDIF +S 5100,2800,5100,3800,300,*,DOWN,PDIF +S 5700,2800,5700,3800,300,*,DOWN,PDIF +S 3900,2800,3900,4500,300,*,DOWN,PDIF +S 6300,2800,6300,4500,300,*,DOWN,PDIF +S 0,3900,9000,3900,2400,*,LEFT,NWELL +S 5400,1500,5400,2600,100,*,DOWN,POLY +S 6600,700,6600,1400,100,*,DOWN,NTRANS +S 6900,900,6900,1600,300,*,UP,NDIF +S 3300,2800,3300,3500,300,*,UP,PDIF +S 6900,2800,6900,3800,300,*,DOWN,PDIF +S 6600,2600,6600,4000,100,*,UP,PTRANS +S 3600,700,3600,1400,100,*,DOWN,NTRANS +S 3600,2600,3600,3700,100,*,UP,PTRANS +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 8000,1000,8000,4000,200,*,DOWN,ALU1 +V 300,4500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,3000,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 2100,4700,CONT_BODY_N,* +V 1500,4500,CONT_DIF_P,* +V 5700,3000,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 6300,4500,CONT_DIF_P,* +V 3300,4700,CONT_BODY_N,* +V 6900,4700,CONT_BODY_N,* +V 4500,3500,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 7500,4000,CONT_DIF_P,* +V 7500,3500,CONT_DIF_P,* +V 8700,3000,CONT_DIF_P,* +V 8700,3500,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 8700,4500,CONT_DIF_P,* +V 3300,3000,CONT_DIF_P,* +V 7000,2900,CONT_DIF_P,* +V 8100,3000,CONT_DIF_P,* +V 8100,3500,CONT_DIF_P,* +V 8100,4000,CONT_DIF_P,* +V 7500,4500,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 6300,500,CONT_DIF_N,* +V 7000,1500,CONT_DIF_N,* +V 8100,1000,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 8700,500,CONT_DIF_N,* +V 7500,500,CONT_DIF_N,* +V 2700,300,CONT_BODY_P,* +V 300,1700,CONT_BODY_P,* +V 3300,300,CONT_BODY_P,* +V 6900,300,CONT_BODY_P,* +V 8700,1700,CONT_BODY_P,* +V 2500,3000,CONT_POLY,* +V 1600,1500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 1600,2500,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 6500,1500,CONT_POLY,* +V 5000,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 4000,1500,CONT_POLY,* +V 3300,2000,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 6000,2000,CONT_POLY,* +V 7000,2000,CONT_POLY,* +V 6500,2500,CONT_POLY,* +V 5000,1600,CONT_POLY,* +V 5100,1100,CONT_DIF_N,* +V 5100,300,CONT_BODY_P,* +V 5700,300,CONT_BODY_P,* +V 4500,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 5100,4700,CONT_BODY_N,* +V 4500,4700,CONT_BODY_N,* +V 5700,4700,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/halfadder_x4.vbe b/alliance/src/cells/src/sxlib/halfadder_x4.vbe new file mode 100644 index 00000000..bbb062f9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/halfadder_x4.vbe @@ -0,0 +1,50 @@ +ENTITY halfadder_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_a : NATURAL := 27; + CONSTANT cin_b : NATURAL := 22; + CONSTANT rdown_a_cout : NATURAL := 810; + CONSTANT rdown_a_sout : NATURAL := 810; + CONSTANT rdown_a_sout : NATURAL := 810; + CONSTANT rdown_b_cout : NATURAL := 810; + CONSTANT rdown_b_sout : NATURAL := 810; + CONSTANT rdown_b_sout : NATURAL := 810; + CONSTANT rup_a_cout : NATURAL := 890; + CONSTANT rup_a_sout : NATURAL := 890; + CONSTANT rup_a_sout : NATURAL := 890; + CONSTANT rup_b_cout : NATURAL := 890; + CONSTANT rup_b_sout : NATURAL := 890; + CONSTANT rup_b_sout : NATURAL := 890; + CONSTANT tphh_a_cout : NATURAL := 467; + CONSTANT tpll_b_cout : NATURAL := 480; + CONSTANT tpll_a_cout : NATURAL := 494; + CONSTANT tphh_b_cout : NATURAL := 500; + CONSTANT tphh_a_sout : NATURAL := 527; + CONSTANT tpll_b_sout : NATURAL := 594; + CONSTANT tphl_b_sout : NATURAL := 607; + CONSTANT tplh_b_sout : NATURAL := 642; + CONSTANT tphh_b_sout : NATURAL := 655; + CONSTANT tphl_a_sout : NATURAL := 656; + CONSTANT tpll_a_sout : NATURAL := 665; + CONSTANT tplh_a_sout : NATURAL := 692; + CONSTANT transistors : NATURAL := 24 +); +PORT ( + a : in BIT; + b : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END halfadder_x4; + +ARCHITECTURE behaviour_data_flow OF halfadder_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on halfadder_x4" + SEVERITY WARNING; + sout <= (a xor b) after 1300 ps; + cout <= (a and b) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/halfadder_x4.vhd b/alliance/src/cells/src/sxlib/halfadder_x4.vhd new file mode 100644 index 00000000..f253a47b --- /dev/null +++ b/alliance/src/cells/src/sxlib/halfadder_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY halfadder_x4 IS +PORT( + a : IN STD_LOGIC; + b : IN STD_LOGIC; + cout : OUT STD_LOGIC; + sout : OUT STD_LOGIC +); +END halfadder_x4; + +ARCHITECTURE RTL OF halfadder_x4 IS +BEGIN + cout <= (a AND b); + sout <= (a XOR b); +END RTL; diff --git a/alliance/src/cells/src/sxlib/inv_x1.al b/alliance/src/cells/src/sxlib/inv_x1.al new file mode 100644 index 00000000..5ae39942 --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x1.al @@ -0,0 +1,17 @@ +V ALLIANCE : 6 +H inv_x1,L,30/10/99 +C i,IN,EXTERNAL,4 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,2.1,9.75,tr_00002 +T N,0.35,1.4,1,4,2,0,0.75,0.75,4.3,4.3,2.1,3,tr_00001 +S 4,EXTERNAL,i +Q 0.00353623 +S 3,EXTERNAL,vdd +Q 0.00230273 +S 2,EXTERNAL,nq +Q 0.00240895 +S 1,EXTERNAL,vss +Q 0.00230273 +EOF diff --git a/alliance/src/cells/src/sxlib/inv_x1.ap b/alliance/src/cells/src/sxlib/inv_x1.ap new file mode 100644 index 00000000..2c3572d7 --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x1.ap @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H inv_x1,P,30/ 8/2000,100 +A 0,0,1500,5000 +R 1000,4000,ref_ref,nq_40 +R 1000,3500,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_30 +R 1000,2500,ref_ref,nq_25 +R 1000,2000,ref_ref,nq_20 +R 1000,1500,ref_ref,nq_15 +R 1000,1000,ref_ref,nq_10 +R 500,1000,ref_ref,i_10 +R 500,1500,ref_ref,i_15 +R 500,2000,ref_ref,i_20 +R 500,2500,ref_ref,i_25 +R 500,3000,ref_ref,i_30 +R 500,3500,ref_ref,i_35 +R 500,4000,ref_ref,i_40 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1000,2800,1000,3700,300,*,DOWN,PDIF +S 700,2600,700,3900,100,*,UP,PTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 400,2000,700,2000,300,*,RIGHT,POLY +S 700,1400,700,2600,100,*,UP,POLY +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 350,400,350,1200,400,*,UP,NDIF +S 350,2800,350,4600,400,*,DOWN,PDIF +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +V 1000,3000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 400,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 1000,4700,CONT_BODY_N,* +V 1000,300,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/inv_x1.sym b/alliance/src/cells/src/sxlib/inv_x1.sym new file mode 100644 index 00000000..dc735e9d Binary files /dev/null and b/alliance/src/cells/src/sxlib/inv_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/inv_x1.vbe b/alliance/src/cells/src/sxlib/inv_x1.vbe new file mode 100644 index 00000000..67e85e02 --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x1.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_i_nq : NATURAL := 3640; + CONSTANT rup_i_nq : NATURAL := 3720; + CONSTANT tphl_i_nq : NATURAL := 101; + CONSTANT tplh_i_nq : NATURAL := 139; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x1; + +ARCHITECTURE behaviour_data_flow OF inv_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x1" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/alliance/src/cells/src/sxlib/inv_x1.vhd b/alliance/src/cells/src/sxlib/inv_x1.vhd new file mode 100644 index 00000000..92c2d59a --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x1.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY inv_x1 IS +PORT( + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END inv_x1; + +ARCHITECTURE RTL OF inv_x1 IS +BEGIN + nq <= NOT(i); +END RTL; diff --git a/alliance/src/cells/src/sxlib/inv_x2.al b/alliance/src/cells/src/sxlib/inv_x2.al new file mode 100644 index 00000000..c02fcb01 --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x2.al @@ -0,0 +1,17 @@ +V ALLIANCE : 6 +H inv_x2,L,30/10/99 +C i,IN,EXTERNAL,4 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,2 +T P,0.35,4.4,1,4,3,0,0.75,0.75,10.3,10.3,2.1,10.5,tr_00002 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00001 +S 4,EXTERNAL,i +Q 0.0031892 +S 3,EXTERNAL,vdd +Q 0.00230273 +S 2,EXTERNAL,vss +Q 0.00230273 +S 1,EXTERNAL,nq +Q 0.00276148 +EOF diff --git a/alliance/src/cells/src/sxlib/inv_x2.ap b/alliance/src/cells/src/sxlib/inv_x2.ap new file mode 100644 index 00000000..4cd20dba --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x2.ap @@ -0,0 +1,43 @@ +V ALLIANCE : 6 +H inv_x2,P,30/ 8/2000,100 +A 0,0,1500,5000 +R 500,4000,ref_ref,i_40 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 500,2500,ref_ref,i_25 +R 500,2000,ref_ref,i_20 +R 500,1500,ref_ref,i_15 +R 500,1000,ref_ref,i_10 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 400,2000,700,2000,300,*,RIGHT,POLY +S 700,2600,700,4400,100,*,UP,PTRANS +S 1000,2800,1000,4200,300,*,DOWN,PDIF +S 700,1900,700,2600,100,*,UP,POLY +S 700,600,700,1900,100,*,DOWN,NTRANS +S 1000,800,1000,1700,300,*,UP,NDIF +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 350,400,350,1700,400,*,UP,NDIF +S 350,2800,350,4600,400,*,DOWN,PDIF +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +V 500,2000,CONT_POLY,* +V 1000,1000,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1000,3500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 1000,1500,CONT_DIF_N,* +V 1000,4700,CONT_BODY_N,* +V 1000,300,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/inv_x2.sym b/alliance/src/cells/src/sxlib/inv_x2.sym new file mode 100644 index 00000000..93f40e69 Binary files /dev/null and b/alliance/src/cells/src/sxlib/inv_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/inv_x2.vbe b/alliance/src/cells/src/sxlib/inv_x2.vbe new file mode 100644 index 00000000..9df0116d --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x2.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 12; + CONSTANT rdown_i_nq : NATURAL := 1620; + CONSTANT rup_i_nq : NATURAL := 2420; + CONSTANT tphl_i_nq : NATURAL := 69; + CONSTANT tplh_i_nq : NATURAL := 163; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x2; + +ARCHITECTURE behaviour_data_flow OF inv_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x2" + SEVERITY WARNING; + nq <= not (i) after 800 ps; +END; diff --git a/alliance/src/cells/src/sxlib/inv_x2.vhd b/alliance/src/cells/src/sxlib/inv_x2.vhd new file mode 100644 index 00000000..d4b14dd6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x2.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY inv_x2 IS +PORT( + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END inv_x2; + +ARCHITECTURE RTL OF inv_x2 IS +BEGIN + nq <= NOT(i); +END RTL; diff --git a/alliance/src/cells/src/sxlib/inv_x4.al b/alliance/src/cells/src/sxlib/inv_x4.al new file mode 100644 index 00000000..bb87114c --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x4.al @@ -0,0 +1,19 @@ +V ALLIANCE : 6 +H inv_x4,L,30/10/99 +C i,IN,EXTERNAL,4 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,2 +T P,0.35,4.1,3,4,1,0,0.75,0.75,9.7,9.7,3.9,12.15,tr_00004 +T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00003 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00002 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00001 +S 4,EXTERNAL,i +Q 0.00530442 +S 3,EXTERNAL,vdd +Q 0.00423058 +S 2,EXTERNAL,vss +Q 0.0038193 +S 1,EXTERNAL,nq +Q 0.00258522 +EOF diff --git a/alliance/src/cells/src/sxlib/inv_x4.ap b/alliance/src/cells/src/sxlib/inv_x4.ap new file mode 100644 index 00000000..a9cd56af --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x4.ap @@ -0,0 +1,54 @@ +V ALLIANCE : 6 +H inv_x4,P,30/ 8/2000,100 +A 0,0,2000,5000 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +R 500,4000,ref_ref,i_40 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 500,2500,ref_ref,i_25 +R 500,2000,ref_ref,i_20 +R 500,1500,ref_ref,i_15 +R 500,1000,ref_ref,i_10 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 0,3900,2000,3900,2400,*,LEFT,NWELL +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 1600,2900,1600,4500,200,*,DOWN,ALU1 +S 1600,500,1600,1700,200,*,DOWN,ALU1 +S 1600,3400,1600,4700,300,*,DOWN,PDIF +S 1300,1400,1300,3200,100,*,UP,POLY +S 1300,3200,1300,4900,100,*,UP,PTRANS +S 400,300,400,1200,300,*,UP,NDIF +S 1000,300,1000,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1300,100,1300,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 500,1500,1300,1500,300,*,RIGHT,POLY +S 400,2800,400,4700,300,*,DOWN,PDIF +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 700,1400,700,2600,100,*,UP,POLY +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +V 1600,2900,CONT_BODY_N,* +V 1600,1700,CONT_BODY_P,* +V 400,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 1600,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 1600,4000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/inv_x4.sym b/alliance/src/cells/src/sxlib/inv_x4.sym new file mode 100644 index 00000000..2a1da33c Binary files /dev/null and b/alliance/src/cells/src/sxlib/inv_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/inv_x4.vbe b/alliance/src/cells/src/sxlib/inv_x4.vbe new file mode 100644 index 00000000..3091ae3f --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x4.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 26; + CONSTANT rdown_i_nq : NATURAL := 810; + CONSTANT rup_i_nq : NATURAL := 1060; + CONSTANT tphl_i_nq : NATURAL := 71; + CONSTANT tplh_i_nq : NATURAL := 143; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x4; + +ARCHITECTURE behaviour_data_flow OF inv_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x4" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/alliance/src/cells/src/sxlib/inv_x4.vhd b/alliance/src/cells/src/sxlib/inv_x4.vhd new file mode 100644 index 00000000..2263c327 --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x4.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY inv_x4 IS +PORT( + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END inv_x4; + +ARCHITECTURE RTL OF inv_x4 IS +BEGIN + nq <= NOT(i); +END RTL; diff --git a/alliance/src/cells/src/sxlib/inv_x8.al b/alliance/src/cells/src/sxlib/inv_x8.al new file mode 100644 index 00000000..f3b8f6ac --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x8.al @@ -0,0 +1,23 @@ +V ALLIANCE : 6 +H inv_x8,L,30/10/99 +C i,IN,EXTERNAL,4 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00008 +T P,0.35,5.9,3,4,2,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00007 +T P,0.35,5.9,3,4,2,0,0.75,0.75,13.3,13.3,7.5,11.25,tr_00006 +T P,0.35,5.9,2,4,3,0,0.75,0.75,13.3,13.3,5.7,11.25,tr_00005 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00004 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00003 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,7.5,2.25,tr_00002 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.7,2.25,tr_00001 +S 4,EXTERNAL,i +Q 0.00785425 +S 3,EXTERNAL,vdd +Q 0.0074877 +S 2,EXTERNAL,nq +Q 0.00599301 +S 1,EXTERNAL,vss +Q 0.00613633 +EOF diff --git a/alliance/src/cells/src/sxlib/inv_x8.ap b/alliance/src/cells/src/sxlib/inv_x8.ap new file mode 100644 index 00000000..e2f85ee0 --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x8.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 6 +H inv_x8,P,30/ 8/2000,100 +A 0,0,3500,5000 +R 500,4000,ref_ref,i_40 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 500,2500,ref_ref,i_25 +R 500,2000,ref_ref,i_20 +R 500,1500,ref_ref,i_15 +R 500,1000,ref_ref,i_10 +R 1000,4000,ref_ref,nq_40 +R 1000,3500,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_30 +R 1000,2500,ref_ref,nq_25 +R 1000,2000,ref_ref,nq_20 +R 1000,1500,ref_ref,nq_15 +R 1000,1000,ref_ref,nq_10 +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 0,3900,3500,3900,2400,*,LEFT,NWELL +S 2800,300,2800,1200,300,*,UP,NDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2500,1400,2500,2600,100,*,UP,POLY +S 1900,1400,1900,2600,100,*,UP,POLY +S 1300,1400,1300,2600,100,*,UP,POLY +S 700,1400,700,2600,100,*,UP,POLY +S 400,2800,400,4700,300,*,DOWN,PDIF +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,DOWN,PDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 2500,2600,2500,4900,100,*,UP,PTRANS +S 2200,2800,2200,4700,300,*,DOWN,PDIF +S 1900,2600,1900,4900,100,*,UP,PTRANS +S 1300,100,1300,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1000,300,1000,1200,300,*,UP,NDIF +S 400,300,400,1200,300,*,UP,NDIF +S 2200,300,2200,1200,300,*,UP,NDIF +S 2500,100,2500,1400,100,*,DOWN,NTRANS +S 1900,100,1900,1400,100,*,DOWN,NTRANS +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1600,500,1600,1000,200,*,DOWN,ALU1 +S 1600,3000,1600,4500,200,*,UP,ALU1 +S 400,1500,2500,1500,300,*,RIGHT,POLY +S 2700,1700,3300,1700,300,*,RIGHT,PTIE +S 2800,3900,2800,4700,300,*,DOWN,PDIF +S 3200,2800,3200,3500,300,*,UP,NTIE +S 2200,1000,2200,4000,200,*,DOWN,ALU1 +S 1000,2000,2200,2000,200,*,LEFT,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 2800,1700,3200,1700,200,*,LEFT,ALU1 +S 2800,500,2800,1700,200,*,DOWN,ALU1 +S 3200,2900,3200,3400,200,*,UP,ALU1 +S 2750,3400,3200,3400,200,*,LEFT,ALU1 +S 2800,3350,2800,4500,200,*,UP,ALU1 +V 2800,500,CONT_DIF_N,* +V 1000,3500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1600,4000,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 1600,3000,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 2200,4000,CONT_DIF_P,* +V 2200,3500,CONT_DIF_P,* +V 2200,3000,CONT_DIF_P,* +V 1000,1000,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 2200,1000,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 1600,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 2800,1700,CONT_BODY_P,* +V 3200,1700,CONT_BODY_P,* +V 3200,2900,CONT_BODY_N,* +V 2800,4500,CONT_DIF_P,* +V 2800,4000,CONT_DIF_P,* +V 3200,3400,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/inv_x8.sym b/alliance/src/cells/src/sxlib/inv_x8.sym new file mode 100644 index 00000000..c0564bf1 Binary files /dev/null and b/alliance/src/cells/src/sxlib/inv_x8.sym differ diff --git a/alliance/src/cells/src/sxlib/inv_x8.vbe b/alliance/src/cells/src/sxlib/inv_x8.vbe new file mode 100644 index 00000000..4e6fa063 --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x8.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i : NATURAL := 54; + CONSTANT rdown_i_nq : NATURAL := 400; + CONSTANT rup_i_nq : NATURAL := 450; + CONSTANT tphl_i_nq : NATURAL := 86; + CONSTANT tplh_i_nq : NATURAL := 133; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x8; + +ARCHITECTURE behaviour_data_flow OF inv_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x8" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/alliance/src/cells/src/sxlib/inv_x8.vhd b/alliance/src/cells/src/sxlib/inv_x8.vhd new file mode 100644 index 00000000..9d32ed3c --- /dev/null +++ b/alliance/src/cells/src/sxlib/inv_x8.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY inv_x8 IS +PORT( + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END inv_x8; + +ARCHITECTURE RTL OF inv_x8 IS +BEGIN + nq <= NOT(i); +END RTL; diff --git a/alliance/src/cells/src/sxlib/mx2_x2.al b/alliance/src/cells/src/sxlib/mx2_x2.al new file mode 100644 index 00000000..719679f7 --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx2_x2.al @@ -0,0 +1,45 @@ +V ALLIANCE : 6 +H mx2_x2,L,30/10/99 +C cmd,IN,EXTERNAL,6 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,9 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,10,7,11,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00012 +T P,0.35,2.9,2,3,12,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00011 +T P,0.35,2.9,11,6,2,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00010 +T P,0.35,2.9,3,6,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009 +T P,0.35,2.9,12,8,10,0,0.75,0.75,7.3,7.3,8.4,11.25,tr_00008 +T P,0.35,5.9,10,2,9,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00007 +T N,0.35,2.9,9,2,1,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00006 +T N,0.35,1.4,4,7,1,0,0.75,0.75,4.3,4.3,3.6,1.5,tr_00005 +T N,0.35,1.4,2,3,4,0,0.75,0.75,4.3,4.3,4.8,1.5,tr_00004 +T N,0.35,1.4,1,6,3,0,0.75,0.75,4.3,4.3,1.8,1.5,tr_00003 +T N,0.35,1.4,5,6,2,0,0.75,0.75,4.3,4.3,7.2,1.5,tr_00002 +T N,0.35,1.4,1,8,5,0,0.75,0.75,4.3,4.3,8.4,1.5,tr_00001 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,vdd +Q 0.00658426 +S 9,EXTERNAL,q +Q 0.00264397 +S 8,EXTERNAL,i1 +Q 0.00371745 +S 7,EXTERNAL,i0 +Q 0.00336619 +S 6,EXTERNAL,cmd +Q 0.00660261 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00595297 +S 2,INTERNAL +Q 0.0047485 +S 1,EXTERNAL,vss +Q 0.00552667 +EOF diff --git a/alliance/src/cells/src/sxlib/mx2_x2.ap b/alliance/src/cells/src/sxlib/mx2_x2.ap new file mode 100644 index 00000000..82901f4c --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx2_x2.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 6 +H mx2_x2,P,30/ 8/2000,100 +A 0,0,4500,5000 +R 3000,4000,ref_ref,i1_40 +R 3000,3500,ref_ref,i1_35 +R 3000,3000,ref_ref,i1_30 +R 3000,2500,ref_ref,i1_25 +R 3000,2000,ref_ref,i1_20 +R 3000,1500,ref_ref,i1_15 +R 3000,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 4000,1000,ref_ref,q_10 +R 4000,3000,ref_ref,q_30 +R 4000,2000,ref_ref,q_20 +R 4000,1500,ref_ref,q_15 +R 4000,4000,ref_ref,q_40 +R 4000,3500,ref_ref,q_35 +R 4000,2500,ref_ref,q_25 +R 1500,4000,ref_ref,cmd_40 +R 1500,3500,ref_ref,cmd_35 +R 1500,3000,ref_ref,cmd_30 +R 1500,2500,ref_ref,cmd_25 +R 1500,2000,ref_ref,cmd_20 +R 1500,1500,ref_ref,cmd_15 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,4000,200,cmd,DOWN,CALU1 +S 4000,950,4000,4050,200,*,DOWN,ALU1 +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 1600,2000,1600,3100,100,*,UP,POLY +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 3800,100,3800,1400,100,*,UP,NTRANS +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 3300,300,3300,1200,700,*,DOWN,NDIF +S 3300,3300,3300,4700,700,*,UP,PDIF +S 3500,3000,3500,4500,200,*,UP,ALU1 +S 2000,2300,3800,2300,100,*,RIGHT,POLY +S 2500,1000,2500,2700,100,*,UP,ALU1 +S 2400,2800,2400,3100,100,*,UP,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 1200,100,1200,900,100,*,UP,NTRANS +S 1600,100,1600,900,100,*,UP,NTRANS +S 3500,500,3500,1700,200,*,DOWN,ALU1 +S 600,100,600,900,100,*,UP,NTRANS +S 900,300,900,700,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 600,900,600,3100,100,*,DOWN,POLY +S 2400,100,2400,900,100,*,UP,NTRANS +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 3800,1400,3800,2600,100,*,DOWN,POLY +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3500,2800,3500,3300,300,*,DOWN,PDIF +V 3000,1500,CONT_POLY,* +V 300,4700,CONT_BODY_N,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 2000,1500,CONT_DIF_N,* +V 2000,3500,CONT_DIF_P,* +V 2000,4700,CONT_BODY_N,* +V 2000,4000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 3500,4000,CONT_DIF_P,* +V 4100,3500,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3000,CONT_DIF_P,* +V 4100,1000,CONT_DIF_N,* +V 3500,500,CONT_DIF_N,* +V 3500,4500,CONT_DIF_P,* +V 3500,1000,CONT_DIF_N,* +V 3500,3000,CONT_DIF_P,* +V 2500,2700,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 3500,1700,CONT_BODY_P,* +V 1500,2000,CONT_POLY,* +V 1600,1000,CONT_POLY,* +V 1500,4700,CONT_BODY_N,* +V 2500,4700,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/mx2_x2.sym b/alliance/src/cells/src/sxlib/mx2_x2.sym new file mode 100644 index 00000000..572a87c6 Binary files /dev/null and b/alliance/src/cells/src/sxlib/mx2_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/mx2_x2.vbe b/alliance/src/cells/src/sxlib/mx2_x2.vbe new file mode 100644 index 00000000..7e478744 --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx2_x2.vbe @@ -0,0 +1,42 @@ +ENTITY mx2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 451; + CONSTANT tphh_i1_q : NATURAL := 451; + CONSTANT tpll_i0_q : NATURAL := 469; + CONSTANT tpll_i1_q : NATURAL := 469; + CONSTANT tphh_cmd_q : NATURAL := 484; + CONSTANT tphl_cmd_q : NATURAL := 485; + CONSTANT tpll_cmd_q : NATURAL := 522; + CONSTANT tplh_cmd_q : NATURAL := 534; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x2; + +ARCHITECTURE behaviour_data_flow OF mx2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x2" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/mx2_x2.vhd b/alliance/src/cells/src/sxlib/mx2_x2.vhd new file mode 100644 index 00000000..c115df14 --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx2_x2.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY mx2_x2 IS +PORT( + cmd : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END mx2_x2; + +ARCHITECTURE RTL OF mx2_x2 IS +BEGIN + q <= ((i1 AND cmd) OR (NOT(cmd) AND i0)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/mx2_x4.al b/alliance/src/cells/src/sxlib/mx2_x4.al new file mode 100644 index 00000000..be51afcd --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx2_x4.al @@ -0,0 +1,47 @@ +V ALLIANCE : 6 +H mx2_x4,L,30/10/99 +C cmd,IN,EXTERNAL,6 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,9 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,11,7,10,0,0.75,0.75,7.3,7.3,8.4,11.25,tr_00014 +T P,0.35,2.9,2,6,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00013 +T P,0.35,2.9,12,6,1,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00012 +T P,0.35,2.9,1,2,11,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00011 +T P,0.35,2.9,10,8,12,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00010 +T P,0.35,5.9,9,1,10,0,0.75,0.75,13.3,13.3,13.2,11.25,tr_00009 +T P,0.35,5.9,10,1,9,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00008 +T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,8.4,1.5,tr_00007 +T N,0.35,1.4,4,6,1,0,0.75,0.75,4.3,4.3,7.2,1.5,tr_00006 +T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,1.8,1.5,tr_00005 +T N,0.35,1.4,1,2,5,0,0.75,0.75,4.3,4.3,4.8,1.5,tr_00004 +T N,0.35,1.4,5,8,3,0,0.75,0.75,4.3,4.3,3.6,1.5,tr_00003 +T N,0.35,2.9,9,1,3,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00002 +T N,0.35,2.9,3,1,9,0,0.75,0.75,7.3,7.3,13.2,2.25,tr_00001 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,vdd +Q 0.00862963 +S 9,EXTERNAL,q +Q 0.00264397 +S 8,EXTERNAL,i0 +Q 0.00336619 +S 7,EXTERNAL,i1 +Q 0.00371745 +S 6,EXTERNAL,cmd +Q 0.00660261 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00721951 +S 2,INTERNAL +Q 0.00595297 +S 1,INTERNAL +Q 0.00607876 +EOF diff --git a/alliance/src/cells/src/sxlib/mx2_x4.ap b/alliance/src/cells/src/sxlib/mx2_x4.ap new file mode 100644 index 00000000..fabbde0d --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx2_x4.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H mx2_x4,P,30/ 8/2000,100 +A 0,0,5000,5000 +R 1500,1500,ref_ref,cmd_15 +R 1500,2000,ref_ref,cmd_20 +R 1500,2500,ref_ref,cmd_25 +R 1500,3000,ref_ref,cmd_30 +R 1500,3500,ref_ref,cmd_35 +R 1500,4000,ref_ref,cmd_40 +R 4000,2500,ref_ref,q_25 +R 4000,3500,ref_ref,q_35 +R 4000,4000,ref_ref,q_40 +R 4000,1500,ref_ref,q_15 +R 4000,2000,ref_ref,q_20 +R 4000,3000,ref_ref,q_30 +R 4000,1000,ref_ref,q_10 +R 1000,1500,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,4000,ref_ref,i0_40 +R 3000,1000,ref_ref,i1_10 +R 3000,1500,ref_ref,i1_15 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 3000,4000,ref_ref,i1_40 +S 1500,1500,1500,4000,200,cmd,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 4000,950,4000,4050,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,100,2400,900,100,*,UP,NTRANS +S 600,900,600,3100,100,*,DOWN,POLY +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,700,300,*,UP,NDIF +S 600,100,600,900,100,*,UP,NTRANS +S 3500,500,3500,1700,200,*,DOWN,ALU1 +S 1600,100,1600,900,100,*,UP,NTRANS +S 1200,100,1200,900,100,*,UP,NTRANS +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 2400,2800,2400,3100,100,*,UP,POLY +S 2500,1000,2500,2700,100,*,UP,ALU1 +S 3500,3000,3500,4500,200,*,UP,ALU1 +S 3300,3300,3300,4700,700,*,UP,PDIF +S 3300,300,3300,1200,700,*,DOWN,NDIF +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 3800,100,3800,1400,100,*,UP,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 1600,2000,1600,3100,100,*,UP,POLY +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 4400,100,4400,1400,100,*,UP,NTRANS +S 4700,300,4700,1200,300,*,DOWN,NDIF +S 2000,2300,4400,2300,100,*,RIGHT,POLY +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 4700,3000,4700,4500,200,*,UP,ALU1 +S 4700,500,4700,1700,200,*,DOWN,ALU1 +S 4400,2600,4400,4900,100,*,DOWN,PTRANS +S 4700,2800,4700,4700,300,*,UP,PDIF +S 4700,2800,4700,3300,300,*,DOWN,PDIF +S 3500,2800,3500,3300,300,*,DOWN,PDIF +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 3800,1400,3800,2600,100,*,DOWN,POLY +S 4400,1400,4400,2600,100,*,DOWN,POLY +V 2500,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 1600,1000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3500,1700,CONT_BODY_P,* +V 2000,2400,CONT_POLY,* +V 2500,2700,CONT_POLY,* +V 3500,3000,CONT_DIF_P,* +V 3500,1000,CONT_DIF_N,* +V 3500,4500,CONT_DIF_P,* +V 3500,500,CONT_DIF_N,* +V 4100,1000,CONT_DIF_N,* +V 4100,3000,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3500,CONT_DIF_P,* +V 3500,4000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 2000,4000,CONT_DIF_P,* +V 2000,4700,CONT_BODY_N,* +V 2000,3500,CONT_DIF_P,* +V 2000,1500,CONT_DIF_N,* +V 3000,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,4700,CONT_BODY_N,* +V 3000,1500,CONT_POLY,* +V 4700,3500,CONT_DIF_P,* +V 4700,3000,CONT_DIF_P,* +V 4700,4500,CONT_DIF_P,* +V 4700,4000,CONT_DIF_P,* +V 4700,1700,CONT_BODY_P,* +V 4700,500,CONT_DIF_N,* +V 4700,1000,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/mx2_x4.sym b/alliance/src/cells/src/sxlib/mx2_x4.sym new file mode 100644 index 00000000..8224e178 Binary files /dev/null and b/alliance/src/cells/src/sxlib/mx2_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/mx2_x4.vbe b/alliance/src/cells/src/sxlib/mx2_x4.vbe new file mode 100644 index 00000000..a27f7c19 --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx2_x4.vbe @@ -0,0 +1,42 @@ +ENTITY mx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 564; + CONSTANT tphh_i1_q : NATURAL := 564; + CONSTANT tphl_cmd_q : NATURAL := 574; + CONSTANT tpll_i0_q : NATURAL := 576; + CONSTANT tpll_i1_q : NATURAL := 576; + CONSTANT tphh_cmd_q : NATURAL := 615; + CONSTANT tplh_cmd_q : NATURAL := 631; + CONSTANT tpll_cmd_q : NATURAL := 647; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x4; + +ARCHITECTURE behaviour_data_flow OF mx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x4" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/mx2_x4.vhd b/alliance/src/cells/src/sxlib/mx2_x4.vhd new file mode 100644 index 00000000..2da047b5 --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx2_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY mx2_x4 IS +PORT( + cmd : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END mx2_x4; + +ARCHITECTURE RTL OF mx2_x4 IS +BEGIN + q <= ((i1 AND cmd) OR (NOT(cmd) AND i0)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/mx3_x2.al b/alliance/src/cells/src/sxlib/mx3_x2.al new file mode 100644 index 00000000..6b49a823 --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx3_x2.al @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H mx3_x2,L,30/10/99 +C cmd0,IN,EXTERNAL,15 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,16,6,1,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00020 +T P,0.35,2.9,7,13,18,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00019 +T P,0.35,2.9,19,15,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00018 +T P,0.35,2.9,1,14,19,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00017 +T P,0.35,2.9,18,8,16,0,0.75,0.75,7.3,7.3,9,12.75,tr_00016 +T P,0.35,2.9,17,10,18,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00015 +T P,0.35,2.9,1,9,17,0,0.75,0.75,7.3,7.3,6,12.75,tr_00014 +T P,0.35,5.9,12,1,7,0,0.75,0.75,13.3,13.3,17.4,11.25,tr_00013 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00012 +T P,0.35,2,7,15,13,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00011 +T N,0.35,1.7,4,8,2,0,0.75,0.75,4.9,4.9,9,2.55,tr_00010 +T N,0.35,1.7,2,9,1,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00009 +T N,0.35,1.7,1,6,5,0,0.75,0.75,4.9,4.9,6,2.55,tr_00008 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00007 +T N,0.35,1.7,3,15,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00006 +T N,0.35,1.7,11,13,3,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00005 +T N,0.35,1.7,1,14,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00004 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00003 +T N,0.35,1.1,13,15,3,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00002 +T N,0.35,2.9,3,1,12,0,0.75,0.75,7.3,7.3,17.4,3.75,tr_00001 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0.00170541 +S 17,INTERNAL +Q 0 +S 16,INTERNAL +Q 0 +S 15,EXTERNAL,cmd0 +Q 0.00553121 +S 14,EXTERNAL,i0 +Q 0.00386191 +S 13,INTERNAL +Q 0.0057783 +S 12,EXTERNAL,q +Q 0.00361343 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00654004 +S 6,INTERNAL +Q 0.00547335 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00671631 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00814817 +EOF diff --git a/alliance/src/cells/src/sxlib/mx3_x2.ap b/alliance/src/cells/src/sxlib/mx3_x2.ap new file mode 100644 index 00000000..79da05fd --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx3_x2.ap @@ -0,0 +1,182 @@ +V ALLIANCE : 6 +H mx3_x2,P, 6/ 9/2000,100 +A 0,0,6500,5000 +R 6000,4000,ref_ref,q_40 +R 6000,3500,ref_ref,q_35 +R 6000,3000,ref_ref,q_30 +R 6000,2500,ref_ref,q_25 +R 6000,1500,ref_ref,q_15 +R 6000,1000,ref_ref,q_10 +R 4500,2500,ref_ref,i0_25 +R 4000,3000,ref_ref,i0_30 +R 4000,2000,ref_ref,i0_20 +R 3500,3000,ref_ref,cmd0_30 +R 3500,2500,ref_ref,cmd0_25 +R 3500,2000,ref_ref,cmd0_20 +R 2500,2500,ref_ref,i1_25 +R 1500,2500,ref_ref,i2_25 +R 500,3500,ref_ref,cmd1_35 +R 500,3000,ref_ref,cmd1_30 +R 500,2500,ref_ref,cmd1_25 +R 500,2000,ref_ref,cmd1_20 +R 500,1500,ref_ref,cmd1_15 +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 4400,3000,4600,3000,300,*,LEFT,POLY +S 4400,2000,4600,2000,300,*,RIGHT,POLY +S 1800,3500,2000,3500,300,*,RIGHT,POLY +S 4000,2000,4000,2000,200,i0,LEFT,CALU1 +S 4500,2500,4500,2500,200,i0,LEFT,CALU1 +S 4000,3000,4000,3000,200,i0,LEFT,CALU1 +S 6000,1000,6000,1500,200,q,DOWN,CALU1 +S 6000,2500,6000,4000,200,q,DOWN,CALU1 +S 6000,950,6000,1550,200,*,DOWN,ALU1 +S 6000,2450,6000,4000,200,*,DOWN,ALU1 +S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1 +S 2500,2500,2500,2500,200,i1,LEFT,CALU1 +S 1500,2500,1500,2500,200,i2,LEFT,CALU1 +S 500,1500,500,3500,200,cmd1,DOWN,CALU1 +S 4900,400,4900,1000,300,*,UP,NDIF +S 5500,2000,5700,2000,200,*,LEFT,ALU1 +S 6050,1500,6250,1500,200,*,LEFT,ALU1 +S 6200,1450,6200,2550,200,*,DOWN,ALU1 +S 6050,2500,6250,2500,200,*,RIGHT,ALU1 +S 5500,500,5500,1700,300,*,DOWN,NDIF +S 6100,800,6100,1700,300,*,UP,NDIF +S 5800,600,5800,1900,100,*,DOWN,NTRANS +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 4900,1000,5500,1000,100,*,RIGHT,ALU1 +S 2300,3500,5500,3500,100,*,RIGHT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 1100,1600,1100,1900,300,*,UP,NDIF +S 800,1400,800,2100,100,*,DOWN,NTRANS +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 3500,1500,3500,3600,100,*,UP,POLY +S 4900,3500,4900,4000,100,*,DOWN,ALU1 +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 4600,200,4600,1100,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 3600,200,3600,1100,100,*,UP,NTRANS +S 1400,400,1400,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 3000,400,3000,1300,100,*,UP,NTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 800,2600,800,3600,100,*,UP,PTRANS +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 3900,400,3900,900,200,*,DOWN,NDIF +S 4200,1100,4200,1500,100,*,UP,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 4900,2800,4900,3400,300,*,UP,PDIF +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 6100,2800,6100,4700,300,*,UP,PDIF +S 5800,2000,5800,2600,100,*,DOWN,POLY +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 4900,3000,5000,3000,100,*,RIGHT,ALU1 +S 4400,2000,4400,3000,100,*,UP,ALU1 +S 5500,2800,5500,4600,300,*,DOWN,PDIF +S 5800,2600,5800,4900,100,*,UP,PTRANS +S 4000,3300,4000,3600,100,*,UP,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2800,2000,3000,2000,100,*,RIGHT,ALU1 +S 1800,3000,2500,3000,100,*,LEFT,ALU1 +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 500,2800,500,4000,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 2300,3500,2300,4700,300,*,UP,PDIF +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1100,3800,1100,4700,300,*,UP,PDIF +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 3300,3800,3300,4700,200,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 4900,3800,4900,4700,300,*,UP,PDIF +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 500,1000,500,1900,300,*,DOWN,NDIF +S 500,2500,800,2500,300,*,RIGHT,POLY +S 800,2100,800,2600,100,*,DOWN,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 2600,3000,2600,3600,100,*,UP,POLY +S 500,400,500,1000,200,*,DOWN,ALU1 +S 1100,1000,3300,1000,100,*,RIGHT,ALU1 +S 500,3500,1800,3500,100,*,LEFT,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1800,1500,1800,2000,100,*,UP,ALU1 +S 1800,2000,1900,2000,100,*,RIGHT,ALU1 +S 1000,3000,1800,3000,100,*,LEFT,ALU1 +S 1100,4000,3300,4000,100,*,RIGHT,ALU1 +S 2300,1500,2800,1500,100,*,RIGHT,ALU1 +S 2800,1500,2800,2000,100,*,UP,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 5200,1900,5200,2600,100,*,DOWN,POLY +S 5200,1300,5200,1900,100,*,DOWN,NTRANS +S 3400,1500,5000,1500,100,*,RIGHT,ALU1 +S 5000,1500,5000,3000,100,*,DOWN,ALU1 +V 6100,300,CONT_BODY_P,* +V 5700,2000,CONT_POLY,* +V 3900,2500,CONT_POLY,* +V 6100,1000,CONT_DIF_N,* +V 6100,1500,CONT_DIF_N,* +V 6100,3000,CONT_DIF_P,* +V 6100,4000,CONT_DIF_P,* +V 6100,3500,CONT_DIF_P,* +V 5500,500,CONT_DIF_N,* +V 5500,4600,CONT_DIF_P,* +V 4400,2000,CONT_POLY,* +V 4400,3000,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 4900,3000,CONT_DIF_P,* +V 1100,3000,CONT_DIF_P,* +V 500,4600,CONT_BODY_N,* +V 500,4000,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 1100,4000,CONT_DIF_P,* +V 2300,3500,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 3900,500,CONT_DIF_N,* +V 500,1000,CONT_DIF_N,* +V 1100,1000,CONT_DIF_N,* +V 4900,1000,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 1100,1800,CONT_DIF_N,* +V 1100,1800,CONT_DIF_N,* +V 2300,1500,CONT_DIF_N,* +V 500,400,CONT_BODY_P,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 1800,1500,CONT_POLY,* +V 3400,1500,CONT_POLY,* +V 4200,1500,CONT_POLY,* +V 1800,3500,CONT_POLY,* +V 4900,1600,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/mx3_x2.vbe b/alliance/src/cells/src/sxlib/mx3_x2.vbe new file mode 100644 index 00000000..5d534511 --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx3_x2.vbe @@ -0,0 +1,59 @@ +ENTITY mx3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 1620; + CONSTANT rdown_cmd0_q : NATURAL := 1620; + CONSTANT rdown_cmd1_q : NATURAL := 1620; + CONSTANT rdown_cmd1_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_cmd0_q : NATURAL := 1790; + CONSTANT rup_cmd0_q : NATURAL := 1790; + CONSTANT rup_cmd1_q : NATURAL := 1790; + CONSTANT rup_cmd1_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 538; + CONSTANT tphh_cmd0_q : NATURAL := 573; + CONSTANT tphh_i1_q : NATURAL := 654; + CONSTANT tphh_i2_q : NATURAL := 654; + CONSTANT tpll_i0_q : NATURAL := 658; + CONSTANT tphh_cmd1_q : NATURAL := 664; + CONSTANT tpll_cmd0_q : NATURAL := 680; + CONSTANT tplh_cmd1_q : NATURAL := 738; + CONSTANT tphl_cmd1_q : NATURAL := 739; + CONSTANT tplh_cmd0_q : NATURAL := 768; + CONSTANT tphl_cmd0_q : NATURAL := 792; + CONSTANT tpll_i1_q : NATURAL := 808; + CONSTANT tpll_i2_q : NATURAL := 808; + CONSTANT tpll_cmd1_q : NATURAL := 817; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x2; + +ARCHITECTURE behaviour_data_flow OF mx3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx3_x2" + SEVERITY WARNING; + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) + and i2)))) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/mx3_x2.vhd b/alliance/src/cells/src/sxlib/mx3_x2.vhd new file mode 100644 index 00000000..9fc27c51 --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx3_x2.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY mx3_x2 IS +PORT( + cmd0 : IN STD_LOGIC; + cmd1 : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END mx3_x2; + +ARCHITECTURE RTL OF mx3_x2 IS +BEGIN + q <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2)))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/mx3_x4.al b/alliance/src/cells/src/sxlib/mx3_x4.al new file mode 100644 index 00000000..a852eb31 --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx3_x4.al @@ -0,0 +1,71 @@ +V ALLIANCE : 6 +H mx3_x4,L,30/10/99 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,15 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,7,2,11,0,0.75,0.75,13.3,13.3,18.9,11.25,tr_00022 +T P,0.35,2.9,18,6,2,0,0.75,0.75,7.3,7.3,7.5,12.75,tr_00021 +T P,0.35,2.9,7,13,17,0,0.75,0.75,7.3,7.3,10.5,12.75,tr_00020 +T P,0.35,2.9,19,14,7,0,0.75,0.75,7.3,7.3,12.3,12.75,tr_00019 +T P,0.35,2.9,2,15,19,0,0.75,0.75,7.3,7.3,13.5,12.75,tr_00018 +T P,0.35,2.9,17,8,18,0,0.75,0.75,7.3,7.3,8.7,12.75,tr_00017 +T P,0.35,2.9,16,10,17,0,0.75,0.75,7.3,7.3,3.9,12.75,tr_00016 +T P,0.35,2.9,2,9,16,0,0.75,0.75,7.3,7.3,5.7,12.75,tr_00015 +T P,0.35,5.9,11,2,7,0,0.75,0.75,13.3,13.3,17.1,11.25,tr_00014 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.1,9.3,tr_00013 +T P,0.35,2,7,14,13,0,0.75,0.75,5.5,5.5,15.3,9.3,tr_00012 +T N,0.35,2.9,11,2,3,0,0.75,0.75,7.3,7.3,18.9,3.75,tr_00011 +T N,0.35,1.7,1,9,2,0,0.75,0.75,4.9,4.9,7.5,2.55,tr_00010 +T N,0.35,1.7,2,6,5,0,0.75,0.75,4.9,4.9,5.7,2.55,tr_00009 +T N,0.35,1.7,12,13,3,0,0.75,0.75,4.9,4.9,12.3,1.95,tr_00008 +T N,0.35,1.7,2,15,12,0,0.75,0.75,4.9,4.9,13.5,1.95,tr_00007 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,8.7,2.55,tr_00006 +T N,0.35,2.9,3,2,11,0,0.75,0.75,7.3,7.3,17.1,3.75,tr_00005 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,3.9,2.55,tr_00004 +T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.5,1.95,tr_00003 +T N,0.35,1.1,13,14,3,0,0.75,0.75,3.7,3.7,15.3,4.95,tr_00002 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.1,5.25,tr_00001 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00170541 +S 16,INTERNAL +Q 0 +S 15,EXTERNAL,i0 +Q 0.00397942 +S 14,EXTERNAL,cmd0 +Q 0.00547246 +S 13,INTERNAL +Q 0.00589104 +S 12,INTERNAL +Q 0 +S 11,EXTERNAL,q +Q 0.00396596 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00864417 +S 6,INTERNAL +Q 0.00586794 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00823288 +S 2,INTERNAL +Q 0.00946154 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/mx3_x4.ap b/alliance/src/cells/src/sxlib/mx3_x4.ap new file mode 100644 index 00000000..728f68b5 --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx3_x4.ap @@ -0,0 +1,203 @@ +V ALLIANCE : 6 +H mx3_x4,P, 6/ 9/2000,100 +A 0,0,7000,5000 +R 6500,2000,ref_ref,q_20 +R 500,1500,ref_ref,cmd1_15 +R 500,2000,ref_ref,cmd1_20 +R 500,2500,ref_ref,cmd1_25 +R 500,3000,ref_ref,cmd1_30 +R 500,3500,ref_ref,cmd1_35 +R 1500,2500,ref_ref,i2_25 +R 2500,2500,ref_ref,i1_25 +R 3500,2000,ref_ref,cmd0_20 +R 3500,2500,ref_ref,cmd0_25 +R 3500,3000,ref_ref,cmd0_30 +R 4000,2000,ref_ref,i0_20 +R 4000,3000,ref_ref,i0_30 +R 4500,2500,ref_ref,i0_25 +R 6000,1000,ref_ref,q_10 +R 6000,1500,ref_ref,q_15 +R 6000,2500,ref_ref,q_25 +R 6000,3000,ref_ref,q_30 +R 6000,3500,ref_ref,q_35 +R 6000,4000,ref_ref,q_40 +S 4300,3000,4500,3000,300,*,RIGHT,POLY +S 4300,2000,4500,2000,300,*,RIGHT,POLY +S 1700,1500,1900,1500,300,*,RIGHT,POLY +S 1700,3500,1900,3500,300,*,RIGHT,POLY +S 1300,2500,1500,2500,300,*,LEFT,POLY +S 500,3500,1700,3500,100,*,LEFT,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 6500,2000,6500,2000,200,q,LEFT,CALU1 +S 6000,1000,6000,1500,200,q,DOWN,CALU1 +S 6000,2500,6000,4000,200,q,DOWN,CALU1 +S 4000,2000,4000,2000,200,i0,LEFT,CALU1 +S 4000,3000,4000,3000,200,i0,LEFT,CALU1 +S 4500,2500,4500,2500,200,i0,LEFT,CALU1 +S 500,1500,500,3500,200,cmd1,DOWN,CALU1 +S 1500,2500,1500,2500,200,i2,LEFT,CALU1 +S 2500,2500,2500,2500,200,i1,LEFT,CALU1 +S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1 +S 4800,400,4800,1000,300,*,UP,NDIF +S 0,4700,7000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,7000,3900,2400,*,RIGHT,NWELL +S 0,300,7000,300,600,vss,RIGHT,CALU1 +S 5950,1500,6150,1500,200,*,LEFT,ALU1 +S 6100,1450,6100,2550,200,*,DOWN,ALU1 +S 5950,2500,6150,2500,200,*,RIGHT,ALU1 +S 6000,2450,6000,4000,200,*,DOWN,ALU1 +S 400,4000,400,4600,200,*,UP,ALU1 +S 4800,3500,4800,4000,100,*,DOWN,ALU1 +S 4300,2000,4300,3000,100,*,UP,ALU1 +S 1000,4000,3200,4000,100,*,RIGHT,ALU1 +S 2200,1500,2700,1500,100,*,RIGHT,ALU1 +S 1700,3000,2400,3000,100,*,LEFT,ALU1 +S 6600,3000,6600,4600,200,*,UP,ALU1 +S 1700,1500,1700,2000,100,*,UP,ALU1 +S 2700,1500,2700,2000,100,*,UP,ALU1 +S 6000,950,6000,1550,200,*,DOWN,ALU1 +S 400,400,400,1000,200,*,DOWN,ALU1 +S 1000,1000,3200,1000,100,*,RIGHT,ALU1 +S 6600,300,6600,1500,200,*,DOWN,ALU1 +S 1900,1300,1900,1500,100,*,DOWN,POLY +S 1300,1300,1300,3600,100,*,DOWN,POLY +S 3900,3300,3900,3600,100,*,UP,POLY +S 3900,3600,4100,3600,100,*,LEFT,POLY +S 4500,1100,4500,2000,100,*,DOWN,POLY +S 3400,3600,3500,3600,100,*,RIGHT,POLY +S 3400,1500,3400,3600,100,*,UP,POLY +S 3900,1900,3900,3300,100,*,DOWN,POLY +S 4400,2000,4500,2000,100,*,RIGHT,POLY +S 4500,3000,4500,3600,100,*,UP,POLY +S 4300,3000,4500,3000,100,*,RIGHT,POLY +S 2400,2500,2900,2500,100,*,RIGHT,POLY +S 4100,1100,4100,1500,100,*,UP,POLY +S 2900,1300,2900,3600,100,*,DOWN,POLY +S 2500,1300,2500,2000,100,*,UP,POLY +S 3500,1100,3700,1100,100,*,RIGHT,POLY +S 3200,1500,3300,1500,100,*,LEFT,POLY +S 2500,3000,2500,3600,100,*,UP,POLY +S 1900,2000,2500,2000,100,*,RIGHT,POLY +S 1900,2000,1900,3600,100,*,DOWN,POLY +S 3900,2500,5100,2500,100,*,RIGHT,POLY +S 3700,1100,3700,1900,100,*,DOWN,POLY +S 3700,1900,3900,1900,100,*,LEFT,POLY +S 5600,2000,6300,2000,100,*,RIGHT,POLY +S 400,2500,700,2500,300,*,RIGHT,POLY +S 700,2100,700,2600,100,*,DOWN,POLY +S 1700,1500,1900,1500,100,*,RIGHT,POLY +S 6300,1900,6300,2600,100,*,DOWN,POLY +S 5700,1900,5700,2600,100,*,DOWN,POLY +S 1000,1600,1000,1900,300,*,UP,NDIF +S 700,1400,700,2100,100,*,DOWN,NTRANS +S 1000,600,1000,1000,300,*,DOWN,NDIF +S 1600,600,1600,1100,200,*,DOWN,NDIF +S 2200,600,2200,1600,300,*,UP,NDIF +S 3200,400,3200,1100,300,*,DOWN,NDIF +S 3500,200,3500,1100,100,*,UP,NTRANS +S 1300,400,1300,1300,100,*,UP,NTRANS +S 5400,500,5400,1700,300,*,DOWN,NDIF +S 6000,800,6000,1700,300,*,UP,NDIF +S 5700,600,5700,1900,100,*,DOWN,NTRANS +S 2900,400,2900,1300,100,*,UP,NTRANS +S 3800,400,3800,900,200,*,DOWN,NDIF +S 4500,200,4500,1100,100,*,UP,NTRANS +S 4100,200,4100,1100,100,*,UP,NTRANS +S 1900,400,1900,1300,100,*,UP,NTRANS +S 2500,400,2500,1300,100,*,UP,NTRANS +S 6300,600,6300,1900,100,*,DOWN,NTRANS +S 6600,800,6600,1700,300,*,DOWN,NDIF +S 400,1000,400,1900,300,*,DOWN,NDIF +S 1000,2800,1000,3400,300,*,UP,PDIF +S 5100,2600,5100,3600,100,*,UP,PTRANS +S 700,2600,700,3600,100,*,UP,PTRANS +S 4800,2800,4800,3400,300,*,UP,PDIF +S 6000,2800,6000,4700,300,*,UP,PDIF +S 5400,2800,5400,4600,300,*,DOWN,PDIF +S 5700,2600,5700,4900,100,*,UP,PTRANS +S 1900,3600,1900,4900,100,*,UP,PTRANS +S 2200,3500,2200,4700,300,*,UP,PDIF +S 1600,3800,1600,4700,200,*,DOWN,PDIF +S 1300,3600,1300,4900,100,*,UP,PTRANS +S 1000,3800,1000,4700,300,*,UP,PDIF +S 2900,3600,2900,4900,100,*,UP,PTRANS +S 3200,3800,3200,4700,200,*,UP,PDIF +S 4500,3600,4500,4900,100,*,UP,PTRANS +S 4800,3800,4800,4700,300,*,UP,PDIF +S 4100,3600,4100,4900,100,*,UP,PTRANS +S 3500,3600,3500,4900,100,*,UP,PTRANS +S 3800,3800,3800,4700,200,*,UP,PDIF +S 2500,3600,2500,4900,100,*,UP,PTRANS +S 6300,2600,6300,4900,100,*,UP,PTRANS +S 6600,2800,6600,4700,300,*,UP,PDIF +S 400,2800,400,4000,300,*,UP,PDIF +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 1000,3000,1700,3000,100,*,LEFT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,3000,4300,3000,200,*,RIGHT,ALU1 +S 4000,2000,4300,2000,200,*,RIGHT,ALU1 +S 4300,2500,4500,2500,200,*,LEFT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 5500,2000,5600,2000,200,*,LEFT,ALU1 +S 4800,1000,5500,1000,100,*,RIGHT,ALU1 +S 2200,3500,5500,3500,100,*,RIGHT,ALU1 +S 6100,2000,6500,2000,200,*,RIGHT,ALU1 +S 4800,2950,5000,2950,100,*,RIGHT,ALU1 +S 3500,2500,3800,2500,200,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2700,2000,3000,2000,100,*,RIGHT,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1700,2000,2000,2000,100,*,RIGHT,ALU1 +S 2000,2950,2400,2950,100,*,RIGHT,ALU1 +S 5100,1300,5100,1900,100,*,DOWN,NTRANS +S 5100,1900,5100,2600,100,*,DOWN,POLY +S 5000,1700,5000,2950,100,*,DOWN,ALU1 +S 3300,1500,4800,1500,100,*,RIGHT,ALU1 +S 4800,1700,5000,1700,100,*,LEFT,ALU1 +S 4800,1500,4800,1700,100,*,DOWN,ALU1 +V 5600,2000,CONT_POLY,* +V 3800,2500,CONT_POLY,* +V 4300,2000,CONT_POLY,* +V 4300,3000,CONT_POLY,* +V 1700,1500,CONT_POLY,* +V 3300,1500,CONT_POLY,* +V 4100,1500,CONT_POLY,* +V 1700,3500,CONT_POLY,* +V 2400,3000,CONT_POLY,* +V 400,2500,CONT_POLY,* +V 6000,300,CONT_BODY_P,* +V 400,400,CONT_BODY_P,* +V 6600,1500,CONT_DIF_N,* +V 6000,1500,CONT_DIF_N,* +V 1000,1800,CONT_DIF_N,* +V 1000,1800,CONT_DIF_N,* +V 2200,1500,CONT_DIF_N,* +V 6000,1000,CONT_DIF_N,* +V 5400,500,CONT_DIF_N,* +V 3800,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 4800,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 6600,1000,CONT_DIF_N,* +V 400,1000,CONT_DIF_N,* +V 1000,3000,CONT_DIF_P,* +V 6600,3000,CONT_DIF_P,* +V 6600,3500,CONT_DIF_P,* +V 6600,4000,CONT_DIF_P,* +V 6000,3000,CONT_DIF_P,* +V 6000,4000,CONT_DIF_P,* +V 6000,3500,CONT_DIF_P,* +V 5400,4600,CONT_DIF_P,* +V 4800,3000,CONT_DIF_P,* +V 6600,4600,CONT_DIF_P,* +V 4800,4000,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 2200,3500,CONT_DIF_P,* +V 3800,4500,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 400,4600,CONT_BODY_N,* +V 400,4000,CONT_DIF_P,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 4800,1600,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/mx3_x4.vbe b/alliance/src/cells/src/sxlib/mx3_x4.vbe new file mode 100644 index 00000000..d69143bd --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx3_x4.vbe @@ -0,0 +1,59 @@ +ENTITY mx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 810; + CONSTANT rdown_cmd0_q : NATURAL := 810; + CONSTANT rdown_cmd1_q : NATURAL := 810; + CONSTANT rdown_cmd1_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_cmd0_q : NATURAL := 890; + CONSTANT rup_cmd0_q : NATURAL := 890; + CONSTANT rup_cmd1_q : NATURAL := 890; + CONSTANT rup_cmd1_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 640; + CONSTANT tphh_cmd0_q : NATURAL := 683; + CONSTANT tphh_i1_q : NATURAL := 770; + CONSTANT tphh_i2_q : NATURAL := 770; + CONSTANT tpll_i0_q : NATURAL := 774; + CONSTANT tpll_cmd0_q : NATURAL := 779; + CONSTANT tphh_cmd1_q : NATURAL := 792; + CONSTANT tplh_cmd0_q : NATURAL := 844; + CONSTANT tplh_cmd1_q : NATURAL := 846; + CONSTANT tphl_cmd1_q : NATURAL := 872; + CONSTANT tphl_cmd0_q : NATURAL := 922; + CONSTANT tpll_i1_q : NATURAL := 948; + CONSTANT tpll_i2_q : NATURAL := 948; + CONSTANT tpll_cmd1_q : NATURAL := 967; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x4; + +ARCHITECTURE behaviour_data_flow OF mx3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx3_x4" + SEVERITY WARNING; + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) + and i2)))) after 1600 ps; +END; diff --git a/alliance/src/cells/src/sxlib/mx3_x4.vhd b/alliance/src/cells/src/sxlib/mx3_x4.vhd new file mode 100644 index 00000000..281c341e --- /dev/null +++ b/alliance/src/cells/src/sxlib/mx3_x4.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY mx3_x4 IS +PORT( + cmd0 : IN STD_LOGIC; + cmd1 : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END mx3_x4; + +ARCHITECTURE RTL OF mx3_x4 IS +BEGIN + q <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2)))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/na2_x1.al b/alliance/src/cells/src/sxlib/na2_x1.al new file mode 100644 index 00000000..e9556bd6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na2_x1.al @@ -0,0 +1,24 @@ +V ALLIANCE : 6 +H na2_x1,L,30/10/99 +C i0,IN,EXTERNAL,5 +C i1,IN,EXTERNAL,4 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,2 +T P,0.35,2.9,1,5,6,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00004 +T P,0.35,2.9,6,4,1,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00003 +T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00002 +T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,3.3,3.75,tr_00001 +S 6,EXTERNAL,vdd +Q 0.00282047 +S 5,EXTERNAL,i0 +Q 0.00353623 +S 4,EXTERNAL,i1 +Q 0.00368237 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.0026442 +S 1,EXTERNAL,nq +Q 0.00279086 +EOF diff --git a/alliance/src/cells/src/sxlib/na2_x1.ap b/alliance/src/cells/src/sxlib/na2_x1.ap new file mode 100644 index 00000000..f900eaf4 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na2_x1.ap @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H na2_x1,P,30/ 8/2000,100 +A 0,0,2000,5000 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +R 1500,4000,ref_ref,i1_40 +R 1500,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 1500,1500,1500,4000,200,i1,DOWN,CALU1 +S 500,1000,500,4000,200,i0,DOWN,CALU1 +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +S 400,3000,700,3000,300,*,RIGHT,POLY +S 1500,1500,1500,4000,100,*,DOWN,ALU1 +S 1600,3300,1600,4600,300,*,DOWN,PDIF +S 400,3300,400,4600,300,*,DOWN,PDIF +S 700,3100,700,4400,100,*,UP,PTRANS +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 1300,2000,1600,2000,300,*,RIGHT,POLY +S 1300,1900,1300,3100,100,*,DOWN,POLY +S 700,600,700,1900,100,*,DOWN,NTRANS +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 700,1900,700,3100,100,*,UP,POLY +S 1100,1900,1600,1900,100,*,RIGHT,POLY +S 1000,1000,1400,1000,200,*,RIGHT,ALU1 +S 1400,800,1400,1700,300,*,UP,NDIF +S 400,400,400,1700,300,*,UP,NDIF +S 1000,950,1000,4000,200,*,UP,ALU1 +V 500,3000,CONT_POLY,* +V 1600,4500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1000,4700,CONT_BODY_N,* +V 1500,2000,CONT_POLY,* +V 400,500,CONT_DIF_N,* +V 1400,1000,CONT_DIF_N,* +V 1250,300,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/na2_x1.sym b/alliance/src/cells/src/sxlib/na2_x1.sym new file mode 100644 index 00000000..0ef443c8 Binary files /dev/null and b/alliance/src/cells/src/sxlib/na2_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/na2_x1.vbe b/alliance/src/cells/src/sxlib/na2_x1.vbe new file mode 100644 index 00000000..486b6aaf --- /dev/null +++ b/alliance/src/cells/src/sxlib/na2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 59; + CONSTANT tphl_i1_nq : NATURAL := 111; + CONSTANT tplh_i1_nq : NATURAL := 234; + CONSTANT tplh_i0_nq : NATURAL := 288; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x1; + +ARCHITECTURE behaviour_data_flow OF na2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x1" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 900 ps; +END; diff --git a/alliance/src/cells/src/sxlib/na2_x1.vhd b/alliance/src/cells/src/sxlib/na2_x1.vhd new file mode 100644 index 00000000..23b74f77 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na2_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na2_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na2_x1; + +ARCHITECTURE RTL OF na2_x1 IS +BEGIN + nq <= NOT((i0 AND i1)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/na2_x4.al b/alliance/src/cells/src/sxlib/na2_x4.al new file mode 100644 index 00000000..49769d58 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na2_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H na2_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,6,3,5,0,0.75,0.75,7.3,7.3,8.7,9.75,tr_00010 +T P,0.35,5.9,2,6,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,5,6,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,2.9,3,8,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T P,0.35,2.9,5,7,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00006 +T N,0.35,2.9,1,6,2,0,0.75,0.75,7.3,7.3,5.1,2.25,tr_00005 +T N,0.35,2.9,2,6,1,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00004 +T N,0.35,1.4,1,3,6,0,0.75,0.75,4.3,4.3,8.7,3,tr_00003 +T N,0.35,2.9,4,7,1,0,0.75,0.75,7.3,7.3,3.3,3.75,tr_00002 +T N,0.35,2.9,3,8,4,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00001 +S 8,EXTERNAL,i0 +Q 0.00260759 +S 7,EXTERNAL,i1 +Q 0.00297253 +S 6,INTERNAL +Q 0.0060306 +S 5,EXTERNAL,vdd +Q 0.0046087 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00560951 +S 2,EXTERNAL,nq +Q 0.00214456 +S 1,EXTERNAL,vss +Q 0.00419742 +EOF diff --git a/alliance/src/cells/src/sxlib/na2_x4.ap b/alliance/src/cells/src/sxlib/na2_x4.ap new file mode 100644 index 00000000..3d02b215 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na2_x4.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H na2_x4,P,30/ 8/2000,100 +A 0,0,3500,5000 +R 2000,1000,ref_ref,nq_10 +R 2000,1500,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_20 +R 2000,2500,ref_ref,nq_25 +R 2000,3000,ref_ref,nq_30 +R 2000,3500,ref_ref,nq_35 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +S 2000,1000,2000,3500,200,nq,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 300,300,900,300,300,*,LEFT,PTIE +S 1700,100,1700,1400,100,*,DOWN,NTRANS +S 2000,300,2000,1200,300,*,UP,NDIF +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 2600,300,2600,1200,300,*,UP,NDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 2900,600,2900,1400,100,*,DOWN,NTRANS +S 3200,800,3200,1200,300,*,DOWN,NDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 2900,2600,2900,3900,100,*,UP,PTRANS +S 3200,2800,3200,3700,300,*,UP,PDIF +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 300,1000,1500,1000,100,*,RIGHT,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,UP,ALU1 +S 900,4000,3000,4000,100,*,RIGHT,ALU1 +S 3200,1000,3200,3500,100,*,DOWN,ALU1 +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 850,3700,850,4200,200,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 2700,4300,2700,4700,300,*,UP,PDIF +S 1200,1900,1200,3100,100,*,UP,POLY +S 900,2000,1200,2000,300,*,RIGHT,POLY +S 2500,2000,3200,2000,100,*,LEFT,ALU1 +S 1700,2000,2600,2000,300,*,RIGHT,POLY +S 1700,1400,1700,2100,100,*,UP,POLY +S 2300,1400,2300,1900,100,*,DOWN,POLY +S 1800,1900,1800,2600,100,*,DOWN,POLY +S 2400,1900,2400,2600,100,*,DOWN,POLY +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 300,800,300,1700,300,*,UP,NDIF +S 900,800,900,1700,300,*,UP,NDIF +S 600,600,600,1900,100,*,DOWN,NTRANS +S 600,1900,600,3100,100,*,DOWN,POLY +S 1400,300,1400,1700,300,*,UP,NDIF +S 2000,1000,2000,3550,200,*,DOWN,ALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +V 3200,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 300,1000,CONT_DIF_N,* +V 1400,500,CONT_DIF_N,* +V 2600,500,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 800,300,CONT_BODY_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3000,4000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 2700,4500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 2500,2000,CONT_POLY,* +V 1500,4500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/na2_x4.sym b/alliance/src/cells/src/sxlib/na2_x4.sym new file mode 100644 index 00000000..be1b6080 Binary files /dev/null and b/alliance/src/cells/src/sxlib/na2_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/na2_x4.vbe b/alliance/src/cells/src/sxlib/na2_x4.vbe new file mode 100644 index 00000000..c73eca05 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 353; + CONSTANT tphl_i0_nq : NATURAL := 412; + CONSTANT tplh_i0_nq : NATURAL := 552; + CONSTANT tplh_i1_nq : NATURAL := 601; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x4; + +ARCHITECTURE behaviour_data_flow OF na2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x4" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/na2_x4.vhd b/alliance/src/cells/src/sxlib/na2_x4.vhd new file mode 100644 index 00000000..ef555cb4 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na2_x4; + +ARCHITECTURE RTL OF na2_x4 IS +BEGIN + nq <= NOT((i0 AND i1)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/na3_x1.al b/alliance/src/cells/src/sxlib/na3_x1.al new file mode 100644 index 00000000..e2da070a --- /dev/null +++ b/alliance/src/cells/src/sxlib/na3_x1.al @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H na3_x1,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,5 +C i2,IN,EXTERNAL,6 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,8 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,2,7,8,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00006 +T P,0.35,2.9,2,6,8,0,0.75,0.75,7.3,7.3,5.7,11.25,tr_00005 +T P,0.35,2.9,8,5,2,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00004 +T N,0.35,2.9,1,6,2,0,0.75,0.75,7.3,7.3,4.2,2.25,tr_00003 +T N,0.35,2.9,4,5,1,0,0.75,0.75,7.3,7.3,3,2.25,tr_00002 +T N,0.35,2.9,3,7,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 8,EXTERNAL,vdd +Q 0.0033382 +S 7,EXTERNAL,i0 +Q 0.00388325 +S 6,EXTERNAL,i2 +Q 0.00352565 +S 5,EXTERNAL,i1 +Q 0.00390877 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00298567 +S 2,EXTERNAL,nq +Q 0.00346654 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/na3_x1.ap b/alliance/src/cells/src/sxlib/na3_x1.ap new file mode 100644 index 00000000..ffa9d262 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na3_x1.ap @@ -0,0 +1,77 @@ +V ALLIANCE : 6 +H na3_x1,P,30/ 8/2000,100 +A 0,0,2500,5000 +R 1500,1000,ref_ref,i2_10 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1500,2500,ref_ref,i2_25 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 2000,1000,ref_ref,nq_10 +R 2000,1500,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_20 +R 2000,3000,ref_ref,nq_30 +R 2000,2500,ref_ref,nq_25 +R 2000,3500,ref_ref,nq_35 +R 2000,4000,ref_ref,nq_40 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 500,1000,500,4000,200,i0,DOWN,CALU1 +S 2000,1000,2000,4000,200,nq,DOWN,CALU1 +S 2000,4000,2200,4000,200,*,RIGHT,ALU1 +S 1000,1400,1000,2100,100,*,UP,POLY +S 1300,1900,1300,3100,100,*,DOWN,POLY +S 900,2000,1300,2000,300,*,RIGHT,POLY +S 400,3000,700,3000,300,*,RIGHT,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 1400,1600,1900,1600,100,*,LEFT,POLY +S 1900,1600,1900,3100,100,*,DOWN,POLY +S 700,3100,700,4400,100,*,UP,PTRANS +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 1600,3300,1600,4600,300,*,DOWN,PDIF +S 400,3300,400,4600,300,*,DOWN,PDIF +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 2200,3300,2200,4200,300,*,DOWN,PDIF +S 1900,800,1900,1200,500,*,UP,NDIF +S 1600,300,1600,1200,200,*,UP,NDIF +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,UP,ALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 800,300,800,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +S 1700,900,1700,1200,300,*,DOWN,NDIF +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 1000,4000,2200,4000,200,*,RIGHT,ALU1 +V 1000,2000,CONT_POLY,* +V 500,3000,CONT_POLY,* +V 2200,4700,CONT_BODY_N,* +V 1000,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 2200,4000,CONT_DIF_P,* +V 1000,4700,CONT_BODY_N,* +V 2000,1000,CONT_DIF_N,* +V 1500,1500,CONT_POLY,* +V 2200,300,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/na3_x1.sym b/alliance/src/cells/src/sxlib/na3_x1.sym new file mode 100644 index 00000000..f2d1f56c Binary files /dev/null and b/alliance/src/cells/src/sxlib/na3_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/na3_x1.vbe b/alliance/src/cells/src/sxlib/na3_x1.vbe new file mode 100644 index 00000000..d51e1207 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 4120; + CONSTANT rdown_i1_nq : NATURAL := 4120; + CONSTANT rdown_i2_nq : NATURAL := 4120; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 119; + CONSTANT tphl_i1_nq : NATURAL := 171; + CONSTANT tphl_i2_nq : NATURAL := 193; + CONSTANT tplh_i2_nq : NATURAL := 265; + CONSTANT tplh_i1_nq : NATURAL := 316; + CONSTANT tplh_i0_nq : NATURAL := 363; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x1; + +ARCHITECTURE behaviour_data_flow OF na3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/na3_x1.vhd b/alliance/src/cells/src/sxlib/na3_x1.vhd new file mode 100644 index 00000000..278daf09 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na3_x1.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na3_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na3_x1; + +ARCHITECTURE RTL OF na3_x1 IS +BEGIN + nq <= NOT(((i0 AND i1) AND i2)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/na3_x4.al b/alliance/src/cells/src/sxlib/na3_x4.al new file mode 100644 index 00000000..caa069a8 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na3_x4.al @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H na3_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,5 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,4 +T P,0.35,2.9,6,9,3,0,0.75,0.75,7.3,7.3,5.4,10.95,tr_00012 +T P,0.35,2.9,3,10,6,0,0.75,0.75,7.3,7.3,3.6,10.95,tr_00011 +T P,0.35,2.9,6,8,3,0,0.75,0.75,7.3,7.3,1.8,10.95,tr_00010 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00009 +T P,0.35,2.9,7,3,6,0,0.75,0.75,7.3,7.3,10.2,9.75,tr_00008 +T P,0.35,5.9,5,7,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00007 +T N,0.35,2.9,2,9,4,0,0.75,0.75,7.3,7.3,4.5,3.75,tr_00006 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00005 +T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,3.3,3.75,tr_00004 +T N,0.35,2.9,4,7,5,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,5,7,4,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002 +T N,0.35,1.4,4,3,7,0,0.75,0.75,4.3,4.3,10.2,3,tr_00001 +S 10,EXTERNAL,i2 +Q 0.00312291 +S 9,EXTERNAL,i1 +Q 0.00275797 +S 8,EXTERNAL,i0 +Q 0.00290312 +S 7,INTERNAL +Q 0.0060306 +S 6,EXTERNAL,vdd +Q 0.00436263 +S 5,EXTERNAL,nq +Q 0.00214456 +S 4,EXTERNAL,vss +Q 0.00436263 +S 3,INTERNAL +Q 0.00663132 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/na3_x4.ap b/alliance/src/cells/src/sxlib/na3_x4.ap new file mode 100644 index 00000000..4022c49c --- /dev/null +++ b/alliance/src/cells/src/sxlib/na3_x4.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H na3_x4,P,30/ 8/2000,100 +A 0,0,4000,5000 +R 1500,3000,ref_ref,i1_30 +R 1500,3500,ref_ref,i1_35 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 2500,1000,ref_ref,nq_10 +R 2500,1500,ref_ref,nq_15 +R 2500,2000,ref_ref,nq_20 +R 2500,2500,ref_ref,nq_25 +R 2500,3000,ref_ref,nq_30 +R 2500,3500,ref_ref,nq_35 +R 1000,3500,ref_ref,i2_35 +R 1000,3000,ref_ref,i2_30 +R 1000,2500,ref_ref,i2_25 +R 1000,2000,ref_ref,i2_20 +R 1000,1500,ref_ref,i2_15 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1500,1500,1500,3500,200,i1,DOWN,CALU1 +S 2500,1000,2500,3500,200,nq,DOWN,CALU1 +S 1000,1500,1000,3500,200,i2,DOWN,CALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1100,1900,1100,2600,100,*,UP,POLY +S 900,2500,1200,2500,300,*,RIGHT,POLY +S 600,1900,600,3000,100,*,DOWN,POLY +S 1200,2400,1200,3000,100,*,DOWN,POLY +S 1800,2100,1800,3000,100,*,DOWN,POLY +S 900,3200,900,4600,300,*,DOWN,PDIF +S 300,3200,300,4100,300,*,DOWN,PDIF +S 1800,3000,1800,4300,100,*,UP,PTRANS +S 1500,3200,1500,4100,300,*,DOWN,PDIF +S 1200,3000,1200,4300,100,*,UP,PTRANS +S 600,3000,600,4300,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1400,2100,1800,2100,100,*,RIGHT,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 400,2000,700,2000,300,*,RIGHT,POLY +S 300,4000,3500,4000,100,*,RIGHT,ALU1 +S 400,1000,2000,1000,100,*,RIGHT,ALU1 +S 400,800,400,1700,300,*,UP,NDIF +S 1800,300,1800,1700,300,*,UP,NDIF +S 1500,600,1500,1900,100,*,DOWN,NTRANS +S 700,600,700,1900,100,*,DOWN,NTRANS +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 3700,800,3700,1200,300,*,DOWN,NDIF +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 1900,300,1900,1700,300,*,UP,NDIF +S 2200,100,2200,1400,100,*,DOWN,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 3100,300,3100,1200,300,*,UP,NDIF +S 3400,600,3400,1400,100,*,DOWN,NTRANS +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,DOWN,PDIF +S 3400,2600,3400,3900,100,*,UP,PTRANS +S 3700,2800,3700,3700,300,*,UP,PDIF +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2200,2000,3100,2000,300,*,RIGHT,POLY +S 2200,1400,2200,2100,100,*,UP,POLY +S 2800,1400,2800,1900,100,*,DOWN,POLY +S 2300,1900,2300,2600,100,*,DOWN,POLY +S 2900,1900,2900,2600,100,*,DOWN,POLY +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 3000,2000,3700,2000,100,*,LEFT,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 3700,1000,3700,3500,100,*,DOWN,ALU1 +S 2500,1000,2500,3550,200,*,DOWN,ALU1 +V 300,300,CONT_BODY_P,* +V 900,4500,CONT_DIF_P,* +V 3200,4600,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 300,4000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 400,1000,CONT_DIF_N,* +V 1900,500,CONT_DIF_N,* +V 3100,500,CONT_DIF_N,* +V 2500,1000,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 3700,3000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 2600,3000,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 3700,300,CONT_BODY_P,* +V 3500,4000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 2000,4600,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/na3_x4.sym b/alliance/src/cells/src/sxlib/na3_x4.sym new file mode 100644 index 00000000..95146908 Binary files /dev/null and b/alliance/src/cells/src/sxlib/na3_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/na3_x4.vbe b/alliance/src/cells/src/sxlib/na3_x4.vbe new file mode 100644 index 00000000..160a97f6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 460; + CONSTANT tphl_i2_nq : NATURAL := 519; + CONSTANT tphl_i0_nq : NATURAL := 556; + CONSTANT tplh_i0_nq : NATURAL := 601; + CONSTANT tplh_i2_nq : NATURAL := 647; + CONSTANT tplh_i1_nq : NATURAL := 691; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x4; + +ARCHITECTURE behaviour_data_flow OF na3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/na3_x4.vhd b/alliance/src/cells/src/sxlib/na3_x4.vhd new file mode 100644 index 00000000..ccf28ce7 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na3_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na3_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na3_x4; + +ARCHITECTURE RTL OF na3_x4 IS +BEGIN + nq <= NOT(((i0 AND i1) AND i2)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/na4_x1.al b/alliance/src/cells/src/sxlib/na4_x1.al new file mode 100644 index 00000000..3287ed3c --- /dev/null +++ b/alliance/src/cells/src/sxlib/na4_x1.al @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H na4_x1,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,6 +C i3,IN,EXTERNAL,9 +C nq,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,10,7,4,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,2.9,4,6,10,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00007 +T P,0.35,2.9,10,9,4,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00006 +T P,0.35,2.9,4,8,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00005 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00004 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3,2.25,tr_00003 +T N,0.35,2.9,2,6,5,0,0.75,0.75,7.3,7.3,4.2,2.25,tr_00002 +T N,0.35,2.9,5,9,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 10,EXTERNAL,vdd +Q 0.00444349 +S 9,EXTERNAL,i3 +Q 0.00381484 +S 8,EXTERNAL,i0 +Q 0.00323647 +S 7,EXTERNAL,i1 +Q 0.00345625 +S 6,EXTERNAL,i2 +Q 0.00367603 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,nq +Q 0.0035253 +S 3,EXTERNAL,vss +Q 0.00332715 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/na4_x1.ap b/alliance/src/cells/src/sxlib/na4_x1.ap new file mode 100644 index 00000000..9207c5af --- /dev/null +++ b/alliance/src/cells/src/sxlib/na4_x1.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H na4_x1,P,30/ 8/2000,100 +A 0,0,3000,5000 +R 2500,4000,ref_ref,nq_40 +R 2500,1000,ref_ref,nq_10 +R 2500,1500,ref_ref,nq_15 +R 2500,2000,ref_ref,nq_20 +R 2500,2500,ref_ref,nq_25 +R 2500,3000,ref_ref,nq_30 +R 2500,3500,ref_ref,nq_35 +R 2000,3500,ref_ref,i3_35 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 2000,1000,ref_ref,i3_10 +R 1500,1000,ref_ref,i2_10 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1500,2500,ref_ref,i2_25 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 500,1000,ref_ref,i0_10 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +S 300,4000,300,4500,200,*,UP,ALU1 +S 900,4000,2550,4000,200,*,LEFT,ALU1 +S 2500,1000,2500,4050,200,*,UP,ALU1 +S 600,1400,600,3100,100,*,DOWN,POLY +S 2400,1900,2400,3100,100,*,UP,POLY +S 1800,1900,2400,1900,100,*,RIGHT,POLY +S 1800,1400,1800,1900,100,*,UP,POLY +S 1800,2600,1800,3100,100,*,UP,POLY +S 1400,2600,1800,2600,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 1000,1400,1000,3100,100,*,UP,POLY +S 2300,800,2300,1200,700,*,UP,NDIF +S 2000,1000,2000,3500,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1500,3300,1500,4600,300,*,DOWN,PDIF +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 2500,1000,2500,4000,200,nq,DOWN,CALU1 +S 2000,1000,2000,3500,200,i3,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +V 300,4000,CONT_DIF_P,* +V 500,1500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 900,4700,CONT_BODY_N,* +V 2100,4700,CONT_BODY_N,* +V 2500,1000,CONT_DIF_N,* +V 2100,4000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 2700,300,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/na4_x1.sym b/alliance/src/cells/src/sxlib/na4_x1.sym new file mode 100644 index 00000000..17cafb1e Binary files /dev/null and b/alliance/src/cells/src/sxlib/na4_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/na4_x1.vbe b/alliance/src/cells/src/sxlib/na4_x1.vbe new file mode 100644 index 00000000..07f51ce0 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 5400; + CONSTANT rdown_i1_nq : NATURAL := 5400; + CONSTANT rdown_i2_nq : NATURAL := 5400; + CONSTANT rdown_i3_nq : NATURAL := 5400; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT rup_i3_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 179; + CONSTANT tphl_i1_nq : NATURAL := 237; + CONSTANT tphl_i2_nq : NATURAL := 269; + CONSTANT tphl_i3_nq : NATURAL := 282; + CONSTANT tplh_i3_nq : NATURAL := 302; + CONSTANT tplh_i2_nq : NATURAL := 350; + CONSTANT tplh_i1_nq : NATURAL := 395; + CONSTANT tplh_i0_nq : NATURAL := 438; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x1; + +ARCHITECTURE behaviour_data_flow OF na4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/na4_x1.vhd b/alliance/src/cells/src/sxlib/na4_x1.vhd new file mode 100644 index 00000000..cedcb1c0 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na4_x1.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na4_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na4_x1; + +ARCHITECTURE RTL OF na4_x1 IS +BEGIN + nq <= NOT((((i0 AND i1) AND i2) AND i3)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/na4_x4.al b/alliance/src/cells/src/sxlib/na4_x4.al new file mode 100644 index 00000000..111fa2f3 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na4_x4.al @@ -0,0 +1,48 @@ +V ALLIANCE : 6 +H na4_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,11 +C i3,IN,EXTERNAL,12 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,5,12,7,0,0.75,0.75,7.3,7.3,13.2,11.25,tr_00014 +T P,0.35,2.9,7,11,5,0,0.75,0.75,7.3,7.3,11.4,11.25,tr_00013 +T P,0.35,2.9,5,8,7,0,0.75,0.75,7.3,7.3,9.6,11.25,tr_00012 +T P,0.35,2.9,7,6,5,0,0.75,0.75,7.3,7.3,7.8,11.25,tr_00011 +T P,0.35,5.9,2,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T P,0.35,5.9,5,4,2,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,2.9,5,7,4,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00008 +T N,0.35,2.9,9,11,10,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00007 +T N,0.35,2.9,1,8,9,0,0.75,0.75,7.3,7.3,9,2.25,tr_00006 +T N,0.35,2.9,3,6,1,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00005 +T N,0.35,2.9,10,12,7,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00004 +T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003 +T N,0.35,2.9,3,4,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,1.4,4,7,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 12,EXTERNAL,i3 +Q 0.00381484 +S 11,EXTERNAL,i2 +Q 0.00367603 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0 +S 8,EXTERNAL,i1 +Q 0.00345625 +S 7,INTERNAL +Q 0.00793105 +S 6,EXTERNAL,i0 +Q 0.00323647 +S 5,EXTERNAL,vdd +Q 0.00557437 +S 4,INTERNAL +Q 0.00589179 +S 3,EXTERNAL,vss +Q 0.00504558 +S 2,EXTERNAL,nq +Q 0.00211518 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/na4_x4.ap b/alliance/src/cells/src/sxlib/na4_x4.ap new file mode 100644 index 00000000..8f6b0f1f --- /dev/null +++ b/alliance/src/cells/src/sxlib/na4_x4.ap @@ -0,0 +1,126 @@ +V ALLIANCE : 6 +H na4_x4,P,30/ 8/2000,100 +A 0,0,5000,5000 +R 1500,1000,ref_ref,nq_10 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 3500,1500,ref_ref,i2_15 +R 3500,1000,ref_ref,i2_10 +R 4000,1000,ref_ref,i3_10 +R 4000,1500,ref_ref,i3_15 +R 4000,2000,ref_ref,i3_20 +R 4000,2500,ref_ref,i3_25 +R 4000,3000,ref_ref,i3_30 +R 4000,3500,ref_ref,i3_35 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 3500,3500,ref_ref,i2_35 +R 3500,3000,ref_ref,i2_30 +R 3500,2500,ref_ref,i2_25 +R 3500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i0_15 +R 2500,2000,ref_ref,i0_20 +R 2500,2500,ref_ref,i0_25 +R 2500,3000,ref_ref,i0_30 +R 2500,3500,ref_ref,i0_35 +R 2500,1000,ref_ref,i0_10 +R 3000,1000,ref_ref,i1_10 +R 3000,1500,ref_ref,i1_15 +S 300,3000,300,3500,100,*,DOWN,ALU1 +S 4550,1000,4550,4000,100,*,UP,ALU1 +S 4400,1900,4400,3100,100,*,UP,POLY +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 2300,3300,2300,4700,300,*,DOWN,PDIF +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 300,1000,300,3000,100,*,DOWN,ALU1 +S 600,2500,800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,2600,600,3900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,DOWN,PDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 3800,100,3800,1400,100,*,DOWN,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 4300,800,4300,1200,700,*,UP,NDIF +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,DOWN,NTRANS +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2600,3100,2600,4400,100,*,UP,PTRANS +S 4700,3300,4700,4600,300,*,DOWN,PDIF +S 3500,3300,3500,4600,300,*,DOWN,PDIF +S 4100,3300,4100,4200,300,*,DOWN,PDIF +S 2900,3300,2900,4200,300,*,DOWN,PDIF +S 3200,3100,3200,4400,100,*,UP,PTRANS +S 3800,3100,3800,4400,100,*,UP,PTRANS +S 4400,3100,4400,4400,100,*,UP,PTRANS +S 2600,1400,2600,3100,100,*,DOWN,POLY +S 3000,1400,3000,3100,100,*,UP,POLY +S 3000,3100,3200,3100,100,*,RIGHT,POLY +S 3400,1400,3400,2600,100,*,UP,POLY +S 3400,2600,3800,2600,100,*,RIGHT,POLY +S 3800,2600,3800,3100,100,*,UP,POLY +S 3800,1400,3800,1900,100,*,UP,POLY +S 3800,1900,4400,1900,100,*,RIGHT,POLY +S 2500,1000,2500,3500,100,*,DOWN,ALU1 +S 3000,1000,3000,3500,100,*,DOWN,ALU1 +S 3500,1000,3500,3500,100,*,DOWN,ALU1 +S 4000,1000,4000,3500,100,*,DOWN,ALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 1050,1500,1050,4000,100,*,DOWN,ALU1 +S 800,2500,1050,2500,200,*,RIGHT,ALU1 +S 800,1500,1050,1500,200,*,RIGHT,ALU1 +S 600,2000,1800,2000,300,*,RIGHT,POLY +S 300,2000,600,2000,200,*,LEFT,ALU1 +S 1050,4000,4550,4000,100,*,LEFT,ALU1 +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 3500,1000,3500,3500,200,i2,DOWN,CALU1 +S 4000,1000,4000,3500,200,i3,DOWN,CALU1 +S 3000,1000,3000,3500,200,i1,DOWN,CALU1 +S 2500,1000,2500,3500,200,i0,DOWN,CALU1 +V 300,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 2200,500,CONT_DIF_N,* +V 2200,4500,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 800,2500,CONT_POLY,* +V 300,300,CONT_BODY_P,* +V 300,4700,CONT_BODY_N,* +V 300,3000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 4500,1000,CONT_DIF_N,* +V 2900,4000,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 3500,4500,CONT_DIF_P,* +V 4700,4500,CONT_DIF_P,* +V 4100,4700,CONT_BODY_N,* +V 2900,4700,CONT_BODY_N,* +V 4700,300,CONT_BODY_P,* +V 3000,2000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 600,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/na4_x4.sym b/alliance/src/cells/src/sxlib/na4_x4.sym new file mode 100644 index 00000000..9b5c878b Binary files /dev/null and b/alliance/src/cells/src/sxlib/na4_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/na4_x4.vbe b/alliance/src/cells/src/sxlib/na4_x4.vbe new file mode 100644 index 00000000..a67d1890 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 578; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i3_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 681; + CONSTANT tplh_i2_nq : NATURAL := 689; + CONSTANT tphl_i3_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 731; + CONSTANT tplh_i0_nq : NATURAL := 771; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x4; + +ARCHITECTURE behaviour_data_flow OF na4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/na4_x4.vhd b/alliance/src/cells/src/sxlib/na4_x4.vhd new file mode 100644 index 00000000..5593da22 --- /dev/null +++ b/alliance/src/cells/src/sxlib/na4_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na4_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na4_x4; + +ARCHITECTURE RTL OF na4_x4 IS +BEGIN + nq <= NOT((((i0 AND i1) AND i2) AND i3)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/nao22_x1.al b/alliance/src/cells/src/sxlib/nao22_x1.al new file mode 100644 index 00000000..22bbb6dc --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao22_x1.al @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H nao22_x1,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,4,8,1,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,5.9,5,6,4,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00005 +T P,0.35,5.9,1,7,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00004 +T N,0.35,2.9,2,6,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00003 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 8,EXTERNAL,i2 +Q 0.00344864 +S 7,EXTERNAL,i1 +Q 0.00288494 +S 6,EXTERNAL,i0 +Q 0.00260759 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00473727 +S 3,EXTERNAL,vss +Q 0.00432598 +S 2,INTERNAL +Q 0.00114171 +S 1,EXTERNAL,nq +Q 0.00282024 +EOF diff --git a/alliance/src/cells/src/sxlib/nao22_x1.ap b/alliance/src/cells/src/sxlib/nao22_x1.ap new file mode 100644 index 00000000..b99b0e5d --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao22_x1.ap @@ -0,0 +1,77 @@ +V ALLIANCE : 6 +H nao22_x1,P,30/ 8/2000,100 +A 0,0,3000,5000 +R 2000,1000,ref_ref,i2_10 +R 2000,4000,ref_ref,i2_40 +R 1500,4000,ref_ref,nq_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 1500,1500,ref_ref,nq_15 +R 1500,2000,ref_ref,nq_20 +R 1500,2500,ref_ref,nq_25 +R 1500,3000,ref_ref,nq_30 +R 1500,3500,ref_ref,nq_35 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 1500,1500,1500,4000,200,nq,DOWN,CALU1 +S 2000,1000,2000,4000,100,*,DOWN,ALU1 +S 2700,500,2700,1700,200,*,DOWN,ALU1 +S 2700,2900,2700,4500,200,*,DOWN,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 300,1000,1500,1000,100,*,RIGHT,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 900,300,900,1600,300,*,UP,NDIF +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1500,1450,1500,4000,200,*,UP,ALU1 +S 900,1500,1550,1500,200,*,RIGHT,ALU1 +V 2700,300,CONT_BODY_P,* +V 2700,4700,CONT_BODY_N,* +V 2700,2900,CONT_BODY_N,* +V 2700,1700,CONT_BODY_P,* +V 2100,4500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/nao22_x1.sym b/alliance/src/cells/src/sxlib/nao22_x1.sym new file mode 100644 index 00000000..865b45a3 Binary files /dev/null and b/alliance/src/cells/src/sxlib/nao22_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/nao22_x1.vbe b/alliance/src/cells/src/sxlib/nao22_x1.vbe new file mode 100644 index 00000000..13c4e6de --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 1790; + CONSTANT tphl_i2_nq : NATURAL := 165; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tplh_i2_nq : NATURAL := 238; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x1; + +ARCHITECTURE behaviour_data_flow OF nao22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 900 ps; +END; diff --git a/alliance/src/cells/src/sxlib/nao22_x1.vhd b/alliance/src/cells/src/sxlib/nao22_x1.vhd new file mode 100644 index 00000000..7873413c --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao22_x1.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nao22_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nao22_x1; + +ARCHITECTURE RTL OF nao22_x1 IS +BEGIN + nq <= NOT(((i0 OR i1) AND i2)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/nao22_x4.al b/alliance/src/cells/src/sxlib/nao22_x4.al new file mode 100644 index 00000000..1be1c88a --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao22_x4.al @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H nao22_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C i2,IN,EXTERNAL,5 +C nq,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,9 +C vss,IN,EXTERNAL,4 +T P,0.35,2.9,10,6,3,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00012 +T P,0.35,2.9,9,7,10,0,0.75,0.75,7.3,7.3,5.7,11.25,tr_00011 +T P,0.35,2.9,3,5,9,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00010 +T P,0.35,2.9,9,3,2,0,0.75,0.75,7.3,7.3,9.3,9.75,tr_00009 +T P,0.35,5.9,9,2,8,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00008 +T P,0.35,5.9,8,2,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00007 +T N,0.35,1.4,4,5,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00006 +T N,0.35,2.9,4,2,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00005 +T N,0.35,1.4,1,6,3,0,0.75,0.75,4.3,4.3,3.9,3,tr_00004 +T N,0.35,1.4,3,7,1,0,0.75,0.75,4.3,4.3,5.7,3,tr_00003 +T N,0.35,1.4,2,3,4,0,0.75,0.75,4.3,4.3,9.3,3,tr_00002 +T N,0.35,2.9,8,2,4,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00001 +S 10,INTERNAL +Q 0 +S 9,EXTERNAL,vdd +Q 0.00768955 +S 8,EXTERNAL,nq +Q 0.00258522 +S 7,EXTERNAL,i0 +Q 0.00358899 +S 6,EXTERNAL,i1 +Q 0.00295012 +S 5,EXTERNAL,i2 +Q 0.00379567 +S 4,EXTERNAL,vss +Q 0.00616192 +S 3,INTERNAL +Q 0.0066832 +S 2,INTERNAL +Q 0.00580421 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/alliance/src/cells/src/sxlib/nao22_x4.ap b/alliance/src/cells/src/sxlib/nao22_x4.ap new file mode 100644 index 00000000..72b06b7a --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao22_x4.ap @@ -0,0 +1,129 @@ +V ALLIANCE : 6 +H nao22_x4,P,30/ 8/2000,100 +A 0,0,5000,5000 +R 500,1000,ref_ref,i2_10 +R 500,1500,ref_ref,i2_15 +R 500,2500,ref_ref,i2_25 +R 500,3000,ref_ref,i2_30 +R 4000,3500,ref_ref,nq_35 +R 4000,3000,ref_ref,nq_30 +R 4000,2000,ref_ref,nq_20 +R 4000,1000,ref_ref,nq_10 +R 4000,1500,ref_ref,nq_15 +R 4000,2500,ref_ref,nq_25 +R 2000,2000,ref_ref,i0_20 +R 2000,2500,ref_ref,i0_25 +R 2000,3000,ref_ref,i0_30 +R 1500,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 500,2000,ref_ref,i2_20 +R 2000,3500,ref_ref,i0_35 +R 1500,3500,ref_ref,i1_35 +R 500,3500,ref_ref,i2_35 +R 500,4000,ref_ref,i2_40 +R 4000,4000,ref_ref,nq_40 +R 2500,1500,ref_ref,i0_15 +S 2000,2000,2400,2000,200,*,RIGHT,ALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 2000,2000,2000,3500,100,*,DOWN,ALU1 +S 1000,1500,1600,1500,100,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,DOWN,ALU1 +S 1600,800,1600,1600,300,*,UP,NDIF +S 400,400,400,1200,300,*,UP,NDIF +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 2800,2000,3500,2000,100,*,RIGHT,ALU1 +S 3300,2500,3300,3500,100,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 1100,4000,2800,4000,100,*,LEFT,ALU1 +S 2800,3500,2800,4000,100,*,UP,ALU1 +S 2800,3500,3300,3500,100,*,LEFT,ALU1 +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,2200,1000,100,*,RIGHT,ALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 500,2000,700,2000,300,*,RIGHT,POLY +S 1300,2000,1500,2000,300,*,RIGHT,POLY +S 3500,2000,4300,2000,300,*,RIGHT,POLY +S 3100,2500,3300,2500,300,*,RIGHT,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 3100,1400,3100,2600,100,*,DOWN,POLY +S 700,1400,700,3100,100,*,DOWN,POLY +S 1300,1400,1300,3100,100,*,DOWN,POLY +S 1900,1400,1900,3100,100,*,DOWN,POLY +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 4600,300,4600,1200,300,*,UP,NDIF +S 3100,600,3100,1400,100,*,DOWN,NTRANS +S 2800,800,2800,1200,300,*,UP,NDIF +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 2200,800,2200,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 3100,2600,3100,3900,100,*,UP,PTRANS +S 2800,2800,2800,3700,300,*,DOWN,PDIF +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 400,3300,400,4600,300,*,DOWN,PDIF +S 1600,3300,1600,4200,300,*,DOWN,PDIF +S 2200,3300,2200,4600,300,*,DOWN,PDIF +S 700,3100,700,4400,100,*,UP,PTRANS +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 2400,1500,2400,2000,100,*,DOWN,ALU1 +S 2400,1500,2500,1500,100,*,RIGHT,ALU1 +S 3500,1000,3500,2000,100,*,DOWN,ALU1 +S 2800,1000,3500,1000,100,*,LEFT,ALU1 +S 2800,2000,2800,3000,100,*,UP,ALU1 +S 500,1000,500,4000,200,i2,DOWN,CALU1 +S 4000,1000,4000,4000,200,nq,DOWN,CALU1 +S 1500,2000,1500,3500,200,i1,DOWN,CALU1 +S 2000,2000,2000,3500,200,i0,DOWN,CALU1 +S 2500,1500,2500,1500,200,i0,LEFT,CALU1 +V 1600,1500,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1600,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 3300,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2200,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 2800,300,CONT_BODY_P,* +V 2800,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 2200,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 3400,4000,CONT_DIF_P,* +V 1000,4700,CONT_BODY_N,* +V 2800,4700,CONT_BODY_N,* +V 2800,3000,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1600,4700,CONT_BODY_N,* +V 1000,3500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 2200,4500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/nao22_x4.sym b/alliance/src/cells/src/sxlib/nao22_x4.sym new file mode 100644 index 00000000..a7c777bd Binary files /dev/null and b/alliance/src/cells/src/sxlib/nao22_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/nao22_x4.vbe b/alliance/src/cells/src/sxlib/nao22_x4.vbe new file mode 100644 index 00000000..ebdcfc51 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 596; + CONSTANT tplh_i2_nq : NATURAL := 636; + CONSTANT tplh_i0_nq : NATURAL := 650; + CONSTANT tphl_i1_nq : NATURAL := 664; + CONSTANT tplh_i1_nq : NATURAL := 723; + CONSTANT tphl_i0_nq : NATURAL := 732; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x4; + +ARCHITECTURE behaviour_data_flow OF nao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/nao22_x4.vhd b/alliance/src/cells/src/sxlib/nao22_x4.vhd new file mode 100644 index 00000000..e45a87a3 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao22_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nao22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nao22_x4; + +ARCHITECTURE RTL OF nao22_x4 IS +BEGIN + nq <= NOT(((i0 OR i1) AND i2)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/nao2o22_x1.al b/alliance/src/cells/src/sxlib/nao2o22_x1.al new file mode 100644 index 00000000..ebf99d47 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao2o22_x1.al @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H nao2o22_x1,L,30/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00008 +T P,0.35,5.9,5,10,4,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00007 +T P,0.35,5.9,6,7,2,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,5.9,4,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005 +T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,2.9,1,7,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003 +T N,0.35,2.9,2,8,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 10,EXTERNAL,i0 +Q 0.00260759 +S 9,EXTERNAL,i2 +Q 0.00288944 +S 8,EXTERNAL,i1 +Q 0.00288494 +S 7,EXTERNAL,i3 +Q 0.00316679 +S 6,INTERNAL +Q 0 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00490248 +S 3,EXTERNAL,vss +Q 0.00449119 +S 2,EXTERNAL,nq +Q 0.00282024 +S 1,INTERNAL +Q 0.00199441 +EOF diff --git a/alliance/src/cells/src/sxlib/nao2o22_x1.ap b/alliance/src/cells/src/sxlib/nao2o22_x1.ap new file mode 100644 index 00000000..a1ae005a --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao2o22_x1.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H nao2o22_x1,P,30/ 8/2000,100 +A 0,0,3500,5000 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2500,3500,ref_ref,i2_35 +R 2000,3500,ref_ref,i3_35 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,4000,ref_ref,i0_40 +R 500,3500,ref_ref,i0_35 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 1500,4000,ref_ref,nq_40 +R 2000,4000,ref_ref,i3_40 +R 2500,4000,ref_ref,i2_40 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 1500,1500,1500,4000,200,nq,DOWN,CALU1 +S 2000,1500,2000,4000,200,i3,DOWN,CALU1 +S 2500,1500,2500,4000,200,i2,DOWN,CALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 3200,500,3200,1700,200,*,DOWN,ALU1 +S 3200,2900,3200,4500,200,*,DOWN,ALU1 +S 2700,3400,2700,4700,300,*,DOWN,PDIF +S 2700,300,2700,1200,300,*,UP,NDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,1400,600,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 900,300,900,1600,300,*,UP,NDIF +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 300,1000,2700,1000,100,*,RIGHT,ALU1 +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 2500,1500,2500,4000,100,*,DOWN,ALU1 +S 2600,2800,2600,3300,300,*,UP,PDIF +S 1500,1450,1500,4000,200,*,UP,ALU1 +S 900,1500,1550,1500,200,*,RIGHT,ALU1 +V 3200,2900,CONT_BODY_N,* +V 3200,1700,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 2700,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/nao2o22_x1.sym b/alliance/src/cells/src/sxlib/nao2o22_x1.sym new file mode 100644 index 00000000..7030a68e Binary files /dev/null and b/alliance/src/cells/src/sxlib/nao2o22_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/nao2o22_x1.vbe b/alliance/src/cells/src/sxlib/nao2o22_x1.vbe new file mode 100644 index 00000000..327e9976 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao2o22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i3_nq : NATURAL := 174; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tphl_i2_nq : NATURAL := 237; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT tplh_i2_nq : NATURAL := 307; + CONSTANT tplh_i3_nq : NATURAL := 382; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x1; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/nao2o22_x1.vhd b/alliance/src/cells/src/sxlib/nao2o22_x1.vhd new file mode 100644 index 00000000..9ddd0b03 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao2o22_x1.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nao2o22_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nao2o22_x1; + +ARCHITECTURE RTL OF nao2o22_x1 IS +BEGIN + nq <= NOT(((i0 OR i1) AND (i2 OR i3))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/nao2o22_x4.al b/alliance/src/cells/src/sxlib/nao2o22_x4.al new file mode 100644 index 00000000..ff51e2b9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao2o22_x4.al @@ -0,0 +1,48 @@ +V ALLIANCE : 6 +H nao2o22_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,4 +C i2,IN,EXTERNAL,7 +C i3,IN,EXTERNAL,5 +C nq,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,10,3,9,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00014 +T P,0.35,5.9,10,9,8,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00013 +T P,0.35,5.9,8,9,10,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00012 +T P,0.35,2.9,11,6,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00011 +T P,0.35,2.9,12,5,3,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010 +T P,0.35,2.9,10,7,12,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00009 +T P,0.35,2.9,3,4,11,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T N,0.35,1.4,9,3,1,0,0.75,0.75,4.3,4.3,10.8,3,tr_00007 +T N,0.35,2.9,8,9,1,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00006 +T N,0.35,2.9,1,9,8,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005 +T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00003 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00002 +T N,0.35,1.4,3,4,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,vdd +Q 0.00820729 +S 9,INTERNAL +Q 0.00518414 +S 8,EXTERNAL,nq +Q 0.00258522 +S 7,EXTERNAL,i2 +Q 0.00295462 +S 6,EXTERNAL,i0 +Q 0.00295462 +S 5,EXTERNAL,i3 +Q 0.00323197 +S 4,EXTERNAL,i1 +Q 0.00323197 +S 3,INTERNAL +Q 0.0066832 +S 2,INTERNAL +Q 0.00199441 +S 1,EXTERNAL,vss +Q 0.00726721 +EOF diff --git a/alliance/src/cells/src/sxlib/nao2o22_x4.ap b/alliance/src/cells/src/sxlib/nao2o22_x4.ap new file mode 100644 index 00000000..7a8c7082 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao2o22_x4.ap @@ -0,0 +1,143 @@ +V ALLIANCE : 6 +H nao2o22_x4,P,30/ 8/2000,100 +A 0,0,5500,5000 +R 4500,2500,ref_ref,nq_25 +R 4500,1500,ref_ref,nq_15 +R 4500,1000,ref_ref,nq_10 +R 4500,2000,ref_ref,nq_20 +R 4500,3000,ref_ref,nq_30 +R 4500,3500,ref_ref,nq_35 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,1500,ref_ref,i3_15 +R 2000,2000,ref_ref,i3_20 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 4500,4000,ref_ref,nq_40 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 2000,3500,ref_ref,i3_35 +R 2500,3500,ref_ref,i2_35 +S 4500,1000,4500,4000,200,nq,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1500,2000,3500,200,i3,DOWN,CALU1 +S 2500,1500,2500,3500,200,i2,DOWN,CALU1 +S 4500,1000,4500,4000,200,*,UP,ALU1 +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 3300,1000,3300,3000,100,*,DOWN,ALU1 +S 3300,800,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,3700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 5100,300,5100,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 3900,300,3900,1200,300,*,UP,NDIF +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 3800,2500,3800,3500,100,*,DOWN,ALU1 +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 3300,2000,4000,2000,100,*,RIGHT,ALU1 +S 3600,2500,3800,2500,300,*,RIGHT,POLY +S 3900,4000,3900,4500,200,*,DOWN,ALU1 +S 5100,3000,5100,4500,200,*,DOWN,ALU1 +S 5100,500,5100,1000,200,*,DOWN,ALU1 +S 3900,500,3900,1000,200,*,DOWN,ALU1 +S 4000,2000,4800,2000,300,*,RIGHT,POLY +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 2700,800,2700,1200,300,*,UP,NDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 300,1000,2700,1000,100,*,RIGHT,ALU1 +S 900,800,900,1600,300,*,UP,NDIF +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 3300,3500,3800,3500,100,*,LEFT,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 1600,4000,3300,4000,100,*,LEFT,ALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 900,4700,2100,4700,300,*,RIGHT,NTIE +S 300,300,1500,300,300,*,RIGHT,PTIE +S 2700,300,3300,300,300,*,RIGHT,PTIE +V 4500,1000,CONT_DIF_N,* +V 3300,300,CONT_BODY_P,* +V 5100,500,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3800,2500,CONT_POLY,* +V 3900,4000,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 3300,3000,CONT_DIF_P,* +V 3300,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 4000,2000,CONT_POLY,* +V 3300,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 1500,4700,CONT_BODY_N,* +V 2700,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 2100,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 2700,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 4500,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/nao2o22_x4.sym b/alliance/src/cells/src/sxlib/nao2o22_x4.sym new file mode 100644 index 00000000..886aab25 Binary files /dev/null and b/alliance/src/cells/src/sxlib/nao2o22_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/nao2o22_x4.vbe b/alliance/src/cells/src/sxlib/nao2o22_x4.vbe new file mode 100644 index 00000000..b5c506fe --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i3_nq : NATURAL := 607; + CONSTANT tplh_i0_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 664; + CONSTANT tphl_i1_nq : NATURAL := 666; + CONSTANT tplh_i1_nq : NATURAL := 717; + CONSTANT tplh_i2_nq : NATURAL := 721; + CONSTANT tphl_i0_nq : NATURAL := 734; + CONSTANT tplh_i3_nq : NATURAL := 807; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/nao2o22_x4.vhd b/alliance/src/cells/src/sxlib/nao2o22_x4.vhd new file mode 100644 index 00000000..4bc6cef6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nao2o22_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nao2o22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nao2o22_x4; + +ARCHITECTURE RTL OF nao2o22_x4 IS +BEGIN + nq <= NOT(((i0 OR i1) AND (i2 OR i3))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/nmx2_x1.al b/alliance/src/cells/src/sxlib/nmx2_x1.al new file mode 100644 index 00000000..92138ed1 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx2_x1.al @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H nmx2_x1,L,30/10/99 +C cmd,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,11 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,3,5,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00010 +T P,0.35,5.9,8,9,3,0,0.75,0.75,13.3,13.3,5.1,11.25,tr_00009 +T P,0.35,5.9,6,11,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00008 +T P,0.35,5.9,7,10,8,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00007 +T P,0.35,2.9,5,9,7,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00006 +T N,0.35,2.9,2,9,3,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00005 +T N,0.35,2.9,3,5,4,0,0.75,0.75,7.3,7.3,5.1,2.25,tr_00004 +T N,0.35,2.9,1,11,2,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00003 +T N,0.35,2.9,4,10,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,1.4,1,9,5,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 11,EXTERNAL,i1 +Q 0.00271107 +S 10,EXTERNAL,i0 +Q 0.00265635 +S 9,EXTERNAL,cmd +Q 0.00492843 +S 8,INTERNAL +Q 0 +S 7,EXTERNAL,vdd +Q 0.00384489 +S 6,INTERNAL +Q 0 +S 5,INTERNAL +Q 0.00698278 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,nq +Q 0.00270273 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00384489 +EOF diff --git a/alliance/src/cells/src/sxlib/nmx2_x1.ap b/alliance/src/cells/src/sxlib/nmx2_x1.ap new file mode 100644 index 00000000..ffdd8fa3 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx2_x1.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H nmx2_x1,P,30/ 8/2000,100 +A 0,0,3500,5000 +R 1500,2000,ref_ref,cmd_20 +R 1500,2500,ref_ref,cmd_25 +R 1500,3000,ref_ref,cmd_30 +R 1500,3500,ref_ref,cmd_35 +R 1000,1500,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 3000,1000,ref_ref,i1_10 +R 3000,1500,ref_ref,i1_15 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 3000,4000,ref_ref,i1_40 +R 2000,3500,ref_ref,nq_35 +R 2000,3000,ref_ref,nq_30 +R 2000,2500,ref_ref,nq_25 +R 2500,1500,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_20 +R 2000,1000,ref_ref,nq_10 +S 2100,950,2100,2050,200,*,UP,ALU1 +S 2050,1500,2500,1500,200,*,LEFT,ALU1 +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 600,1400,600,3100,100,*,DOWN,POLY +S 300,800,300,1200,300,*,UP,NDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 1200,100,1200,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 900,2600,1200,2600,100,*,RIGHT,POLY +S 2000,2800,2000,4700,500,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,DOWN,ALU1 +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 2900,100,2900,1400,100,*,UP,NTRANS +S 3200,300,3200,1200,300,*,UP,NDIF +S 300,4000,2500,4000,100,*,RIGHT,ALU1 +S 2500,2500,2500,4000,100,*,DOWN,ALU1 +S 2000,300,2000,1200,500,*,DOWN,NDIF +S 1550,1000,1550,1500,100,*,UP,ALU1 +S 300,1000,1550,1000,100,*,RIGHT,ALU1 +S 1700,2600,1700,4900,100,*,DOWN,PTRANS +S 1700,2000,1700,2600,100,*,UP,POLY +S 1700,100,1700,1400,100,*,UP,NTRANS +S 2300,100,2300,1400,100,*,UP,NTRANS +S 2300,1400,2300,2000,100,*,DOWN,POLY +S 600,2000,2300,2000,100,*,RIGHT,POLY +S 2300,2600,2300,4900,100,*,DOWN,PTRANS +S 2300,2600,2500,2600,100,*,RIGHT,POLY +S 2600,2800,2600,4700,200,*,UP,PDIF +S 2600,300,2600,1200,200,*,DOWN,NDIF +S 2000,1950,2000,3500,200,*,DOWN,ALU1 +S 1500,2000,1500,3500,200,cmd,DOWN,CALU1 +S 1000,1500,1000,3500,200,i0,DOWN,CALU1 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 2000,2000,2000,3500,200,nq,DOWN,CALU1 +S 2000,1000,2000,1000,200,nq,LEFT,CALU1 +S 2500,1500,2500,1500,200,nq,LEFT,CALU1 +V 1500,2000,CONT_POLY,* +V 2000,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 300,4700,CONT_BODY_N,* +V 3000,1500,CONT_POLY,* +V 1600,1500,CONT_POLY,* +V 900,500,CONT_DIF_N,* +V 300,300,CONT_BODY_P,* +V 1000,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 2000,3000,CONT_DIF_P,* +V 3200,4500,CONT_DIF_P,* +V 2500,2500,CONT_POLY,* +V 3200,500,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/nmx2_x1.sym b/alliance/src/cells/src/sxlib/nmx2_x1.sym new file mode 100644 index 00000000..b7abb919 Binary files /dev/null and b/alliance/src/cells/src/sxlib/nmx2_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/nmx2_x1.vbe b/alliance/src/cells/src/sxlib/nmx2_x1.vbe new file mode 100644 index 00000000..cd7873d4 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx2_x1.vbe @@ -0,0 +1,42 @@ +ENTITY nmx2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_cmd : NATURAL := 21; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 217; + CONSTANT tphl_i1_nq : NATURAL := 217; + CONSTANT tphl_cmd_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 256; + CONSTANT tplh_i1_nq : NATURAL := 256; + CONSTANT tplh_cmd_nq : NATURAL := 287; + CONSTANT tphh_cmd_nq : NATURAL := 379; + CONSTANT tpll_cmd_nq : NATURAL := 410; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x1; + +ARCHITECTURE behaviour_data_flow OF nmx2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x1" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/nmx2_x1.vhd b/alliance/src/cells/src/sxlib/nmx2_x1.vhd new file mode 100644 index 00000000..46309893 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx2_x1.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nmx2_x1 IS +PORT( + cmd : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nmx2_x1; + +ARCHITECTURE RTL OF nmx2_x1 IS +BEGIN + nq <= NOT(((i0 AND NOT(cmd)) OR (i1 AND cmd))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/nmx2_x4.al b/alliance/src/cells/src/sxlib/nmx2_x4.al new file mode 100644 index 00000000..1af7115f --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx2_x4.al @@ -0,0 +1,51 @@ +V ALLIANCE : 6 +H nmx2_x4,L,30/10/99 +C cmd,IN,EXTERNAL,7 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,6 +C nq,OUT,EXTERNAL,10 +C vdd,IN,EXTERNAL,11 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,11,8,12,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00016 +T P,0.35,2.9,3,4,13,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00015 +T P,0.35,2.9,12,7,3,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00014 +T P,0.35,2.9,4,7,11,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00013 +T P,0.35,2.9,13,6,11,0,0.75,0.75,7.3,7.3,8.4,11.25,tr_00012 +T P,0.35,2.9,11,3,9,0,0.75,0.75,7.3,7.3,10.2,11.25,tr_00011 +T P,0.35,5.9,11,9,10,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00010 +T P,0.35,5.9,10,9,11,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00009 +T N,0.35,1.4,5,8,1,0,0.75,0.75,4.3,4.3,3.6,1.5,tr_00008 +T N,0.35,1.4,3,4,5,0,0.75,0.75,4.3,4.3,4.8,1.5,tr_00007 +T N,0.35,1.4,1,7,4,0,0.75,0.75,4.3,4.3,1.8,1.5,tr_00006 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,7.2,1.5,tr_00005 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,8.4,1.5,tr_00004 +T N,0.35,1.4,9,3,1,0,0.75,0.75,4.3,4.3,10.2,1.5,tr_00003 +T N,0.35,2.9,10,9,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00002 +T N,0.35,2.9,1,9,10,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00001 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0 +S 11,EXTERNAL,vdd +Q 0.00966511 +S 10,EXTERNAL,nq +Q 0.00258522 +S 9,INTERNAL +Q 0.00573596 +S 8,EXTERNAL,i0 +Q 0.00336619 +S 7,EXTERNAL,cmd +Q 0.00660261 +S 6,EXTERNAL,i1 +Q 0.00371745 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00595297 +S 3,INTERNAL +Q 0.00516493 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00807873 +EOF diff --git a/alliance/src/cells/src/sxlib/nmx2_x4.ap b/alliance/src/cells/src/sxlib/nmx2_x4.ap new file mode 100644 index 00000000..aa630ade --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx2_x4.ap @@ -0,0 +1,147 @@ +V ALLIANCE : 6 +H nmx2_x4,P,30/ 8/2000,100 +A 0,0,6000,5000 +R 3000,4000,ref_ref,i1_40 +R 3000,3500,ref_ref,i1_35 +R 3000,3000,ref_ref,i1_30 +R 3000,2500,ref_ref,i1_25 +R 3000,2000,ref_ref,i1_20 +R 3000,1500,ref_ref,i1_15 +R 3000,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1500,4000,ref_ref,cmd_40 +R 1500,3500,ref_ref,cmd_35 +R 1500,3000,ref_ref,cmd_30 +R 1500,2500,ref_ref,cmd_25 +R 1500,2000,ref_ref,cmd_20 +R 1500,1500,ref_ref,cmd_15 +R 5000,4000,ref_ref,nq_40 +R 5000,3500,ref_ref,nq_35 +R 5000,2500,ref_ref,nq_25 +R 5000,1000,ref_ref,nq_10 +R 5000,3000,ref_ref,nq_30 +R 5000,2000,ref_ref,nq_20 +R 5000,1500,ref_ref,nq_15 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 1500,1500,1500,4000,200,cmd,DOWN,CALU1 +S 5000,1000,5000,4000,200,nq,DOWN,CALU1 +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 1600,2000,1600,3100,100,*,UP,POLY +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 2500,1000,2500,2700,100,*,UP,ALU1 +S 2400,2800,2400,3100,100,*,UP,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 1200,100,1200,900,100,*,UP,NTRANS +S 1600,100,1600,900,100,*,UP,NTRANS +S 600,100,600,900,100,*,UP,NTRANS +S 900,300,900,700,300,*,UP,NDIF +S 600,900,600,3100,100,*,DOWN,POLY +S 2400,100,2400,900,100,*,UP,NTRANS +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 3400,100,3400,900,100,*,UP,NTRANS +S 3100,300,3100,700,300,*,DOWN,NDIF +S 3700,300,3700,1100,300,*,DOWN,NDIF +S 300,300,300,1100,300,*,UP,NDIF +S 3400,3100,3400,4400,100,*,DOWN,PTRANS +S 3700,3300,3700,4200,300,*,DOWN,PDIF +S 3100,3300,3100,4600,300,*,DOWN,PDIF +S 3700,1000,3700,4000,100,*,DOWN,ALU1 +S 3400,900,3400,3100,100,*,DOWN,POLY +S 2000,2300,3400,2300,100,*,RIGHT,POLY +S 5600,3000,5600,4500,200,*,UP,ALU1 +S 5600,500,5600,1700,200,*,DOWN,ALU1 +S 4400,500,4400,1700,200,*,DOWN,ALU1 +S 4400,3000,4400,4500,200,*,UP,ALU1 +S 5600,2900,5600,3300,300,*,DOWN,PDIF +S 4700,100,4700,1400,100,*,UP,NTRANS +S 5000,300,5000,1200,300,*,DOWN,NDIF +S 5300,100,5300,1400,100,*,UP,NTRANS +S 5600,300,5600,1200,300,*,DOWN,NDIF +S 4400,300,4400,1200,300,*,DOWN,NDIF +S 3800,2500,5300,2500,100,*,LEFT,POLY +S 4700,1400,4700,2600,100,*,DOWN,POLY +S 4700,2600,4700,4900,100,*,DOWN,PTRANS +S 5300,1400,5300,2600,100,*,DOWN,POLY +S 5300,2600,5300,4900,100,*,DOWN,PTRANS +S 4400,2800,4400,4700,300,*,UP,PDIF +S 5600,2800,5600,4700,300,*,UP,PDIF +S 5000,2800,5000,4700,300,*,UP,PDIF +V 3000,1500,CONT_POLY,* +V 300,4700,CONT_BODY_N,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 2000,1500,CONT_DIF_N,* +V 2000,3500,CONT_DIF_P,* +V 2000,4700,CONT_BODY_N,* +V 2000,4000,CONT_DIF_P,* +V 2500,2700,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1600,1000,CONT_POLY,* +V 1500,4700,CONT_BODY_N,* +V 2500,4700,CONT_BODY_N,* +V 3100,500,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 3100,4500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3400,CONT_DIF_P,* +V 3700,4700,CONT_BODY_N,* +V 3800,2500,CONT_POLY,* +V 4400,1700,CONT_BODY_P,* +V 5600,1700,CONT_BODY_P,* +V 4400,3000,CONT_DIF_P,* +V 4400,4500,CONT_DIF_P,* +V 5600,3000,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 5600,4000,CONT_DIF_P,* +V 5000,3000,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 5000,3500,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 5600,3500,CONT_DIF_P,* +V 4400,1000,CONT_DIF_N,* +V 4400,500,CONT_DIF_N,* +V 5600,500,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 5000,1000,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/nmx2_x4.sym b/alliance/src/cells/src/sxlib/nmx2_x4.sym new file mode 100644 index 00000000..2f3c726d Binary files /dev/null and b/alliance/src/cells/src/sxlib/nmx2_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/nmx2_x4.vbe b/alliance/src/cells/src/sxlib/nmx2_x4.vbe new file mode 100644 index 00000000..b939997d --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx2_x4.vbe @@ -0,0 +1,42 @@ +ENTITY nmx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_cmd_nq : NATURAL := 890; + CONSTANT rup_cmd_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 610; + CONSTANT tphl_cmd_nq : NATURAL := 632; + CONSTANT tplh_i0_nq : NATURAL := 653; + CONSTANT tplh_i1_nq : NATURAL := 653; + CONSTANT tphh_cmd_nq : NATURAL := 688; + CONSTANT tpll_cmd_nq : NATURAL := 703; + CONSTANT tplh_cmd_nq : NATURAL := 708; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x4; + +ARCHITECTURE behaviour_data_flow OF nmx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x4" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/nmx2_x4.vhd b/alliance/src/cells/src/sxlib/nmx2_x4.vhd new file mode 100644 index 00000000..d8d2a999 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx2_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nmx2_x4 IS +PORT( + cmd : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nmx2_x4; + +ARCHITECTURE RTL OF nmx2_x4 IS +BEGIN + nq <= NOT(((i0 AND NOT(cmd)) OR (i1 AND cmd))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/nmx3_x1.al b/alliance/src/cells/src/sxlib/nmx3_x1.al new file mode 100644 index 00000000..d88bd558 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx3_x1.al @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H nmx3_x1,L,30/10/99 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,15,6,1,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00018 +T P,0.35,2.9,7,12,17,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00017 +T P,0.35,2.9,18,14,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00016 +T P,0.35,2.9,1,13,18,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00015 +T P,0.35,2.9,17,8,15,0,0.75,0.75,7.3,7.3,9,12.75,tr_00014 +T P,0.35,2.9,16,10,17,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00013 +T P,0.35,2.9,1,9,16,0,0.75,0.75,7.3,7.3,6,12.75,tr_00012 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00011 +T P,0.35,2,7,14,12,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00010 +T N,0.35,1.7,4,8,2,0,0.75,0.75,4.9,4.9,9,2.55,tr_00009 +T N,0.35,1.7,2,9,1,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00008 +T N,0.35,1.7,1,6,5,0,0.75,0.75,4.9,4.9,6,2.55,tr_00007 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00006 +T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00005 +T N,0.35,1.7,11,12,3,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00004 +T N,0.35,1.7,1,13,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00003 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00002 +T N,0.35,1.1,12,14,3,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00001 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00170541 +S 16,INTERNAL +Q 0 +S 15,INTERNAL +Q 0 +S 14,EXTERNAL,cmd0 +Q 0.00553121 +S 13,EXTERNAL,i0 +Q 0.00386192 +S 12,INTERNAL +Q 0.0057783 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00690363 +S 6,INTERNAL +Q 0.00547335 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00619857 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,nq +Q 0.00696213 +EOF diff --git a/alliance/src/cells/src/sxlib/nmx3_x1.ap b/alliance/src/cells/src/sxlib/nmx3_x1.ap new file mode 100644 index 00000000..5a6d6e6e --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx3_x1.ap @@ -0,0 +1,167 @@ +V ALLIANCE : 6 +H nmx3_x1,P, 6/ 9/2000,100 +A 0,0,6000,5000 +R 5500,1000,ref_ref,nq_10 +R 5500,3000,ref_ref,nq_30 +R 5500,2500,ref_ref,nq_25 +R 5500,2000,ref_ref,nq_20 +R 5500,1500,ref_ref,nq_15 +R 5500,3500,ref_ref,nq_35 +R 500,1500,ref_ref,cmd1_15 +R 500,2000,ref_ref,cmd1_20 +R 500,2500,ref_ref,cmd1_25 +R 500,3000,ref_ref,cmd1_30 +R 500,3500,ref_ref,cmd1_35 +R 1500,2500,ref_ref,i2_25 +R 2500,2500,ref_ref,i1_25 +R 3500,2000,ref_ref,cmd0_20 +R 3500,2500,ref_ref,cmd0_25 +R 3500,3000,ref_ref,cmd0_30 +R 4000,2000,ref_ref,i0_20 +R 4000,3000,ref_ref,i0_30 +R 4500,2500,ref_ref,i0_25 +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 4400,2000,4600,2000,300,*,RIGHT,POLY +S 4400,3000,4600,3000,300,*,RIGHT,POLY +S 1800,3500,2000,3500,300,*,RIGHT,POLY +S 4000,2000,4000,2000,200,i0,LEFT,CALU1 +S 4500,2500,4500,2500,200,i0,LEFT,CALU1 +S 4000,3000,4000,3000,200,i0,LEFT,CALU1 +S 5500,1000,5500,3500,200,nq,DOWN,CALU1 +S 500,1500,500,3500,200,cmd1,DOWN,CALU1 +S 1500,2500,1500,2500,200,i2,LEFT,CALU1 +S 2500,2500,2500,2500,200,i1,LEFT,CALU1 +S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1 +S 5500,4000,5500,4700,200,*,UP,ALU1 +S 5500,2800,5500,4000,300,*,DOWN,PDIF +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 5500,500,5500,1800,300,*,DOWN,NDIF +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 2800,1500,2800,2000,100,*,UP,ALU1 +S 2300,1500,2800,1500,100,*,RIGHT,ALU1 +S 1100,4000,3300,4000,100,*,RIGHT,ALU1 +S 1000,3000,1800,3000,100,*,LEFT,ALU1 +S 1800,2000,1900,2000,100,*,RIGHT,ALU1 +S 1800,1500,1800,2000,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 500,3500,1800,3500,100,*,LEFT,ALU1 +S 1100,1000,3300,1000,100,*,RIGHT,ALU1 +S 500,400,500,1000,200,*,DOWN,ALU1 +S 2600,3000,2600,3600,100,*,UP,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 800,2100,800,2600,100,*,DOWN,POLY +S 500,2500,800,2500,300,*,RIGHT,POLY +S 500,1000,500,1900,300,*,DOWN,NDIF +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 4900,3800,4900,4700,300,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 3300,3800,3300,4700,200,*,UP,PDIF +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 1100,3800,1100,4700,300,*,UP,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 2300,3500,2300,4700,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 500,2800,500,4000,300,*,UP,PDIF +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 1800,3000,2500,3000,100,*,LEFT,ALU1 +S 2800,2000,3000,2000,100,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 3400,1500,4900,1500,100,*,RIGHT,ALU1 +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 4000,3300,4000,3600,100,*,UP,POLY +S 4400,2000,4400,3000,100,*,UP,ALU1 +S 4900,3000,5000,3000,100,*,RIGHT,ALU1 +S 5000,1800,5000,3000,100,*,DOWN,ALU1 +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 4900,2800,4900,3400,300,*,UP,PDIF +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 4200,1100,4200,1500,100,*,UP,POLY +S 3900,400,3900,900,200,*,DOWN,NDIF +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 800,2600,800,3600,100,*,UP,PTRANS +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 3000,400,3000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 1400,400,1400,1300,100,*,UP,NTRANS +S 3600,200,3600,1100,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 4600,200,4600,1100,100,*,UP,NTRANS +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 4900,3500,4900,4000,100,*,DOWN,ALU1 +S 3500,1500,3500,3600,100,*,UP,POLY +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 800,1400,800,2100,100,*,DOWN,NTRANS +S 1100,1600,1100,1900,300,*,UP,NDIF +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 2300,3500,5500,3500,100,*,RIGHT,ALU1 +S 4900,1000,5500,1000,100,*,RIGHT,ALU1 +S 5200,1300,5200,2000,100,*,DOWN,NTRANS +S 5200,2000,5200,2600,100,*,DOWN,POLY +S 4900,1700,5000,1700,100,*,LEFT,ALU1 +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 4900,1500,4900,1700,200,*,DOWN,ALU1 +S 4900,400,4900,1000,300,*,UP,NDIF +V 5600,4700,CONT_BODY_N,* +V 5500,4000,CONT_DIF_P,* +V 1800,3500,CONT_POLY,* +V 4200,1500,CONT_POLY,* +V 3400,1500,CONT_POLY,* +V 1800,1500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 500,400,CONT_BODY_P,* +V 2300,1500,CONT_DIF_N,* +V 1100,1800,CONT_DIF_N,* +V 1100,1800,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 4900,1000,CONT_DIF_N,* +V 1100,1000,CONT_DIF_N,* +V 500,1000,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 3300,4000,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 2300,3500,CONT_DIF_P,* +V 1100,4000,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 500,4600,CONT_BODY_N,* +V 1100,3000,CONT_DIF_P,* +V 4900,3000,CONT_DIF_P,* +V 2500,3000,CONT_POLY,* +V 4400,3000,CONT_POLY,* +V 4400,2000,CONT_POLY,* +V 5500,500,CONT_DIF_N,* +V 3900,2500,CONT_POLY,* +V 4900,1700,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/nmx3_x1.vbe b/alliance/src/cells/src/sxlib/nmx3_x1.vbe new file mode 100644 index 00000000..e36e7d6f --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx3_x1.vbe @@ -0,0 +1,59 @@ +ENTITY nmx3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 5140; + CONSTANT rdown_cmd0_nq : NATURAL := 7420; + CONSTANT rdown_cmd1_nq : NATURAL := 7420; + CONSTANT rdown_cmd1_nq : NATURAL := 7420; + CONSTANT rdown_i0_nq : NATURAL := 5140; + CONSTANT rdown_i1_nq : NATURAL := 7420; + CONSTANT rdown_i2_nq : NATURAL := 7420; + CONSTANT rup_cmd0_nq : NATURAL := 6680; + CONSTANT rup_cmd0_nq : NATURAL := 9760; + CONSTANT rup_cmd1_nq : NATURAL := 9760; + CONSTANT rup_cmd1_nq : NATURAL := 9760; + CONSTANT rup_i0_nq : NATURAL := 6680; + CONSTANT rup_i1_nq : NATURAL := 9760; + CONSTANT rup_i2_nq : NATURAL := 9760; + CONSTANT tphl_i0_nq : NATURAL := 315; + CONSTANT tphl_cmd0_nq : NATURAL := 356; + CONSTANT tphl_cmd1_nq : NATURAL := 414; + CONSTANT tphl_i1_nq : NATURAL := 429; + CONSTANT tphl_i2_nq : NATURAL := 429; + CONSTANT tplh_i0_nq : NATURAL := 441; + CONSTANT tplh_cmd0_nq : NATURAL := 495; + CONSTANT tphh_cmd1_nq : NATURAL := 519; + CONSTANT tpll_cmd1_nq : NATURAL := 520; + CONSTANT tplh_cmd1_nq : NATURAL := 566; + CONSTANT tphh_cmd0_nq : NATURAL := 582; + CONSTANT tplh_i1_nq : NATURAL := 582; + CONSTANT tplh_i2_nq : NATURAL := 582; + CONSTANT tpll_cmd0_nq : NATURAL := 586; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x1; + +ARCHITECTURE behaviour_data_flow OF nmx3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx3_x1" + SEVERITY WARNING; + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not + (cmd1) and i2))))) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/nmx3_x1.vhd b/alliance/src/cells/src/sxlib/nmx3_x1.vhd new file mode 100644 index 00000000..7fe6277f --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx3_x1.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nmx3_x1 IS +PORT( + cmd0 : IN STD_LOGIC; + cmd1 : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nmx3_x1; + +ARCHITECTURE RTL OF nmx3_x1 IS +BEGIN + nq <= NOT(((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2))))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/nmx3_x4.al b/alliance/src/cells/src/sxlib/nmx3_x4.al new file mode 100644 index 00000000..eec6d89f --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx3_x4.al @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H nmx3_x4,L,30/10/99 +C cmd0,IN,EXTERNAL,15 +C cmd1,IN,EXTERNAL,8 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,2,7,15,11,0,0.75,0.75,5.5,5.5,15.3,9.3,tr_00024 +T P,0.35,2,2,8,7,0,0.75,0.75,5.5,5.5,2.1,9.3,tr_00023 +T P,0.35,5.9,12,16,7,0,0.75,0.75,13.3,13.3,17.1,11.25,tr_00022 +T P,0.35,2.9,3,8,18,0,0.75,0.75,7.3,7.3,5.7,12.75,tr_00021 +T P,0.35,2.9,18,10,17,0,0.75,0.75,7.3,7.3,3.9,12.75,tr_00020 +T P,0.35,2.9,17,9,19,0,0.75,0.75,7.3,7.3,8.7,12.75,tr_00019 +T P,0.35,2.9,3,14,20,0,0.75,0.75,7.3,7.3,13.5,12.75,tr_00018 +T P,0.35,2.9,20,15,7,0,0.75,0.75,7.3,7.3,12.3,12.75,tr_00017 +T P,0.35,2.9,7,11,17,0,0.75,0.75,7.3,7.3,10.5,12.75,tr_00016 +T P,0.35,2.9,19,2,3,0,0.75,0.75,7.3,7.3,7.5,12.75,tr_00015 +T P,0.35,5.9,7,16,12,0,0.75,0.75,13.3,13.3,18.9,11.25,tr_00014 +T P,0.35,2.9,16,3,7,0,0.75,0.75,7.3,7.3,20.7,9.75,tr_00013 +T N,0.35,1.1,1,8,2,0,0.75,0.75,3.7,3.7,2.1,5.25,tr_00012 +T N,0.35,1.1,11,15,1,0,0.75,0.75,3.7,3.7,15.3,4.95,tr_00011 +T N,0.35,1.7,1,15,6,0,0.75,0.75,4.9,4.9,10.5,1.95,tr_00010 +T N,0.35,1.7,4,10,6,0,0.75,0.75,4.9,4.9,3.9,2.55,tr_00009 +T N,0.35,1.7,6,9,5,0,0.75,0.75,4.9,4.9,8.7,2.55,tr_00008 +T N,0.35,1.7,3,14,13,0,0.75,0.75,4.9,4.9,13.5,1.95,tr_00007 +T N,0.35,1.7,13,11,1,0,0.75,0.75,4.9,4.9,12.3,1.95,tr_00006 +T N,0.35,1.7,3,2,4,0,0.75,0.75,4.9,4.9,5.7,2.55,tr_00005 +T N,0.35,1.7,5,8,3,0,0.75,0.75,4.9,4.9,7.5,2.55,tr_00004 +T N,0.35,2.9,12,16,1,0,0.75,0.75,7.3,7.3,18.9,2.55,tr_00003 +T N,0.35,1.4,1,3,16,0,0.75,0.75,4.3,4.3,20.7,3.3,tr_00002 +T N,0.35,2.9,1,16,12,0,0.75,0.75,7.3,7.3,17.1,2.55,tr_00001 +S 20,INTERNAL +Q 0 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00170541 +S 16,INTERNAL +Q 0.00532834 +S 15,EXTERNAL,cmd0 +Q 0.00547246 +S 14,EXTERNAL,i0 +Q 0.00397942 +S 13,INTERNAL +Q 0 +S 12,EXTERNAL,nq +Q 0.00232082 +S 11,INTERNAL +Q 0.00589104 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,i1 +Q 0.0025589 +S 8,EXTERNAL,cmd1 +Q 0.00604152 +S 7,EXTERNAL,vdd +Q 0.00916191 +S 6,INTERNAL +Q 0.00170541 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.0105263 +S 2,INTERNAL +Q 0.00586794 +S 1,EXTERNAL,vss +Q 0.00757552 +EOF diff --git a/alliance/src/cells/src/sxlib/nmx3_x4.ap b/alliance/src/cells/src/sxlib/nmx3_x4.ap new file mode 100644 index 00000000..2c669cc9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx3_x4.ap @@ -0,0 +1,209 @@ +V ALLIANCE : 6 +H nmx3_x4,P, 6/ 9/2000,100 +A 0,0,7500,5000 +R 500,1500,ref_ref,cmd1_15 +R 500,2000,ref_ref,cmd1_20 +R 500,2500,ref_ref,cmd1_25 +R 500,3000,ref_ref,cmd1_30 +R 500,3500,ref_ref,cmd1_35 +R 1500,2500,ref_ref,i2_25 +R 2500,2500,ref_ref,i1_25 +R 3500,2000,ref_ref,cmd0_20 +R 3500,2500,ref_ref,cmd0_25 +R 3500,3000,ref_ref,cmd0_30 +R 4000,2000,ref_ref,i0_20 +R 4000,3000,ref_ref,i0_30 +R 4500,2500,ref_ref,i0_25 +R 6000,1500,ref_ref,nq_15 +R 6000,2500,ref_ref,nq_25 +R 6000,3000,ref_ref,nq_30 +R 6000,3500,ref_ref,nq_35 +R 6000,4000,ref_ref,nq_40 +R 6000,2000,ref_ref,nq_20 +S 4300,2000,4500,2000,300,*,RIGHT,POLY +S 4300,3000,4500,3000,300,*,RIGHT,POLY +S 1300,2500,1500,2500,300,*,RIGHT,POLY +S 1700,1500,1900,1500,300,*,RIGHT,POLY +S 1700,3500,1900,3500,300,*,RIGHT,POLY +S 500,3500,1700,3500,100,*,LEFT,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 4000,2000,4000,2000,200,i0,LEFT,CALU1 +S 4000,3000,4000,3000,200,i0,LEFT,CALU1 +S 4500,2500,4500,2500,200,i0,LEFT,CALU1 +S 500,1500,500,3500,200,cmd1,DOWN,CALU1 +S 1500,2500,1500,2500,200,i2,LEFT,CALU1 +S 2500,2500,2500,2500,200,i1,LEFT,CALU1 +S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1 +S 6000,1500,6000,4000,200,nq,DOWN,CALU1 +S 4800,400,4800,1000,300,*,UP,NDIF +S 4800,1500,4800,1700,200,*,DOWN,ALU1 +S 400,4000,400,4600,200,*,UP,ALU1 +S 4800,3500,4800,4000,100,*,DOWN,ALU1 +S 4300,2000,4300,3000,100,*,UP,ALU1 +S 1000,4000,3200,4000,100,*,RIGHT,ALU1 +S 2200,1500,2700,1500,100,*,RIGHT,ALU1 +S 3300,1500,4800,1500,100,*,RIGHT,ALU1 +S 1700,3000,2400,3000,100,*,LEFT,ALU1 +S 6600,3000,6600,4600,200,*,UP,ALU1 +S 1700,1500,1700,2000,100,*,UP,ALU1 +S 2700,1500,2700,2000,100,*,UP,ALU1 +S 400,400,400,1000,200,*,DOWN,ALU1 +S 1000,1000,3200,1000,100,*,RIGHT,ALU1 +S 1900,1300,1900,1500,100,*,DOWN,POLY +S 1300,1300,1300,3600,100,*,DOWN,POLY +S 3900,3300,3900,3600,100,*,UP,POLY +S 3900,3600,4100,3600,100,*,LEFT,POLY +S 4500,1100,4500,2000,100,*,DOWN,POLY +S 5100,2000,5100,2600,100,*,DOWN,POLY +S 3400,3600,3500,3600,100,*,RIGHT,POLY +S 3400,1500,3400,3600,100,*,UP,POLY +S 3900,1900,3900,3300,100,*,DOWN,POLY +S 4400,2000,4500,2000,100,*,RIGHT,POLY +S 4500,3000,4500,3600,100,*,UP,POLY +S 4300,3000,4500,3000,100,*,RIGHT,POLY +S 2400,2500,2900,2500,100,*,RIGHT,POLY +S 4100,1100,4100,1500,100,*,UP,POLY +S 2900,1300,2900,3600,100,*,DOWN,POLY +S 2500,1300,2500,2000,100,*,UP,POLY +S 3500,1100,3700,1100,100,*,RIGHT,POLY +S 3200,1500,3300,1500,100,*,LEFT,POLY +S 2500,3000,2500,3600,100,*,UP,POLY +S 1900,2000,2500,2000,100,*,RIGHT,POLY +S 1900,2000,1900,3600,100,*,DOWN,POLY +S 3900,2500,5100,2500,100,*,RIGHT,POLY +S 3700,1100,3700,1900,100,*,DOWN,POLY +S 3700,1900,3900,1900,100,*,LEFT,POLY +S 400,2500,700,2500,300,*,RIGHT,POLY +S 700,2100,700,2600,100,*,DOWN,POLY +S 1700,1500,1900,1500,100,*,RIGHT,POLY +S 1000,1600,1000,1900,300,*,UP,NDIF +S 700,1400,700,2100,100,*,DOWN,NTRANS +S 4800,1500,4800,1700,300,*,DOWN,NDIF +S 5100,1300,5100,2000,100,*,DOWN,NTRANS +S 1000,600,1000,1000,300,*,DOWN,NDIF +S 1600,600,1600,1100,200,*,DOWN,NDIF +S 2200,600,2200,1600,300,*,UP,NDIF +S 3200,400,3200,1100,300,*,DOWN,NDIF +S 3500,200,3500,1100,100,*,UP,NTRANS +S 1300,400,1300,1300,100,*,UP,NTRANS +S 2900,400,2900,1300,100,*,UP,NTRANS +S 3800,400,3800,900,200,*,DOWN,NDIF +S 4500,200,4500,1100,100,*,UP,NTRANS +S 4100,200,4100,1100,100,*,UP,NTRANS +S 1900,400,1900,1300,100,*,UP,NTRANS +S 2500,400,2500,1300,100,*,UP,NTRANS +S 400,1000,400,1900,300,*,DOWN,NDIF +S 1000,2800,1000,3400,300,*,UP,PDIF +S 5100,2600,5100,3600,100,*,UP,PTRANS +S 700,2600,700,3600,100,*,UP,PTRANS +S 4800,2800,4800,3400,300,*,UP,PDIF +S 6000,2800,6000,4700,300,*,UP,PDIF +S 5400,2800,5400,4600,300,*,DOWN,PDIF +S 5700,2600,5700,4900,100,*,UP,PTRANS +S 1900,3600,1900,4900,100,*,UP,PTRANS +S 2200,3500,2200,4700,300,*,UP,PDIF +S 1600,3800,1600,4700,200,*,DOWN,PDIF +S 1300,3600,1300,4900,100,*,UP,PTRANS +S 1000,3800,1000,4700,300,*,UP,PDIF +S 2900,3600,2900,4900,100,*,UP,PTRANS +S 3200,3800,3200,4700,200,*,UP,PDIF +S 4500,3600,4500,4900,100,*,UP,PTRANS +S 4800,3800,4800,4700,300,*,UP,PDIF +S 4100,3600,4100,4900,100,*,UP,PTRANS +S 3500,3600,3500,4900,100,*,UP,PTRANS +S 3800,3800,3800,4700,200,*,UP,PDIF +S 2500,3600,2500,4900,100,*,UP,PTRANS +S 6300,2600,6300,4900,100,*,UP,PTRANS +S 6600,2800,6600,4700,300,*,UP,PDIF +S 400,2800,400,4000,300,*,UP,PDIF +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 1000,3000,1700,3000,100,*,LEFT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,3000,4300,3000,200,*,RIGHT,ALU1 +S 4000,2000,4300,2000,200,*,RIGHT,ALU1 +S 4300,2500,4500,2500,200,*,LEFT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 4800,1000,5500,1000,100,*,RIGHT,ALU1 +S 2200,3500,5500,3500,100,*,RIGHT,ALU1 +S 4800,1750,5000,1750,100,*,LEFT,ALU1 +S 4800,2950,5000,2950,100,*,RIGHT,ALU1 +S 5000,1750,5000,2950,100,*,DOWN,ALU1 +S 3500,2500,3800,2500,200,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2700,2000,3000,2000,100,*,RIGHT,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1700,2000,2000,2000,100,*,RIGHT,ALU1 +S 2000,2950,2400,2950,100,*,RIGHT,ALU1 +S 0,300,7500,300,600,vss,RIGHT,CALU1 +S 0,3900,7500,3900,2400,*,RIGHT,NWELL +S 0,4700,7500,4700,600,vdd,RIGHT,CALU1 +S 6900,2600,6900,3900,100,*,UP,PTRANS +S 7200,2800,7200,3700,300,*,DOWN,PDIF +S 6700,2500,6700,2600,100,*,UP,POLY +S 6700,2600,6900,2600,100,*,RIGHT,POLY +S 6300,1400,6300,2600,100,*,DOWN,POLY +S 6700,1500,6700,1600,100,*,UP,POLY +S 6700,1500,6900,1500,100,*,LEFT,POLY +S 7200,900,7200,1300,300,*,DOWN,NDIF +S 6300,200,6300,1500,100,*,DOWN,NTRANS +S 6600,400,6600,1300,300,*,DOWN,NDIF +S 6900,700,6900,1500,100,*,DOWN,NTRANS +S 5700,200,5700,1500,100,*,DOWN,NTRANS +S 5500,1000,6700,1000,100,*,RIGHT,ALU1 +S 6700,1000,6700,2500,100,*,UP,ALU1 +S 5400,500,5400,1800,300,*,DOWN,NDIF +S 6000,1450,6000,4000,200,*,DOWN,ALU1 +S 5700,1500,5700,2600,100,*,DOWN,POLY +S 5700,2100,7200,2100,100,*,RIGHT,POLY +S 7200,1100,7200,3500,100,*,DOWN,ALU1 +S 6000,400,6000,1500,300,*,UP,NDIF +V 3800,2500,CONT_POLY,* +V 4300,2000,CONT_POLY,* +V 4300,3000,CONT_POLY,* +V 1700,1500,CONT_POLY,* +V 3300,1500,CONT_POLY,* +V 4100,1500,CONT_POLY,* +V 1700,3500,CONT_POLY,* +V 2400,3000,CONT_POLY,* +V 400,2500,CONT_POLY,* +V 400,400,CONT_BODY_P,* +V 4800,1700,CONT_DIF_N,* +V 1000,1800,CONT_DIF_N,* +V 1000,1800,CONT_DIF_N,* +V 2200,1500,CONT_DIF_N,* +V 5400,500,CONT_DIF_N,* +V 3800,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 4800,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 400,1000,CONT_DIF_N,* +V 1000,3000,CONT_DIF_P,* +V 6600,3000,CONT_DIF_P,* +V 6600,3500,CONT_DIF_P,* +V 6600,4000,CONT_DIF_P,* +V 6000,3000,CONT_DIF_P,* +V 6000,4000,CONT_DIF_P,* +V 6000,3500,CONT_DIF_P,* +V 5400,4600,CONT_DIF_P,* +V 4800,3000,CONT_DIF_P,* +V 6600,4600,CONT_DIF_P,* +V 4800,4000,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 2200,3500,CONT_DIF_P,* +V 3800,4500,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 400,4600,CONT_BODY_N,* +V 400,4000,CONT_DIF_P,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 7200,3000,CONT_DIF_P,* +V 7200,3500,CONT_DIF_P,* +V 6700,2500,CONT_POLY,* +V 7200,2100,CONT_POLY,* +V 6700,1600,CONT_POLY,* +V 7200,400,CONT_BODY_P,* +V 7200,1100,CONT_DIF_N,* +V 6600,500,CONT_DIF_N,* +V 6000,1500,CONT_DIF_N,* +V 7200,4600,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/nmx3_x4.vbe b/alliance/src/cells/src/sxlib/nmx3_x4.vbe new file mode 100644 index 00000000..1db2d242 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx3_x4.vbe @@ -0,0 +1,59 @@ +ENTITY nmx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 810; + CONSTANT rdown_cmd0_nq : NATURAL := 810; + CONSTANT rdown_cmd1_nq : NATURAL := 810; + CONSTANT rdown_cmd1_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_cmd0_nq : NATURAL := 890; + CONSTANT rup_cmd0_nq : NATURAL := 890; + CONSTANT rup_cmd1_nq : NATURAL := 890; + CONSTANT rup_cmd1_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 748; + CONSTANT tphl_cmd0_nq : NATURAL := 790; + CONSTANT tphl_cmd1_nq : NATURAL := 866; + CONSTANT tphl_i1_nq : NATURAL := 869; + CONSTANT tphl_i2_nq : NATURAL := 869; + CONSTANT tplh_i0_nq : NATURAL := 900; + CONSTANT tplh_cmd0_nq : NATURAL := 936; + CONSTANT tpll_cmd1_nq : NATURAL := 952; + CONSTANT tphh_cmd1_nq : NATURAL := 981; + CONSTANT tpll_cmd0_nq : NATURAL := 993; + CONSTANT tphh_cmd0_nq : NATURAL := 1041; + CONSTANT tplh_cmd1_nq : NATURAL := 1048; + CONSTANT tplh_i1_nq : NATURAL := 1053; + CONSTANT tplh_i2_nq : NATURAL := 1053; + CONSTANT transistors : NATURAL := 24 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x4; + +ARCHITECTURE behaviour_data_flow OF nmx3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx3_x4" + SEVERITY WARNING; + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not + (cmd1) and i2))))) after 1700 ps; +END; diff --git a/alliance/src/cells/src/sxlib/nmx3_x4.vhd b/alliance/src/cells/src/sxlib/nmx3_x4.vhd new file mode 100644 index 00000000..ae619dda --- /dev/null +++ b/alliance/src/cells/src/sxlib/nmx3_x4.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nmx3_x4 IS +PORT( + cmd0 : IN STD_LOGIC; + cmd1 : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nmx3_x4; + +ARCHITECTURE RTL OF nmx3_x4 IS +BEGIN + nq <= NOT(((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2))))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/no2_x1.al b/alliance/src/cells/src/sxlib/no2_x1.al new file mode 100644 index 00000000..827dc1ee --- /dev/null +++ b/alliance/src/cells/src/sxlib/no2_x1.al @@ -0,0 +1,24 @@ +V ALLIANCE : 6 +H no2_x1,L,30/10/99 +C i0,IN,EXTERNAL,5 +C i1,IN,EXTERNAL,6 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,4,6,2,0,0.75,0.75,13.3,13.3,3,11.25,tr_00004 +T P,0.35,5.9,3,5,4,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00003 +T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,3.9,3,tr_00002 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,2.1,3,tr_00001 +S 6,EXTERNAL,i1 +Q 0.00303982 +S 5,EXTERNAL,i0 +Q 0.00343734 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vdd +Q 0.0026442 +S 2,EXTERNAL,nq +Q 0.00305526 +S 1,EXTERNAL,vss +Q 0.00299673 +EOF diff --git a/alliance/src/cells/src/sxlib/no2_x1.ap b/alliance/src/cells/src/sxlib/no2_x1.ap new file mode 100644 index 00000000..2adf55c9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no2_x1.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H no2_x1,P,30/ 8/2000,100 +A 0,0,2000,5000 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 500,1500,ref_ref,nq_15 +R 500,2000,ref_ref,nq_20 +R 500,2500,ref_ref,nq_25 +R 500,3000,ref_ref,nq_30 +R 500,3500,ref_ref,nq_35 +R 500,4000,ref_ref,nq_40 +R 500,1000,ref_ref,nq_10 +R 1500,1000,ref_ref,i0_10 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 500,1000,500,4000,200,nq,DOWN,CALU1 +S 1500,1000,1500,4000,200,i0,DOWN,CALU1 +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 1700,2800,1700,4700,300,*,UP,PDIF +S 700,2400,1000,2400,100,*,LEFT,POLY +S 1300,1900,1500,1900,100,*,LEFT,POLY +S 700,1400,700,2400,100,*,DOWN,POLY +S 400,400,400,1200,300,*,UP,NDIF +S 1600,400,1600,1200,300,*,UP,NDIF +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1400,2050,1400,2600,100,*,DOWN,POLY +S 1300,1400,1300,2000,100,*,UP,POLY +S 450,1000,1000,1000,200,*,LEFT,ALU1 +S 500,950,500,4000,200,*,DOWN,ALU1 +V 500,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 1700,4500,CONT_DIF_P,* +V 1000,300,CONT_BODY_P,* +V 1000,1000,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 1000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/no2_x1.sym b/alliance/src/cells/src/sxlib/no2_x1.sym new file mode 100644 index 00000000..0736b807 Binary files /dev/null and b/alliance/src/cells/src/sxlib/no2_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/no2_x1.vbe b/alliance/src/cells/src/sxlib/no2_x1.vbe new file mode 100644 index 00000000..37a91f3f --- /dev/null +++ b/alliance/src/cells/src/sxlib/no2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tplh_i0_nq : NATURAL := 121; + CONSTANT tplh_i1_nq : NATURAL := 161; + CONSTANT tphl_i1_nq : NATURAL := 193; + CONSTANT tphl_i0_nq : NATURAL := 298; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x1; + +ARCHITECTURE behaviour_data_flow OF no2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x1" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 900 ps; +END; diff --git a/alliance/src/cells/src/sxlib/no2_x1.vhd b/alliance/src/cells/src/sxlib/no2_x1.vhd new file mode 100644 index 00000000..095b74bf --- /dev/null +++ b/alliance/src/cells/src/sxlib/no2_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no2_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no2_x1; + +ARCHITECTURE RTL OF no2_x1 IS +BEGIN + nq <= NOT((i0 OR i1)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/no2_x4.al b/alliance/src/cells/src/sxlib/no2_x4.al new file mode 100644 index 00000000..368b9380 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no2_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H no2_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,3,11.25,tr_00010 +T P,0.35,5.9,5,7,1,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00009 +T P,0.35,5.9,3,6,4,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00008 +T P,0.35,5.9,4,6,3,0,0.75,0.75,13.3,13.3,5.1,11.25,tr_00007 +T P,0.35,2.9,4,1,6,0,0.75,0.75,7.3,7.3,8.7,9.75,tr_00006 +T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00005 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004 +T N,0.35,1.4,6,1,2,0,0.75,0.75,4.3,4.3,8.7,3,tr_00003 +T N,0.35,2.9,2,6,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00002 +T N,0.35,2.9,3,6,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 8,EXTERNAL,i0 +Q 0.00275797 +S 7,EXTERNAL,i1 +Q 0.00260759 +S 6,INTERNAL +Q 0.00628215 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00384489 +S 3,EXTERNAL,nq +Q 0.00214456 +S 2,EXTERNAL,vss +Q 0.0046087 +S 1,INTERNAL +Q 0.00676363 +EOF diff --git a/alliance/src/cells/src/sxlib/no2_x4.ap b/alliance/src/cells/src/sxlib/no2_x4.ap new file mode 100644 index 00000000..8e38eb36 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no2_x4.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H no2_x4,P,30/ 8/2000,100 +A 0,0,3500,5000 +R 2000,1000,ref_ref,nq_10 +R 500,3500,ref_ref,i1_35 +R 500,3000,ref_ref,i1_30 +R 500,2500,ref_ref,i1_25 +R 500,2000,ref_ref,i1_20 +R 500,1500,ref_ref,i1_15 +R 1000,1500,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 2000,3500,ref_ref,nq_35 +R 2000,3000,ref_ref,nq_30 +R 2000,2500,ref_ref,nq_25 +R 2000,2000,ref_ref,nq_20 +R 2000,1500,ref_ref,nq_15 +S 500,1500,500,3500,200,i1,DOWN,CALU1 +S 1000,1500,1000,3500,200,i0,DOWN,CALU1 +S 2000,1000,2000,3500,200,nq,DOWN,CALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 2000,950,2000,3500,200,*,DOWN,ALU1 +S 3200,3000,3200,3500,100,*,DOWN,ALU1 +S 900,2400,1200,2400,100,*,LEFT,POLY +S 1200,1400,1200,2400,100,*,UP,POLY +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,1000,1500,1000,100,*,LEFT,ALU1 +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 300,400,300,1200,300,*,UP,NDIF +S 600,1400,600,2600,100,*,DOWN,POLY +S 1300,2800,1300,4700,300,*,DOWN,PDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 300,2800,300,4700,300,*,DOWN,PDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2500,2000,3200,2000,100,*,RIGHT,ALU1 +S 2600,2500,2900,2500,300,*,RIGHT,POLY +S 1700,2000,2600,2000,300,*,RIGHT,POLY +S 1800,1400,1800,2100,100,*,DOWN,POLY +S 1700,1900,1700,2600,100,*,UP,POLY +S 2300,1900,2300,2600,100,*,DOWN,POLY +S 2400,1400,2400,2100,100,*,UP,POLY +S 2700,2500,2700,4000,100,*,DOWN,ALU1 +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 500,1500,500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 2900,600,2900,1400,100,*,UP,NTRANS +S 3200,800,3200,1200,300,*,DOWN,NDIF +S 3200,2800,3200,3700,300,*,UP,PDIF +S 2300,2600,2300,4900,100,*,DOWN,PTRANS +S 1700,2600,1700,4900,100,*,DOWN,PTRANS +S 2000,2800,2000,4700,300,*,UP,PDIF +S 2600,2800,2600,4700,300,*,UP,PDIF +S 2900,2600,2900,3900,100,*,DOWN,PTRANS +S 1400,2800,1400,4700,300,*,UP,PDIF +S 3200,1000,3200,3000,100,*,UP,ALU1 +S 2400,100,2400,1400,100,*,UP,NTRANS +S 1800,100,1800,1400,100,*,UP,NTRANS +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +V 300,1000,CONT_DIF_N,* +V 3200,3500,CONT_DIF_P,* +V 1500,400,CONT_DIF_N,* +V 900,300,CONT_BODY_P,* +V 900,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 300,4000,CONT_DIF_P,* +V 2500,2000,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 1000,2500,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3200,1000,CONT_DIF_N,* +V 1400,4500,CONT_DIF_P,* +V 2600,4500,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,4700,CONT_BODY_N,* +V 2700,2500,CONT_POLY,* +V 2700,300,CONT_DIF_N,* +V 2000,3000,CONT_DIF_P,* +V 2000,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/no2_x4.sym b/alliance/src/cells/src/sxlib/no2_x4.sym new file mode 100644 index 00000000..dfc6d710 Binary files /dev/null and b/alliance/src/cells/src/sxlib/no2_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/no2_x4.vbe b/alliance/src/cells/src/sxlib/no2_x4.vbe new file mode 100644 index 00000000..5060db0e --- /dev/null +++ b/alliance/src/cells/src/sxlib/no2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tplh_i0_nq : NATURAL := 447; + CONSTANT tplh_i1_nq : NATURAL := 504; + CONSTANT tphl_i1_nq : NATURAL := 522; + CONSTANT tphl_i0_nq : NATURAL := 618; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x4; + +ARCHITECTURE behaviour_data_flow OF no2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x4" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/no2_x4.vhd b/alliance/src/cells/src/sxlib/no2_x4.vhd new file mode 100644 index 00000000..43e59322 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no2_x4; + +ARCHITECTURE RTL OF no2_x4 IS +BEGIN + nq <= NOT((i0 OR i1)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/no3_x1.al b/alliance/src/cells/src/sxlib/no3_x1.al new file mode 100644 index 00000000..ff99b0b4 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no3_x1.al @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H no3_x1,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,5,6,3,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00006 +T P,0.35,5.9,3,7,1,0,0.75,0.75,13.3,13.3,3,11.25,tr_00005 +T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00004 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,1.4,2,6,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001 +S 8,EXTERNAL,i2 +Q 0.00361086 +S 7,EXTERNAL,i1 +Q 0.00317863 +S 6,EXTERNAL,i0 +Q 0.0032596 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00298567 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.0033382 +S 1,EXTERNAL,nq +Q 0.00381907 +EOF diff --git a/alliance/src/cells/src/sxlib/no3_x1.ap b/alliance/src/cells/src/sxlib/no3_x1.ap new file mode 100644 index 00000000..7d5a3e3c --- /dev/null +++ b/alliance/src/cells/src/sxlib/no3_x1.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H no3_x1,P,30/ 8/2000,100 +A 0,0,2500,5000 +R 2000,1000,ref_ref,i2_10 +R 500,4000,ref_ref,nq_40 +R 500,3500,ref_ref,nq_35 +R 500,3000,ref_ref,nq_30 +R 500,2500,ref_ref,nq_25 +R 500,2000,ref_ref,nq_20 +R 500,1500,ref_ref,nq_15 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 1500,4000,ref_ref,i0_40 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 2000,4000,ref_ref,i2_40 +R 500,1000,ref_ref,nq_10 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 500,1000,500,4000,200,nq,DOWN,CALU1 +S 300,1000,500,1000,200,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 1500,800,1500,1200,300,*,UP,NDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 900,400,900,1200,300,*,UP,NDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,2400,1100,2400,100,*,LEFT,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 300,1000,1500,1000,200,*,LEFT,ALU1 +S 500,1000,500,4000,200,*,DOWN,ALU1 +V 2100,500,CONT_DIF_N,* +V 1500,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2100,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 500,3000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 1000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/no3_x1.sym b/alliance/src/cells/src/sxlib/no3_x1.sym new file mode 100644 index 00000000..ca5f63b1 Binary files /dev/null and b/alliance/src/cells/src/sxlib/no3_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/no3_x1.vbe b/alliance/src/cells/src/sxlib/no3_x1.vbe new file mode 100644 index 00000000..6711f8b1 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT tplh_i2_nq : NATURAL := 192; + CONSTANT tphl_i1_nq : NATURAL := 215; + CONSTANT tplh_i1_nq : NATURAL := 243; + CONSTANT tplh_i0_nq : NATURAL := 246; + CONSTANT tphl_i0_nq : NATURAL := 318; + CONSTANT tphl_i2_nq : NATURAL := 407; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x1; + +ARCHITECTURE behaviour_data_flow OF no3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/no3_x1.vhd b/alliance/src/cells/src/sxlib/no3_x1.vhd new file mode 100644 index 00000000..9ba7168a --- /dev/null +++ b/alliance/src/cells/src/sxlib/no3_x1.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no3_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no3_x1; + +ARCHITECTURE RTL OF no3_x1 IS +BEGIN + nq <= NOT(((i0 OR i1) OR i2)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/no3_x4.al b/alliance/src/cells/src/sxlib/no3_x4.al new file mode 100644 index 00000000..1ec48c9c --- /dev/null +++ b/alliance/src/cells/src/sxlib/no3_x4.al @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H no3_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,2.9,4,3,7,0,0.75,0.75,7.3,7.3,10.2,9.75,tr_00012 +T P,0.35,5.9,4,7,1,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00011 +T P,0.35,5.9,1,7,4,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00010 +T P,0.35,5.9,6,10,3,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00009 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,3,11.25,tr_00008 +T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00007 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00006 +T N,0.35,2.9,2,7,1,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00005 +T N,0.35,1.4,7,3,2,0,0.75,0.75,4.3,4.3,10.2,3,tr_00004 +T N,0.35,1.4,2,9,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003 +T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,1.4,3,10,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 10,EXTERNAL,i2 +Q 0.00260759 +S 9,EXTERNAL,i1 +Q 0.00282737 +S 8,EXTERNAL,i0 +Q 0.00282737 +S 7,INTERNAL +Q 0.00571129 +S 6,INTERNAL +Q 0 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00418636 +S 3,INTERNAL +Q 0.00784181 +S 2,EXTERNAL,vss +Q 0.00436263 +S 1,EXTERNAL,nq +Q 0.00214456 +EOF diff --git a/alliance/src/cells/src/sxlib/no3_x4.ap b/alliance/src/cells/src/sxlib/no3_x4.ap new file mode 100644 index 00000000..79e688d5 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no3_x4.ap @@ -0,0 +1,99 @@ +V ALLIANCE : 6 +H no3_x4,P,30/ 8/2000,100 +A 0,0,4000,5000 +R 2500,1500,ref_ref,nq_15 +R 2500,2000,ref_ref,nq_20 +R 2500,2500,ref_ref,nq_25 +R 2500,3000,ref_ref,nq_30 +R 2500,3500,ref_ref,nq_35 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,3000,ref_ref,i2_30 +R 500,2500,ref_ref,i2_25 +R 500,2000,ref_ref,i2_20 +R 500,1500,ref_ref,i2_15 +R 500,3500,ref_ref,i2_35 +R 2500,1000,ref_ref,nq_10 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i2,DOWN,CALU1 +S 2500,1000,2500,3500,200,nq,DOWN,CALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 2100,300,2100,1200,300,*,UP,NDIF +S 2300,100,2300,1400,100,*,UP,NTRANS +S 2900,100,2900,1400,100,*,UP,NTRANS +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 3700,1000,3700,3000,100,*,UP,ALU1 +S 1900,2800,1900,4700,300,*,UP,PDIF +S 3400,2600,3400,3900,100,*,DOWN,PTRANS +S 3100,2800,3100,4700,300,*,UP,PDIF +S 2500,2800,2500,4700,300,*,UP,PDIF +S 2200,2600,2200,4900,100,*,DOWN,PTRANS +S 2800,2600,2800,4900,100,*,DOWN,PTRANS +S 3700,2800,3700,3700,300,*,UP,PDIF +S 3700,800,3700,1200,300,*,DOWN,NDIF +S 3400,600,3400,1400,100,*,UP,NTRANS +S 3100,300,3100,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,400,900,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1700,2800,1700,4700,300,*,DOWN,PDIF +S 600,1400,600,2600,100,*,DOWN,POLY +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,UP,ALU1 +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1800,1400,1800,2400,100,*,UP,POLY +S 1400,2400,1800,2400,100,*,LEFT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 300,1000,2000,1000,100,*,LEFT,ALU1 +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 3200,2500,3200,4000,100,*,DOWN,ALU1 +S 2900,1400,2900,2100,100,*,UP,POLY +S 2800,1900,2800,2600,100,*,DOWN,POLY +S 2200,1900,2200,2600,100,*,UP,POLY +S 2300,1400,2300,2100,100,*,DOWN,POLY +S 2200,2000,3100,2000,300,*,RIGHT,POLY +S 3100,2500,3400,2500,300,*,RIGHT,POLY +S 3000,2000,3700,2000,100,*,RIGHT,ALU1 +S 2500,950,2500,3500,200,*,DOWN,ALU1 +V 2500,3500,CONT_DIF_P,* +V 2500,3000,CONT_DIF_P,* +V 2000,300,CONT_DIF_N,* +V 3200,300,CONT_DIF_N,* +V 3200,2500,CONT_POLY,* +V 3700,4700,CONT_BODY_N,* +V 3700,3000,CONT_DIF_P,* +V 3100,4500,CONT_DIF_P,* +V 1900,4500,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,300,CONT_BODY_P,* +V 300,4000,CONT_DIF_P,* +V 1000,2000,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2600,1000,CONT_DIF_N,* +V 3000,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/no3_x4.sym b/alliance/src/cells/src/sxlib/no3_x4.sym new file mode 100644 index 00000000..bfea318a Binary files /dev/null and b/alliance/src/cells/src/sxlib/no3_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/no3_x4.vbe b/alliance/src/cells/src/sxlib/no3_x4.vbe new file mode 100644 index 00000000..52e3d602 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 545; + CONSTANT tplh_i0_nq : NATURAL := 561; + CONSTANT tplh_i1_nq : NATURAL := 623; + CONSTANT tphl_i1_nq : NATURAL := 638; + CONSTANT tplh_i2_nq : NATURAL := 640; + CONSTANT tphl_i0_nq : NATURAL := 722; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x4; + +ARCHITECTURE behaviour_data_flow OF no3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/no3_x4.vhd b/alliance/src/cells/src/sxlib/no3_x4.vhd new file mode 100644 index 00000000..1d621496 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no3_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no3_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no3_x4; + +ARCHITECTURE RTL OF no3_x4 IS +BEGIN + nq <= NOT(((i0 OR i1) OR i2)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/no4_x1.al b/alliance/src/cells/src/sxlib/no4_x1.al new file mode 100644 index 00000000..315b53be --- /dev/null +++ b/alliance/src/cells/src/sxlib/no4_x1.al @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H no4_x1,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,10 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,3,8,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00008 +T P,0.35,5.9,6,10,2,0,0.75,0.75,13.3,13.3,3,11.25,tr_00007 +T P,0.35,5.9,4,7,6,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00006 +T P,0.35,5.9,5,9,3,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00005 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004 +T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003 +T N,0.35,1.4,1,10,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00002 +T N,0.35,1.4,2,9,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00001 +S 10,EXTERNAL,i1 +Q 0.00317863 +S 9,EXTERNAL,i3 +Q 0.00310922 +S 8,EXTERNAL,i2 +Q 0.00332901 +S 7,EXTERNAL,i0 +Q 0.0032596 +S 6,INTERNAL +Q 0 +S 5,EXTERNAL,vdd +Q 0.00332715 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,nq +Q 0.00399534 +S 1,EXTERNAL,vss +Q 0.00403221 +EOF diff --git a/alliance/src/cells/src/sxlib/no4_x1.ap b/alliance/src/cells/src/sxlib/no4_x1.ap new file mode 100644 index 00000000..c9954ac3 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no4_x1.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 6 +H no4_x1,P,30/ 8/2000,100 +A 0,0,3000,5000 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 2500,4000,ref_ref,i3_40 +R 2500,3500,ref_ref,i3_35 +R 2500,3000,ref_ref,i3_30 +R 2500,2500,ref_ref,i3_25 +R 2500,2000,ref_ref,i3_20 +R 2500,1500,ref_ref,i3_15 +R 500,4000,ref_ref,nq_40 +R 500,1500,ref_ref,nq_15 +R 500,2000,ref_ref,nq_20 +R 500,2500,ref_ref,nq_25 +R 500,3000,ref_ref,nq_30 +R 500,3500,ref_ref,nq_35 +R 500,1000,ref_ref,nq_10 +S 2000,1500,2000,4000,200,i2,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 2500,1500,2500,4000,200,i3,DOWN,CALU1 +S 500,1000,500,4000,200,nq,DOWN,CALU1 +S 850,1000,2100,1000,200,*,LEFT,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 600,2400,1100,2400,100,*,LEFT,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2000,1500,2000,4000,100,*,UP,ALU1 +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 300,400,300,1200,300,*,UP,NDIF +S 1500,400,1500,1200,300,*,UP,NDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2500,1500,2500,4000,100,*,UP,ALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 500,950,500,4000,200,*,DOWN,ALU1 +S 450,1000,850,1000,200,*,LEFT,ALU1 +V 1500,2000,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 900,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,4700,CONT_BODY_N,* +V 900,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 500,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 2500,4500,CONT_DIF_P,* +V 2700,500,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/no4_x1.sym b/alliance/src/cells/src/sxlib/no4_x1.sym new file mode 100644 index 00000000..b45e1477 Binary files /dev/null and b/alliance/src/cells/src/sxlib/no4_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/no4_x1.vbe b/alliance/src/cells/src/sxlib/no4_x1.vbe new file mode 100644 index 00000000..5d15a3cd --- /dev/null +++ b/alliance/src/cells/src/sxlib/no4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rdown_i3_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT tphl_i1_nq : NATURAL := 230; + CONSTANT tplh_i3_nq : NATURAL := 271; + CONSTANT tplh_i1_nq : NATURAL := 320; + CONSTANT tphl_i0_nq : NATURAL := 330; + CONSTANT tplh_i2_nq : NATURAL := 333; + CONSTANT tplh_i0_nq : NATURAL := 340; + CONSTANT tphl_i2_nq : NATURAL := 419; + CONSTANT tphl_i3_nq : NATURAL := 499; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x1; + +ARCHITECTURE behaviour_data_flow OF no4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x1" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/no4_x1.vhd b/alliance/src/cells/src/sxlib/no4_x1.vhd new file mode 100644 index 00000000..651a0b4f --- /dev/null +++ b/alliance/src/cells/src/sxlib/no4_x1.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no4_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no4_x1; + +ARCHITECTURE RTL OF no4_x1 IS +BEGIN + nq <= NOT((((i0 OR i1) OR i2) OR i3)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/no4_x4.al b/alliance/src/cells/src/sxlib/no4_x4.al new file mode 100644 index 00000000..df49bccf --- /dev/null +++ b/alliance/src/cells/src/sxlib/no4_x4.al @@ -0,0 +1,48 @@ +V ALLIANCE : 6 +H no4_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,10 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C nq,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00014 +T P,0.35,5.9,3,10,1,0,0.75,0.75,13.3,13.3,3,11.25,tr_00013 +T P,0.35,5.9,5,7,3,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00012 +T P,0.35,5.9,6,9,4,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00011 +T P,0.35,5.9,11,12,6,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00010 +T P,0.35,5.9,6,12,11,0,0.75,0.75,13.3,13.3,9.6,11.25,tr_00009 +T P,0.35,2.9,6,1,12,0,0.75,0.75,7.3,7.3,13.2,9.75,tr_00008 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00007 +T N,0.35,1.4,2,8,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00006 +T N,0.35,1.4,2,10,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005 +T N,0.35,1.4,1,9,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00004 +T N,0.35,2.9,11,12,2,0,0.75,0.75,7.3,7.3,9.6,2.25,tr_00003 +T N,0.35,2.9,2,12,11,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00002 +T N,0.35,1.4,12,1,2,0,0.75,0.75,4.3,4.3,13.2,3,tr_00001 +S 12,INTERNAL +Q 0.00586076 +S 11,EXTERNAL,nq +Q 0.00229144 +S 10,EXTERNAL,i1 +Q 0.00317863 +S 9,EXTERNAL,i3 +Q 0.00310922 +S 8,EXTERNAL,i2 +Q 0.00332901 +S 7,EXTERNAL,i0 +Q 0.0032596 +S 6,EXTERNAL,vdd +Q 0.00674947 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.00575064 +S 1,INTERNAL +Q 0.00812639 +EOF diff --git a/alliance/src/cells/src/sxlib/no4_x4.ap b/alliance/src/cells/src/sxlib/no4_x4.ap new file mode 100644 index 00000000..2fa594d6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no4_x4.ap @@ -0,0 +1,138 @@ +V ALLIANCE : 6 +H no4_x4,P,30/ 8/2000,100 +A 0,0,5000,5000 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 2500,4000,ref_ref,i3_40 +R 2500,3500,ref_ref,i3_35 +R 2500,3000,ref_ref,i3_30 +R 2500,2500,ref_ref,i3_25 +R 2500,2000,ref_ref,i3_20 +R 2500,1500,ref_ref,i3_15 +R 3500,3500,ref_ref,nq_35 +R 3500,4000,ref_ref,nq_40 +R 3500,1500,ref_ref,nq_15 +R 3500,2000,ref_ref,nq_20 +R 3500,2500,ref_ref,nq_25 +R 3500,3000,ref_ref,nq_30 +S 2000,1500,2000,4000,200,i2,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 2500,1500,2500,4000,200,i3,DOWN,CALU1 +S 3500,1500,3500,4000,200,nq,DOWN,CALU1 +S 3500,1500,3500,4000,200,*,DOWN,ALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 600,2400,1100,2400,100,*,LEFT,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2000,1500,2000,4000,100,*,UP,ALU1 +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 300,400,300,1200,300,*,UP,NDIF +S 1500,400,1500,1200,300,*,UP,NDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2500,1500,2500,4000,100,*,UP,ALU1 +S 4000,2500,4200,2500,200,*,RIGHT,ALU1 +S 2900,300,2900,1200,300,*,DOWN,NDIF +S 3200,100,3200,1400,100,*,UP,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 3800,100,3800,1400,100,*,UP,NTRANS +S 4400,600,4400,1400,100,*,UP,NTRANS +S 4700,800,4700,1200,300,*,DOWN,NDIF +S 4700,2800,4700,3700,300,*,UP,PDIF +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 3200,2600,3200,4900,100,*,DOWN,PTRANS +S 3500,2800,3500,4700,300,*,UP,PDIF +S 4100,2800,4100,4700,300,*,UP,PDIF +S 4400,2600,4400,3900,100,*,DOWN,PTRANS +S 2900,2800,2900,4700,300,*,UP,PDIF +S 3200,1400,3200,2600,100,*,UP,POLY +S 3800,1400,3800,2600,100,*,UP,POLY +S 4200,2500,4400,2500,300,*,RIGHT,POLY +S 4700,1000,4700,3000,100,*,UP,ALU1 +S 3200,2000,4700,2000,300,*,RIGHT,POLY +S 4200,1500,4400,1500,300,*,RIGHT,POLY +S 4000,1500,4200,1500,200,*,RIGHT,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 2800,2800,2800,4700,300,*,UP,PDIF +S 2700,300,2700,1200,300,*,UP,NDIF +S 4000,1000,4000,2500,100,*,UP,ALU1 +S 3500,300,3500,1600,300,*,DOWN,NDIF +S 4100,3000,4100,4500,200,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,DOWN,ALU1 +S 500,3000,500,4000,100,*,UP,ALU1 +S 500,1000,4000,1000,100,*,LEFT,ALU1 +S 500,1000,900,1000,200,*,LEFT,ALU1 +S 4700,3000,4700,3500,100,*,DOWN,ALU1 +V 1500,2000,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 900,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,4700,CONT_BODY_N,* +V 900,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 4700,1000,CONT_DIF_N,* +V 4100,500,CONT_DIF_N,* +V 4100,4500,CONT_DIF_P,* +V 4700,3000,CONT_DIF_P,* +V 4700,4700,CONT_BODY_N,* +V 4700,300,CONT_BODY_P,* +V 4200,2500,CONT_POLY,* +V 4700,2000,CONT_POLY,* +V 4200,1500,CONT_POLY,* +V 2800,500,CONT_DIF_N,* +V 3500,4000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 3500,3000,CONT_DIF_P,* +V 3500,1500,CONT_DIF_N,* +V 500,3000,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3500,CONT_DIF_P,* +V 4100,3000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 2500,4500,CONT_DIF_P,* +V 2900,4500,CONT_DIF_P,* +V 4700,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/no4_x4.sym b/alliance/src/cells/src/sxlib/no4_x4.sym new file mode 100644 index 00000000..ca15cbb2 Binary files /dev/null and b/alliance/src/cells/src/sxlib/no4_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/no4_x4.vbe b/alliance/src/cells/src/sxlib/no4_x4.vbe new file mode 100644 index 00000000..cffb179c --- /dev/null +++ b/alliance/src/cells/src/sxlib/no4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 564; + CONSTANT tphl_i0_nq : NATURAL := 656; + CONSTANT tplh_i3_nq : NATURAL := 693; + CONSTANT tphl_i2_nq : NATURAL := 739; + CONSTANT tplh_i2_nq : NATURAL := 761; + CONSTANT tplh_i1_nq : NATURAL := 768; + CONSTANT tplh_i0_nq : NATURAL := 777; + CONSTANT tphl_i3_nq : NATURAL := 816; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x4; + +ARCHITECTURE behaviour_data_flow OF no4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x4" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/no4_x4.vhd b/alliance/src/cells/src/sxlib/no4_x4.vhd new file mode 100644 index 00000000..855a29a7 --- /dev/null +++ b/alliance/src/cells/src/sxlib/no4_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no4_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no4_x4; + +ARCHITECTURE RTL OF no4_x4 IS +BEGIN + nq <= NOT((((i0 OR i1) OR i2) OR i3)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa22_x1.al b/alliance/src/cells/src/sxlib/noa22_x1.al new file mode 100644 index 00000000..fe536c46 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa22_x1.al @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H noa22_x1,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,5,8,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,5.9,2,6,4,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00005 +T P,0.35,5.9,4,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00004 +T N,0.35,2.9,3,6,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00003 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 8,EXTERNAL,i2 +Q 0.00344864 +S 7,EXTERNAL,i1 +Q 0.00288494 +S 6,EXTERNAL,i0 +Q 0.00260759 +S 5,EXTERNAL,vdd +Q 0.004561 +S 4,INTERNAL +Q 0.00171257 +S 3,EXTERNAL,vss +Q 0.00450225 +S 2,EXTERNAL,nq +Q 0.0026146 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/noa22_x1.ap b/alliance/src/cells/src/sxlib/noa22_x1.ap new file mode 100644 index 00000000..dcb02458 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa22_x1.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H noa22_x1,P,30/ 8/2000,100 +A 0,0,3000,5000 +R 2000,4000,ref_ref,i2_40 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 2000,1000,ref_ref,i2_10 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 1500,1000,ref_ref,nq_10 +R 1500,1500,ref_ref,nq_15 +R 1500,2000,ref_ref,nq_20 +R 1500,2500,ref_ref,nq_25 +R 1500,3000,ref_ref,nq_30 +R 1500,3500,ref_ref,nq_35 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 0,3900,3000,3900,2400,*,LEFT,NWELL +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2700,500,2700,1700,200,*,DOWN,ALU1 +S 2700,2900,2700,4500,200,*,DOWN,ALU1 +S 2000,1000,2000,4000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 900,3500,1500,3500,200,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 1500,1000,1500,3550,200,*,UP,ALU1 +V 2700,300,CONT_BODY_P,* +V 2700,4700,CONT_BODY_N,* +V 2700,2900,CONT_BODY_N,* +V 2700,1700,CONT_BODY_P,* +V 2100,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 300,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa22_x1.sym b/alliance/src/cells/src/sxlib/noa22_x1.sym new file mode 100644 index 00000000..feab1697 Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa22_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/noa22_x1.vbe b/alliance/src/cells/src/sxlib/noa22_x1.vbe new file mode 100644 index 00000000..5c13864f --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 1620; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tphl_i2_nq : NATURAL := 218; + CONSTANT tplh_i2_nq : NATURAL := 241; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x1; + +ARCHITECTURE behaviour_data_flow OF noa22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 900 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa22_x1.vhd b/alliance/src/cells/src/sxlib/noa22_x1.vhd new file mode 100644 index 00000000..50447019 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa22_x1.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa22_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa22_x1; + +ARCHITECTURE RTL OF noa22_x1 IS +BEGIN + nq <= NOT(((i0 AND i1) OR i2)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa22_x4.al b/alliance/src/cells/src/sxlib/noa22_x4.al new file mode 100644 index 00000000..8157586a --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa22_x4.al @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H noa22_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,5 +C i2,IN,EXTERNAL,6 +C nq,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,9 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,8,4,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00012 +T P,0.35,5.9,9,4,8,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00011 +T P,0.35,2.9,9,1,4,0,0.75,0.75,7.3,7.3,9.3,9.75,tr_00010 +T P,0.35,2.9,10,6,9,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00009 +T P,0.35,2.9,10,7,1,0,0.75,0.75,7.3,7.3,5.7,11.25,tr_00008 +T P,0.35,2.9,1,5,10,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00007 +T N,0.35,2.9,8,4,3,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00006 +T N,0.35,1.4,4,1,3,0,0.75,0.75,4.3,4.3,9.3,3,tr_00005 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,5.7,3,tr_00004 +T N,0.35,1.4,1,5,2,0,0.75,0.75,4.3,4.3,3.9,3,tr_00003 +T N,0.35,2.9,3,4,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00002 +T N,0.35,1.4,3,6,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00001 +S 10,INTERNAL +Q 0.00114171 +S 9,EXTERNAL,vdd +Q 0.00768955 +S 8,EXTERNAL,nq +Q 0.00258522 +S 7,EXTERNAL,i0 +Q 0.00295462 +S 6,EXTERNAL,i2 +Q 0.00379567 +S 5,EXTERNAL,i1 +Q 0.00323197 +S 4,INTERNAL +Q 0.00518414 +S 3,EXTERNAL,vss +Q 0.00674947 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00560501 +EOF diff --git a/alliance/src/cells/src/sxlib/noa22_x4.ap b/alliance/src/cells/src/sxlib/noa22_x4.ap new file mode 100644 index 00000000..090e7de7 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa22_x4.ap @@ -0,0 +1,122 @@ +V ALLIANCE : 6 +H noa22_x4,P,30/ 8/2000,100 +A 0,0,5000,5000 +R 500,4000,ref_ref,i2_40 +R 500,3500,ref_ref,i2_35 +R 4000,3500,ref_ref,nq_35 +R 4000,3000,ref_ref,nq_30 +R 4000,2000,ref_ref,nq_20 +R 4000,1000,ref_ref,nq_10 +R 4000,1500,ref_ref,nq_15 +R 4000,2500,ref_ref,nq_25 +R 500,1000,ref_ref,i2_10 +R 500,1500,ref_ref,i2_15 +R 500,2000,ref_ref,i2_20 +R 500,2500,ref_ref,i2_25 +R 500,3000,ref_ref,i2_30 +R 2000,2000,ref_ref,i0_20 +R 2000,2500,ref_ref,i0_25 +R 2000,3000,ref_ref,i0_30 +R 1500,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 1500,1000,ref_ref,i1_10 +R 4000,4000,ref_ref,nq_40 +R 2000,1000,ref_ref,i0_10 +R 2000,1500,ref_ref,i0_15 +S 500,1000,500,4000,200,i2,DOWN,CALU1 +S 1500,1000,1500,3000,200,i1,DOWN,CALU1 +S 4000,1000,4000,4000,200,nq,DOWN,CALU1 +S 2000,1000,2000,3000,200,i0,DOWN,CALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 400,3300,400,4600,300,*,DOWN,PDIF +S 1600,3300,1600,4200,300,*,DOWN,PDIF +S 1000,3500,3300,3500,100,*,RIGHT,ALU1 +S 1500,1000,1500,3000,100,*,DOWN,ALU1 +S 2800,1000,2800,3000,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,UP,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 2800,2000,3500,2000,100,*,RIGHT,ALU1 +S 3300,2500,3300,3500,100,*,DOWN,ALU1 +S 2000,1000,2000,3000,100,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 1000,4000,2200,4000,100,*,RIGHT,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 500,2000,700,2000,300,*,RIGHT,POLY +S 1300,2000,1500,2000,300,*,RIGHT,POLY +S 3500,2000,4300,2000,300,*,RIGHT,POLY +S 3100,2500,3300,2500,300,*,RIGHT,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 3100,1400,3100,2600,100,*,DOWN,POLY +S 700,1400,700,3100,100,*,DOWN,POLY +S 1300,1400,1300,3100,100,*,DOWN,POLY +S 1900,1400,1900,3100,100,*,DOWN,POLY +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 4600,300,4600,1200,300,*,UP,NDIF +S 3100,600,3100,1400,100,*,DOWN,NTRANS +S 2800,800,2800,1200,300,*,UP,NDIF +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 1600,800,1600,1200,300,*,UP,NDIF +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 2200,400,2200,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 400,400,400,1200,300,*,UP,NDIF +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 3100,2600,3100,3900,100,*,UP,PTRANS +S 2800,2800,2800,3700,300,*,DOWN,PDIF +S 700,3100,700,4400,100,*,UP,PTRANS +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 2200,3300,2200,4200,300,*,DOWN,PDIF +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +V 1600,4700,CONT_BODY_N,* +V 400,4500,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 3500,2000,CONT_POLY,* +V 3300,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1600,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 2800,300,CONT_BODY_P,* +V 1000,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 2200,500,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 3400,4500,CONT_DIF_P,* +V 3400,4000,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 2200,4000,CONT_DIF_P,* +V 1000,4700,CONT_BODY_N,* +V 2800,4700,CONT_BODY_N,* +V 2800,3000,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 2200,4700,CONT_BODY_N,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa22_x4.sym b/alliance/src/cells/src/sxlib/noa22_x4.sym new file mode 100644 index 00000000..cbc2e448 Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa22_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/noa22_x4.vbe b/alliance/src/cells/src/sxlib/noa22_x4.vbe new file mode 100644 index 00000000..6288a32e --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 550; + CONSTANT tphl_i2_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i2_nq : NATURAL := 646; + CONSTANT tplh_i1_nq : NATURAL := 709; + CONSTANT tplh_i0_nq : NATURAL := 740; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x4; + +ARCHITECTURE behaviour_data_flow OF noa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa22_x4.vhd b/alliance/src/cells/src/sxlib/noa22_x4.vhd new file mode 100644 index 00000000..8723b663 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa22_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa22_x4; + +ARCHITECTURE RTL OF noa22_x4 IS +BEGIN + nq <= NOT(((i0 AND i1) OR i2)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa2a22_x1.al b/alliance/src/cells/src/sxlib/noa2a22_x1.al new file mode 100644 index 00000000..3e8dac59 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a22_x1.al @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H noa2a22_x1,L,30/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,5,8,3,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00008 +T P,0.35,5.9,3,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00007 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005 +T N,0.35,2.9,4,9,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,2.9,3,7,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003 +T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 10,EXTERNAL,i0 +Q 0.00260759 +S 9,EXTERNAL,i2 +Q 0.00288944 +S 8,EXTERNAL,i1 +Q 0.00288494 +S 7,EXTERNAL,i3 +Q 0.00316679 +S 6,EXTERNAL,vdd +Q 0.00472621 +S 5,INTERNAL +Q 0.00199441 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,nq +Q 0.00264397 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00466746 +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a22_x1.ap b/alliance/src/cells/src/sxlib/noa2a22_x1.ap new file mode 100644 index 00000000..05679626 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a22_x1.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H noa2a22_x1,P,30/ 8/2000,100 +A 0,0,3500,5000 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 2500,1000,ref_ref,i2_10 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2500,3500,ref_ref,i2_35 +R 2000,3500,ref_ref,i3_35 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 2000,1000,ref_ref,i3_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 2500,1000,2500,3500,200,i2,DOWN,CALU1 +S 2000,1000,2000,3500,200,i3,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 0,3900,3500,3900,2400,*,LEFT,NWELL +S 3200,500,3200,1700,200,*,DOWN,ALU1 +S 3200,2900,3200,4500,200,*,DOWN,ALU1 +S 2700,3400,2700,4700,300,*,DOWN,PDIF +S 2700,300,2700,1200,300,*,UP,NDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,1400,600,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 2000,1000,2000,3500,100,*,DOWN,ALU1 +S 2500,1000,2500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2600,2800,2600,3300,300,*,UP,PDIF +S 1500,1000,1500,3550,200,*,UP,ALU1 +S 900,3500,1550,3500,200,*,RIGHT,ALU1 +V 3200,2900,CONT_BODY_N,* +V 3200,1700,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a22_x1.sym b/alliance/src/cells/src/sxlib/noa2a22_x1.sym new file mode 100644 index 00000000..8a5d4d5c Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa2a22_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/noa2a22_x1.vbe b/alliance/src/cells/src/sxlib/noa2a22_x1.vbe new file mode 100644 index 00000000..d6348198 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i3_nq : NATURAL := 256; + CONSTANT tphl_i2_nq : NATURAL := 284; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i2_nq : NATURAL := 289; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT tphl_i3_nq : NATURAL := 372; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa2a22_x1.vhd b/alliance/src/cells/src/sxlib/noa2a22_x1.vhd new file mode 100644 index 00000000..acb4a088 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a22_x1.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a22_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a22_x1; + +ARCHITECTURE RTL OF noa2a22_x1 IS +BEGIN + nq <= NOT(((i0 AND i1) OR (i2 AND i3))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa2a22_x4.al b/alliance/src/cells/src/sxlib/noa2a22_x4.al new file mode 100644 index 00000000..d5b7bc86 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a22_x4.al @@ -0,0 +1,48 @@ +V ALLIANCE : 6 +H noa2a22_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,5 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,9 +C vdd,IN,EXTERNAL,11 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,12,5,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00014 +T P,0.35,2.9,12,8,11,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00013 +T P,0.35,2.9,11,7,12,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00012 +T P,0.35,2.9,3,6,12,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00011 +T P,0.35,5.9,9,10,11,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00010 +T P,0.35,5.9,11,10,9,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00009 +T P,0.35,2.9,11,3,10,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00008 +T N,0.35,1.4,2,5,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00007 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006 +T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00005 +T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004 +T N,0.35,2.9,1,10,9,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00003 +T N,0.35,2.9,9,10,1,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00002 +T N,0.35,1.4,10,3,1,0,0.75,0.75,4.3,4.3,10.8,3,tr_00001 +S 12,INTERNAL +Q 0.00199441 +S 11,EXTERNAL,vdd +Q 0.00803103 +S 10,INTERNAL +Q 0.00518414 +S 9,EXTERNAL,nq +Q 0.00258522 +S 8,EXTERNAL,i2 +Q 0.00295462 +S 7,EXTERNAL,i3 +Q 0.00323197 +S 6,EXTERNAL,i0 +Q 0.00295462 +S 5,EXTERNAL,i1 +Q 0.00323197 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00594323 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00726721 +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a22_x4.ap b/alliance/src/cells/src/sxlib/noa2a22_x4.ap new file mode 100644 index 00000000..4f40230e --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a22_x4.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 6 +H noa2a22_x4,P,30/ 8/2000,100 +A 0,0,5500,5000 +R 4500,4000,ref_ref,nq_40 +R 2500,1000,ref_ref,i2_10 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 2000,1000,ref_ref,i3_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 4500,3500,ref_ref,nq_35 +R 4500,3000,ref_ref,nq_30 +R 4500,2000,ref_ref,nq_20 +R 4500,1000,ref_ref,nq_10 +R 4500,1500,ref_ref,nq_15 +R 4500,2500,ref_ref,nq_25 +S 2500,1000,2500,3000,200,i2,DOWN,CALU1 +S 2000,1000,2000,3000,200,i3,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 4500,1000,4500,4000,200,nq,DOWN,CALU1 +S 4500,1000,4500,4000,200,*,UP,ALU1 +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 2700,400,2700,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 600,1400,600,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2700,3300,2700,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 4000,2000,4800,2000,300,*,RIGHT,POLY +S 3900,500,3900,1000,200,*,DOWN,ALU1 +S 5100,500,5100,1000,200,*,DOWN,ALU1 +S 5100,3000,5100,4500,200,*,DOWN,ALU1 +S 3900,4000,3900,4500,200,*,DOWN,ALU1 +S 3600,2500,3800,2500,300,*,RIGHT,POLY +S 3300,2000,4000,2000,100,*,RIGHT,ALU1 +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3800,2500,3800,3500,100,*,DOWN,ALU1 +S 900,3500,3800,3500,100,*,RIGHT,ALU1 +S 2500,1000,2500,3000,100,*,DOWN,ALU1 +S 2000,1000,2000,3000,100,*,DOWN,ALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 3900,300,3900,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 5100,300,5100,1200,300,*,UP,NDIF +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 3300,2800,3300,3700,300,*,DOWN,PDIF +S 3300,800,3300,1200,300,*,UP,NDIF +S 3300,1000,3300,3000,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 300,4700,1500,4700,300,*,RIGHT,NTIE +S 900,300,2100,300,300,*,LEFT,PTIE +V 1500,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 3300,4700,CONT_BODY_N,* +V 4000,2000,CONT_POLY,* +V 5100,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 3300,3000,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 3900,4000,CONT_DIF_P,* +V 3800,2500,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 3900,500,CONT_DIF_N,* +V 5100,500,CONT_DIF_N,* +V 3300,300,CONT_BODY_P,* +V 4500,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 900,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 4500,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a22_x4.sym b/alliance/src/cells/src/sxlib/noa2a22_x4.sym new file mode 100644 index 00000000..aac4b28c Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa2a22_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/noa2a22_x4.vbe b/alliance/src/cells/src/sxlib/noa2a22_x4.vbe new file mode 100644 index 00000000..93e31d34 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 562; + CONSTANT tphl_i1_nq : NATURAL := 646; + CONSTANT tplh_i3_nq : NATURAL := 677; + CONSTANT tphl_i2_nq : NATURAL := 701; + CONSTANT tplh_i2_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 714; + CONSTANT tplh_i0_nq : NATURAL := 745; + CONSTANT tphl_i3_nq : NATURAL := 805; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa2a22_x4.vhd b/alliance/src/cells/src/sxlib/noa2a22_x4.vhd new file mode 100644 index 00000000..73870fd0 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a22_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a22_x4; + +ARCHITECTURE RTL OF noa2a22_x4 IS +BEGIN + nq <= NOT(((i0 AND i1) OR (i2 AND i3))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa2a2a23_x1.al b/alliance/src/cells/src/sxlib/noa2a2a23_x1.al new file mode 100644 index 00000000..c68647d7 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a23_x1.al @@ -0,0 +1,52 @@ +V ALLIANCE : 6 +H noa2a2a23_x1,L,30/10/99 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,14 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,12 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,5,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00012 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,12,13,6,0,0.75,0.75,13.3,13.3,13.2,11.25,tr_00008 +T P,0.35,5.9,6,14,12,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00007 +T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00006 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,2.9,1,13,11,0,0.75,0.75,7.3,7.3,13.2,2.25,tr_00004 +T N,0.35,2.9,11,14,2,0,0.75,0.75,7.3,7.3,12,2.25,tr_00003 +T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00002 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00001 +S 14,EXTERNAL,i1 +Q 0.0026959 +S 13,EXTERNAL,i0 +Q 0.00232574 +S 12,EXTERNAL,vdd +Q 0.00651445 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i5 +Q 0.00276531 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i3 +Q 0.00262649 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00198726 +S 5,INTERNAL +Q 0.00199441 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,nq +Q 0.00458289 +S 1,EXTERNAL,vss +Q 0.00575064 +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a2a23_x1.ap b/alliance/src/cells/src/sxlib/noa2a2a23_x1.ap new file mode 100644 index 00000000..a7d59c4a --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a23_x1.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H noa2a2a23_x1,P,30/ 8/2000,100 +A 0,0,5000,5000 +R 1000,2000,ref_ref,i5_20 +R 1000,2500,ref_ref,i5_25 +R 1000,3000,ref_ref,i5_30 +R 1000,1500,ref_ref,i5_15 +R 2000,1500,ref_ref,i3_15 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2000,2000,ref_ref,i3_20 +R 1500,1500,ref_ref,i4_15 +R 1500,2000,ref_ref,i4_20 +R 1500,2500,ref_ref,i4_25 +R 500,2500,ref_ref,nq_25 +R 500,2000,ref_ref,nq_20 +R 500,1500,ref_ref,nq_15 +R 500,3500,ref_ref,nq_35 +R 500,3000,ref_ref,nq_30 +R 4000,2000,ref_ref,i1_20 +R 4500,2500,ref_ref,i0_25 +R 4500,2000,ref_ref,i0_20 +R 4500,1500,ref_ref,i0_15 +R 4500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i1_30 +R 4000,2500,ref_ref,i1_25 +R 4000,1500,ref_ref,i1_15 +R 500,1000,ref_ref,nq_10 +R 1500,3000,ref_ref,i4_30 +R 1500,3500,ref_ref,i4_35 +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 4500,1500,4500,3000,200,i0,DOWN,CALU1 +S 4000,1500,4000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3500,200,nq,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 4700,300,4700,1000,200,*,DOWN,ALU1 +S 4400,1400,4400,2600,100,*,DOWN,POLY +S 4400,100,4400,1400,100,*,UP,NTRANS +S 4400,2600,4400,4900,100,*,UP,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3800,2600,3800,4900,100,*,UP,PTRANS +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 900,1400,900,2600,100,*,DOWN,POLY +S 500,950,500,3550,200,*,DOWN,ALU1 +S 450,3500,900,3500,200,*,RIGHT,ALU1 +S 3500,4000,3500,4700,200,*,UP,ALU1 +S 2100,3500,4100,3500,100,*,RIGHT,ALU1 +S 4100,3500,4100,4000,100,*,UP,ALU1 +S 4700,2800,4700,4700,300,*,UP,PDIF +S 4700,3500,4700,4600,200,*,DOWN,ALU1 +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4700,300,4700,1200,300,*,DOWN,NDIF +S 4000,1400,4000,2500,100,*,UP,POLY +S 3800,2500,4000,2500,100,*,LEFT,POLY +S 3800,2500,3800,2700,100,*,UP,POLY +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 800,100,800,1400,100,*,UP,NTRANS +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,1400,900,1400,100,*,LEFT,POLY +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 2700,2800,2700,4100,300,*,UP,PDIF +S 3500,2800,3500,4100,300,*,UP,PDIF +S 450,1000,3700,1000,200,*,LEFT,ALU1 +V 1500,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 3900,2500,CONT_POLY,* +V 4700,1000,CONT_DIF_N,* +V 4100,4000,CONT_DIF_P,* +V 4700,4000,CONT_DIF_P,* +V 3100,4600,CONT_BODY_N,* +V 2500,2500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 3500,4000,CONT_DIF_P,* +V 4700,4500,CONT_DIF_P,* +V 4700,3500,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 4700,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 3100,400,CONT_BODY_P,* +V 4500,2500,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a2a23_x1.sym b/alliance/src/cells/src/sxlib/noa2a2a23_x1.sym new file mode 100644 index 00000000..87e8c14f Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa2a2a23_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/noa2a2a23_x1.vbe b/alliance/src/cells/src/sxlib/noa2a2a23_x1.vbe new file mode 100644 index 00000000..2d90886a --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a23_x1.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT rup_i3_nq : NATURAL := 4690; + CONSTANT rup_i4_nq : NATURAL := 4690; + CONSTANT rup_i5_nq : NATURAL := 4690; + CONSTANT tphl_i5_nq : NATURAL := 178; + CONSTANT tphl_i4_nq : NATURAL := 250; + CONSTANT tphl_i2_nq : NATURAL := 307; + CONSTANT tplh_i1_nq : NATURAL := 388; + CONSTANT tphl_i3_nq : NATURAL := 398; + CONSTANT tplh_i4_nq : NATURAL := 416; + CONSTANT tplh_i0_nq : NATURAL := 425; + CONSTANT tplh_i3_nq : NATURAL := 438; + CONSTANT tplh_i5_nq : NATURAL := 464; + CONSTANT tplh_i2_nq : NATURAL := 479; + CONSTANT tphl_i0_nq : NATURAL := 525; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa2a2a23_x1.vhd b/alliance/src/cells/src/sxlib/noa2a2a23_x1.vhd new file mode 100644 index 00000000..13c08812 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a23_x1.vhd @@ -0,0 +1,24 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a2a23_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a2a23_x1; + +ARCHITECTURE RTL OF noa2a2a23_x1 IS +BEGIN + nq <= NOT((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa2a2a23_x4.al b/alliance/src/cells/src/sxlib/noa2a2a23_x4.al new file mode 100644 index 00000000..5bd111a2 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a23_x4.al @@ -0,0 +1,62 @@ +V ALLIANCE : 6 +H noa2a2a23_x4,L,30/10/99 +C i0,IN,EXTERNAL,15 +C i1,IN,EXTERNAL,16 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,10 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,11,4,14,0,0.75,0.75,7.3,7.3,17.7,9.75,tr_00018 +T P,0.35,5.9,5,16,14,0,0.75,0.75,13.3,13.3,10.5,11.25,tr_00017 +T P,0.35,5.9,13,11,14,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00016 +T P,0.35,5.9,14,11,13,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00015 +T P,0.35,5.9,14,15,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00014 +T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00013 +T P,0.35,5.9,6,9,5,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00012 +T P,0.35,5.9,4,8,6,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011 +T P,0.35,5.9,6,7,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T N,0.35,1.4,1,4,11,0,0.75,0.75,4.3,4.3,17.7,3,tr_00009 +T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00008 +T N,0.35,2.9,12,16,4,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00007 +T N,0.35,2.9,13,11,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00006 +T N,0.35,2.9,13,11,1,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00005 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,10,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 16,EXTERNAL,i1 +Q 0.00247612 +S 15,EXTERNAL,i0 +Q 0.00232574 +S 14,EXTERNAL,vdd +Q 0.00830269 +S 13,EXTERNAL,nq +Q 0.0023502 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0.0053368 +S 10,EXTERNAL,i3 +Q 0.00262649 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i5 +Q 0.0027653 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00199441 +S 5,INTERNAL +Q 0.00181815 +S 4,INTERNAL +Q 0.00716684 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00624627 +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a2a23_x4.ap b/alliance/src/cells/src/sxlib/noa2a2a23_x4.ap new file mode 100644 index 00000000..2f058c38 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a23_x4.ap @@ -0,0 +1,156 @@ +V ALLIANCE : 6 +H noa2a2a23_x4,P, 6/ 9/2000,100 +A 0,0,6500,5000 +R 1000,2000,ref_ref,i5_20 +R 1000,2500,ref_ref,i5_25 +R 1000,3000,ref_ref,i5_30 +R 1000,1500,ref_ref,i5_15 +R 2000,1500,ref_ref,i3_15 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2000,2000,ref_ref,i3_20 +R 1500,1500,ref_ref,i4_15 +R 1500,2000,ref_ref,i4_20 +R 1500,2500,ref_ref,i4_25 +R 1500,3000,ref_ref,i4_30 +R 1500,3500,ref_ref,i4_35 +R 4000,2000,ref_ref,i0_20 +R 4000,2500,ref_ref,i0_25 +R 3500,2000,ref_ref,i1_20 +R 3500,1500,ref_ref,i1_15 +R 3500,2500,ref_ref,i1_25 +R 3500,3000,ref_ref,i1_30 +R 4000,3000,ref_ref,i0_30 +R 4000,1500,ref_ref,i0_15 +R 5000,2000,ref_ref,nq_20 +R 5000,2500,ref_ref,nq_25 +R 5000,3000,ref_ref,nq_30 +R 5000,3500,ref_ref,nq_35 +R 5000,1500,ref_ref,nq_15 +R 5000,4000,ref_ref,nq_40 +S 5700,1500,5900,1500,300,*,RIGHT,POLY +S 5300,2000,5500,2000,300,*,LEFT,POLY +S 5000,300,5000,1500,300,*,DOWN,NDIF +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 900,1400,900,2600,100,*,DOWN,POLY +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 800,100,800,1400,100,*,UP,NTRANS +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,1400,900,1400,100,*,LEFT,POLY +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 4400,3500,4400,4600,200,*,DOWN,ALU1 +S 3800,3500,3800,4000,100,*,UP,ALU1 +S 5600,3500,5600,4600,200,*,DOWN,ALU1 +S 3500,1400,3500,2500,100,*,UP,POLY +S 4100,1400,4100,2600,100,*,DOWN,POLY +S 3500,1400,3700,1400,100,*,LEFT,POLY +S 4700,1400,4700,2600,100,*,DOWN,POLY +S 5300,1400,5300,2600,100,*,DOWN,POLY +S 5300,100,5300,1400,100,*,DOWN,NTRANS +S 4700,100,4700,1400,100,*,UP,NTRANS +S 5600,300,5600,1200,300,*,DOWN,NDIF +S 4400,300,4400,1200,300,*,DOWN,NDIF +S 3400,300,3400,1200,300,*,DOWN,NDIF +S 3700,100,3700,1400,100,*,UP,NTRANS +S 4100,100,4100,1400,100,*,UP,NTRANS +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 3800,2800,3800,4700,300,*,UP,PDIF +S 4400,2800,4400,4700,300,*,UP,PDIF +S 5600,2800,5600,4700,300,*,UP,PDIF +S 5000,2800,5000,4700,300,*,UP,PDIF +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 3500,2600,3500,4900,100,*,UP,PTRANS +S 5900,600,5900,1400,100,*,DOWN,NTRANS +S 5900,2600,5900,3900,100,*,UP,PTRANS +S 6200,800,6200,1200,300,*,DOWN,NDIF +S 6200,2800,6200,3700,300,*,UP,PDIF +S 2700,2800,2700,4000,300,*,UP,PDIF +S 3250,2800,3250,4600,200,*,DOWN,PDIF +S 5000,1450,5000,4050,200,*,DOWN,ALU1 +S 5900,1400,5900,2600,100,*,UP,POLY +S 4700,2000,5300,2000,100,*,RIGHT,POLY +S 500,1000,5700,1000,100,*,RIGHT,ALU1 +S 5700,1000,5700,1500,100,*,UP,ALU1 +S 5500,2000,6200,2000,100,*,RIGHT,ALU1 +S 6200,1000,6200,3500,100,*,DOWN,ALU1 +S 2100,3500,3800,3500,100,*,RIGHT,ALU1 +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 4000,1500,4000,3000,200,i0,DOWN,CALU1 +S 3500,1500,3500,3000,200,i1,DOWN,CALU1 +S 5000,1500,5000,4000,200,nq,DOWN,CALU1 +V 5000,1500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2500,2500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2500,500,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 4000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 5600,500,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 4400,500,CONT_DIF_N,* +V 5000,3000,CONT_DIF_P,* +V 5600,4000,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 5600,3500,CONT_DIF_P,* +V 3800,4000,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 4400,4500,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 5000,3500,CONT_DIF_P,* +V 6200,1000,CONT_DIF_N,* +V 6200,3000,CONT_DIF_P,* +V 6200,3500,CONT_DIF_P,* +V 6200,4600,CONT_BODY_N,* +V 6200,300,CONT_BODY_P,* +V 3200,4600,CONT_DIF_P,* +V 5500,2000,CONT_POLY,* +V 5700,1500,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a2a23_x4.sym b/alliance/src/cells/src/sxlib/noa2a2a23_x4.sym new file mode 100644 index 00000000..2fd94d25 Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa2a2a23_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/noa2a2a23_x4.vbe b/alliance/src/cells/src/sxlib/noa2a2a23_x4.vbe new file mode 100644 index 00000000..32820940 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT tphl_i5_nq : NATURAL := 496; + CONSTANT tphl_i4_nq : NATURAL := 574; + CONSTANT tphl_i2_nq : NATURAL := 620; + CONSTANT tphl_i3_nq : NATURAL := 716; + CONSTANT tplh_i1_nq : NATURAL := 778; + CONSTANT tplh_i0_nq : NATURAL := 814; + CONSTANT tplh_i4_nq : NATURAL := 819; + CONSTANT tplh_i3_nq : NATURAL := 833; + CONSTANT tphl_i0_nq : NATURAL := 834; + CONSTANT tplh_i5_nq : NATURAL := 865; + CONSTANT tplh_i2_nq : NATURAL := 873; + CONSTANT tphl_i1_nq : NATURAL := 955; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1600 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa2a2a23_x4.vhd b/alliance/src/cells/src/sxlib/noa2a2a23_x4.vhd new file mode 100644 index 00000000..c7141298 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a23_x4.vhd @@ -0,0 +1,24 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a2a23_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a2a23_x4; + +ARCHITECTURE RTL OF noa2a2a23_x4 IS +BEGIN + nq <= NOT((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.al b/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.al new file mode 100644 index 00000000..2221c84b --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.al @@ -0,0 +1,66 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x1,L,30/10/99 +C i0,IN,EXTERNAL,18 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,16 +C i3,IN,EXTERNAL,15 +C i4,IN,EXTERNAL,10 +C i5,IN,EXTERNAL,9 +C i6,IN,EXTERNAL,8 +C i7,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,13,15,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00016 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00015 +T P,0.35,5.9,3,7,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00014 +T P,0.35,5.9,14,18,13,0,0.75,0.75,13.3,13.3,18,11.25,tr_00013 +T P,0.35,5.9,6,16,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00012 +T P,0.35,5.9,6,10,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00011 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,5,8,3,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00008 +T N,0.35,2.9,11,15,3,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00007 +T N,0.35,2.9,3,8,4,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,2,16,11,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005 +T N,0.35,2.9,2,18,12,0,0.75,0.75,7.3,7.3,18,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,12,17,3,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00002 +T N,0.35,2.9,4,7,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 18,EXTERNAL,i0 +Q 0.00260759 +S 17,EXTERNAL,i1 +Q 0.00260759 +S 16,EXTERNAL,i2 +Q 0.00232574 +S 15,EXTERNAL,i3 +Q 0.00232574 +S 14,EXTERNAL,vdd +Q 0.00670525 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i4 +Q 0.00232574 +S 9,EXTERNAL,i5 +Q 0.00232574 +S 8,EXTERNAL,i6 +Q 0.00269068 +S 7,EXTERNAL,i7 +Q 0.00260759 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,nq +Q 0.00490604 +S 2,EXTERNAL,vss +Q 0.00711654 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.ap b/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.ap new file mode 100644 index 00000000..eb9e15df --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.ap @@ -0,0 +1,157 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x1,P, 6/ 9/2000,100 +A 0,0,7000,5000 +R 6000,3500,ref_ref,i0_35 +R 6000,3000,ref_ref,i0_30 +R 6000,2500,ref_ref,i0_25 +R 6000,2000,ref_ref,i0_20 +R 6000,1500,ref_ref,i0_15 +R 5500,3500,ref_ref,i1_35 +R 5500,3000,ref_ref,i1_30 +R 5500,2500,ref_ref,i1_25 +R 5500,2000,ref_ref,i1_20 +R 5500,1500,ref_ref,i1_15 +R 4000,3000,ref_ref,i2_30 +R 4000,2500,ref_ref,i2_25 +R 4000,2000,ref_ref,i2_20 +R 4000,1500,ref_ref,i2_15 +R 3500,3000,ref_ref,i3_30 +R 3500,2500,ref_ref,i3_25 +R 3500,2000,ref_ref,i3_20 +R 3500,1500,ref_ref,i3_15 +R 3000,3000,ref_ref,i4_30 +R 3000,2500,ref_ref,i4_25 +R 3000,2000,ref_ref,i4_20 +R 3000,1500,ref_ref,i4_15 +R 2500,3000,ref_ref,i5_30 +R 2500,2500,ref_ref,i5_25 +R 2500,2000,ref_ref,i5_20 +R 2500,1500,ref_ref,i5_15 +R 1500,3000,ref_ref,i6_30 +R 1500,2500,ref_ref,i6_25 +R 1500,2000,ref_ref,i6_20 +R 1500,1500,ref_ref,i6_15 +R 1000,3500,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_30 +R 1000,2500,ref_ref,nq_25 +R 1000,2000,ref_ref,nq_20 +R 1000,1500,ref_ref,nq_15 +R 1000,1000,ref_ref,nq_10 +R 500,3000,ref_ref,i7_30 +R 500,2500,ref_ref,i7_25 +R 500,2000,ref_ref,i7_20 +R 500,1500,ref_ref,i7_15 +R 500,1000,ref_ref,i7_10 +S 4000,2500,4200,2500,300,*,RIGHT,POLY +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 5400,100,5400,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 6000,100,6000,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 5700,300,5700,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 4500,300,4500,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 5100,300,5100,1200,300,*,DOWN,NDIF +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 6000,1400,6000,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 6300,300,6300,1000,200,*,DOWN,ALU1 +S 0,3900,7000,3900,2400,*,RIGHT,NWELL +S 0,300,7000,300,600,vss,RIGHT,CALU1 +S 0,4700,7000,4700,600,vdd,RIGHT,CALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4500,2800,4500,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 6000,2600,6000,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,UP,PDIF +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 6300,2800,6300,4200,300,*,UP,PDIF +S 6300,4000,6300,4600,200,*,DOWN,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 6000,1500,6000,3500,100,*,UP,ALU1 +S 5500,1500,5500,3500,100,*,UP,ALU1 +S 5000,4000,5700,4000,100,*,LEFT,ALU1 +S 5000,3500,5000,4000,100,*,DOWN,ALU1 +S 3900,3500,5000,3500,100,*,LEFT,ALU1 +S 950,1000,5100,1000,200,*,LEFT,ALU1 +S 1000,950,1000,3550,200,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 6000,1500,6000,3500,200,i0,DOWN,CALU1 +S 5500,1500,5500,3500,200,i1,DOWN,CALU1 +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 1000,1000,1000,3500,200,nq,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +V 3300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 6700,4700,CONT_BODY_N,* +V 6300,4000,CONT_DIF_P,* +V 6300,1000,CONT_DIF_N,* +V 6700,300,CONT_BODY_P,* +V 500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 6000,2500,CONT_POLY,* +V 3300,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.sym b/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.sym new file mode 100644 index 00000000..85b0df92 Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.vbe b/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.vbe new file mode 100644 index 00000000..ed253ca4 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rdown_i6_nq : NATURAL := 2850; + CONSTANT rdown_i7_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT rup_i4_nq : NATURAL := 6190; + CONSTANT rup_i5_nq : NATURAL := 6190; + CONSTANT rup_i6_nq : NATURAL := 6190; + CONSTANT rup_i7_nq : NATURAL := 6190; + CONSTANT tphl_i7_nq : NATURAL := 200; + CONSTANT tphl_i6_nq : NATURAL := 270; + CONSTANT tphl_i5_nq : NATURAL := 329; + CONSTANT tphl_i4_nq : NATURAL := 419; + CONSTANT tplh_i6_nq : NATURAL := 535; + CONSTANT tphl_i2_nq : NATURAL := 550; + CONSTANT tplh_i1_nq : NATURAL := 562; + CONSTANT tplh_i7_nq : NATURAL := 591; + CONSTANT tplh_i0_nq : NATURAL := 606; + CONSTANT tplh_i4_nq : NATURAL := 613; + CONSTANT tplh_i3_nq : NATURAL := 616; + CONSTANT tphl_i0_nq : NATURAL := 649; + CONSTANT tplh_i2_nq : NATURAL := 662; + CONSTANT tplh_i5_nq : NATURAL := 662; + CONSTANT tphl_i3_nq : NATURAL := 667; + CONSTANT tphl_i1_nq : NATURAL := 775; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x1" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.vhd b/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.vhd new file mode 100644 index 00000000..dbac8f6e --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a2a24_x1.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a2a2a24_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + i7 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a2a2a24_x1; + +ARCHITECTURE RTL OF noa2a2a2a24_x1 IS +BEGIN + nq <= NOT(((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.al b/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.al new file mode 100644 index 00000000..63a60e34 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.al @@ -0,0 +1,76 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x4,L,30/10/99 +C i0,IN,EXTERNAL,20 +C i1,IN,EXTERNAL,15 +C i2,IN,EXTERNAL,16 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C i6,IN,EXTERNAL,9 +C i7,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,19 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,18,2,14,0,0.75,0.75,7.3,7.3,23.7,9.75,tr_00022 +T P,0.35,5.9,13,15,14,0,0.75,0.75,13.3,13.3,16.5,11.25,tr_00021 +T P,0.35,5.9,14,18,19,0,0.75,0.75,13.3,13.3,21.9,11.25,tr_00020 +T P,0.35,5.9,19,18,14,0,0.75,0.75,13.3,13.3,20.1,11.25,tr_00019 +T P,0.35,5.9,14,20,13,0,0.75,0.75,13.3,13.3,18.3,11.25,tr_00018 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00017 +T P,0.35,5.9,5,8,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00016 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00015 +T P,0.35,5.9,6,16,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00014 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00013 +T P,0.35,5.9,13,17,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00012 +T N,0.35,1.4,3,2,18,0,0.75,0.75,4.3,4.3,23.7,3,tr_00011 +T N,0.35,2.9,3,20,12,0,0.75,0.75,7.3,7.3,18.3,2.25,tr_00010 +T N,0.35,2.9,19,18,3,0,0.75,0.75,7.3,7.3,21.9,2.25,tr_00009 +T N,0.35,2.9,12,15,2,0,0.75,0.75,7.3,7.3,17.1,2.25,tr_00008 +T N,0.35,2.9,19,18,3,0,0.75,0.75,7.3,7.3,20.1,2.25,tr_00007 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00006 +T N,0.35,2.9,2,9,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,2.9,11,17,2,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00004 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003 +T N,0.35,2.9,3,16,11,0,0.75,0.75,7.3,7.3,12,2.25,tr_00002 +T N,0.35,2.9,4,8,3,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00001 +S 20,EXTERNAL,i0 +Q 0.00284261 +S 19,EXTERNAL,nq +Q 0.0023502 +S 18,INTERNAL +Q 0.00547561 +S 17,EXTERNAL,i3 +Q 0.00232574 +S 16,EXTERNAL,i2 +Q 0.00254552 +S 15,EXTERNAL,i1 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00984486 +S 13,INTERNAL +Q 0.00193089 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i7 +Q 0.00260759 +S 9,EXTERNAL,i6 +Q 0.00269068 +S 8,EXTERNAL,i5 +Q 0.00232574 +S 7,EXTERNAL,i4 +Q 0.00232574 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00778843 +S 2,INTERNAL +Q 0.00816047 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.ap b/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.ap new file mode 100644 index 00000000..54f0b8c1 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.ap @@ -0,0 +1,194 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x4,P, 6/ 9/2000,100 +A 0,0,8500,5000 +R 6500,3500,ref_ref,i0_35 +R 5500,2000,ref_ref,i1_20 +R 5500,2500,ref_ref,i1_25 +R 5500,3000,ref_ref,i1_30 +R 5500,1500,ref_ref,i1_15 +R 6500,1500,ref_ref,i0_15 +R 6500,2000,ref_ref,i0_20 +R 6500,2500,ref_ref,i0_25 +R 6500,3000,ref_ref,i0_30 +R 7000,4000,ref_ref,nq_40 +R 7000,2000,ref_ref,nq_20 +R 7000,1500,ref_ref,nq_15 +R 7000,3500,ref_ref,nq_35 +R 7000,3000,ref_ref,nq_30 +R 7000,2500,ref_ref,nq_25 +R 500,1000,ref_ref,i7_10 +R 500,1500,ref_ref,i7_15 +R 500,2000,ref_ref,i7_20 +R 500,2500,ref_ref,i7_25 +R 500,3000,ref_ref,i7_30 +R 1500,1500,ref_ref,i6_15 +R 1500,2000,ref_ref,i6_20 +R 1500,2500,ref_ref,i6_25 +R 1500,3000,ref_ref,i6_30 +R 2500,1500,ref_ref,i5_15 +R 2500,2000,ref_ref,i5_20 +R 2500,2500,ref_ref,i5_25 +R 2500,3000,ref_ref,i5_30 +R 3000,1500,ref_ref,i4_15 +R 3000,2000,ref_ref,i4_20 +R 3000,2500,ref_ref,i4_25 +R 3000,3000,ref_ref,i4_30 +R 3500,1500,ref_ref,i3_15 +R 3500,2000,ref_ref,i3_20 +R 3500,2500,ref_ref,i3_25 +R 3500,3000,ref_ref,i3_30 +R 4000,1500,ref_ref,i2_15 +R 4000,2000,ref_ref,i2_20 +R 4000,2500,ref_ref,i2_25 +R 4000,3000,ref_ref,i2_30 +S 7700,1500,7900,1500,300,*,RIGHT,POLY +S 7300,2000,7500,2000,300,*,LEFT,POLY +S 7000,300,7000,1500,300,*,DOWN,NDIF +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3300,2800,3300,4700,300,*,UP,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +S 0,300,8500,300,600,vss,RIGHT,CALU1 +S 0,3900,8500,3900,2400,*,RIGHT,NWELL +S 0,4700,8500,4700,600,vdd,RIGHT,CALU1 +S 4500,2800,4500,4700,300,*,UP,PDIF +S 7600,3500,7600,4600,200,*,DOWN,ALU1 +S 5200,4000,5200,4600,200,*,DOWN,ALU1 +S 6400,4000,6400,4600,200,*,DOWN,ALU1 +S 5800,3500,5800,4000,100,*,UP,ALU1 +S 7300,1400,7300,2600,100,*,DOWN,POLY +S 6700,1400,6700,2600,100,*,DOWN,POLY +S 6700,100,6700,1400,100,*,UP,NTRANS +S 5700,100,5700,1400,100,*,UP,NTRANS +S 5400,300,5400,1200,300,*,DOWN,NDIF +S 7300,100,7300,1400,100,*,DOWN,NTRANS +S 6400,300,6400,1200,300,*,DOWN,NDIF +S 7600,300,7600,1200,300,*,DOWN,NDIF +S 6100,100,6100,1400,100,*,UP,NTRANS +S 6100,2600,6100,4900,100,*,UP,PTRANS +S 5800,2800,5800,4700,300,*,UP,PDIF +S 7000,2800,7000,4700,300,*,UP,PDIF +S 7600,2800,7600,4700,300,*,UP,PDIF +S 6700,2600,6700,4900,100,*,UP,PTRANS +S 6400,2800,6400,4700,300,*,UP,PDIF +S 7300,2600,7300,4900,100,*,UP,PTRANS +S 5500,2600,5500,4900,100,*,UP,PTRANS +S 5200,2800,5200,4700,300,*,UP,PDIF +S 6500,1500,6500,3500,100,*,UP,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 1000,1000,5400,1000,100,*,RIGHT,ALU1 +S 7900,600,7900,1400,100,*,DOWN,NTRANS +S 7900,2600,7900,3900,100,*,UP,PTRANS +S 8200,800,8200,1200,300,*,UP,NDIF +S 8200,2800,8200,3700,300,*,UP,PDIF +S 8200,1000,8200,3500,100,*,UP,ALU1 +S 7000,1450,7000,4050,200,*,DOWN,ALU1 +S 7900,1400,7900,2600,100,*,UP,POLY +S 5400,1000,7700,1000,100,*,RIGHT,ALU1 +S 7700,1000,7700,1500,100,*,UP,ALU1 +S 3900,3500,5800,3500,100,*,RIGHT,ALU1 +S 7500,2000,8200,2000,100,*,RIGHT,ALU1 +S 6200,2000,6400,2000,200,*,RIGHT,ALU1 +S 6700,2000,7500,2000,100,*,LEFT,POLY +S 5500,1400,5700,1400,100,*,LEFT,POLY +S 5500,1400,5500,2600,100,*,UP,POLY +S 6100,1400,6100,2600,100,*,DOWN,POLY +S 6500,1500,6500,3500,200,i0,DOWN,CALU1 +S 5500,1500,5500,3000,200,i1,DOWN,CALU1 +S 7000,1500,7000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +V 7000,1500,CONT_DIF_N,* +V 2300,500,CONT_DIF_N,* +V 4300,500,CONT_DIF_N,* +V 3900,3500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 4000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 8200,4600,CONT_BODY_N,* +V 5400,1000,CONT_DIF_N,* +V 6400,500,CONT_DIF_N,* +V 7600,500,CONT_DIF_N,* +V 7000,3500,CONT_DIF_P,* +V 6400,4500,CONT_DIF_P,* +V 7000,4000,CONT_DIF_P,* +V 6400,4000,CONT_DIF_P,* +V 7600,3500,CONT_DIF_P,* +V 7600,4500,CONT_DIF_P,* +V 5200,4000,CONT_DIF_P,* +V 5800,4000,CONT_DIF_P,* +V 7600,4000,CONT_DIF_P,* +V 7000,3000,CONT_DIF_P,* +V 5200,4500,CONT_DIF_P,* +V 8200,300,CONT_BODY_P,* +V 8200,2900,CONT_DIF_P,* +V 8200,3500,CONT_DIF_P,* +V 8200,1000,CONT_DIF_N,* +V 7700,1500,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 6200,2000,CONT_POLY,* +V 5500,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.sym b/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.sym new file mode 100644 index 00000000..7df574ee Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.vbe b/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.vbe new file mode 100644 index 00000000..2499cd71 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4250; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rdown_i7_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT rup_i7_nq : NATURAL := 890; + CONSTANT tphl_i7_nq : NATURAL := 525; + CONSTANT tphl_i6_nq : NATURAL := 606; + CONSTANT tphl_i5_nq : NATURAL := 649; + CONSTANT tphl_i4_nq : NATURAL := 748; + CONSTANT tphl_i2_nq : NATURAL := 867; + CONSTANT tphl_i0_nq : NATURAL := 966; + CONSTANT tphl_i3_nq : NATURAL := 990; + CONSTANT tplh_i6_nq : NATURAL := 999; + CONSTANT tplh_i1_nq : NATURAL := 1005; + CONSTANT tplh_i0_nq : NATURAL := 1049; + CONSTANT tplh_i7_nq : NATURAL := 1052; + CONSTANT tplh_i3_nq : NATURAL := 1061; + CONSTANT tplh_i4_nq : NATURAL := 1061; + CONSTANT tphl_i1_nq : NATURAL := 1097; + CONSTANT tplh_i2_nq : NATURAL := 1106; + CONSTANT tplh_i5_nq : NATURAL := 1109; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x4" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1700 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.vhd b/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.vhd new file mode 100644 index 00000000..e349c824 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2a2a2a24_x4.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a2a2a24_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + i7 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a2a2a24_x4; + +ARCHITECTURE RTL OF noa2a2a2a24_x4 IS +BEGIN + nq <= NOT(((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa2ao222_x1.al b/alliance/src/cells/src/sxlib/noa2ao222_x1.al new file mode 100644 index 00000000..a39f8b03 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2ao222_x1.al @@ -0,0 +1,45 @@ +V ALLIANCE : 6 +H noa2ao222_x1,L,30/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00010 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00009 +T P,0.35,4.25,7,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00008 +T P,0.35,4.25,6,11,7,0,0.75,0.75,10,10,3.6,10.42,tr_00007 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00006 +T N,0.35,2.6,3,8,1,0,0.75,0.75,6.7,6.7,8.7,3.9,tr_00005 +T N,0.35,2.6,4,12,1,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00004 +T N,0.35,2.6,1,9,3,0,0.75,0.75,6.7,6.7,6.9,3.9,tr_00003 +T N,0.35,2.6,3,10,2,0,0.75,0.75,6.7,6.7,5.1,3.9,tr_00002 +T N,0.35,2.6,2,11,4,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00001 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL +Q 0.00212909 +S 8,EXTERNAL +Q 0.00226057 +S 7,EXTERNAL,vdd +Q 0.00366862 +S 6,INTERNAL +Q 0.00227626 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00114171 +S 2,EXTERNAL,nq +Q 0.0026146 +S 1,EXTERNAL,vss +Q 0.00419742 +EOF diff --git a/alliance/src/cells/src/sxlib/noa2ao222_x1.ap b/alliance/src/cells/src/sxlib/noa2ao222_x1.ap new file mode 100644 index 00000000..ba84f0ff --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2ao222_x1.ap @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H noa2ao222_x1,P, 6/ 9/2000,100 +A 0,0,3500,5000 +R 3000,3500,ref_ref,i3_35 +R 3000,3000,ref_ref,i3_30 +R 3000,2500,ref_ref,i3_25 +R 3000,2000,ref_ref,i3_20 +R 3000,1500,ref_ref,i3_15 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 1500,1000,ref_ref,nq_10 +R 2000,1500,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_20 +R 2000,2500,ref_ref,nq_25 +R 2000,3000,ref_ref,nq_30 +R 2000,3500,ref_ref,nq_35 +R 1500,2000,ref_ref,i4_20 +R 1500,2500,ref_ref,i4_25 +R 1500,3000,ref_ref,i4_30 +R 1500,3500,ref_ref,i4_35 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +S 1500,2000,1700,2000,300,*,RIGHT,POLY +S 1500,1000,1500,1500,200,nq,DOWN,CALU1 +S 2000,1500,2000,3500,200,nq,DOWN,CALU1 +S 3000,1500,3000,3500,200,i3,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 1500,2000,1500,3500,200,i4,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 2000,1450,2000,3550,200,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 600,1900,600,2600,100,i0,UP,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 1500,2800,1500,4150,200,*,UP,PDIF +S 600,2600,600,4350,100,*,UP,PTRANS +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1450,1500,2050,1500,200,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 3000,1500,3000,3500,100,*,UP,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 2900,1900,2900,2600,100,i4,UP,POLY +S 2400,1900,2400,2600,100,i3,UP,POLY +S 1700,1900,1700,2600,100,i2,UP,POLY +S 1100,1900,1100,2600,100,i1,UP,POLY +S 2600,500,2600,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 300,500,300,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1500,950,1500,1500,200,*,UP,ALU1 +S 1400,900,1400,1700,200,*,UP,NDIF +S 2900,700,2900,1900,100,*,UP,NTRANS +S 3200,900,3200,1700,300,*,UP,NDIF +S 600,700,600,1900,100,*,UP,NTRANS +S 2300,700,2300,1900,100,*,UP,NTRANS +S 1700,700,1700,1900,100,*,UP,NTRANS +S 2000,900,2000,1700,200,*,UP,NDIF +S 1100,700,1100,1900,100,*,UP,NTRANS +S 1200,400,2000,400,300,*,RIGHT,PTIE +V 2100,3500,CONT_DIF_P,* +V 2600,500,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 1400,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 2000,400,CONT_BODY_P,* +V 1600,400,CONT_BODY_P,* +V 1200,400,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa2ao222_x1.vbe b/alliance/src/cells/src/sxlib/noa2ao222_x1.vbe new file mode 100644 index 00000000..034393fe --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2ao222_x1.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3210; + CONSTANT rdown_i1_nq : NATURAL := 3210; + CONSTANT rdown_i2_nq : NATURAL := 3210; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 5260; + CONSTANT rup_i1_nq : NATURAL := 5260; + CONSTANT rup_i2_nq : NATURAL := 5260; + CONSTANT rup_i3_nq : NATURAL := 5260; + CONSTANT rup_i4_nq : NATURAL := 3750; + CONSTANT tphl_i2_nq : NATURAL := 186; + CONSTANT tphl_i4_nq : NATURAL := 240; + CONSTANT tphl_i3_nq : NATURAL := 256; + CONSTANT tplh_i4_nq : NATURAL := 309; + CONSTANT tphl_i0_nq : NATURAL := 348; + CONSTANT tplh_i1_nq : NATURAL := 378; + CONSTANT tplh_i0_nq : NATURAL := 422; + CONSTANT tphl_i1_nq : NATURAL := 440; + CONSTANT tplh_i3_nq : NATURAL := 459; + CONSTANT tplh_i2_nq : NATURAL := 473; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x1; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa2ao222_x1.vhd b/alliance/src/cells/src/sxlib/noa2ao222_x1.vhd new file mode 100644 index 00000000..065e8073 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2ao222_x1.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2ao222_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2ao222_x1; + +ARCHITECTURE RTL OF noa2ao222_x1 IS +BEGIN + nq <= NOT(((i0 AND i1) OR ((i2 OR i3) AND i4))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa2ao222_x2.sym b/alliance/src/cells/src/sxlib/noa2ao222_x2.sym new file mode 100644 index 00000000..0f226fcc Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa2ao222_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/noa2ao222_x4.al b/alliance/src/cells/src/sxlib/noa2ao222_x4.al new file mode 100644 index 00000000..3af0440f --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2ao222_x4.al @@ -0,0 +1,55 @@ +V ALLIANCE : 6 +H noa2ao222_x4,L,30/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00016 +T P,0.35,5.9,5,9,1,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00015 +T P,0.35,4.25,7,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00014 +T P,0.35,4.25,6,11,7,0,0.75,0.75,10,10,3.6,10.42,tr_00013 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00012 +T P,0.35,5.9,14,13,7,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00011 +T P,0.35,2.9,7,1,13,0,0.75,0.75,7.3,7.3,12.3,9.75,tr_00010 +T P,0.35,5.9,7,13,14,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00009 +T N,0.35,1.7,3,10,1,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00008 +T N,0.35,2.6,4,12,2,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00007 +T N,0.35,2.6,1,11,4,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00006 +T N,0.35,1.7,3,8,2,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00005 +T N,0.35,1.7,2,9,3,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00004 +T N,0.35,1.4,13,1,2,0,0.75,0.75,4.3,4.3,12.3,4.5,tr_00003 +T N,0.35,2.9,14,13,2,0,0.75,0.75,7.3,7.3,15.9,3.75,tr_00002 +T N,0.35,2.9,2,13,14,0,0.75,0.75,7.3,7.3,14.1,3.75,tr_00001 +S 14,EXTERNAL,nq +Q 0.00276148 +S 13,INTERNAL +Q 0.00420824 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL +Q 0.00212909 +S 8,EXTERNAL +Q 0.00197871 +S 7,EXTERNAL,vdd +Q 0.00825499 +S 6,INTERNAL +Q 0.00227626 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00114171 +S 2,EXTERNAL,vss +Q 0.00913632 +S 1,INTERNAL +Q 0.00576981 +EOF diff --git a/alliance/src/cells/src/sxlib/noa2ao222_x4.ap b/alliance/src/cells/src/sxlib/noa2ao222_x4.ap new file mode 100644 index 00000000..7b30dfec --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2ao222_x4.ap @@ -0,0 +1,158 @@ +V ALLIANCE : 6 +H noa2ao222_x4,P, 6/ 9/2000,100 +A 0,0,6000,5000 +R 5000,4000,ref_ref,nq_40 +R 5000,2000,ref_ref,nq_20 +R 5000,2500,ref_ref,nq_25 +R 5000,3000,ref_ref,nq_30 +R 5000,1000,ref_ref,nq_10 +R 5000,3500,ref_ref,nq_35 +R 5000,1500,ref_ref,nq_15 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,2500,ref_ref,i4_25 +R 1500,2000,ref_ref,i4_20 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 3000,1500,ref_ref,i3_15 +R 3000,2000,ref_ref,i3_20 +R 3000,2500,ref_ref,i3_25 +R 3000,3000,ref_ref,i3_30 +S 4100,2500,4300,2500,300,*,LEFT,POLY +S 1500,2000,1700,2000,300,*,RIGHT,POLY +S 2100,3500,4300,3500,100,*,LEFT,ALU1 +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 4100,2600,4100,3900,100,*,UP,PTRANS +S 3800,2800,3800,3700,300,*,UP,PDIF +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 5600,2800,5600,4700,300,*,DOWN,PDIF +S 3800,1300,3800,1700,300,*,UP,NDIF +S 4700,600,4700,1900,100,*,DOWN,NTRANS +S 5000,800,5000,1700,300,*,UP,NDIF +S 4400,800,4400,1700,300,*,UP,NDIF +S 5300,600,5300,1900,100,*,DOWN,NTRANS +S 5600,800,5600,1700,300,*,UP,NDIF +S 4100,1100,4100,1900,100,*,DOWN,NTRANS +S 4100,1900,4100,2600,100,*,DOWN,POLY +S 4500,2000,5300,2000,300,*,RIGHT,POLY +S 4700,1900,4700,2600,100,*,UP,POLY +S 5300,1900,5300,2600,100,*,UP,POLY +S 4400,300,4400,1500,200,*,DOWN,ALU1 +S 4400,4000,4400,4700,200,*,UP,ALU1 +S 5600,3000,5600,4700,200,*,UP,ALU1 +S 3800,1500,3800,3000,100,*,UP,ALU1 +S 3800,2000,4500,2000,100,*,LEFT,ALU1 +S 4300,2500,4300,3500,100,*,UP,ALU1 +S 5600,300,5600,1500,200,*,DOWN,ALU1 +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 2000,900,2000,1700,200,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 1400,900,1400,1700,200,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 300,500,300,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 2600,500,2600,1700,300,*,UP,NDIF +S 1100,1900,1100,2600,100,i1,UP,POLY +S 1700,1900,1700,2600,100,i2,UP,POLY +S 2400,1900,2400,2600,100,i3,UP,POLY +S 2900,1900,2900,2600,100,i4,UP,POLY +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 600,2600,600,4350,100,*,UP,PTRANS +S 1500,2800,1500,4150,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 2700,2800,2700,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,1900,600,2600,100,i0,UP,POLY +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 5000,1000,5000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,2000,1500,3500,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 3000,1500,3000,3000,200,i3,DOWN,CALU1 +V 5000,3000,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 3800,3000,CONT_DIF_P,* +V 3800,4600,CONT_BODY_N,* +V 5600,3000,CONT_DIF_P,* +V 5000,3500,CONT_DIF_P,* +V 4400,4500,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 5600,3500,CONT_DIF_P,* +V 5600,4000,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 5000,1500,CONT_DIF_N,* +V 4400,1000,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 5600,1500,CONT_DIF_N,* +V 3800,1500,CONT_DIF_N,* +V 4400,1500,CONT_DIF_N,* +V 5000,1000,CONT_DIF_N,* +V 3800,300,CONT_BODY_P,* +V 5600,300,CONT_BODY_P,* +V 4400,300,CONT_BODY_P,* +V 5000,300,CONT_BODY_P,* +V 4500,2000,CONT_POLY,* +V 4300,2500,CONT_POLY,* +V 1200,400,CONT_BODY_P,* +V 1600,400,CONT_BODY_P,* +V 2000,400,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3200,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 900,4500,CONT_DIF_P,* +V 1400,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2600,500,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 3200,300,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa2ao222_x4.sym b/alliance/src/cells/src/sxlib/noa2ao222_x4.sym new file mode 100644 index 00000000..7315791a Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa2ao222_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/noa2ao222_x4.vbe b/alliance/src/cells/src/sxlib/noa2ao222_x4.vbe new file mode 100644 index 00000000..89b9f12c --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 638; + CONSTANT tplh_i4_nq : NATURAL := 664; + CONSTANT tphl_i0_nq : NATURAL := 684; + CONSTANT tphl_i4_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 732; + CONSTANT tplh_i1_nq : NATURAL := 758; + CONSTANT tphl_i1_nq : NATURAL := 780; + CONSTANT tplh_i3_nq : NATURAL := 795; + CONSTANT tplh_i0_nq : NATURAL := 801; + CONSTANT tplh_i2_nq : NATURAL := 809; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa2ao222_x4.vhd b/alliance/src/cells/src/sxlib/noa2ao222_x4.vhd new file mode 100644 index 00000000..b2e57b15 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa2ao222_x4.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2ao222_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2ao222_x4; + +ARCHITECTURE RTL OF noa2ao222_x4 IS +BEGIN + nq <= NOT(((i0 AND i1) OR ((i2 OR i3) AND i4))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa3ao322_x1.al b/alliance/src/cells/src/sxlib/noa3ao322_x1.al new file mode 100644 index 00000000..181eded8 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa3ao322_x1.al @@ -0,0 +1,59 @@ +V ALLIANCE : 6 +H noa3ao322_x1,L,30/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C i3,IN,EXTERNAL,11 +C i4,IN,EXTERNAL,15 +C i5,IN,EXTERNAL,16 +C i6,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,4 +T P,0.35,4.4,6,12,7,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00014 +T P,0.35,4.4,7,9,6,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00013 +T P,0.35,4.4,6,10,7,0,0.75,0.75,10.3,10.3,5.1,10.5,tr_00012 +T P,0.35,5.9,6,16,14,0,0.75,0.75,13.3,13.3,11.7,11.25,tr_00011 +T P,0.35,5.9,14,15,13,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00010 +T P,0.35,5.9,1,8,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009 +T P,0.35,5.9,13,11,1,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00008 +T N,0.35,2.6,4,16,3,0,0.75,0.75,6.7,6.7,11.7,3.9,tr_00007 +T N,0.35,2.6,3,15,4,0,0.75,0.75,6.7,6.7,9.9,3.9,tr_00006 +T N,0.35,2.6,4,11,3,0,0.75,0.75,6.7,6.7,8.4,3.9,tr_00005 +T N,0.35,2.6,3,8,1,0,0.75,0.75,6.7,6.7,6.6,3.9,tr_00004 +T N,0.35,3.5,1,10,2,0,0.75,0.75,8.5,8.5,4.8,3.45,tr_00003 +T N,0.35,3.5,2,9,5,0,0.75,0.75,8.5,8.5,3.3,3.45,tr_00002 +T N,0.35,3.5,5,12,4,0,0.75,0.75,8.5,8.5,1.8,3.45,tr_00001 +S 16,EXTERNAL,i5 +Q 0.00226056 +S 15,EXTERNAL,i4 +Q 0.00241094 +S 14,INTERNAL +Q 0 +S 13,INTERNAL +Q 0 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i3 +Q 0.00199028 +S 10,EXTERNAL,i2 +Q 0.00241094 +S 9,EXTERNAL,i1 +Q 0.00269279 +S 8,EXTERNAL,i6 +Q 0.00212909 +S 7,EXTERNAL,vdd +Q 0.0052329 +S 6,INTERNAL +Q 0.00250174 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vss +Q 0.00558543 +S 3,INTERNAL +Q 0.00108534 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,nq +Q 0.0026146 +EOF diff --git a/alliance/src/cells/src/sxlib/noa3ao322_x1.ap b/alliance/src/cells/src/sxlib/noa3ao322_x1.ap new file mode 100644 index 00000000..ca0b1ae9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa3ao322_x1.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 6 +H noa3ao322_x1,P, 6/ 9/2000,100 +A 0,0,4500,5000 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 4000,3500,ref_ref,i5_35 +R 4000,3000,ref_ref,i5_30 +R 4000,2500,ref_ref,i5_25 +R 4000,2000,ref_ref,i5_20 +R 4000,1500,ref_ref,i5_15 +R 3500,3500,ref_ref,i4_35 +R 3500,3000,ref_ref,i4_30 +R 3500,2500,ref_ref,i4_25 +R 3500,2000,ref_ref,i4_20 +R 3500,1500,ref_ref,i4_15 +R 3000,3000,ref_ref,i3_30 +R 3000,2500,ref_ref,i3_25 +R 3000,2000,ref_ref,i3_20 +R 3000,1500,ref_ref,i3_15 +R 2500,3500,ref_ref,nq_35 +R 2500,3000,ref_ref,nq_30 +R 2500,2500,ref_ref,nq_25 +R 2500,2000,ref_ref,nq_20 +R 2500,1500,ref_ref,nq_15 +R 2000,3500,ref_ref,i6_35 +R 2000,3000,ref_ref,i6_30 +R 2000,2500,ref_ref,i6_25 +R 2000,2000,ref_ref,i6_20 +R 2000,1000,ref_ref,nq_10 +R 1500,3500,ref_ref,i2_35 +R 1500,3000,ref_ref,i2_30 +R 1500,2500,ref_ref,i2_25 +R 1500,2000,ref_ref,i2_20 +R 1500,1500,ref_ref,i2_15 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +S 2000,2000,2200,2000,300,*,RIGHT,POLY +S 2000,1000,2000,1500,200,nq,DOWN,CALU1 +S 2500,1500,2500,3500,200,nq,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 4000,1500,4000,3500,200,i5,DOWN,CALU1 +S 3500,1500,3500,3500,200,i4,DOWN,CALU1 +S 3000,1500,3000,3000,200,i3,DOWN,CALU1 +S 2000,2000,2000,3500,200,i6,DOWN,CALU1 +S 1500,1500,1500,3500,200,i2,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 3700,400,4100,400,300,*,RIGHT,PTIE +S 1900,600,1900,1700,200,*,UP,NDIF +S 600,400,600,1900,100,*,UP,NTRANS +S 1100,400,1100,1900,100,*,UP,NTRANS +S 1600,400,1600,1900,100,*,UP,NTRANS +S 450,4700,850,4700,300,*,RIGHT,NTIE +S 2000,2000,2000,3500,100,*,UP,ALU1 +S 1950,1500,2550,1500,200,*,RIGHT,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1450,2500,3550,200,*,UP,ALU1 +S 2000,950,2000,1500,200,*,UP,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 3500,1500,3500,3500,100,*,UP,ALU1 +S 900,4000,4200,4000,100,*,RIGHT,ALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 300,4000,300,4700,200,*,UP,ALU1 +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 2200,2600,2300,2600,100,*,RIGHT,POLY +S 1600,2600,1700,2600,100,*,RIGHT,POLY +S 3400,1900,3400,2600,100,i4,UP,POLY +S 600,1900,600,2600,100,i0,UP,POLY +S 2200,1900,2200,2600,100,i6,UP,POLY +S 3900,1900,3900,2600,100,i5,DOWN,POLY +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 1600,1900,1600,2600,100,i2,UP,POLY +S 1100,1900,1100,2600,100,i1,UP,POLY +S 2500,900,2500,1700,200,*,UP,NDIF +S 2200,700,2200,1900,100,*,UP,NTRANS +S 2800,700,2800,1900,100,*,UP,NTRANS +S 300,500,300,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,200,*,UP,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 2600,2800,2600,4700,200,*,UP,PDIF +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 4200,2800,4200,4700,300,*,UP,PDIF +S 3900,2600,3900,4900,100,*,UP,PTRANS +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 2800,2400,2900,2400,100,*,RIGHT,POLY +S 2800,1900,2800,2400,100,i3,UP,POLY +S 3300,700,3300,1900,100,*,UP,NTRANS +S 3600,900,3600,1700,300,*,UP,NDIF +S 3900,700,3900,1900,100,*,UP,NTRANS +S 2500,1000,3600,1000,100,*,RIGHT,ALU1 +S 3300,1900,3400,1900,100,*,RIGHT,POLY +S 4000,1500,4000,3500,100,*,DOWN,ALU1 +S 4200,900,4200,1700,300,*,UP,NDIF +S 4200,300,4200,1000,200,*,DOWN,ALU1 +S 2000,2800,2000,4200,200,*,UP,PDIF +S 1700,2600,1700,4400,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 900,2800,900,4200,300,*,UP,PDIF +S 600,2600,600,4400,100,*,UP,PTRANS +S 300,2800,300,4200,300,*,UP,PDIF +S 1450,2800,1450,4650,200,*,UP,PDIF +S 3050,350,3050,1700,200,*,UP,NDIF +V 3700,400,CONT_BODY_P,* +V 4100,400,CONT_BODY_P,* +V 2450,400,CONT_BODY_P,* +V 450,4700,CONT_BODY_N,* +V 2000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 1900,1000,CONT_DIF_N,* +V 2500,1000,CONT_DIF_N,* +V 2000,4000,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 4200,4000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 850,4700,CONT_BODY_N,* +V 300,4000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3600,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 4000,2000,CONT_POLY,* +V 4200,1000,CONT_DIF_N,* +V 3050,400,CONT_DIF_N,* +V 1450,4700,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa3ao322_x1.vbe b/alliance/src/cells/src/sxlib/noa3ao322_x1.vbe new file mode 100644 index 00000000..ff022776 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa3ao322_x1.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3370; + CONSTANT rdown_i1_nq : NATURAL := 3370; + CONSTANT rdown_i2_nq : NATURAL := 3370; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rdown_i5_nq : NATURAL := 3210; + CONSTANT rdown_i6_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 6700; + CONSTANT rup_i1_nq : NATURAL := 6700; + CONSTANT rup_i2_nq : NATURAL := 6700; + CONSTANT rup_i3_nq : NATURAL := 6700; + CONSTANT rup_i4_nq : NATURAL := 6700; + CONSTANT rup_i5_nq : NATURAL := 6700; + CONSTANT rup_i6_nq : NATURAL := 3690; + CONSTANT tphl_i3_nq : NATURAL := 196; + CONSTANT tphl_i6_nq : NATURAL := 246; + CONSTANT tphl_i4_nq : NATURAL := 264; + CONSTANT tplh_i6_nq : NATURAL := 311; + CONSTANT tphl_i5_nq : NATURAL := 328; + CONSTANT tphl_i0_nq : NATURAL := 396; + CONSTANT tphl_i1_nq : NATURAL := 486; + CONSTANT tplh_i2_nq : NATURAL := 488; + CONSTANT tphl_i2_nq : NATURAL := 546; + CONSTANT tplh_i1_nq : NATURAL := 552; + CONSTANT tplh_i5_nq : NATURAL := 581; + CONSTANT tplh_i3_nq : NATURAL := 599; + CONSTANT tplh_i4_nq : NATURAL := 608; + CONSTANT tplh_i0_nq : NATURAL := 616; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x1; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa3ao322_x1.vhd b/alliance/src/cells/src/sxlib/noa3ao322_x1.vhd new file mode 100644 index 00000000..56c06273 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa3ao322_x1.vhd @@ -0,0 +1,25 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa3ao322_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa3ao322_x1; + +ARCHITECTURE RTL OF noa3ao322_x1 IS +BEGIN + nq <= NOT((((i0 AND i1) AND i2) OR (((i3 OR i4) OR i5) AND i6))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/noa3ao322_x4.al b/alliance/src/cells/src/sxlib/noa3ao322_x4.al new file mode 100644 index 00000000..b2d65294 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa3ao322_x4.al @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H noa3ao322_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,18 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,14 +C i5,IN,EXTERNAL,15 +C i6,IN,EXTERNAL,16 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,4.4,11,17,6,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00020 +T P,0.35,5.9,5,4,3,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00019 +T P,0.35,3.5,6,16,12,0,0.75,0.75,8.5,8.5,12.6,10.95,tr_00018 +T P,0.35,3.2,12,18,5,0,0.75,0.75,7.9,7.9,10.8,11.1,tr_00017 +T P,0.35,5.9,3,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00016 +T P,0.35,3.2,12,7,5,0,0.75,0.75,7.9,7.9,7.2,11.1,tr_00015 +T P,0.35,4.4,13,14,11,0,0.75,0.75,10.3,10.3,16.2,10.5,tr_00014 +T P,0.35,4.4,12,15,13,0,0.75,0.75,10.3,10.3,17.7,10.5,tr_00013 +T P,0.35,3.2,5,8,12,0,0.75,0.75,7.9,7.9,9,11.1,tr_00012 +T P,0.35,3.5,5,6,4,0,0.75,0.75,8.5,8.5,1.8,10.05,tr_00011 +T N,0.35,1.7,9,16,6,0,0.75,0.75,4.9,4.9,12.3,3.45,tr_00010 +T N,0.35,2.3,10,8,2,0,0.75,0.75,6.1,6.1,9,3.75,tr_00009 +T N,0.35,1.1,9,14,1,0,0.75,0.75,3.7,3.7,15.9,3.15,tr_00008 +T N,0.35,2.3,6,18,10,0,0.75,0.75,6.1,6.1,10.5,3.75,tr_00007 +T N,0.35,2.3,2,7,1,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00006 +T N,0.35,1.1,1,17,9,0,0.75,0.75,3.7,3.7,14.1,3.15,tr_00005 +T N,0.35,1.1,1,15,9,0,0.75,0.75,3.7,3.7,17.7,3.15,tr_00004 +T N,0.35,2,4,6,1,0,0.75,0.75,5.5,5.5,1.8,3.3,tr_00003 +T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,5.4,2.85,tr_00002 +T N,0.35,2.9,1,4,3,0,0.75,0.75,7.3,7.3,3.6,2.85,tr_00001 +S 18,EXTERNAL,i2 +Q 0.00247612 +S 17,EXTERNAL,i3 +Q 0.00290834 +S 16,EXTERNAL,i6 +Q 0.00262649 +S 15,EXTERNAL,i5 +Q 0.00275797 +S 14,EXTERNAL,i4 +Q 0.00283894 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0.00261448 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.00114171 +S 8,EXTERNAL,i1 +Q 0.00275797 +S 7,EXTERNAL,i0 +Q 0.00290834 +S 6,INTERNAL +Q 0.00675598 +S 5,EXTERNAL,vdd +Q 0.00900775 +S 4,INTERNAL +Q 0.00543312 +S 3,EXTERNAL,nq +Q 0.00258522 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00847896 +EOF diff --git a/alliance/src/cells/src/sxlib/noa3ao322_x4.ap b/alliance/src/cells/src/sxlib/noa3ao322_x4.ap new file mode 100644 index 00000000..3e8b73c9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa3ao322_x4.ap @@ -0,0 +1,191 @@ +V ALLIANCE : 6 +H noa3ao322_x4,P, 6/ 9/2000,100 +A 0,0,6500,5000 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 1500,4000,ref_ref,nq_40 +R 2500,3500,ref_ref,i0_35 +R 5000,3500,ref_ref,i3_35 +R 6000,2500,ref_ref,i5_25 +R 6000,3000,ref_ref,i5_30 +R 6000,3500,ref_ref,i5_35 +R 2500,1500,ref_ref,i0_15 +R 2500,2000,ref_ref,i0_20 +R 2500,2500,ref_ref,i0_25 +R 2500,3000,ref_ref,i0_30 +R 5000,3000,ref_ref,i3_30 +R 5500,1500,ref_ref,i4_15 +R 5500,2000,ref_ref,i4_20 +R 5500,2500,ref_ref,i4_25 +R 5500,3000,ref_ref,i4_30 +R 5500,3500,ref_ref,i4_35 +R 6000,1500,ref_ref,i5_15 +R 6000,2000,ref_ref,i5_20 +R 5000,1500,ref_ref,i3_15 +R 5000,2000,ref_ref,i3_20 +R 5000,2500,ref_ref,i3_25 +R 3500,2500,ref_ref,i2_25 +R 3500,3000,ref_ref,i2_30 +R 3500,3500,ref_ref,i2_35 +R 4000,2000,ref_ref,i6_20 +R 4000,2500,ref_ref,i6_25 +R 4000,3000,ref_ref,i6_30 +R 4000,3500,ref_ref,i6_35 +R 3000,1500,ref_ref,i1_15 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 1500,3500,ref_ref,nq_35 +R 3500,2000,ref_ref,i2_20 +S 4500,2800,4500,4200,300,*,DOWN,PDIF +S 4000,2000,4200,2000,300,*,RIGHT,POLY +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 600,2600,600,4100,100,*,UP,PTRANS +S 300,2800,300,3900,300,*,UP,PDIF +S 2100,2800,2100,4700,200,*,DOWN,PDIF +S 3000,3000,3000,4400,100,*,UP,PTRANS +S 3300,3200,3300,4500,300,*,DOWN,PDIF +S 3900,3100,3900,4200,200,*,UP,PDIF +S 5900,2600,5900,4400,100,*,UP,PTRANS +S 5400,2600,5400,4400,100,*,UP,PTRANS +S 2400,3000,2400,4400,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 6200,2800,6200,4200,300,*,UP,PDIF +S 3600,3000,3600,4400,100,*,UP,PTRANS +S 4200,2900,4200,4400,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2700,3200,2700,4200,300,*,UP,PDIF +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 5000,400,5000,1200,300,*,DOWN,NDIF +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1500,500,1500,1400,300,*,UP,NDIF +S 2200,400,2200,1600,300,*,UP,NDIF +S 900,500,900,1400,300,*,DOWN,NDIF +S 600,600,600,1600,100,*,DOWN,NTRANS +S 300,800,300,1400,300,*,DOWN,NDIF +S 5900,700,5900,1400,100,*,UP,NTRANS +S 6200,900,6200,1200,300,*,UP,NDIF +S 4700,700,4700,1400,100,*,UP,NTRANS +S 2500,700,2500,1800,100,*,UP,NTRANS +S 3500,700,3500,1800,100,*,UP,NTRANS +S 5300,700,5300,1400,100,*,UP,NTRANS +S 3800,900,3800,1400,200,*,UP,NDIF +S 3000,700,3000,1800,100,*,UP,NTRANS +S 5600,900,5600,1200,300,*,UP,NDIF +S 4100,700,4100,1600,100,*,UP,NTRANS +S 4400,900,4400,1400,200,*,UP,NDIF +S 2800,400,4300,400,300,*,RIGHT,PTIE +S 5700,400,6100,400,300,*,RIGHT,PTIE +S 600,1600,600,2600,100,*,DOWN,POLY +S 1000,1600,1000,1700,100,*,DOWN,POLY +S 1000,1600,1800,1600,100,*,RIGHT,POLY +S 1000,2600,1800,2600,100,*,LEFT,POLY +S 1000,2500,1000,2600,100,*,DOWN,POLY +S 600,2100,2000,2100,100,*,LEFT,POLY +S 5300,1400,5300,1900,100,*,UP,POLY +S 4100,1600,4100,1900,100,*,UP,POLY +S 4700,1900,4900,1900,100,*,RIGHT,POLY +S 3600,1900,3600,3000,100,i2,UP,POLY +S 3500,1800,3500,2000,100,*,UP,POLY +S 4700,1400,4700,1900,100,*,UP,POLY +S 4100,1900,4200,1900,100,*,LEFT,POLY +S 2400,1900,2500,1900,100,*,RIGHT,POLY +S 3000,1900,3000,3000,100,*,DOWN,POLY +S 2500,1800,2500,2000,100,*,DOWN,POLY +S 5900,1900,5900,2600,100,i5,DOWN,POLY +S 5400,1900,5400,2600,100,i4,UP,POLY +S 2400,1900,2400,3000,100,*,DOWN,POLY +S 5300,1900,5400,1900,100,*,RIGHT,POLY +S 3000,1800,3000,2000,100,*,UP,POLY +S 5900,1400,5900,2000,100,*,UP,POLY +S 4200,1900,4200,2900,100,i6,UP,POLY +S 4900,1900,4900,2600,100,*,UP,POLY +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 6200,300,6200,1000,200,*,DOWN,ALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 300,2500,1000,2500,100,*,LEFT,ALU1 +S 300,1700,1000,1700,100,*,LEFT,ALU1 +S 300,1200,300,3500,100,*,DOWN,ALU1 +S 3500,2000,3500,3500,100,*,UP,ALU1 +S 900,3000,900,4500,200,*,UP,ALU1 +S 900,600,900,1200,200,*,DOWN,ALU1 +S 4400,1000,5600,1000,100,*,RIGHT,ALU1 +S 5000,1500,5000,3500,100,*,UP,ALU1 +S 4500,1500,4500,3500,100,*,DOWN,ALU1 +S 2000,1000,3800,1000,100,*,LEFT,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 2100,4000,2100,4700,200,*,UP,ALU1 +S 3800,1500,4500,1500,100,*,RIGHT,ALU1 +S 3800,1000,3800,1500,100,*,UP,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 3000,1500,3000,3500,100,*,DOWN,ALU1 +S 5500,1500,5500,3500,100,*,UP,ALU1 +S 4000,2000,4000,3500,100,*,UP,ALU1 +S 6000,1500,6000,3500,100,*,DOWN,ALU1 +S 2700,4000,6200,4000,100,*,RIGHT,ALU1 +S 2000,1000,2000,2000,100,*,UP,ALU1 +S 1500,1000,1500,4000,200,nq,DOWN,CALU1 +S 2500,1500,2500,3500,200,i0,DOWN,CALU1 +S 5000,1500,5000,3500,200,i3,DOWN,CALU1 +S 6000,1500,6000,3500,200,i5,DOWN,CALU1 +S 5500,1500,5500,3500,200,i4,DOWN,CALU1 +S 3500,2000,3500,3500,200,i2,DOWN,CALU1 +S 4000,2000,4000,3500,200,i6,DOWN,CALU1 +S 3000,1500,3000,3500,200,i1,DOWN,CALU1 +V 300,4700,CONT_BODY_N,* +V 300,3000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 2700,4700,CONT_BODY_N,* +V 6200,4000,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,3000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 4500,4700,CONT_BODY_N,* +V 3900,4700,CONT_BODY_N,* +V 2100,4000,CONT_DIF_P,* +V 5700,4700,CONT_BODY_N,* +V 4500,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 3900,4000,CONT_DIF_P,* +V 5100,4700,CONT_BODY_N,* +V 1500,3500,CONT_DIF_P,* +V 2200,500,CONT_DIF_N,* +V 5000,500,CONT_DIF_N,* +V 300,1200,CONT_DIF_N,* +V 4400,1000,CONT_DIF_N,* +V 900,1200,CONT_DIF_N,* +V 900,700,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3800,1000,CONT_DIF_N,* +V 6200,1000,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 300,300,CONT_BODY_P,* +V 2800,400,CONT_BODY_P,* +V 4350,400,CONT_BODY_P,* +V 3300,400,CONT_BODY_P,* +V 3800,400,CONT_BODY_P,* +V 6100,400,CONT_BODY_P,* +V 5700,400,CONT_BODY_P,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 1000,1700,CONT_POLY,* +V 5000,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 6000,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/noa3ao322_x4.sym b/alliance/src/cells/src/sxlib/noa3ao322_x4.sym new file mode 100644 index 00000000..25b1ee2e Binary files /dev/null and b/alliance/src/cells/src/sxlib/noa3ao322_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/noa3ao322_x4.vbe b/alliance/src/cells/src/sxlib/noa3ao322_x4.vbe new file mode 100644 index 00000000..1fc4b8a6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT tplh_i6_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 729; + CONSTANT tphl_i6_nq : NATURAL := 738; + CONSTANT tphl_i0_nq : NATURAL := 819; + CONSTANT tphl_i4_nq : NATURAL := 821; + CONSTANT tplh_i2_nq : NATURAL := 874; + CONSTANT tplh_i5_nq : NATURAL := 900; + CONSTANT tphl_i5_nq : NATURAL := 907; + CONSTANT tphl_i1_nq : NATURAL := 914; + CONSTANT tplh_i4_nq : NATURAL := 924; + CONSTANT tplh_i3_nq : NATURAL := 926; + CONSTANT tplh_i1_nq : NATURAL := 931; + CONSTANT tplh_i0_nq : NATURAL := 987; + CONSTANT tphl_i2_nq : NATURAL := 990; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1600 ps; +END; diff --git a/alliance/src/cells/src/sxlib/noa3ao322_x4.vhd b/alliance/src/cells/src/sxlib/noa3ao322_x4.vhd new file mode 100644 index 00000000..610f1dff --- /dev/null +++ b/alliance/src/cells/src/sxlib/noa3ao322_x4.vhd @@ -0,0 +1,25 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa3ao322_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa3ao322_x4; + +ARCHITECTURE RTL OF noa3ao322_x4 IS +BEGIN + nq <= NOT((((i0 AND i1) AND i2) OR (((i3 OR i4) OR i5) AND i6))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/nts_x1.al b/alliance/src/cells/src/sxlib/nts_x1.al new file mode 100644 index 00000000..69a2f5ec --- /dev/null +++ b/alliance/src/cells/src/sxlib/nts_x1.al @@ -0,0 +1,30 @@ +V ALLIANCE : 6 +H nts_x1,L,30/10/99 +C cmd,IN,EXTERNAL,7 +C i,IN,EXTERNAL,8 +C nq,TRISTATE,EXTERNAL,1 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00006 +T P,0.35,5.9,5,4,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00005 +T P,0.35,2.9,4,7,6,0,0.75,0.75,7.3,7.3,7.2,9.75,tr_00004 +T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00003 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,7.2,3,tr_00001 +S 8,EXTERNAL,i +Q 0.00317129 +S 7,EXTERNAL,cmd +Q 0.00472134 +S 6,EXTERNAL,vdd +Q 0.00497229 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00329099 +S 3,EXTERNAL,vss +Q 0.00420847 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,nq +Q 0.00258522 +EOF diff --git a/alliance/src/cells/src/sxlib/nts_x1.ap b/alliance/src/cells/src/sxlib/nts_x1.ap new file mode 100644 index 00000000..5f2664b5 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nts_x1.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H nts_x1,P,30/ 8/2000,100 +A 0,0,3000,5000 +R 500,3000,ref_ref,i_30 +R 500,3500,ref_ref,i_35 +R 1500,1500,ref_ref,nq_15 +R 1500,2000,ref_ref,nq_20 +R 1500,3000,ref_ref,nq_30 +R 1500,3500,ref_ref,nq_35 +R 1500,4000,ref_ref,nq_40 +R 1500,1000,ref_ref,nq_10 +R 1000,1000,ref_ref,cmd_10 +R 1000,1500,ref_ref,cmd_15 +R 1000,2000,ref_ref,cmd_20 +R 500,1000,ref_ref,i_10 +R 500,1500,ref_ref,i_15 +R 500,2000,ref_ref,i_20 +R 500,2500,ref_ref,i_25 +R 1500,2500,ref_ref,nq_25 +R 500,4000,ref_ref,i_40 +R 1000,2500,ref_ref,cmd_25 +R 1000,3000,ref_ref,cmd_30 +R 1000,3500,ref_ref,cmd_35 +R 1000,4000,ref_ref,cmd_40 +S 1500,1000,1500,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 1000,1000,1000,4000,200,cmd,DOWN,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2100,1000,2100,3500,100,*,DOWN,ALU1 +S 1200,2600,2000,2600,100,*,RIGHT,POLY +S 2000,2500,2000,2600,100,*,DOWN,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,100,600,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 2700,800,2700,1200,300,*,UP,NDIF +S 2100,800,2100,1200,300,*,UP,NDIF +S 2400,600,2400,1400,100,*,UP,NTRANS +S 600,2600,600,4900,100,*,DOWN,PTRANS +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 2700,2800,2700,3700,300,*,DOWN,PDIF +S 2100,2800,2100,3700,300,*,DOWN,PDIF +S 2400,2600,2400,3900,100,*,DOWN,PTRANS +S 500,1000,500,4000,100,*,UP,ALU1 +S 600,1400,600,2600,100,*,UP,POLY +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1200,1400,1200,2000,100,*,UP,POLY +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 2700,300,2700,1000,200,*,DOWN,ALU1 +S 2700,3000,2700,4700,200,*,UP,ALU1 +V 2000,2500,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2700,300,CONT_BODY_P,* +V 2700,4700,CONT_BODY_N,* +V 2100,300,CONT_BODY_P,* +V 2100,4700,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/nts_x1.sym b/alliance/src/cells/src/sxlib/nts_x1.sym new file mode 100644 index 00000000..f4ed35b4 Binary files /dev/null and b/alliance/src/cells/src/sxlib/nts_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/nts_x1.vbe b/alliance/src/cells/src/sxlib/nts_x1.vbe new file mode 100644 index 00000000..f6cada4a --- /dev/null +++ b/alliance/src/cells/src/sxlib/nts_x1.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_cmd : NATURAL := 14; + CONSTANT cin_i : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i_nq : NATURAL := 3210; + CONSTANT tphl_cmd_nq : NATURAL := 41; + CONSTANT tphl_i_nq : NATURAL := 169; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 249; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x1; + +ARCHITECTURE behaviour_data_flow OF nts_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x1" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 800 ps; + END BLOCK label0; + +END; diff --git a/alliance/src/cells/src/sxlib/nts_x1.vhd b/alliance/src/cells/src/sxlib/nts_x1.vhd new file mode 100644 index 00000000..e1177332 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nts_x1.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nts_x1 IS +PORT( + cmd : IN STD_LOGIC; + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nts_x1; + +ARCHITECTURE RTL OF nts_x1 IS +BEGIN + PROCESS ( i, cmd ) + BEGIN + IF (cmd = '1') + THEN nq <= NOT(i); + ELSE nq <= 'Z'; + END IF; + END PROCESS; +END RTL; diff --git a/alliance/src/cells/src/sxlib/nts_x2.al b/alliance/src/cells/src/sxlib/nts_x2.al new file mode 100644 index 00000000..c5f00858 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nts_x2.al @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H nts_x2,L,30/10/99 +C cmd,IN,EXTERNAL,9 +C i,IN,EXTERNAL,10 +C nq,TRISTATE,EXTERNAL,2 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,6,10,7,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00010 +T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009 +T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00008 +T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00007 +T P,0.35,2.9,6,9,8,0,0.75,0.75,7.3,7.3,10.2,9.75,tr_00006 +T N,0.35,2.9,2,9,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004 +T N,0.35,2.9,4,10,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,3,10,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00002 +T N,0.35,1.4,8,9,4,0,0.75,0.75,4.3,4.3,10.2,3,tr_00001 +S 10,EXTERNAL,i +Q 0.00541538 +S 9,EXTERNAL,cmd +Q 0.00510823 +S 8,INTERNAL +Q 0.00545178 +S 7,INTERNAL +Q 0 +S 6,EXTERNAL,vdd +Q 0.00589026 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vss +Q 0.00495018 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,nq +Q 0.00258522 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/nts_x2.ap b/alliance/src/cells/src/sxlib/nts_x2.ap new file mode 100644 index 00000000..b50cc0a0 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nts_x2.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H nts_x2,P,30/ 8/2000,100 +A 0,0,4000,5000 +R 1000,4000,ref_ref,i_40 +R 1000,3500,ref_ref,i_35 +R 1000,3000,ref_ref,i_30 +R 1000,2500,ref_ref,i_25 +R 1000,2000,ref_ref,i_20 +R 1000,1500,ref_ref,i_15 +R 1000,1000,ref_ref,i_10 +R 1500,4000,ref_ref,nq_40 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 3000,2000,ref_ref,cmd_20 +R 3000,1500,ref_ref,cmd_15 +R 3000,1000,ref_ref,cmd_10 +R 3000,2500,ref_ref,cmd_25 +R 3000,3000,ref_ref,cmd_30 +R 3000,3500,ref_ref,cmd_35 +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,nq,DOWN,CALU1 +S 3000,1000,3000,3500,200,cmd,DOWN,CALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1200,2600,2000,2600,100,*,RIGHT,POLY +S 1200,1400,2000,1400,100,*,RIGHT,POLY +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,100,2400,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,2600,600,4900,100,*,DOWN,PTRANS +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 1800,2600,1800,4900,100,*,DOWN,PTRANS +S 2400,2600,2400,4900,100,*,DOWN,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 600,1400,600,2600,100,*,UP,POLY +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 3400,2600,3400,3900,100,*,DOWN,PTRANS +S 3700,2800,3700,3700,300,*,DOWN,PDIF +S 300,3000,300,4500,200,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 3400,600,3400,1400,100,*,UP,NTRANS +S 3700,800,3700,1200,300,*,UP,NDIF +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2000,1500,3000,1500,100,*,RIGHT,ALU1 +S 3000,2000,3400,2000,300,*,RIGHT,POLY +S 2000,4000,3700,4000,100,*,RIGHT,ALU1 +S 3700,1000,3700,4000,100,*,DOWN,ALU1 +S 2000,2500,2000,4000,100,*,DOWN,ALU1 +S 3000,1000,3000,3500,100,*,UP,ALU1 +S 2900,300,2900,1200,700,*,DOWN,NDIF +S 2900,2800,2900,4700,700,*,UP,PDIF +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +V 3700,3500,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2000,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 3700,4700,CONT_BODY_N,* +V 300,4500,CONT_DIF_P,* +V 3700,300,CONT_BODY_P,* +V 2000,1500,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2700,4500,CONT_DIF_P,* +V 2700,500,CONT_DIF_N,* +V 3100,4500,CONT_DIF_P,* +V 3100,500,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/nts_x2.sym b/alliance/src/cells/src/sxlib/nts_x2.sym new file mode 100644 index 00000000..c821e1e9 Binary files /dev/null and b/alliance/src/cells/src/sxlib/nts_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/nts_x2.vbe b/alliance/src/cells/src/sxlib/nts_x2.vbe new file mode 100644 index 00000000..4bb47086 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nts_x2.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_cmd : NATURAL := 18; + CONSTANT cin_i : NATURAL := 28; + CONSTANT rdown_cmd_nq : NATURAL := 1430; + CONSTANT rdown_i_nq : NATURAL := 1430; + CONSTANT rup_cmd_nq : NATURAL := 1600; + CONSTANT rup_i_nq : NATURAL := 1600; + CONSTANT tphl_cmd_nq : NATURAL := 33; + CONSTANT tphl_i_nq : NATURAL := 167; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 330; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x2; + +ARCHITECTURE behaviour_data_flow OF nts_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x2" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 900 ps; + END BLOCK label0; + +END; diff --git a/alliance/src/cells/src/sxlib/nts_x2.vhd b/alliance/src/cells/src/sxlib/nts_x2.vhd new file mode 100644 index 00000000..b982932d --- /dev/null +++ b/alliance/src/cells/src/sxlib/nts_x2.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nts_x2 IS +PORT( + cmd : IN STD_LOGIC; + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nts_x2; + +ARCHITECTURE RTL OF nts_x2 IS +BEGIN + PROCESS ( i, cmd ) + BEGIN + IF (cmd = '1') + THEN nq <= NOT(i); + ELSE nq <= 'Z'; + END IF; + END PROCESS; +END RTL; diff --git a/alliance/src/cells/src/sxlib/nxr2_x1.al b/alliance/src/cells/src/sxlib/nxr2_x1.al new file mode 100644 index 00000000..be155f9d --- /dev/null +++ b/alliance/src/cells/src/sxlib/nxr2_x1.al @@ -0,0 +1,40 @@ +V ALLIANCE : 6 +H nxr2_x1,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,7,9,6,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012 +T P,0.35,5.9,6,5,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,6,8,7,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,2.9,7,8,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00008 +T P,0.35,2.9,9,10,7,0,0.75,0.75,7.3,7.3,10.8,11.25,tr_00007 +T N,0.35,2.9,4,8,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005 +T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,2.9,3,10,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003 +T N,0.35,1.4,4,10,9,0,0.75,0.75,4.3,4.3,10.8,3,tr_00002 +T N,0.35,1.4,5,8,4,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 10,EXTERNAL,i1 +Q 0.00533757 +S 9,INTERNAL +Q 0.00655161 +S 8,EXTERNAL,i0 +Q 0.00413388 +S 7,EXTERNAL,vdd +Q 0.0047041 +S 6,INTERNAL +Q 0.00217068 +S 5,INTERNAL +Q 0.0053513 +S 4,EXTERNAL,vss +Q 0.0047041 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,nq +Q 0.00299651 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/nxr2_x1.ap b/alliance/src/cells/src/sxlib/nxr2_x1.ap new file mode 100644 index 00000000..4cd41052 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nxr2_x1.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H nxr2_x1,P,30/ 8/2000,100 +A 0,0,4500,5000 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1000,1000,ref_ref,i0_10 +R 1000,1500,ref_ref,i0_15 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,4000,ref_ref,i0_40 +R 3500,1000,ref_ref,i1_10 +R 3500,1500,ref_ref,i1_15 +R 3500,2000,ref_ref,i1_20 +R 3500,2500,ref_ref,i1_25 +R 3500,3000,ref_ref,i1_30 +R 3500,3500,ref_ref,i1_35 +R 3500,4000,ref_ref,i1_40 +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 3500,1000,3500,4000,200,i1,DOWN,CALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 600,2600,600,3100,100,*,DOWN,POLY +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 3600,3100,3600,4400,100,*,UP,PTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,2600,3600,3100,100,*,DOWN,POLY +S 3500,1000,3500,4000,100,*,DOWN,ALU1 +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 4000,1000,4000,3500,100,*,DOWN,ALU1 +S 4000,3300,4000,4200,300,*,DOWN,PDIF +S 4000,800,4000,1200,300,*,UP,NDIF +S 3000,2000,3000,2600,100,*,DOWN,POLY +S 2000,2500,3500,2500,100,*,RIGHT,ALU1 +S 3000,1400,3600,1400,100,*,RIGHT,POLY +S 2000,1500,2500,1500,100,*,RIGHT,ALU1 +S 2500,1500,2500,2000,100,*,DOWN,ALU1 +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 1450,3500,2100,3500,200,*,RIGHT,ALU1 +S 1500,950,1500,3550,200,*,UP,ALU1 +S 1450,1000,2100,1000,200,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,DOWN,ALU1 +S 4000,3500,4000,4000,100,*,UP,ALU1 +S 2700,3000,2700,4000,100,*,UP,ALU1 +V 300,2000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 3900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 3900,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 3300,4500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 3300,500,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 2000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 4000,3500,CONT_DIF_P,* +V 4000,1000,CONT_DIF_N,* +V 3000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/nxr2_x1.sym b/alliance/src/cells/src/sxlib/nxr2_x1.sym new file mode 100644 index 00000000..94e1c85d Binary files /dev/null and b/alliance/src/cells/src/sxlib/nxr2_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/nxr2_x1.vbe b/alliance/src/cells/src/sxlib/nxr2_x1.vbe new file mode 100644 index 00000000..6a25e761 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nxr2_x1.vbe @@ -0,0 +1,40 @@ +ENTITY nxr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i1_nq : NATURAL := 156; + CONSTANT tphl_i0_nq : NATURAL := 288; + CONSTANT tplh_i0_nq : NATURAL := 293; + CONSTANT tplh_i1_nq : NATURAL := 327; + CONSTANT tphh_i0_nq : NATURAL := 366; + CONSTANT tpll_i0_nq : NATURAL := 389; + CONSTANT tphh_i1_nq : NATURAL := 395; + CONSTANT tpll_i1_nq : NATURAL := 503; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x1; + +ARCHITECTURE behaviour_data_flow OF nxr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x1" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/nxr2_x1.vhd b/alliance/src/cells/src/sxlib/nxr2_x1.vhd new file mode 100644 index 00000000..9ad239ca --- /dev/null +++ b/alliance/src/cells/src/sxlib/nxr2_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nxr2_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nxr2_x1; + +ARCHITECTURE RTL OF nxr2_x1 IS +BEGIN + nq <= NOT((i0 XOR i1)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/nxr2_x4.al b/alliance/src/cells/src/sxlib/nxr2_x4.al new file mode 100644 index 00000000..eec8e730 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nxr2_x4.al @@ -0,0 +1,46 @@ +V ALLIANCE : 6 +H nxr2_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,9,10,6,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00016 +T P,0.35,2.9,6,8,4,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00015 +T P,0.35,5.9,11,2,6,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00014 +T P,0.35,5.9,6,2,11,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00013 +T P,0.35,5.9,2,9,7,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012 +T P,0.35,5.9,7,8,6,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00011 +T P,0.35,5.9,7,4,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,6,10,7,0,0.75,0.75,13.3,13.3,9,11.25,tr_00009 +T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00008 +T N,0.35,2.9,1,2,11,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00007 +T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006 +T N,0.35,1.4,1,10,9,0,0.75,0.75,4.3,4.3,10.8,3,tr_00005 +T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004 +T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,5,10,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00002 +T N,0.35,2.9,1,8,5,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00001 +S 11,EXTERNAL,nq +Q 0.00258522 +S 10,EXTERNAL,i1 +Q 0.00462772 +S 9,INTERNAL +Q 0.00536068 +S 8,EXTERNAL,i0 +Q 0.00370588 +S 7,INTERNAL +Q 0.00114171 +S 6,EXTERNAL,vdd +Q 0.00866628 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.0044986 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00780232 +S 1,EXTERNAL,vss +Q 0.00666861 +EOF diff --git a/alliance/src/cells/src/sxlib/nxr2_x4.ap b/alliance/src/cells/src/sxlib/nxr2_x4.ap new file mode 100644 index 00000000..40f36fe5 --- /dev/null +++ b/alliance/src/cells/src/sxlib/nxr2_x4.ap @@ -0,0 +1,135 @@ +V ALLIANCE : 6 +H nxr2_x4,P, 6/ 9/2000,100 +A 0,0,6000,5000 +R 5000,4000,ref_ref,nq_40 +R 5000,1000,ref_ref,nq_10 +R 5000,3000,ref_ref,nq_30 +R 5000,3500,ref_ref,nq_35 +R 5000,2500,ref_ref,nq_25 +R 5000,2000,ref_ref,nq_20 +R 5000,1500,ref_ref,nq_15 +R 3500,4000,ref_ref,i1_40 +R 3500,3500,ref_ref,i1_35 +R 3500,3000,ref_ref,i1_30 +R 3500,2500,ref_ref,i1_25 +R 3500,2000,ref_ref,i1_20 +R 3500,1500,ref_ref,i1_15 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,1500,ref_ref,i0_15 +R 1000,1000,ref_ref,i0_10 +S 4500,2000,5400,2000,300,*,RIGHT,POLY +S 5000,1000,5000,4000,200,nq,DOWN,CALU1 +S 3500,1500,3500,4000,200,i1,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 300,1000,300,3000,100,*,DOWN,ALU1 +S 3000,2600,3600,2600,100,*,RIGHT,POLY +S 3000,1400,3000,2000,100,*,DOWN,POLY +S 2000,1500,3500,1500,100,*,RIGHT,ALU1 +S 2500,2000,2500,2500,100,*,DOWN,ALU1 +S 2000,2500,2500,2500,100,*,RIGHT,ALU1 +S 4500,300,4500,1000,300,*,UP,NDIF +S 3900,800,3900,1600,300,*,UP,NDIF +S 1500,1000,4500,1000,100,*,RIGHT,ALU1 +S 4500,1000,4500,2000,100,*,DOWN,ALU1 +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 5700,500,5700,1000,200,*,DOWN,ALU1 +S 5700,3000,5700,4500,200,*,DOWN,ALU1 +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 3500,1500,3500,4000,100,*,DOWN,ALU1 +S 4000,1500,4000,2900,100,*,DOWN,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 5700,300,5700,1200,300,*,UP,NDIF +S 5100,300,5100,1200,300,*,UP,NDIF +S 5400,100,5400,1400,100,*,DOWN,NTRANS +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 3900,2800,3900,3700,300,*,DOWN,PDIF +S 4500,3400,4500,4700,300,*,DOWN,PDIF +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 600,2600,600,3900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,UP,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,DOWN,PDIF +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 1500,3500,2100,3500,100,*,RIGHT,ALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 0,3900,6000,3900,2400,*,LEFT,NWELL +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +V 4500,2000,CONT_POLY,* +V 4000,2900,CONT_DIF_P,* +V 4000,1500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 5100,3000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 5700,3000,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5700,4500,CONT_DIF_P,* +V 5700,1000,CONT_DIF_N,* +V 5700,500,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 300,3000,CONT_DIF_P,* +V 3000,2000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 3900,4700,CONT_BODY_N,* +V 300,300,CONT_BODY_P,* +V 3900,300,CONT_BODY_P,* +V 1000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/nxr2_x4.sym b/alliance/src/cells/src/sxlib/nxr2_x4.sym new file mode 100644 index 00000000..4e7a0cde Binary files /dev/null and b/alliance/src/cells/src/sxlib/nxr2_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/nxr2_x4.vbe b/alliance/src/cells/src/sxlib/nxr2_x4.vbe new file mode 100644 index 00000000..69c3294a --- /dev/null +++ b/alliance/src/cells/src/sxlib/nxr2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY nxr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tpll_i1_nq : NATURAL := 453; + CONSTANT tphh_i0_nq : NATURAL := 469; + CONSTANT tpll_i0_nq : NATURAL := 481; + CONSTANT tphl_i0_nq : NATURAL := 522; + CONSTANT tplh_i1_nq : NATURAL := 542; + CONSTANT tphl_i1_nq : NATURAL := 553; + CONSTANT tplh_i0_nq : NATURAL := 553; + CONSTANT tphh_i1_nq : NATURAL := 568; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x4; + +ARCHITECTURE behaviour_data_flow OF nxr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x4" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/nxr2_x4.vhd b/alliance/src/cells/src/sxlib/nxr2_x4.vhd new file mode 100644 index 00000000..929c679a --- /dev/null +++ b/alliance/src/cells/src/sxlib/nxr2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nxr2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nxr2_x4; + +ARCHITECTURE RTL OF nxr2_x4 IS +BEGIN + nq <= NOT((i0 XOR i1)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/o2_x2.al b/alliance/src/cells/src/sxlib/o2_x2.al new file mode 100644 index 00000000..e0196360 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o2_x2.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H o2_x2,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,3,2,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00005 +T P,0.35,4.4,5,7,2,0,0.75,0.75,10.3,10.3,2.4,10.5,tr_00004 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,2,6,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002 +T N,0.35,2.9,3,2,1,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 7,EXTERNAL,i1 +Q 0.00282737 +S 6,EXTERNAL,i0 +Q 0.00344095 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00298567 +S 3,EXTERNAL,q +Q 0.00264397 +S 2,INTERNAL +Q 0.00463918 +S 1,EXTERNAL,vss +Q 0.0033382 +EOF diff --git a/alliance/src/cells/src/sxlib/o2_x2.ap b/alliance/src/cells/src/sxlib/o2_x2.ap new file mode 100644 index 00000000..4b3c3f88 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o2_x2.ap @@ -0,0 +1,70 @@ +V ALLIANCE : 6 +H o2_x2,P,30/ 8/2000,100 +A 0,0,2500,5000 +R 2000,1000,ref_ref,q_10 +R 2000,4000,ref_ref,q_40 +R 2000,3500,ref_ref,q_35 +R 2000,3000,ref_ref,q_30 +R 2000,2500,ref_ref,q_25 +R 2000,2000,ref_ref,q_20 +R 2000,1500,ref_ref,q_15 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,1000,ref_ref,i0_10 +R 500,2500,ref_ref,i1_25 +R 500,2000,ref_ref,i1_20 +R 500,1500,ref_ref,i1_15 +R 500,3500,ref_ref,i1_35 +R 500,3000,ref_ref,i1_30 +S 2000,1000,2000,4000,200,q,DOWN,CALU1 +S 1500,1000,1500,4000,200,i0,DOWN,CALU1 +S 500,1500,500,3500,200,i1,DOWN,CALU1 +S 2000,950,2000,4050,200,*,UP,ALU1 +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1000,2000,1800,2000,100,*,RIGHT,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 600,2600,800,2600,100,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 1500,2800,1500,4700,300,*,UP,PDIF +S 500,2800,500,4200,300,*,DOWN,PDIF +S 300,2800,300,4200,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 800,2600,800,4400,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 300,400,300,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,LEFT,NWELL +S 950,1000,950,4000,100,*,UP,ALU1 +S 300,4000,950,4000,100,*,LEFT,ALU1 +V 2100,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 1400,2500,CONT_POLY,* +V 1400,1500,CONT_POLY,* +V 900,300,CONT_BODY_P,* +V 300,4700,CONT_BODY_N,* +V 1500,4500,CONT_DIF_P,* +V 1500,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/o2_x2.sym b/alliance/src/cells/src/sxlib/o2_x2.sym new file mode 100644 index 00000000..d70269b2 Binary files /dev/null and b/alliance/src/cells/src/sxlib/o2_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/o2_x2.vbe b/alliance/src/cells/src/sxlib/o2_x2.vbe new file mode 100644 index 00000000..9e115a06 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tpll_i0_q : NATURAL := 310; + CONSTANT tphh_i1_q : NATURAL := 335; + CONSTANT tpll_i1_q : NATURAL := 364; + CONSTANT tphh_i0_q : NATURAL := 406; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x2; + +ARCHITECTURE behaviour_data_flow OF o2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x2" + SEVERITY WARNING; + q <= (i0 or i1) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/o2_x2.vhd b/alliance/src/cells/src/sxlib/o2_x2.vhd new file mode 100644 index 00000000..6ff6bde5 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o2_x2.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o2_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o2_x2; + +ARCHITECTURE RTL OF o2_x2 IS +BEGIN + q <= (i0 OR i1); +END RTL; diff --git a/alliance/src/cells/src/sxlib/o2_x4.al b/alliance/src/cells/src/sxlib/o2_x4.al new file mode 100644 index 00000000..396b7653 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o2_x4.al @@ -0,0 +1,30 @@ +V ALLIANCE : 6 +H o2_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,4,1,3,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,5.9,3,1,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00007 +T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00006 +T P,0.35,4.4,5,7,1,0,0.75,0.75,10.3,10.3,2.4,10.5,tr_00005 +T N,0.35,2.9,2,1,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002 +T N,0.35,2.9,3,1,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 7,EXTERNAL,i1 +Q 0.00282737 +S 6,EXTERNAL,i0 +Q 0.00344095 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00503104 +S 3,EXTERNAL,q +Q 0.00264397 +S 2,EXTERNAL,vss +Q 0.00444349 +S 1,INTERNAL +Q 0.00596944 +EOF diff --git a/alliance/src/cells/src/sxlib/o2_x4.ap b/alliance/src/cells/src/sxlib/o2_x4.ap new file mode 100644 index 00000000..439a0eca --- /dev/null +++ b/alliance/src/cells/src/sxlib/o2_x4.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H o2_x4,P,30/ 8/2000,100 +A 0,0,3000,5000 +R 2000,1000,ref_ref,q_10 +R 2000,4000,ref_ref,q_40 +R 2000,3500,ref_ref,q_35 +R 2000,3000,ref_ref,q_30 +R 2000,2500,ref_ref,q_25 +R 2000,2000,ref_ref,q_20 +R 2000,1500,ref_ref,q_15 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,1000,ref_ref,i0_10 +R 500,2500,ref_ref,i1_25 +R 500,2000,ref_ref,i1_20 +R 500,1500,ref_ref,i1_15 +R 500,3500,ref_ref,i1_35 +R 500,3000,ref_ref,i1_30 +S 2000,1000,2000,4000,200,q,DOWN,CALU1 +S 1500,1000,1500,4000,200,i0,DOWN,CALU1 +S 500,1500,500,3500,200,i1,DOWN,CALU1 +S 2000,950,2000,4050,200,*,UP,ALU1 +S 2700,3000,2700,4500,200,*,UP,ALU1 +S 2700,500,2700,1000,200,*,DOWN,ALU1 +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 600,2600,800,2600,100,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1500,2800,1500,4700,300,*,UP,PDIF +S 500,2800,500,4200,300,*,DOWN,PDIF +S 300,2800,300,4200,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 800,2600,800,4400,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 300,400,300,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 950,1000,950,4000,100,*,UP,ALU1 +S 300,4000,950,4000,100,*,LEFT,ALU1 +V 2700,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 1400,2500,CONT_POLY,* +V 1400,1500,CONT_POLY,* +V 900,300,CONT_BODY_P,* +V 300,4700,CONT_BODY_N,* +V 1500,4500,CONT_DIF_P,* +V 1500,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/o2_x4.sym b/alliance/src/cells/src/sxlib/o2_x4.sym new file mode 100644 index 00000000..fe8d315f Binary files /dev/null and b/alliance/src/cells/src/sxlib/o2_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/o2_x4.vbe b/alliance/src/cells/src/sxlib/o2_x4.vbe new file mode 100644 index 00000000..e22a9361 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 394; + CONSTANT tphh_i1_q : NATURAL := 427; + CONSTANT tpll_i1_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 491; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x4; + +ARCHITECTURE behaviour_data_flow OF o2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x4" + SEVERITY WARNING; + q <= (i0 or i1) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/o2_x4.vhd b/alliance/src/cells/src/sxlib/o2_x4.vhd new file mode 100644 index 00000000..c4dbf96e --- /dev/null +++ b/alliance/src/cells/src/sxlib/o2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o2_x4; + +ARCHITECTURE RTL OF o2_x4 IS +BEGIN + q <= (i0 OR i1); +END RTL; diff --git a/alliance/src/cells/src/sxlib/o3_x2.al b/alliance/src/cells/src/sxlib/o3_x2.al new file mode 100644 index 00000000..d476fb88 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o3_x2.al @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H o3_x2,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,4.4,6,7,3,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00007 +T P,0.35,4.4,5,9,6,0,0.75,0.75,10.3,10.3,3,10.5,tr_00006 +T P,0.35,4.4,4,8,5,0,0.75,0.75,10.3,10.3,4.2,10.5,tr_00005 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,1.4,2,9,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003 +T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,1.4,3,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 9,EXTERNAL,i1 +Q 0.00282737 +S 8,EXTERNAL,i0 +Q 0.00282737 +S 7,EXTERNAL,i2 +Q 0.00260759 +S 6,INTERNAL +Q 0 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00350341 +S 3,INTERNAL +Q 0.00620074 +S 2,EXTERNAL,vss +Q 0.00367968 +S 1,EXTERNAL,q +Q 0.00358405 +EOF diff --git a/alliance/src/cells/src/sxlib/o3_x2.ap b/alliance/src/cells/src/sxlib/o3_x2.ap new file mode 100644 index 00000000..75d6139b --- /dev/null +++ b/alliance/src/cells/src/sxlib/o3_x2.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H o3_x2,P,30/ 8/2000,100 +A 0,0,3000,5000 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,2000,ref_ref,q_20 +R 2500,2500,ref_ref,q_25 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,2500,ref_ref,i2_25 +R 500,2000,ref_ref,i2_20 +R 500,1500,ref_ref,i2_15 +R 500,3500,ref_ref,i2_35 +R 500,3000,ref_ref,i2_30 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i2,DOWN,CALU1 +S 0,3900,3000,3900,2400,*,LEFT,NWELL +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,400,900,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,UP,ALU1 +S 600,1400,600,2600,100,*,DOWN,POLY +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2000,2000,2400,2000,100,*,RIGHT,POLY +S 300,2800,300,4200,300,*,DOWN,PDIF +S 300,4000,2000,4000,100,*,LEFT,ALU1 +S 600,2600,600,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1600,1400,1800,1400,100,*,LEFT,POLY +S 1600,1400,1600,2600,100,*,UP,POLY +S 1800,2800,1800,4700,500,*,DOWN,PDIF +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 2500,4000,2700,4000,200,*,RIGHT,ALU1 +S 2500,3500,2700,3500,200,*,LEFT,ALU1 +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +S 2500,1000,2700,1000,200,*,LEFT,ALU1 +V 2700,1000,CONT_DIF_N,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 2100,4500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 2100,500,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,2500,CONT_POLY,* +V 1700,4500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/o3_x2.sym b/alliance/src/cells/src/sxlib/o3_x2.sym new file mode 100644 index 00000000..10ad4b42 Binary files /dev/null and b/alliance/src/cells/src/sxlib/o3_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/o3_x2.vbe b/alliance/src/cells/src/sxlib/o3_x2.vbe new file mode 100644 index 00000000..5aad7aba --- /dev/null +++ b/alliance/src/cells/src/sxlib/o3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 360; + CONSTANT tpll_i0_q : NATURAL := 407; + CONSTANT tphh_i1_q : NATURAL := 430; + CONSTANT tpll_i1_q : NATURAL := 482; + CONSTANT tphh_i0_q : NATURAL := 494; + CONSTANT tpll_i2_q : NATURAL := 506; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x2; + +ARCHITECTURE behaviour_data_flow OF o3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x2" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/o3_x2.vhd b/alliance/src/cells/src/sxlib/o3_x2.vhd new file mode 100644 index 00000000..020e5378 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o3_x2.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o3_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o3_x2; + +ARCHITECTURE RTL OF o3_x2 IS +BEGIN + q <= ((i0 OR i1) OR i2); +END RTL; diff --git a/alliance/src/cells/src/sxlib/o3_x4.al b/alliance/src/cells/src/sxlib/o3_x4.al new file mode 100644 index 00000000..c0ae14bd --- /dev/null +++ b/alliance/src/cells/src/sxlib/o3_x4.al @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H o3_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,3,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00010 +T P,0.35,5.9,1,3,5,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009 +T P,0.35,4.4,5,7,4,0,0.75,0.75,10.3,10.3,4.2,10.5,tr_00008 +T P,0.35,4.4,4,9,6,0,0.75,0.75,10.3,10.3,3,10.5,tr_00007 +T P,0.35,4.4,6,8,3,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00006 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00005 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00004 +T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,3,7,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,1.4,2,9,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001 +S 9,EXTERNAL,i1 +Q 0.00282737 +S 8,EXTERNAL,i2 +Q 0.00260759 +S 7,EXTERNAL,i0 +Q 0.00282737 +S 6,INTERNAL +Q 0 +S 5,EXTERNAL,vdd +Q 0.00537252 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00773401 +S 2,EXTERNAL,vss +Q 0.00519625 +S 1,EXTERNAL,q +Q 0.00258522 +EOF diff --git a/alliance/src/cells/src/sxlib/o3_x4.ap b/alliance/src/cells/src/sxlib/o3_x4.ap new file mode 100644 index 00000000..f0ab0df9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o3_x4.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 6 +H o3_x4,P,30/ 8/2000,100 +A 0,0,3500,5000 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,2000,ref_ref,q_20 +R 2500,2500,ref_ref,q_25 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,2500,ref_ref,i2_25 +R 500,2000,ref_ref,i2_20 +R 500,1500,ref_ref,i2_15 +R 500,3500,ref_ref,i2_35 +R 500,3000,ref_ref,i2_30 +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,400,900,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,UP,ALU1 +S 600,1400,600,2600,100,*,DOWN,POLY +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,2800,300,4200,300,*,DOWN,PDIF +S 300,4000,2000,4000,100,*,LEFT,ALU1 +S 600,2600,600,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1600,1400,1800,1400,100,*,LEFT,POLY +S 1600,1400,1600,2600,100,*,UP,POLY +S 1800,2800,1800,4700,500,*,DOWN,PDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 2300,1400,2300,2600,100,*,DOWN,POLY +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 2600,2800,2600,4700,300,*,UP,PDIF +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 3200,300,3200,1200,300,*,DOWN,NDIF +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 1900,2000,2900,2000,300,*,RIGHT,POLY +S 3200,2800,3200,4700,300,*,UP,PDIF +S 3200,3000,3200,4500,200,*,UP,ALU1 +S 3200,500,3200,1700,200,*,UP,ALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i2,DOWN,CALU1 +V 300,4700,CONT_BODY_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,300,CONT_BODY_P,* +V 500,1500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,2500,CONT_POLY,* +V 2000,300,CONT_DIF_N,* +V 2000,4500,CONT_DIF_P,* +V 2600,1000,CONT_DIF_N,* +V 2600,3000,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 2600,4000,CONT_DIF_P,* +V 3200,500,CONT_DIF_N,* +V 3200,4500,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,1000,CONT_DIF_N,* +V 3200,1700,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/o3_x4.sym b/alliance/src/cells/src/sxlib/o3_x4.sym new file mode 100644 index 00000000..6453b559 Binary files /dev/null and b/alliance/src/cells/src/sxlib/o3_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/o3_x4.vbe b/alliance/src/cells/src/sxlib/o3_x4.vbe new file mode 100644 index 00000000..1e7ea94f --- /dev/null +++ b/alliance/src/cells/src/sxlib/o3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 447; + CONSTANT tpll_i0_q : NATURAL := 501; + CONSTANT tphh_i1_q : NATURAL := 510; + CONSTANT tphh_i0_q : NATURAL := 569; + CONSTANT tpll_i1_q : NATURAL := 585; + CONSTANT tpll_i2_q : NATURAL := 622; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x4; + +ARCHITECTURE behaviour_data_flow OF o3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x4" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/o3_x4.vhd b/alliance/src/cells/src/sxlib/o3_x4.vhd new file mode 100644 index 00000000..76e4c9ba --- /dev/null +++ b/alliance/src/cells/src/sxlib/o3_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o3_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o3_x4; + +ARCHITECTURE RTL OF o3_x4 IS +BEGIN + q <= ((i0 OR i1) OR i2); +END RTL; diff --git a/alliance/src/cells/src/sxlib/o4_x2.al b/alliance/src/cells/src/sxlib/o4_x2.al new file mode 100644 index 00000000..7be3125b --- /dev/null +++ b/alliance/src/cells/src/sxlib/o4_x2.al @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H o4_x2,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,1 +T P,0.35,4.4,3,10,2,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00010 +T P,0.35,4.4,6,8,3,0,0.75,0.75,10.3,10.3,3,10.5,tr_00009 +T P,0.35,4.4,5,7,6,0,0.75,0.75,10.3,10.3,4.2,10.5,tr_00008 +T P,0.35,4.4,4,9,5,0,0.75,0.75,10.3,10.3,5.4,10.5,tr_00007 +T P,0.35,5.9,4,2,11,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00006 +T N,0.35,1.4,2,9,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00005 +T N,0.35,1.4,1,10,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003 +T N,0.35,1.4,2,8,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002 +T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00001 +S 11,EXTERNAL,q +Q 0.00258522 +S 10,EXTERNAL,i3 +Q 0.00260759 +S 9,EXTERNAL,i2 +Q 0.00318597 +S 8,EXTERNAL,i1 +Q 0.00282737 +S 7,EXTERNAL,i0 +Q 0.00319753 +S 6,INTERNAL +Q 0 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00384489 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.0066641 +S 1,EXTERNAL,vss +Q 0.00419742 +EOF diff --git a/alliance/src/cells/src/sxlib/o4_x2.ap b/alliance/src/cells/src/sxlib/o4_x2.ap new file mode 100644 index 00000000..25229dda --- /dev/null +++ b/alliance/src/cells/src/sxlib/o4_x2.ap @@ -0,0 +1,103 @@ +V ALLIANCE : 6 +H o4_x2,P,30/ 8/2000,100 +A 0,0,3500,5000 +R 500,1500,ref_ref,i3_15 +R 500,3500,ref_ref,i3_35 +R 500,3000,ref_ref,i3_30 +R 500,2500,ref_ref,i3_25 +R 500,2000,ref_ref,i3_20 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 3000,1500,ref_ref,q_15 +R 3000,1000,ref_ref,q_10 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +S 3000,1000,3200,1000,200,*,LEFT,ALU1 +S 3000,3000,3200,3000,200,*,LEFT,ALU1 +S 3000,3500,3200,3500,200,*,LEFT,ALU1 +S 3000,4000,3200,4000,200,*,LEFT,ALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 900,1000,2550,1000,100,*,LEFT,ALU1 +S 300,4000,2550,4000,100,*,RIGHT,ALU1 +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 2100,1400,2100,2600,100,*,DOWN,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 1600,1400,1800,1400,100,*,RIGHT,POLY +S 1600,1400,1600,2100,100,*,DOWN,POLY +S 1400,1900,1400,2600,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2900,100,2900,1400,100,*,UP,NTRANS +S 3200,300,3200,1200,300,*,DOWN,NDIF +S 2400,2000,2900,2000,300,*,RIGHT,POLY +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 3200,2800,3200,4700,300,*,UP,PDIF +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 2200,2800,2200,4700,500,*,DOWN,PDIF +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 2100,1400,2400,1400,100,*,RIGHT,POLY +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 600,2600,600,4400,100,*,UP,PTRANS +S 300,2800,300,4200,300,*,DOWN,PDIF +S 600,1400,600,2600,100,*,DOWN,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1400,2000,1400,2100,100,*,DOWN,POLY +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 300,400,300,1200,300,*,UP,NDIF +S 1500,400,1500,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 500,1500,500,3500,200,i3,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 2000,1500,2000,3500,200,i2,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +V 2200,4500,CONT_DIF_P,* +V 2600,4500,CONT_DIF_P,* +V 2600,300,CONT_DIF_N,* +V 3200,3500,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 3200,1000,CONT_DIF_N,* +V 300,4000,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 900,300,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,4700,CONT_BODY_N,* +V 900,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/o4_x2.sym b/alliance/src/cells/src/sxlib/o4_x2.sym new file mode 100644 index 00000000..4e5ebc9a Binary files /dev/null and b/alliance/src/cells/src/sxlib/o4_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/o4_x2.vbe b/alliance/src/cells/src/sxlib/o4_x2.vbe new file mode 100644 index 00000000..09652e62 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i3_q : NATURAL := 378; + CONSTANT tphh_i1_q : NATURAL := 446; + CONSTANT tphh_i0_q : NATURAL := 508; + CONSTANT tpll_i2_q : NATURAL := 531; + CONSTANT tphh_i2_q : NATURAL := 567; + CONSTANT tpll_i0_q : NATURAL := 601; + CONSTANT tpll_i3_q : NATURAL := 626; + CONSTANT tpll_i1_q : NATURAL := 631; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x2; + +ARCHITECTURE behaviour_data_flow OF o4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x2" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/o4_x2.vhd b/alliance/src/cells/src/sxlib/o4_x2.vhd new file mode 100644 index 00000000..b7b15c9d --- /dev/null +++ b/alliance/src/cells/src/sxlib/o4_x2.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o4_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o4_x2; + +ARCHITECTURE RTL OF o4_x2 IS +BEGIN + q <= (((i0 OR i1) OR i2) OR i3); +END RTL; diff --git a/alliance/src/cells/src/sxlib/o4_x4.al b/alliance/src/cells/src/sxlib/o4_x4.al new file mode 100644 index 00000000..9b33d0a1 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o4_x4.al @@ -0,0 +1,44 @@ +V ALLIANCE : 6 +H o4_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,10 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,5,7,6,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00012 +T P,0.35,5.9,3,8,4,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00011 +T P,0.35,5.9,4,10,1,0,0.75,0.75,13.3,13.3,3,11.25,tr_00010 +T P,0.35,5.9,6,9,3,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,5,1,11,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00008 +T P,0.35,5.9,11,1,5,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00007 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00006 +T N,0.35,1.4,2,10,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005 +T N,0.35,1.4,2,9,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004 +T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003 +T N,0.35,2.9,11,1,2,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002 +T N,0.35,2.9,2,1,11,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00001 +S 11,EXTERNAL,q +Q 0.00343717 +S 10,EXTERNAL,i1 +Q 0.00317863 +S 9,EXTERNAL,i2 +Q 0.00332901 +S 8,EXTERNAL,i0 +Q 0.0032596 +S 7,EXTERNAL,i3 +Q 0.00282737 +S 6,INTERNAL +Q 0 +S 5,EXTERNAL,vdd +Q 0.00524395 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.00471516 +S 1,INTERNAL +Q 0.00811076 +EOF diff --git a/alliance/src/cells/src/sxlib/o4_x4.ap b/alliance/src/cells/src/sxlib/o4_x4.ap new file mode 100644 index 00000000..dc223427 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o4_x4.ap @@ -0,0 +1,122 @@ +V ALLIANCE : 6 +H o4_x4,P,30/ 8/2000,100 +A 0,0,4000,5000 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2500,3500,ref_ref,i3_35 +R 2500,4000,ref_ref,i3_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 1500,4000,ref_ref,i0_40 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 2000,4000,ref_ref,i2_40 +R 3500,2500,ref_ref,q_25 +R 3500,2000,ref_ref,q_20 +R 3500,1500,ref_ref,q_15 +R 3500,1000,ref_ref,q_10 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 3000,3000,ref_ref,q_30 +S 2550,300,2550,1200,200,*,UP,NDIF +S 2300,1400,2400,1400,100,*,RIGHT,POLY +S 1700,1400,1900,1400,100,*,RIGHT,POLY +S 2300,600,2300,1400,100,*,DOWN,NTRANS +S 2000,1000,2500,1000,200,*,RIGHT,ALU1 +S 1700,600,1700,1400,100,*,DOWN,NTRANS +S 1450,250,1450,1200,200,*,UP,NDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 500,1000,500,3000,100,*,DOWN,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 300,400,300,1200,300,*,UP,NDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2000,1500,2000,4000,100,*,UP,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,2400,1100,2400,100,*,LEFT,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 2800,2600,2800,4900,100,*,DOWN,PTRANS +S 3400,2600,3400,4900,100,*,DOWN,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3100,2800,3100,4700,300,*,UP,PDIF +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 2800,100,2800,1400,100,*,UP,NTRANS +S 3400,100,3400,1400,100,*,UP,NTRANS +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 3100,300,3100,1200,300,*,DOWN,NDIF +S 2500,1500,3000,1500,100,*,LEFT,ALU1 +S 2500,1000,2500,1500,100,*,DOWN,ALU1 +S 500,1000,2500,1000,100,*,LEFT,ALU1 +S 2500,2000,2500,4000,100,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 2800,2600,3400,2600,100,*,RIGHT,POLY +S 2800,1400,3400,1400,100,*,RIGHT,POLY +S 3000,1500,3000,2500,100,*,DOWN,ALU1 +S 3100,1000,3500,1000,200,*,RIGHT,ALU1 +S 500,3000,500,4000,100,*,UP,ALU1 +S 3500,1000,3500,3050,200,*,DOWN,ALU1 +S 3100,3000,3500,3000,200,*,LEFT,ALU1 +S 3700,3500,3700,4500,200,*,UP,ALU1 +S 500,1000,900,1000,200,*,LEFT,ALU1 +S 2500,2000,2500,4000,200,i3,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 2000,1500,2000,4000,200,i2,DOWN,CALU1 +S 3000,3000,3000,4000,200,*,UP,ALU1 +S 3500,1000,3500,3000,200,q,DOWN,CALU1 +S 3000,3000,3000,4000,200,q,DOWN,CALU1 +V 2000,2000,CONT_POLY,* +V 2000,1000,CONT_DIF_N,* +V 1500,300,CONT_DIF_N,* +V 500,3000,CONT_DIF_P,* +V 2500,2000,CONT_POLY,* +V 900,1000,CONT_DIF_N,* +V 300,4700,CONT_BODY_N,* +V 300,500,CONT_DIF_N,* +V 900,300,CONT_BODY_P,* +V 1000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3700,4500,CONT_DIF_P,* +V 3700,500,CONT_DIF_N,* +V 3000,1500,CONT_POLY,* +V 2500,4500,CONT_DIF_P,* +V 2500,300,CONT_DIF_N,* +V 3000,2500,CONT_POLY,* +V 3100,1000,CONT_DIF_N,* +V 3100,3000,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 3100,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/o4_x4.sym b/alliance/src/cells/src/sxlib/o4_x4.sym new file mode 100644 index 00000000..390104b3 Binary files /dev/null and b/alliance/src/cells/src/sxlib/o4_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/o4_x4.vbe b/alliance/src/cells/src/sxlib/o4_x4.vbe new file mode 100644 index 00000000..bc869a8f --- /dev/null +++ b/alliance/src/cells/src/sxlib/o4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 492; + CONSTANT tpll_i3_q : NATURAL := 536; + CONSTANT tphh_i0_q : NATURAL := 574; + CONSTANT tpll_i2_q : NATURAL := 611; + CONSTANT tpll_i0_q : NATURAL := 638; + CONSTANT tphh_i2_q : NATURAL := 649; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 721; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x4; + +ARCHITECTURE behaviour_data_flow OF o4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x4" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/o4_x4.vhd b/alliance/src/cells/src/sxlib/o4_x4.vhd new file mode 100644 index 00000000..240d2176 --- /dev/null +++ b/alliance/src/cells/src/sxlib/o4_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o4_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o4_x4; + +ARCHITECTURE RTL OF o4_x4 IS +BEGIN + q <= (((i0 OR i1) OR i2) OR i3); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa22_x2.al b/alliance/src/cells/src/sxlib/oa22_x2.al new file mode 100644 index 00000000..fea0e23c --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa22_x2.al @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H oa22_x2,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,6 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,2.9,1,6,9,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,2.9,9,8,1,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T P,0.35,2.9,9,7,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006 +T P,0.35,5.9,5,1,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005 +T N,0.35,1.4,1,6,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004 +T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,2.9,4,1,2,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00001 +S 9,INTERNAL +Q 0.00171257 +S 8,EXTERNAL,i0 +Q 0.00295461 +S 7,EXTERNAL,i2 +Q 0.00383259 +S 6,EXTERNAL,i1 +Q 0.00270208 +S 5,EXTERNAL,vdd +Q 0.00367968 +S 4,EXTERNAL,q +Q 0.00358405 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.00367968 +S 1,INTERNAL +Q 0.00439855 +EOF diff --git a/alliance/src/cells/src/sxlib/oa22_x2.ap b/alliance/src/cells/src/sxlib/oa22_x2.ap new file mode 100644 index 00000000..abc74245 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa22_x2.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 6 +H oa22_x2,P,30/ 8/2000,100 +A 0,0,3000,5000 +R 2500,4000,ref_ref,q_40 +R 2500,3500,ref_ref,q_35 +R 2500,3000,ref_ref,q_30 +R 2500,2500,ref_ref,q_25 +R 2500,2000,ref_ref,q_20 +R 2500,1500,ref_ref,q_15 +R 2500,1000,ref_ref,q_10 +R 2000,1000,ref_ref,i2_10 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 2000,4000,ref_ref,i2_40 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,100,*,UP,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 900,3500,1500,3500,100,*,RIGHT,ALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 600,1400,600,3100,100,*,UP,POLY +S 2400,1400,2400,2600,100,*,UP,POLY +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 900,800,900,1200,300,*,DOWN,NDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1800,600,1800,1400,100,*,UP,NTRANS +S 300,400,300,1200,300,*,DOWN,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 1500,3300,1500,4200,300,*,UP,PDIF +S 300,3300,300,4200,300,*,UP,PDIF +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2400,2600,2400,4900,100,*,DOWN,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 2500,4000,2700,4000,200,*,RIGHT,ALU1 +S 2500,3500,2700,3500,200,*,RIGHT,ALU1 +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +S 2500,1000,2700,1000,200,*,RIGHT,ALU1 +S 1800,2500,2000,2500,300,*,RIGHT,POLY +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1000,1500,1200,1500,300,*,RIGHT,POLY +S 1000,3000,1200,3000,300,*,RIGHT,POLY +S 1500,2000,2400,2000,100,*,RIGHT,POLY +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +V 500,2000,CONT_POLY,* +V 1500,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 2700,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 900,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 2700,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 300,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa22_x2.sym b/alliance/src/cells/src/sxlib/oa22_x2.sym new file mode 100644 index 00000000..803280de Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa22_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/oa22_x2.vbe b/alliance/src/cells/src/sxlib/oa22_x2.vbe new file mode 100644 index 00000000..d2d26760 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 390; + CONSTANT tphh_i2_q : NATURAL := 438; + CONSTANT tpll_i2_q : NATURAL := 454; + CONSTANT tphh_i1_q : NATURAL := 488; + CONSTANT tpll_i1_q : NATURAL := 525; + CONSTANT tpll_i0_q : NATURAL := 555; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x2; + +ARCHITECTURE behaviour_data_flow OF oa22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa22_x2.vhd b/alliance/src/cells/src/sxlib/oa22_x2.vhd new file mode 100644 index 00000000..882c5eac --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa22_x2.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa22_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa22_x2; + +ARCHITECTURE RTL OF oa22_x2 IS +BEGIN + q <= ((i0 AND i1) OR i2); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa22_x4.al b/alliance/src/cells/src/sxlib/oa22_x4.al new file mode 100644 index 00000000..63de95c1 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa22_x4.al @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H oa22_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,2.9,9,7,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010 +T P,0.35,2.9,9,6,3,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009 +T P,0.35,2.9,3,8,9,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,8.1,11.25,tr_00007 +T P,0.35,5.9,4,3,5,0,0.75,0.75,13.3,13.3,9.9,11.25,tr_00006 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00005 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004 +T N,0.35,1.4,3,8,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003 +T N,0.35,2.9,2,3,4,0,0.75,0.75,7.3,7.3,9.9,2.25,tr_00002 +T N,0.35,2.9,4,3,2,0,0.75,0.75,7.3,7.3,8.1,2.25,tr_00001 +S 9,INTERNAL +Q 0.00114171 +S 8,EXTERNAL,i1 +Q 0.00270208 +S 7,EXTERNAL,i2 +Q 0.00383259 +S 6,EXTERNAL,i0 +Q 0.00295461 +S 5,EXTERNAL,vdd +Q 0.00606652 +S 4,EXTERNAL,q +Q 0.00258522 +S 3,INTERNAL +Q 0.00611125 +S 2,EXTERNAL,vss +Q 0.00512644 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/oa22_x4.ap b/alliance/src/cells/src/sxlib/oa22_x4.ap new file mode 100644 index 00000000..7fd5a166 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa22_x4.ap @@ -0,0 +1,105 @@ +V ALLIANCE : 6 +H oa22_x4,P,30/ 8/2000,100 +A 0,0,4000,5000 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 2000,1000,ref_ref,i2_10 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 3000,3000,ref_ref,q_30 +R 3000,2500,ref_ref,q_25 +R 3000,2000,ref_ref,q_20 +R 3000,1500,ref_ref,q_15 +R 3000,1000,ref_ref,q_10 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 1000,3000,1200,3000,300,*,RIGHT,POLY +S 1000,1500,1200,1500,300,*,RIGHT,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 1800,2500,2000,2500,300,*,RIGHT,POLY +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1500,3300,1500,4200,300,*,UP,PDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 300,400,300,1200,300,*,DOWN,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 600,600,600,1400,100,*,UP,NTRANS +S 900,800,900,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 600,1400,600,3100,100,*,UP,POLY +S 900,3500,1500,3500,100,*,RIGHT,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 1000,1000,1000,3000,100,*,UP,ALU1 +S 3600,3000,3600,4500,200,*,UP,ALU1 +S 3600,500,3600,1000,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3300,1400,3300,2600,100,*,DOWN,POLY +S 2700,1400,2700,2600,100,*,UP,POLY +S 3600,300,3600,1200,300,*,DOWN,NDIF +S 3300,100,3300,1400,100,*,UP,NTRANS +S 3000,300,3000,1200,300,*,DOWN,NDIF +S 2700,100,2700,1400,100,*,UP,NTRANS +S 2700,2600,2700,4900,100,*,DOWN,PTRANS +S 3000,2800,3000,4700,300,*,UP,PDIF +S 3600,2800,3600,4700,300,*,UP,PDIF +S 3300,2600,3300,4900,100,*,DOWN,PTRANS +S 2300,2800,2300,4700,300,*,UP,PDIF +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 1500,2000,3300,2000,200,*,RIGHT,POLY +V 2300,500,CONT_DIF_N,* +V 2300,4500,CONT_DIF_P,* +V 1500,2000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 300,4700,CONT_BODY_N,* +V 900,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 900,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 3600,500,CONT_DIF_N,* +V 3600,1000,CONT_DIF_N,* +V 3000,1000,CONT_DIF_N,* +V 3600,4000,CONT_DIF_P,* +V 3600,4500,CONT_DIF_P,* +V 3000,3000,CONT_DIF_P,* +V 3000,3500,CONT_DIF_P,* +V 3000,4000,CONT_DIF_P,* +V 3600,3000,CONT_DIF_P,* +V 3600,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa22_x4.sym b/alliance/src/cells/src/sxlib/oa22_x4.sym new file mode 100644 index 00000000..50b52fb7 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa22_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/oa22_x4.vbe b/alliance/src/cells/src/sxlib/oa22_x4.vbe new file mode 100644 index 00000000..fa425e33 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 511; + CONSTANT tphh_i2_q : NATURAL := 523; + CONSTANT tpll_i2_q : NATURAL := 571; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tpll_i0_q : NATURAL := 677; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x4; + +ARCHITECTURE behaviour_data_flow OF oa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa22_x4.vhd b/alliance/src/cells/src/sxlib/oa22_x4.vhd new file mode 100644 index 00000000..3c61d808 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa22_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa22_x4; + +ARCHITECTURE RTL OF oa22_x4 IS +BEGIN + q <= ((i0 AND i1) OR i2); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa2a22_x2.al b/alliance/src/cells/src/sxlib/oa2a22_x2.al new file mode 100644 index 00000000..e82135ab --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a22_x2.al @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H oa2a22_x2,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,5 +C i2,IN,EXTERNAL,7 +C i3,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,9 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,11,5,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00010 +T P,0.35,2.9,11,8,10,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00009 +T P,0.35,2.9,10,7,11,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00008 +T P,0.35,2.9,3,6,11,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T P,0.35,5.9,9,3,10,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00006 +T N,0.35,1.4,2,5,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00005 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004 +T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00003 +T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,2.9,1,3,9,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00001 +S 11,INTERNAL +Q 0.00199441 +S 10,EXTERNAL,vdd +Q 0.00564418 +S 9,EXTERNAL,q +Q 0.00258522 +S 8,EXTERNAL,i3 +Q 0.00295462 +S 7,EXTERNAL,i2 +Q 0.00323197 +S 6,EXTERNAL,i0 +Q 0.00295462 +S 5,EXTERNAL,i1 +Q 0.00323197 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00577862 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00564418 +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a22_x2.ap b/alliance/src/cells/src/sxlib/oa2a22_x2.ap new file mode 100644 index 00000000..45e3abf5 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a22_x2.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H oa2a22_x2,P, 6/ 9/2000,100 +A 0,0,4500,5000 +R 4000,2500,ref_ref,q_25 +R 4000,1500,ref_ref,q_15 +R 4000,1000,ref_ref,q_10 +R 4000,2000,ref_ref,q_20 +R 4000,3000,ref_ref,q_30 +R 4000,3500,ref_ref,q_35 +R 4000,4000,ref_ref,q_40 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 2000,1000,ref_ref,i2_10 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2500,3000,ref_ref,i3_30 +R 2500,2500,ref_ref,i3_25 +R 2500,2000,ref_ref,i3_20 +R 2500,1500,ref_ref,i3_15 +R 2500,1000,ref_ref,i3_10 +S 3500,2000,3700,2000,300,*,RIGHT,POLY +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 3500,2000,3500,3500,100,*,DOWN,ALU1 +S 900,3500,3500,3500,100,*,RIGHT,ALU1 +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 4000,300,4000,1200,300,*,UP,NDIF +S 3400,300,3400,1200,300,*,UP,NDIF +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 2000,1000,2000,3000,100,*,DOWN,ALU1 +S 2500,1000,2500,3000,100,*,DOWN,ALU1 +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 2700,3300,2700,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 300,400,300,1200,300,*,UP,NDIF +S 2700,400,2700,1200,300,*,UP,NDIF +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 2000,1000,2000,3000,200,i2,DOWN,CALU1 +S 2500,1000,2500,3000,200,i3,DOWN,CALU1 +V 2100,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 2700,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 3400,4000,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 3400,500,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 3500,2000,CONT_POLY,* +V 1500,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2700,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1500,300,CONT_BODY_P,* +V 300,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a22_x2.sym b/alliance/src/cells/src/sxlib/oa2a22_x2.sym new file mode 100644 index 00000000..44737138 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa2a22_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/oa2a22_x2.vbe b/alliance/src/cells/src/sxlib/oa2a22_x2.vbe new file mode 100644 index 00000000..1c5c4088 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 403; + CONSTANT tpll_i2_q : NATURAL := 487; + CONSTANT tphh_i1_q : NATURAL := 495; + CONSTANT tpll_i3_q : NATURAL := 512; + CONSTANT tpll_i1_q : NATURAL := 534; + CONSTANT tphh_i3_q : NATURAL := 537; + CONSTANT tpll_i0_q : NATURAL := 564; + CONSTANT tphh_i2_q : NATURAL := 646; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa2a22_x2.vhd b/alliance/src/cells/src/sxlib/oa2a22_x2.vhd new file mode 100644 index 00000000..fc749b4f --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a22_x2.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a22_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a22_x2; + +ARCHITECTURE RTL OF oa2a22_x2 IS +BEGIN + q <= ((i0 AND i1) OR (i2 AND i3)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa2a22_x4.al b/alliance/src/cells/src/sxlib/oa2a22_x4.al new file mode 100644 index 00000000..1d11346d --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a22_x4.al @@ -0,0 +1,44 @@ +V ALLIANCE : 6 +H oa2a22_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,5 +C i2,IN,EXTERNAL,6 +C i3,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,9 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,9,4,10,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00012 +T P,0.35,5.9,10,4,9,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00011 +T P,0.35,2.9,4,7,11,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010 +T P,0.35,2.9,10,6,11,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00009 +T P,0.35,2.9,11,8,10,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00008 +T P,0.35,2.9,11,5,4,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00007 +T N,0.35,2.9,1,4,9,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00006 +T N,0.35,2.9,9,4,1,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00005 +T N,0.35,1.4,4,6,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004 +T N,0.35,1.4,3,8,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00003 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00002 +T N,0.35,1.4,2,5,4,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001 +S 11,INTERNAL +Q 0.00199441 +S 10,EXTERNAL,vdd +Q 0.00768955 +S 9,EXTERNAL,q +Q 0.00258522 +S 8,EXTERNAL,i3 +Q 0.00295462 +S 7,EXTERNAL,i0 +Q 0.00295462 +S 6,EXTERNAL,i2 +Q 0.00323197 +S 5,EXTERNAL,i1 +Q 0.00323197 +S 4,INTERNAL +Q 0.00732866 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00674947 +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a22_x4.ap b/alliance/src/cells/src/sxlib/oa2a22_x4.ap new file mode 100644 index 00000000..0954420e --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a22_x4.ap @@ -0,0 +1,123 @@ +V ALLIANCE : 6 +H oa2a22_x4,P,30/ 8/2000,100 +A 0,0,5000,5000 +R 4000,2500,ref_ref,q_25 +R 4000,1500,ref_ref,q_15 +R 4000,1000,ref_ref,q_10 +R 4000,2000,ref_ref,q_20 +R 4000,3000,ref_ref,q_30 +R 4000,3500,ref_ref,q_35 +R 4000,4000,ref_ref,q_40 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 2000,1000,ref_ref,i2_10 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2500,3000,ref_ref,i3_30 +R 2500,2500,ref_ref,i3_25 +R 2500,2000,ref_ref,i3_20 +R 2500,1500,ref_ref,i3_15 +R 2500,1000,ref_ref,i3_10 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 2000,1000,2000,3000,200,i2,DOWN,CALU1 +S 2500,1000,2500,3000,200,i3,DOWN,CALU1 +S 3500,2000,4300,2000,100,*,RIGHT,POLY +S 3500,2000,3500,3500,100,*,DOWN,ALU1 +S 900,3500,3500,3500,100,*,RIGHT,ALU1 +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4600,300,4600,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 4000,300,4000,1200,300,*,UP,NDIF +S 3400,300,3400,1200,300,*,UP,NDIF +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 2000,1000,2000,3000,100,*,DOWN,ALU1 +S 2500,1000,2500,3000,100,*,DOWN,ALU1 +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 2700,3300,2700,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 300,400,300,1200,300,*,UP,NDIF +S 2700,400,2700,1200,300,*,UP,NDIF +V 2100,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 2700,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 4600,3000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 3400,4000,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 4600,1000,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 3500,2000,CONT_POLY,* +V 1500,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2700,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1500,300,CONT_BODY_P,* +V 300,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a22_x4.sym b/alliance/src/cells/src/sxlib/oa2a22_x4.sym new file mode 100644 index 00000000..cc180c20 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa2a22_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/oa2a22_x4.vbe b/alliance/src/cells/src/sxlib/oa2a22_x4.vbe new file mode 100644 index 00000000..a233499c --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 519; + CONSTANT tpll_i2_q : NATURAL := 596; + CONSTANT tpll_i3_q : NATURAL := 619; + CONSTANT tphh_i1_q : NATURAL := 624; + CONSTANT tphh_i3_q : NATURAL := 644; + CONSTANT tpll_i1_q : NATURAL := 669; + CONSTANT tpll_i0_q : NATURAL := 696; + CONSTANT tphh_i2_q : NATURAL := 763; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa2a22_x4.vhd b/alliance/src/cells/src/sxlib/oa2a22_x4.vhd new file mode 100644 index 00000000..9cf43446 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a22_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a22_x4; + +ARCHITECTURE RTL OF oa2a22_x4 IS +BEGIN + q <= ((i0 AND i1) OR (i2 AND i3)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa2a2a23_x2.al b/alliance/src/cells/src/sxlib/oa2a2a23_x2.al new file mode 100644 index 00000000..bcf6fd25 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a23_x2.al @@ -0,0 +1,56 @@ +V ALLIANCE : 6 +H oa2a2a23_x2,L,30/10/99 +C i0,IN,EXTERNAL,15 +C i1,IN,EXTERNAL,14 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,5,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00014 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00013 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00012 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00011 +T P,0.35,5.9,6,14,13,0,0.75,0.75,13.3,13.3,12,11.25,tr_00010 +T P,0.35,5.9,13,15,6,0,0.75,0.75,13.3,13.3,13.8,11.25,tr_00009 +T P,0.35,5.9,12,2,13,0,0.75,0.75,13.3,13.3,15.6,11.25,tr_00008 +T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00007 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00005 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,11,14,2,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00003 +T N,0.35,2.9,1,15,11,0,0.75,0.75,7.3,7.3,13.8,2.25,tr_00002 +T N,0.35,2.9,12,2,1,0,0.75,0.75,7.3,7.3,15.6,2.25,tr_00001 +S 15,EXTERNAL,i0 +Q 0.00232574 +S 14,EXTERNAL,i1 +Q 0.00247612 +S 13,EXTERNAL,vdd +Q 0.0071974 +S 12,EXTERNAL,q +Q 0.00264397 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i5 +Q 0.00276531 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i3 +Q 0.00262649 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.0021 +S 5,INTERNAL +Q 0.00199441 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.0070541 +S 1,EXTERNAL,vss +Q 0.00572853 +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a2a23_x2.ap b/alliance/src/cells/src/sxlib/oa2a2a23_x2.ap new file mode 100644 index 00000000..afcf715b --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a23_x2.ap @@ -0,0 +1,135 @@ +V ALLIANCE : 6 +H oa2a2a23_x2,P, 6/ 9/2000,100 +A 0,0,6000,5000 +R 4500,1500,ref_ref,i0_15 +R 4500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i1_30 +R 4000,2500,ref_ref,i1_25 +R 4000,1500,ref_ref,i1_15 +R 4000,2000,ref_ref,i1_20 +R 4500,2500,ref_ref,i0_25 +R 4500,2000,ref_ref,i0_20 +R 5500,1000,ref_ref,q_10 +R 5500,1500,ref_ref,q_15 +R 5500,3500,ref_ref,q_35 +R 5500,3000,ref_ref,q_30 +R 5500,2500,ref_ref,q_25 +R 5500,2000,ref_ref,q_20 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,2500,ref_ref,i4_25 +R 1500,2000,ref_ref,i4_20 +R 1500,1500,ref_ref,i4_15 +R 2000,2000,ref_ref,i3_20 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,1500,ref_ref,i3_15 +R 1000,1500,ref_ref,i5_15 +R 1000,3000,ref_ref,i5_30 +R 1000,2500,ref_ref,i5_25 +R 1000,2000,ref_ref,i5_20 +R 5500,4000,ref_ref,q_40 +S 5000,2000,5200,2000,300,*,RIGHT,POLY +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 5200,1400,5200,2600,100,*,DOWN,POLY +S 5000,1000,5000,2000,100,*,UP,ALU1 +S 500,1000,5000,1000,100,*,RIGHT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2100,3500,4300,3500,100,*,RIGHT,ALU1 +S 4000,1400,4200,1400,100,*,LEFT,POLY +S 4600,1400,4600,2600,100,*,DOWN,POLY +S 4000,1400,4000,2500,100,*,UP,POLY +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 5200,2600,5200,4900,100,*,UP,PTRANS +S 5500,2800,5500,4700,300,*,UP,PDIF +S 4900,2800,4900,4700,300,*,UP,PDIF +S 4300,2800,4300,4700,300,*,UP,PDIF +S 4600,2600,4600,4900,100,*,UP,PTRANS +S 4000,2600,4000,4900,100,*,UP,PTRANS +S 3700,2800,3700,4100,300,*,UP,PDIF +S 4900,300,4900,1200,300,*,DOWN,NDIF +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5200,100,5200,1400,100,*,UP,NTRANS +S 4600,100,4600,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 5500,950,5500,4050,200,*,DOWN,ALU1 +S 3700,4000,3700,4700,200,*,UP,ALU1 +S 4300,3500,4300,4000,100,*,UP,ALU1 +S 4900,3500,4900,4600,200,*,DOWN,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 900,1400,900,2600,100,*,DOWN,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 4500,1500,4500,3000,200,i0,DOWN,CALU1 +S 4000,1500,4000,3000,200,i1,DOWN,CALU1 +S 5500,1000,5500,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +V 5000,2000,CONT_POLY,* +V 3300,4600,CONT_BODY_N,* +V 3200,400,CONT_BODY_P,* +V 4000,2500,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 5500,3000,CONT_DIF_P,* +V 5500,3500,CONT_DIF_P,* +V 5500,4000,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 4900,4500,CONT_DIF_P,* +V 4900,3500,CONT_DIF_P,* +V 4300,4000,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 5500,1000,CONT_DIF_N,* +V 4900,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a2a23_x2.sym b/alliance/src/cells/src/sxlib/oa2a2a23_x2.sym new file mode 100644 index 00000000..5bd6e787 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa2a2a23_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/oa2a2a23_x2.vbe b/alliance/src/cells/src/sxlib/oa2a2a23_x2.vbe new file mode 100644 index 00000000..189ed715 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a23_x2.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT tphh_i5_q : NATURAL := 321; + CONSTANT tphh_i4_q : NATURAL := 402; + CONSTANT tphh_i2_q : NATURAL := 441; + CONSTANT tphh_i3_q : NATURAL := 540; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT tpll_i4_q : NATURAL := 591; + CONSTANT tpll_i3_q : NATURAL := 600; + CONSTANT tpll_i5_q : NATURAL := 636; + CONSTANT tpll_i2_q : NATURAL := 639; + CONSTANT tphh_i0_q : NATURAL := 653; + CONSTANT tphh_i1_q : NATURAL := 775; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x2" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa2a2a23_x2.vhd b/alliance/src/cells/src/sxlib/oa2a2a23_x2.vhd new file mode 100644 index 00000000..fc4cca2e --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a23_x2.vhd @@ -0,0 +1,24 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a2a23_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a2a23_x2; + +ARCHITECTURE RTL OF oa2a2a23_x2 IS +BEGIN + q <= (((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa2a2a23_x4.al b/alliance/src/cells/src/sxlib/oa2a2a23_x4.al new file mode 100644 index 00000000..5b478925 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a23_x4.al @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H oa2a2a23_x4,L,30/10/99 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,15 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,10 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,12,4,13,0,0.75,0.75,13.3,13.3,15.6,11.25,tr_00016 +T P,0.35,5.9,13,4,12,0,0.75,0.75,13.3,13.3,17.4,11.25,tr_00015 +T P,0.35,5.9,13,14,5,0,0.75,0.75,13.3,13.3,13.8,11.25,tr_00014 +T P,0.35,5.9,5,15,13,0,0.75,0.75,13.3,13.3,12,11.25,tr_00013 +T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012 +T P,0.35,5.9,6,9,5,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,4,8,6,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00010 +T P,0.35,5.9,6,7,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009 +T N,0.35,2.9,12,4,1,0,0.75,0.75,7.3,7.3,15.6,2.25,tr_00008 +T N,0.35,2.9,12,4,1,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00007 +T N,0.35,2.9,1,14,11,0,0.75,0.75,7.3,7.3,13.8,2.25,tr_00006 +T N,0.35,2.9,11,15,4,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,10,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 15,EXTERNAL,i1 +Q 0.00247612 +S 14,EXTERNAL,i0 +Q 0.00232574 +S 13,EXTERNAL,vdd +Q 0.00883149 +S 12,EXTERNAL,q +Q 0.00264397 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i3 +Q 0.00262649 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i5 +Q 0.0027653 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00199441 +S 5,INTERNAL +Q 0.0021 +S 4,INTERNAL +Q 0.00860414 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00695133 +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a2a23_x4.ap b/alliance/src/cells/src/sxlib/oa2a2a23_x4.ap new file mode 100644 index 00000000..bef2d02c --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a23_x4.ap @@ -0,0 +1,147 @@ +V ALLIANCE : 6 +H oa2a2a23_x4,P,30/ 8/2000,100 +A 0,0,6500,5000 +R 4500,1500,ref_ref,i0_15 +R 4500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i1_30 +R 4000,2500,ref_ref,i1_25 +R 4000,1500,ref_ref,i1_15 +R 4000,2000,ref_ref,i1_20 +R 4500,2500,ref_ref,i0_25 +R 4500,2000,ref_ref,i0_20 +R 5500,1000,ref_ref,q_10 +R 5500,1500,ref_ref,q_15 +R 5500,3500,ref_ref,q_35 +R 5500,3000,ref_ref,q_30 +R 5500,2500,ref_ref,q_25 +R 5500,2000,ref_ref,q_20 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,2500,ref_ref,i4_25 +R 1500,2000,ref_ref,i4_20 +R 1500,1500,ref_ref,i4_15 +R 2000,2000,ref_ref,i3_20 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,1500,ref_ref,i3_15 +R 1000,1500,ref_ref,i5_15 +R 1000,3000,ref_ref,i5_30 +R 1000,2500,ref_ref,i5_25 +R 1000,2000,ref_ref,i5_20 +R 5500,4000,ref_ref,q_40 +S 4000,1500,4000,3000,200,i1,DOWN,CALU1 +S 4500,1500,4500,3000,200,i0,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +S 5500,1000,5500,4000,200,q,DOWN,CALU1 +S 5000,2000,5800,2000,100,*,RIGHT,POLY +S 5800,1400,5800,2600,100,*,DOWN,POLY +S 5200,1400,5200,2600,100,*,DOWN,POLY +S 5000,1000,5000,2000,100,*,UP,ALU1 +S 500,1000,5000,1000,100,*,RIGHT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2100,3500,4300,3500,100,*,RIGHT,ALU1 +S 4000,1400,4200,1400,100,*,LEFT,POLY +S 4600,1400,4600,2600,100,*,DOWN,POLY +S 4000,1400,4000,2500,100,*,UP,POLY +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 5200,2600,5200,4900,100,*,UP,PTRANS +S 5800,2600,5800,4900,100,*,UP,PTRANS +S 5500,2800,5500,4700,300,*,UP,PDIF +S 6100,2800,6100,4700,300,*,UP,PDIF +S 4900,2800,4900,4700,300,*,UP,PDIF +S 4300,2800,4300,4700,300,*,UP,PDIF +S 4600,2600,4600,4900,100,*,UP,PTRANS +S 4000,2600,4000,4900,100,*,UP,PTRANS +S 3700,2800,3700,4100,300,*,UP,PDIF +S 4900,300,4900,1200,300,*,DOWN,NDIF +S 6100,300,6100,1200,300,*,DOWN,NDIF +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5200,100,5200,1400,100,*,UP,NTRANS +S 5800,100,5800,1400,100,*,DOWN,NTRANS +S 4600,100,4600,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 5500,950,5500,4050,200,*,DOWN,ALU1 +S 6100,300,6100,1000,200,*,DOWN,ALU1 +S 6100,3500,6100,4600,200,*,DOWN,ALU1 +S 3700,4000,3700,4700,200,*,UP,ALU1 +S 4300,3500,4300,4000,100,*,UP,ALU1 +S 4900,3500,4900,4600,200,*,DOWN,ALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 900,1400,900,2600,100,*,DOWN,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +V 5000,2000,CONT_POLY,* +V 3300,4600,CONT_BODY_N,* +V 3200,400,CONT_BODY_P,* +V 4000,2500,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 6100,3500,CONT_DIF_P,* +V 6100,4500,CONT_DIF_P,* +V 6100,4000,CONT_DIF_P,* +V 5500,3000,CONT_DIF_P,* +V 5500,3500,CONT_DIF_P,* +V 5500,4000,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 4900,4500,CONT_DIF_P,* +V 4900,3500,CONT_DIF_P,* +V 4300,4000,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 6100,500,CONT_DIF_N,* +V 6100,1000,CONT_DIF_N,* +V 5500,1000,CONT_DIF_N,* +V 4900,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a2a23_x4.sym b/alliance/src/cells/src/sxlib/oa2a2a23_x4.sym new file mode 100644 index 00000000..19dec265 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa2a2a23_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/oa2a2a23_x4.vbe b/alliance/src/cells/src/sxlib/oa2a2a23_x4.vbe new file mode 100644 index 00000000..c39f56f9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT tphh_i5_q : NATURAL := 379; + CONSTANT tphh_i4_q : NATURAL := 464; + CONSTANT tphh_i2_q : NATURAL := 493; + CONSTANT tphh_i3_q : NATURAL := 594; + CONSTANT tpll_i1_q : NATURAL := 613; + CONSTANT tpll_i0_q : NATURAL := 648; + CONSTANT tpll_i4_q : NATURAL := 673; + CONSTANT tpll_i3_q : NATURAL := 677; + CONSTANT tphh_i0_q : NATURAL := 699; + CONSTANT tpll_i5_q : NATURAL := 714; + CONSTANT tpll_i2_q : NATURAL := 715; + CONSTANT tphh_i1_q : NATURAL := 822; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x4" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa2a2a23_x4.vhd b/alliance/src/cells/src/sxlib/oa2a2a23_x4.vhd new file mode 100644 index 00000000..61d3a82a --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a23_x4.vhd @@ -0,0 +1,24 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a2a23_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a2a23_x4; + +ARCHITECTURE RTL OF oa2a2a23_x4 IS +BEGIN + q <= (((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.al b/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.al new file mode 100644 index 00000000..56c387c7 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.al @@ -0,0 +1,70 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x2,L,30/10/99 +C i0,IN,EXTERNAL,19 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,15 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,10 +C i5,IN,EXTERNAL,9 +C i6,IN,EXTERNAL,8 +C i7,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,18 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,18,1,14,0,0.75,0.75,13.3,13.3,20.4,11.25,tr_00018 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.8,11.25,tr_00017 +T P,0.35,5.9,14,19,13,0,0.75,0.75,13.3,13.3,18.6,11.25,tr_00016 +T P,0.35,5.9,13,16,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00015 +T P,0.35,5.9,1,7,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00014 +T P,0.35,5.9,6,15,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00013 +T P,0.35,5.9,6,10,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,5,8,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00009 +T N,0.35,2.9,4,15,12,0,0.75,0.75,7.3,7.3,12,2.25,tr_00008 +T N,0.35,2.9,11,17,1,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00007 +T N,0.35,2.9,4,19,11,0,0.75,0.75,7.3,7.3,18.6,2.25,tr_00006 +T N,0.35,2.9,18,1,4,0,0.75,0.75,7.3,7.3,20.4,2.25,tr_00005 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004 +T N,0.35,2.9,12,16,1,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00003 +T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 19,EXTERNAL,i0 +Q 0.00261741 +S 18,EXTERNAL,q +Q 0.00264397 +S 17,EXTERNAL,i1 +Q 0.00210054 +S 16,EXTERNAL,i3 +Q 0.00232574 +S 15,EXTERNAL,i2 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00769303 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i4 +Q 0.00232574 +S 9,EXTERNAL,i5 +Q 0.00232574 +S 8,EXTERNAL,i6 +Q 0.00269068 +S 7,EXTERNAL,i7 +Q 0.00260759 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,EXTERNAL,vss +Q 0.00692922 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00855851 +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.ap b/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.ap new file mode 100644 index 00000000..4f989559 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.ap @@ -0,0 +1,171 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x2,P,30/ 8/2000,100 +A 0,0,7500,5000 +R 6500,3500,ref_ref,i0_35 +R 5500,2000,ref_ref,i1_20 +R 5500,2500,ref_ref,i1_25 +R 5500,3000,ref_ref,i1_30 +R 5500,1500,ref_ref,i1_15 +R 6500,1500,ref_ref,i0_15 +R 6500,2000,ref_ref,i0_20 +R 6500,2500,ref_ref,i0_25 +R 6500,3000,ref_ref,i0_30 +R 7000,1000,ref_ref,q_10 +R 7000,4000,ref_ref,q_40 +R 7000,2000,ref_ref,q_20 +R 7000,1500,ref_ref,q_15 +R 7000,3500,ref_ref,q_35 +R 7000,3000,ref_ref,q_30 +R 7000,2500,ref_ref,q_25 +R 500,1000,ref_ref,i7_10 +R 500,1500,ref_ref,i7_15 +R 500,2000,ref_ref,i7_20 +R 500,2500,ref_ref,i7_25 +R 500,3000,ref_ref,i7_30 +R 1500,1500,ref_ref,i6_15 +R 1500,2000,ref_ref,i6_20 +R 1500,2500,ref_ref,i6_25 +R 1500,3000,ref_ref,i6_30 +R 2500,1500,ref_ref,i5_15 +R 2500,2000,ref_ref,i5_20 +R 2500,2500,ref_ref,i5_25 +R 2500,3000,ref_ref,i5_30 +R 3000,1500,ref_ref,i4_15 +R 3000,2000,ref_ref,i4_20 +R 3000,2500,ref_ref,i4_25 +R 3000,3000,ref_ref,i4_30 +R 3500,1500,ref_ref,i3_15 +R 3500,2000,ref_ref,i3_20 +R 3500,2500,ref_ref,i3_25 +R 3500,3000,ref_ref,i3_30 +R 4000,1500,ref_ref,i2_15 +R 4000,2000,ref_ref,i2_20 +R 4000,2500,ref_ref,i2_25 +R 4000,3000,ref_ref,i2_30 +S 5500,1500,5500,3000,200,i1,DOWN,CALU1 +S 6500,1500,6500,3500,200,i0,DOWN,CALU1 +S 7000,1000,7000,4000,200,q,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 6500,1500,6500,3500,100,*,UP,ALU1 +S 5500,1500,5700,1500,200,*,RIGHT,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 4800,1000,4800,2000,100,*,UP,ALU1 +S 6300,1500,6500,1500,200,*,RIGHT,ALU1 +S 6300,2500,6500,2500,200,*,RIGHT,ALU1 +S 7000,950,7000,4050,200,*,DOWN,ALU1 +S 1000,1000,5500,1000,100,*,RIGHT,ALU1 +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 5800,100,5800,1400,100,*,UP,NTRANS +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5300,4000,5300,4600,200,*,DOWN,ALU1 +S 6500,4000,6500,4600,200,*,DOWN,ALU1 +S 5900,3500,5900,4000,100,*,UP,ALU1 +S 3900,3500,5900,3500,100,*,RIGHT,ALU1 +S 5300,2800,5300,4200,300,*,UP,PDIF +S 4500,2800,4500,4200,300,*,UP,PDIF +S 7100,2800,7100,4700,300,*,UP,PDIF +S 6800,2600,6800,4900,100,*,UP,PTRANS +S 6500,2800,6500,4700,300,*,UP,PDIF +S 5600,2600,5600,4900,100,*,UP,PTRANS +S 6200,2600,6200,4900,100,*,UP,PTRANS +S 5900,2800,5900,4700,300,*,UP,PDIF +S 6500,300,6500,1200,300,*,DOWN,NDIF +S 6200,100,6200,1400,100,*,UP,NTRANS +S 7100,300,7100,1200,300,*,DOWN,NDIF +S 6800,100,6800,1400,100,*,UP,NTRANS +S 6800,1400,6800,2600,100,*,DOWN,POLY +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3300,2800,3300,4700,300,*,UP,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +S 4800,2000,6800,2000,100,*,RIGHT,POLY +S 0,300,7500,300,600,vss,RIGHT,CALU1 +S 0,3900,7500,3900,2400,*,RIGHT,NWELL +S 0,4700,7500,4700,600,vdd,RIGHT,CALU1 +V 5700,1500,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 4800,2000,CONT_POLY,* +V 6300,2500,CONT_POLY,* +V 6300,1500,CONT_POLY,* +V 4900,400,CONT_BODY_P,* +V 2300,500,CONT_DIF_N,* +V 4300,500,CONT_DIF_N,* +V 5500,1000,CONT_DIF_N,* +V 5300,4000,CONT_DIF_P,* +V 5900,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 4900,4700,CONT_BODY_N,* +V 7100,3000,CONT_DIF_P,* +V 7100,3500,CONT_DIF_P,* +V 6500,4500,CONT_DIF_P,* +V 7100,4000,CONT_DIF_P,* +V 6500,4000,CONT_DIF_P,* +V 6500,500,CONT_DIF_N,* +V 7100,1000,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 4000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.sym b/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.sym new file mode 100644 index 00000000..f3db5d90 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.vbe b/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.vbe new file mode 100644 index 00000000..39a24492 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rdown_i7_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT rup_i7_q : NATURAL := 1790; + CONSTANT tphh_i7_q : NATURAL := 346; + CONSTANT tphh_i6_q : NATURAL := 426; + CONSTANT tphh_i5_q : NATURAL := 467; + CONSTANT tphh_i4_q : NATURAL := 565; + CONSTANT tphh_i2_q : NATURAL := 682; + CONSTANT tpll_i6_q : NATURAL := 748; + CONSTANT tpll_i1_q : NATURAL := 753; + CONSTANT tphh_i0_q : NATURAL := 780; + CONSTANT tpll_i0_q : NATURAL := 797; + CONSTANT tpll_i7_q : NATURAL := 800; + CONSTANT tphh_i3_q : NATURAL := 803; + CONSTANT tpll_i3_q : NATURAL := 810; + CONSTANT tpll_i4_q : NATURAL := 813; + CONSTANT tpll_i2_q : NATURAL := 856; + CONSTANT tpll_i5_q : NATURAL := 861; + CONSTANT tphh_i1_q : NATURAL := 909; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x2" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1500 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.vhd b/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.vhd new file mode 100644 index 00000000..3615b807 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a2a24_x2.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a2a2a24_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + i7 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a2a2a24_x2; + +ARCHITECTURE RTL OF oa2a2a2a24_x2 IS +BEGIN + q <= ((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.al b/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.al new file mode 100644 index 00000000..08c8f70f --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.al @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x4,L,30/10/99 +C i0,IN,EXTERNAL,19 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,15 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C i6,IN,EXTERNAL,9 +C i7,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,18 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00020 +T P,0.35,5.9,5,8,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00019 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00018 +T P,0.35,5.9,6,15,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00017 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00016 +T P,0.35,5.9,13,16,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00015 +T P,0.35,5.9,14,19,13,0,0.75,0.75,13.3,13.3,18.6,11.25,tr_00014 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.8,11.25,tr_00013 +T P,0.35,5.9,14,2,18,0,0.75,0.75,13.3,13.3,22.2,11.25,tr_00012 +T P,0.35,5.9,18,2,14,0,0.75,0.75,13.3,13.3,20.4,11.25,tr_00011 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00010 +T N,0.35,2.9,2,9,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00009 +T N,0.35,2.9,12,16,2,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00008 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00007 +T N,0.35,2.9,18,2,3,0,0.75,0.75,7.3,7.3,20.4,2.25,tr_00006 +T N,0.35,2.9,3,19,11,0,0.75,0.75,7.3,7.3,18.6,2.25,tr_00005 +T N,0.35,2.9,18,2,3,0,0.75,0.75,7.3,7.3,22.2,2.25,tr_00004 +T N,0.35,2.9,11,17,2,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00003 +T N,0.35,2.9,3,15,12,0,0.75,0.75,7.3,7.3,12,2.25,tr_00002 +T N,0.35,2.9,4,8,3,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00001 +S 19,EXTERNAL,i0 +Q 0.00261741 +S 18,EXTERNAL,q +Q 0.00264397 +S 17,EXTERNAL,i1 +Q 0.00210054 +S 16,EXTERNAL,i3 +Q 0.00232574 +S 15,EXTERNAL,i2 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00932712 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i7 +Q 0.00260759 +S 9,EXTERNAL,i6 +Q 0.00269068 +S 8,EXTERNAL,i5 +Q 0.00232574 +S 7,EXTERNAL,i4 +Q 0.00232574 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00815202 +S 2,INTERNAL +Q 0.00988877 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.ap b/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.ap new file mode 100644 index 00000000..306d765a --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.ap @@ -0,0 +1,183 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x4,P,30/ 8/2000,100 +A 0,0,8000,5000 +R 4000,3000,ref_ref,i2_30 +R 4000,2500,ref_ref,i2_25 +R 4000,2000,ref_ref,i2_20 +R 4000,1500,ref_ref,i2_15 +R 3500,3000,ref_ref,i3_30 +R 3500,2500,ref_ref,i3_25 +R 3500,2000,ref_ref,i3_20 +R 3500,1500,ref_ref,i3_15 +R 3000,3000,ref_ref,i4_30 +R 3000,2500,ref_ref,i4_25 +R 3000,2000,ref_ref,i4_20 +R 3000,1500,ref_ref,i4_15 +R 2500,3000,ref_ref,i5_30 +R 2500,2500,ref_ref,i5_25 +R 2500,2000,ref_ref,i5_20 +R 2500,1500,ref_ref,i5_15 +R 1500,3000,ref_ref,i6_30 +R 1500,2500,ref_ref,i6_25 +R 1500,2000,ref_ref,i6_20 +R 1500,1500,ref_ref,i6_15 +R 500,3000,ref_ref,i7_30 +R 500,2500,ref_ref,i7_25 +R 500,2000,ref_ref,i7_20 +R 500,1500,ref_ref,i7_15 +R 500,1000,ref_ref,i7_10 +R 7000,2500,ref_ref,q_25 +R 7000,3000,ref_ref,q_30 +R 7000,3500,ref_ref,q_35 +R 7000,1500,ref_ref,q_15 +R 7000,2000,ref_ref,q_20 +R 7000,4000,ref_ref,q_40 +R 7000,1000,ref_ref,q_10 +R 6500,3000,ref_ref,i0_30 +R 6500,2500,ref_ref,i0_25 +R 6500,2000,ref_ref,i0_20 +R 6500,1500,ref_ref,i0_15 +R 5500,1500,ref_ref,i1_15 +R 5500,3000,ref_ref,i1_30 +R 5500,2500,ref_ref,i1_25 +R 5500,2000,ref_ref,i1_20 +R 6500,3500,ref_ref,i0_35 +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +S 7000,1000,7000,4000,200,q,DOWN,CALU1 +S 5500,1500,5500,3000,200,i1,DOWN,CALU1 +S 6500,1500,6500,3500,200,i0,DOWN,CALU1 +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 0,300,8000,300,600,vss,RIGHT,CALU1 +S 0,3900,8000,3900,2400,*,RIGHT,NWELL +S 0,4700,8000,4700,600,vdd,RIGHT,CALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 7700,3500,7700,4600,200,*,DOWN,ALU1 +S 7700,300,7700,1000,200,*,DOWN,ALU1 +S 7400,1400,7400,2600,100,*,DOWN,POLY +S 6800,1400,6800,2600,100,*,DOWN,POLY +S 6800,100,6800,1400,100,*,UP,NTRANS +S 7100,300,7100,1200,300,*,DOWN,NDIF +S 6200,100,6200,1400,100,*,UP,NTRANS +S 7700,300,7700,1200,300,*,DOWN,NDIF +S 6500,300,6500,1200,300,*,DOWN,NDIF +S 7400,100,7400,1400,100,*,DOWN,NTRANS +S 5900,2800,5900,4700,300,*,UP,PDIF +S 6200,2600,6200,4900,100,*,UP,PTRANS +S 5600,2600,5600,4900,100,*,UP,PTRANS +S 7400,2600,7400,4900,100,*,UP,PTRANS +S 6500,2800,6500,4700,300,*,UP,PDIF +S 6800,2600,6800,4900,100,*,UP,PTRANS +S 7700,2800,7700,4700,300,*,UP,PDIF +S 7100,2800,7100,4700,300,*,UP,PDIF +S 4500,2800,4500,4200,300,*,UP,PDIF +S 5300,2800,5300,4200,300,*,UP,PDIF +S 3900,3500,5900,3500,100,*,RIGHT,ALU1 +S 5900,3500,5900,4000,100,*,UP,ALU1 +S 6500,4000,6500,4600,200,*,DOWN,ALU1 +S 5300,4000,5300,4600,200,*,DOWN,ALU1 +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5800,100,5800,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 1000,1000,5500,1000,100,*,RIGHT,ALU1 +S 7000,950,7000,4050,200,*,DOWN,ALU1 +S 6300,2500,6500,2500,200,*,RIGHT,ALU1 +S 6300,1500,6500,1500,200,*,RIGHT,ALU1 +S 4800,1000,4800,2000,100,*,UP,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 5500,1500,5700,1500,200,*,RIGHT,ALU1 +S 4800,2000,7400,2000,100,*,RIGHT,POLY +S 6500,1500,6500,3500,100,*,UP,ALU1 +V 3300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 3300,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 7700,500,CONT_DIF_N,* +V 7100,1000,CONT_DIF_N,* +V 6500,500,CONT_DIF_N,* +V 7700,1000,CONT_DIF_N,* +V 7700,4500,CONT_DIF_P,* +V 7700,3500,CONT_DIF_P,* +V 6500,4000,CONT_DIF_P,* +V 7100,4000,CONT_DIF_P,* +V 6500,4500,CONT_DIF_P,* +V 7100,3500,CONT_DIF_P,* +V 7100,3000,CONT_DIF_P,* +V 7700,4000,CONT_DIF_P,* +V 4900,4700,CONT_BODY_N,* +V 3900,3500,CONT_DIF_P,* +V 5900,4000,CONT_DIF_P,* +V 5300,4000,CONT_DIF_P,* +V 5500,1000,CONT_DIF_N,* +V 4300,500,CONT_DIF_N,* +V 2300,500,CONT_DIF_N,* +V 4900,400,CONT_BODY_P,* +V 6300,1500,CONT_POLY,* +V 6300,2500,CONT_POLY,* +V 4800,2000,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 5700,1500,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.sym b/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.sym new file mode 100644 index 00000000..90d92064 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.vbe b/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.vbe new file mode 100644 index 00000000..33d16844 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rdown_i7_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT rup_i7_q : NATURAL := 890; + CONSTANT tphh_i7_q : NATURAL := 399; + CONSTANT tphh_i6_q : NATURAL := 487; + CONSTANT tphh_i5_q : NATURAL := 515; + CONSTANT tphh_i4_q : NATURAL := 619; + CONSTANT tphh_i2_q : NATURAL := 726; + CONSTANT tphh_i0_q : NATURAL := 823; + CONSTANT tpll_i1_q : NATURAL := 835; + CONSTANT tpll_i6_q : NATURAL := 845; + CONSTANT tphh_i3_q : NATURAL := 851; + CONSTANT tpll_i0_q : NATURAL := 879; + CONSTANT tpll_i3_q : NATURAL := 895; + CONSTANT tpll_i7_q : NATURAL := 895; + CONSTANT tpll_i4_q : NATURAL := 902; + CONSTANT tpll_i2_q : NATURAL := 940; + CONSTANT tpll_i5_q : NATURAL := 949; + CONSTANT tphh_i1_q : NATURAL := 955; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x4" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1600 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.vhd b/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.vhd new file mode 100644 index 00000000..480fb8b8 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2a2a2a24_x4.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a2a2a24_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + i7 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a2a2a24_x4; + +ARCHITECTURE RTL OF oa2a2a2a24_x4 IS +BEGIN + q <= ((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7)); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa2ao222_x2.al b/alliance/src/cells/src/sxlib/oa2ao222_x2.al new file mode 100644 index 00000000..4491d151 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2ao222_x2.al @@ -0,0 +1,49 @@ +V ALLIANCE : 6 +H oa2ao222_x2,L,30/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C i4,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,13,2,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00012 +T P,0.35,5.9,6,9,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00011 +T P,0.35,4.25,6,11,5,0,0.75,0.75,10,10,3.6,10.42,tr_00010 +T P,0.35,4.25,5,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00009 +T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00007 +T N,0.35,2.9,4,2,13,0,0.75,0.75,7.3,7.3,12.3,3.75,tr_00006 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00005 +T N,0.35,1.7,1,9,4,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00004 +T N,0.35,2.6,2,11,3,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00003 +T N,0.35,2.6,3,12,4,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00002 +T N,0.35,1.7,1,10,2,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00001 +S 13,EXTERNAL,q +Q 0.00276148 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL,i3 +Q 0.00197871 +S 8,EXTERNAL +Q 0.00212909 +S 7,INTERNAL +Q 0 +S 6,INTERNAL +Q 0.00227626 +S 5,EXTERNAL,vdd +Q 0.00557437 +S 4,EXTERNAL,vss +Q 0.00657321 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00590927 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/alliance/src/cells/src/sxlib/oa2ao222_x2.ap b/alliance/src/cells/src/sxlib/oa2ao222_x2.ap new file mode 100644 index 00000000..739f64cc --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2ao222_x2.ap @@ -0,0 +1,129 @@ +V ALLIANCE : 6 +H oa2ao222_x2,P, 6/ 9/2000,100 +A 0,0,5000,5000 +R 4500,4000,ref_ref,q_40 +R 4500,2000,ref_ref,q_20 +R 4500,2500,ref_ref,q_25 +R 4500,3000,ref_ref,q_30 +R 4500,1000,ref_ref,q_10 +R 4500,3500,ref_ref,q_35 +R 4500,1500,ref_ref,q_15 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,2500,ref_ref,i4_25 +R 1500,2000,ref_ref,i4_20 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 3000,1500,ref_ref,i3_15 +R 3000,2000,ref_ref,i3_20 +R 3000,2500,ref_ref,i3_25 +R 3000,3000,ref_ref,i3_30 +S 1500,2000,1700,2000,300,*,RIGHT,POLY +S 4500,1000,4500,4000,200,q,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,2000,1500,3500,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 3000,1500,3000,3000,200,i3,DOWN,CALU1 +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 2100,3500,3900,3500,100,*,RIGHT,ALU1 +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 3800,800,3800,1700,300,*,UP,NDIF +S 4100,600,4100,1900,100,*,DOWN,NTRANS +S 4400,800,4400,1700,300,*,UP,NDIF +S 3800,2500,4100,2500,300,*,RIGHT,POLY +S 4100,1900,4100,2600,100,*,UP,POLY +S 3800,300,3800,1500,200,*,DOWN,ALU1 +S 3800,4000,3800,4700,200,*,UP,ALU1 +S 3900,2500,3900,3500,100,*,DOWN,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 2000,900,2000,1700,200,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 1400,900,1400,1700,200,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 300,500,300,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 2600,500,2600,1700,300,*,UP,NDIF +S 1100,1900,1100,2600,100,i1,UP,POLY +S 1700,1900,1700,2600,100,i2,UP,POLY +S 2400,1900,2400,2600,100,i3,UP,POLY +S 2900,1900,2900,2600,100,i4,UP,POLY +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 600,2600,600,4350,100,*,UP,PTRANS +S 1500,2800,1500,4150,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 2700,2800,2700,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,1900,600,2600,100,i0,UP,POLY +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 4500,1000,4500,4000,200,*,DOWN,ALU1 +V 4400,3000,CONT_DIF_P,* +V 3800,4000,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 3800,4500,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 3800,1500,CONT_DIF_N,* +V 4400,1000,CONT_DIF_N,* +V 4400,1500,CONT_DIF_N,* +V 3800,1000,CONT_DIF_N,* +V 4400,300,CONT_BODY_P,* +V 3900,2500,CONT_POLY,* +V 1200,400,CONT_BODY_P,* +V 1600,400,CONT_BODY_P,* +V 2000,400,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3200,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 900,4500,CONT_DIF_P,* +V 1400,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2600,500,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa2ao222_x2.sym b/alliance/src/cells/src/sxlib/oa2ao222_x2.sym new file mode 100644 index 00000000..1e610a78 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa2ao222_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/oa2ao222_x2.vbe b/alliance/src/cells/src/sxlib/oa2ao222_x2.vbe new file mode 100644 index 00000000..2a96b29e --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2ao222_x2.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT tpll_i4_q : NATURAL := 453; + CONSTANT tphh_i2_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 495; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphh_i3_q : NATURAL := 556; + CONSTANT tphh_i4_q : NATURAL := 558; + CONSTANT tpll_i3_q : NATURAL := 578; + CONSTANT tpll_i0_q : NATURAL := 581; + CONSTANT tphh_i1_q : NATURAL := 598; + CONSTANT tpll_i2_q : NATURAL := 604; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x2; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1200 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa2ao222_x2.vhd b/alliance/src/cells/src/sxlib/oa2ao222_x2.vhd new file mode 100644 index 00000000..5ef47e62 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2ao222_x2.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2ao222_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2ao222_x2; + +ARCHITECTURE RTL OF oa2ao222_x2 IS +BEGIN + q <= ((i0 AND i1) OR (i4 AND (i2 OR i3))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa2ao222_x4.al b/alliance/src/cells/src/sxlib/oa2ao222_x4.al new file mode 100644 index 00000000..3aafc2a2 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2ao222_x4.al @@ -0,0 +1,51 @@ +V ALLIANCE : 6 +H oa2ao222_x4,L,30/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C i4,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,13,2,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00014 +T P,0.35,5.9,6,9,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00013 +T P,0.35,4.25,6,11,5,0,0.75,0.75,10,10,3.6,10.42,tr_00012 +T P,0.35,4.25,5,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00011 +T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,5,2,13,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00008 +T N,0.35,2.9,4,2,13,0,0.75,0.75,7.3,7.3,12.3,3.75,tr_00007 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00006 +T N,0.35,1.7,1,9,4,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00005 +T N,0.35,2.6,2,11,3,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00004 +T N,0.35,2.6,3,12,4,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00003 +T N,0.35,1.7,1,10,2,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00002 +T N,0.35,2.9,13,2,4,0,0.75,0.75,7.3,7.3,14.1,3.75,tr_00001 +S 13,EXTERNAL,q +Q 0.00276148 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL,i3 +Q 0.00197871 +S 8,EXTERNAL +Q 0.00212909 +S 7,INTERNAL +Q 0 +S 6,INTERNAL +Q 0.00227626 +S 5,EXTERNAL,vdd +Q 0.00773725 +S 4,EXTERNAL,vss +Q 0.00861858 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00727894 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/alliance/src/cells/src/sxlib/oa2ao222_x4.ap b/alliance/src/cells/src/sxlib/oa2ao222_x4.ap new file mode 100644 index 00000000..a57a27f7 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2ao222_x4.ap @@ -0,0 +1,146 @@ +V ALLIANCE : 6 +H oa2ao222_x4,P, 6/ 9/2000,100 +A 0,0,5500,5000 +R 4500,4000,ref_ref,q_40 +R 4500,2000,ref_ref,q_20 +R 4500,2500,ref_ref,q_25 +R 4500,3000,ref_ref,q_30 +R 4500,1000,ref_ref,q_10 +R 4500,3500,ref_ref,q_35 +R 4500,1500,ref_ref,q_15 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,2500,ref_ref,i4_25 +R 1500,2000,ref_ref,i4_20 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 3000,1500,ref_ref,i3_15 +R 3000,2000,ref_ref,i3_20 +R 3000,2500,ref_ref,i3_25 +R 3000,3000,ref_ref,i3_30 +S 1500,2000,1700,2000,300,*,RIGHT,POLY +S 4500,1000,4500,4000,200,q,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,2000,1500,3500,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 3000,1500,3000,3000,200,i3,DOWN,CALU1 +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 2100,3500,3900,3500,100,*,RIGHT,ALU1 +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 3800,800,3800,1700,300,*,UP,NDIF +S 4100,600,4100,1900,100,*,DOWN,NTRANS +S 4400,800,4400,1700,300,*,UP,NDIF +S 3800,2500,4100,2500,300,*,RIGHT,POLY +S 4100,1900,4100,2600,100,*,UP,POLY +S 3800,300,3800,1500,200,*,DOWN,ALU1 +S 3800,4000,3800,4700,200,*,UP,ALU1 +S 3900,2500,3900,3500,100,*,DOWN,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 2000,900,2000,1700,200,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 1400,900,1400,1700,200,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 300,500,300,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 2600,500,2600,1700,300,*,UP,NDIF +S 1100,1900,1100,2600,100,i1,UP,POLY +S 1700,1900,1700,2600,100,i2,UP,POLY +S 2400,1900,2400,2600,100,i3,UP,POLY +S 2900,1900,2900,2600,100,i4,UP,POLY +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 600,2600,600,4350,100,*,UP,PTRANS +S 1500,2800,1500,4150,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 2700,2800,2700,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,1900,600,2600,100,i0,UP,POLY +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 4700,600,4700,1900,100,*,DOWN,NTRANS +S 4700,1900,4700,2600,100,*,UP,POLY +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 5000,300,5000,1500,200,*,DOWN,ALU1 +S 5000,800,5000,1700,300,*,UP,NDIF +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 5000,3000,5000,4700,200,*,UP,ALU1 +S 3900,2500,4700,2500,300,*,RIGHT,POLY +S 4500,1000,4500,4000,200,*,DOWN,ALU1 +V 4400,3000,CONT_DIF_P,* +V 3800,4000,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 3800,4500,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 3800,1500,CONT_DIF_N,* +V 4400,1000,CONT_DIF_N,* +V 4400,1500,CONT_DIF_N,* +V 3800,1000,CONT_DIF_N,* +V 4400,300,CONT_BODY_P,* +V 3900,2500,CONT_POLY,* +V 1200,400,CONT_BODY_P,* +V 1600,400,CONT_BODY_P,* +V 2000,400,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3200,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 900,4500,CONT_DIF_P,* +V 1400,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2600,500,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 5000,1500,CONT_DIF_N,* +V 5000,1000,CONT_DIF_N,* +V 5000,4500,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 5000,3500,CONT_DIF_P,* +V 5000,3000,CONT_DIF_P,* +V 3800,300,CONT_BODY_P,* +V 5000,300,CONT_BODY_P,* +V 3200,300,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa2ao222_x4.sym b/alliance/src/cells/src/sxlib/oa2ao222_x4.sym new file mode 100644 index 00000000..d4716284 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa2ao222_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/oa2ao222_x4.vbe b/alliance/src/cells/src/sxlib/oa2ao222_x4.vbe new file mode 100644 index 00000000..d8e7b2ab --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT tpll_i4_q : NATURAL := 529; + CONSTANT tphh_i2_q : NATURAL := 552; + CONSTANT tphh_i0_q : NATURAL := 553; + CONSTANT tpll_i1_q : NATURAL := 616; + CONSTANT tphh_i3_q : NATURAL := 640; + CONSTANT tphh_i4_q : NATURAL := 656; + CONSTANT tpll_i0_q : NATURAL := 657; + CONSTANT tpll_i3_q : NATURAL := 660; + CONSTANT tphh_i1_q : NATURAL := 662; + CONSTANT tpll_i2_q : NATURAL := 693; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa2ao222_x4.vhd b/alliance/src/cells/src/sxlib/oa2ao222_x4.vhd new file mode 100644 index 00000000..11ed1fc9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa2ao222_x4.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2ao222_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2ao222_x4; + +ARCHITECTURE RTL OF oa2ao222_x4 IS +BEGIN + q <= ((i0 AND i1) OR (i4 AND (i2 OR i3))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x1.sym b/alliance/src/cells/src/sxlib/oa3ao322_x1.sym new file mode 100644 index 00000000..3b587ba7 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa3ao322_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x2.al b/alliance/src/cells/src/sxlib/oa3ao322_x2.al new file mode 100644 index 00000000..6f7a0954 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa3ao322_x2.al @@ -0,0 +1,63 @@ +V ALLIANCE : 6 +H oa3ao322_x2,L,30/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,15 +C i5,IN,EXTERNAL,16 +C i6,IN,EXTERNAL,11 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,7,2,4,0,0.75,0.75,13.3,13.3,2.4,11.25,tr_00016 +T P,0.35,4.4,14,17,2,0,0.75,0.75,10.3,10.3,11.7,10.5,tr_00015 +T P,0.35,4.4,13,15,14,0,0.75,0.75,10.3,10.3,13.2,10.5,tr_00014 +T P,0.35,4.4,6,16,13,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00013 +T P,0.35,3.2,6,10,7,0,0.75,0.75,7.9,7.9,4.2,11.1,tr_00012 +T P,0.35,3.2,7,9,6,0,0.75,0.75,7.9,7.9,6,11.1,tr_00011 +T P,0.35,3.2,6,8,7,0,0.75,0.75,7.9,7.9,7.8,11.1,tr_00010 +T P,0.35,3.5,2,11,6,0,0.75,0.75,8.5,8.5,9.6,10.95,tr_00009 +T N,0.35,2.9,4,2,3,0,0.75,0.75,7.3,7.3,2.4,3.75,tr_00008 +T N,0.35,1.7,12,11,2,0,0.75,0.75,4.9,4.9,9.3,3.45,tr_00007 +T N,0.35,1.1,3,17,12,0,0.75,0.75,3.7,3.7,11.1,3.15,tr_00006 +T N,0.35,1.1,12,15,3,0,0.75,0.75,3.7,3.7,12.9,3.15,tr_00005 +T N,0.35,1.1,3,16,12,0,0.75,0.75,3.7,3.7,14.7,3.15,tr_00004 +T N,0.35,2.3,2,8,1,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00003 +T N,0.35,2.3,1,9,5,0,0.75,0.75,6.1,6.1,6,3.75,tr_00002 +T N,0.35,2.3,5,10,3,0,0.75,0.75,6.1,6.1,4.5,3.75,tr_00001 +S 17,EXTERNAL,i3 +Q 0.00290834 +S 16,EXTERNAL,i5 +Q 0.00275797 +S 15,EXTERNAL,i4 +Q 0.00283894 +S 14,INTERNAL +Q 0 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0.00114171 +S 11,EXTERNAL,i6 +Q 0.00262649 +S 10,EXTERNAL,i0 +Q 0.00290834 +S 9,EXTERNAL,i1 +Q 0.00275797 +S 8,EXTERNAL,i2 +Q 0.00247612 +S 7,EXTERNAL,vdd +Q 0.00644464 +S 6,INTERNAL +Q 0.00261448 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,q +Q 0.00258522 +S 3,EXTERNAL,vss +Q 0.00679717 +S 2,INTERNAL +Q 0.00549512 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x2.ap b/alliance/src/cells/src/sxlib/oa3ao322_x2.ap new file mode 100644 index 00000000..f587d74e --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa3ao322_x2.ap @@ -0,0 +1,161 @@ +V ALLIANCE : 6 +H oa3ao322_x2,P, 6/ 9/2000,100 +A 0,0,5500,5000 +R 500,3500,ref_ref,q_35 +R 500,3000,ref_ref,q_30 +R 500,2500,ref_ref,q_25 +R 500,2000,ref_ref,q_20 +R 500,1500,ref_ref,q_15 +R 500,1000,ref_ref,q_10 +R 500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,i0_35 +R 4000,3500,ref_ref,i3_35 +R 5000,2500,ref_ref,i5_25 +R 5000,3000,ref_ref,i5_30 +R 5000,3500,ref_ref,i5_35 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i3_30 +R 4500,1500,ref_ref,i4_15 +R 4500,2000,ref_ref,i4_20 +R 4500,2500,ref_ref,i4_25 +R 4500,3000,ref_ref,i4_30 +R 4500,3500,ref_ref,i4_35 +R 5000,1500,ref_ref,i5_15 +R 5000,2000,ref_ref,i5_20 +R 4000,1500,ref_ref,i3_15 +R 4000,2000,ref_ref,i3_20 +R 4000,2500,ref_ref,i3_25 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2500,3500,ref_ref,i2_35 +R 3000,2000,ref_ref,i6_20 +R 3000,2500,ref_ref,i6_25 +R 3000,3000,ref_ref,i6_30 +R 3000,3500,ref_ref,i6_35 +R 2000,1500,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_20 +R 2000,2500,ref_ref,i1_25 +R 2000,3000,ref_ref,i1_30 +R 2000,3500,ref_ref,i1_35 +R 2500,2000,ref_ref,i2_20 +S 3000,2000,3200,2000,300,*,RIGHT,POLY +S 800,2000,1000,2000,300,*,LEFT,POLY +S 500,1000,500,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 4500,1500,4500,3500,200,i4,DOWN,CALU1 +S 5000,1500,5000,3500,200,i5,DOWN,CALU1 +S 4000,1500,4000,3500,200,i3,DOWN,CALU1 +S 3000,2000,3000,3500,200,i6,DOWN,CALU1 +S 2000,1500,2000,3500,200,i1,DOWN,CALU1 +S 2500,2000,2500,3500,200,i2,DOWN,CALU1 +S 3100,1900,3200,1900,100,*,LEFT,POLY +S 1400,1900,1500,1900,100,*,RIGHT,POLY +S 3900,1900,3900,2600,100,*,UP,POLY +S 3700,1900,3900,1900,100,*,RIGHT,POLY +S 800,2600,800,4900,100,*,UP,PTRANS +S 500,2800,500,4700,300,*,DOWN,PDIF +S 1100,2800,1100,4200,200,*,DOWN,PDIF +S 500,800,500,1700,300,*,UP,NDIF +S 800,600,800,1900,100,*,DOWN,NTRANS +S 1200,500,1200,1700,300,*,UP,NDIF +S 4700,400,5100,400,300,*,RIGHT,PTIE +S 800,1900,800,2600,100,*,DOWN,POLY +S 4900,1900,4900,2600,100,i5,DOWN,POLY +S 4400,1900,4400,2600,100,i4,UP,POLY +S 4300,1900,4400,1900,100,*,RIGHT,POLY +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 500,1000,500,4000,200,*,UP,ALU1 +S 1100,4000,1100,4700,200,*,UP,ALU1 +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,1000,2000,100,*,UP,ALU1 +S 3400,1000,4600,1000,100,*,RIGHT,ALU1 +S 4000,1500,4000,3500,100,*,UP,ALU1 +S 3500,1500,3500,3500,100,*,DOWN,ALU1 +S 1500,1500,1500,3500,100,*,DOWN,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 4500,1500,4500,3500,100,*,UP,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 5200,300,5200,1000,200,*,DOWN,ALU1 +S 5000,1500,5000,3500,100,*,DOWN,ALU1 +S 2500,2000,2500,3500,100,*,UP,ALU1 +S 2800,1000,2800,1500,100,*,UP,ALU1 +S 2800,1500,3500,1500,100,*,RIGHT,ALU1 +S 1000,1000,2800,1000,100,*,LEFT,ALU1 +S 1700,4000,5200,4000,100,*,RIGHT,ALU1 +S 3900,2600,3900,4400,100,*,UP,PTRANS +S 4400,2600,4400,4400,100,*,UP,PTRANS +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 3100,700,3100,1600,100,*,UP,NTRANS +S 3700,700,3700,1400,100,*,UP,NTRANS +S 4300,700,4300,1400,100,*,UP,NTRANS +S 4900,700,4900,1400,100,*,UP,NTRANS +S 5200,900,5200,1200,300,*,UP,NDIF +S 4600,900,4600,1200,300,*,UP,NDIF +S 4000,400,4000,1200,300,*,DOWN,NDIF +S 3400,900,3400,1400,200,*,UP,NDIF +S 2800,900,2800,1400,200,*,UP,NDIF +S 3100,1600,3100,1900,100,*,UP,POLY +S 3700,1400,3700,1900,100,*,UP,POLY +S 4300,1400,4300,1900,100,*,UP,POLY +S 1400,3000,1400,4400,100,*,UP,PTRANS +S 2000,3000,2000,4400,100,*,UP,PTRANS +S 2600,3000,2600,4400,100,*,UP,PTRANS +S 3200,2900,3200,4400,100,*,UP,PTRANS +S 5200,2800,5200,4200,300,*,UP,PDIF +S 1700,3200,1700,4200,300,*,UP,PDIF +S 2300,3200,2300,4500,300,*,DOWN,PDIF +S 2900,3100,2900,4200,200,*,UP,PDIF +S 3500,3100,3500,4200,400,*,DOWN,PDIF +S 1400,1900,1400,3000,100,*,DOWN,POLY +S 2000,1900,2000,3000,100,*,DOWN,POLY +S 2600,1900,2600,3000,100,i2,UP,POLY +S 3200,1900,3200,2900,100,i6,UP,POLY +S 2500,700,2500,1800,100,*,UP,NTRANS +S 2000,700,2000,1800,100,*,UP,NTRANS +S 1500,700,1500,1800,100,*,UP,NTRANS +S 1800,400,3300,400,300,*,RIGHT,PTIE +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 1500,1800,1500,2000,100,*,DOWN,POLY +S 2000,1800,2000,2000,100,*,UP,POLY +S 2500,1800,2500,2000,100,*,UP,POLY +S 4900,1400,4900,2000,100,*,UP,POLY +V 500,3500,CONT_DIF_P,* +V 1100,4000,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 3500,3000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 2300,4500,CONT_DIF_P,* +V 1600,4700,CONT_BODY_N,* +V 5200,4000,CONT_DIF_P,* +V 500,1500,CONT_DIF_N,* +V 4000,500,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 1200,500,CONT_DIF_N,* +V 5200,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 5100,400,CONT_BODY_P,* +V 4700,400,CONT_BODY_P,* +V 1000,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 5000,2000,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 2900,4000,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 2900,4700,CONT_BODY_N,* +V 3500,4700,CONT_BODY_N,* +V 4100,4700,CONT_BODY_N,* +V 4700,4700,CONT_BODY_N,* +V 2800,400,CONT_BODY_P,* +V 2300,400,CONT_BODY_P,* +V 1800,400,CONT_BODY_P,* +V 3350,400,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x2.sym b/alliance/src/cells/src/sxlib/oa3ao322_x2.sym new file mode 100644 index 00000000..5fbf4f56 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa3ao322_x2.sym differ diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x2.vbe b/alliance/src/cells/src/sxlib/oa3ao322_x2.vbe new file mode 100644 index 00000000..dc2a7188 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa3ao322_x2.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT tpll_i6_q : NATURAL := 540; + CONSTANT tphh_i3_q : NATURAL := 560; + CONSTANT tphh_i6_q : NATURAL := 563; + CONSTANT tphh_i0_q : NATURAL := 638; + CONSTANT tphh_i4_q : NATURAL := 649; + CONSTANT tpll_i2_q : NATURAL := 707; + CONSTANT tphh_i5_q : NATURAL := 734; + CONSTANT tpll_i5_q : NATURAL := 734; + CONSTANT tphh_i1_q : NATURAL := 735; + CONSTANT tpll_i4_q : NATURAL := 760; + CONSTANT tpll_i1_q : NATURAL := 764; + CONSTANT tpll_i3_q : NATURAL := 765; + CONSTANT tphh_i2_q : NATURAL := 806; + CONSTANT tpll_i0_q : NATURAL := 820; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x2; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x2.vhd b/alliance/src/cells/src/sxlib/oa3ao322_x2.vhd new file mode 100644 index 00000000..23b695b4 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa3ao322_x2.vhd @@ -0,0 +1,25 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa3ao322_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa3ao322_x2; + +ARCHITECTURE RTL OF oa3ao322_x2 IS +BEGIN + q <= (((i0 AND i1) AND i2) OR (i6 AND ((i3 OR i4) OR i5))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x4.al b/alliance/src/cells/src/sxlib/oa3ao322_x4.al new file mode 100644 index 00000000..eacaab98 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa3ao322_x4.al @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H oa3ao322_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,14 +C i5,IN,EXTERNAL,15 +C i6,IN,EXTERNAL,17 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,3.2,11,9,5,0,0.75,0.75,7.9,7.9,9.3,11.1,tr_00018 +T P,0.35,3.5,8,17,11,0,0.75,0.75,8.5,8.5,11.1,10.95,tr_00017 +T P,0.35,5.9,5,8,2,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00016 +T P,0.35,4.4,13,16,8,0,0.75,0.75,10.3,10.3,13.2,10.5,tr_00015 +T P,0.35,3.2,5,7,11,0,0.75,0.75,7.9,7.9,7.5,11.1,tr_00014 +T P,0.35,4.4,11,15,12,0,0.75,0.75,10.3,10.3,16.2,10.5,tr_00013 +T P,0.35,4.4,12,14,13,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00012 +T P,0.35,3.2,11,6,5,0,0.75,0.75,7.9,7.9,5.7,11.1,tr_00011 +T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00010 +T N,0.35,2.3,3,7,4,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00009 +T N,0.35,1.7,10,17,8,0,0.75,0.75,4.9,4.9,10.8,3.45,tr_00008 +T N,0.35,1.1,1,16,10,0,0.75,0.75,3.7,3.7,12.6,3.15,tr_00007 +T N,0.35,2.3,4,6,1,0,0.75,0.75,6.1,6.1,6,3.75,tr_00006 +T N,0.35,2.3,8,9,3,0,0.75,0.75,6.1,6.1,9,3.75,tr_00005 +T N,0.35,2.9,2,8,1,0,0.75,0.75,7.3,7.3,3.9,3.75,tr_00004 +T N,0.35,1.1,10,14,1,0,0.75,0.75,3.7,3.7,14.4,3.15,tr_00003 +T N,0.35,1.1,1,15,10,0,0.75,0.75,3.7,3.7,16.2,3.15,tr_00002 +T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00001 +S 17,EXTERNAL,i6 +Q 0.00262649 +S 16,EXTERNAL,i3 +Q 0.00290835 +S 15,EXTERNAL,i5 +Q 0.00275797 +S 14,EXTERNAL,i4 +Q 0.00283894 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0.00261448 +S 10,INTERNAL +Q 0.00114171 +S 9,EXTERNAL,i2 +Q 0.00247612 +S 8,INTERNAL +Q 0.00668962 +S 7,EXTERNAL,i1 +Q 0.00275797 +S 6,EXTERNAL,i0 +Q 0.00290834 +S 5,EXTERNAL,vdd +Q 0.00849001 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,q +Q 0.00258522 +S 1,EXTERNAL,vss +Q 0.00825499 +EOF diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x4.ap b/alliance/src/cells/src/sxlib/oa3ao322_x4.ap new file mode 100644 index 00000000..9bb123a6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa3ao322_x4.ap @@ -0,0 +1,174 @@ +V ALLIANCE : 6 +H oa3ao322_x4,P, 6/ 9/2000,100 +A 0,0,6000,5000 +R 3500,3500,ref_ref,i6_35 +R 2500,1500,ref_ref,i1_15 +R 2500,2000,ref_ref,i1_20 +R 2500,2500,ref_ref,i1_25 +R 2500,3000,ref_ref,i1_30 +R 2500,3500,ref_ref,i1_35 +R 1000,3500,ref_ref,q_35 +R 3000,2000,ref_ref,i2_20 +R 4500,2000,ref_ref,i3_20 +R 4500,2500,ref_ref,i3_25 +R 3000,2500,ref_ref,i2_25 +R 3000,3000,ref_ref,i2_30 +R 3000,3500,ref_ref,i2_35 +R 3500,2000,ref_ref,i6_20 +R 3500,2500,ref_ref,i6_25 +R 3500,3000,ref_ref,i6_30 +R 5000,1500,ref_ref,i4_15 +R 5000,2000,ref_ref,i4_20 +R 5000,2500,ref_ref,i4_25 +R 5000,3000,ref_ref,i4_30 +R 5000,3500,ref_ref,i4_35 +R 5500,1500,ref_ref,i5_15 +R 5500,2000,ref_ref,i5_20 +R 4500,1500,ref_ref,i3_15 +R 5500,2500,ref_ref,i5_25 +R 5500,3000,ref_ref,i5_30 +R 5500,3500,ref_ref,i5_35 +R 2000,1500,ref_ref,i0_15 +R 2000,2000,ref_ref,i0_20 +R 2000,2500,ref_ref,i0_25 +R 2000,3000,ref_ref,i0_30 +R 4500,3000,ref_ref,i3_30 +R 1000,3000,ref_ref,q_30 +R 1000,2500,ref_ref,q_25 +R 1000,2000,ref_ref,q_20 +R 1000,1500,ref_ref,q_15 +R 1000,1000,ref_ref,q_10 +R 1000,4000,ref_ref,q_40 +R 2000,3500,ref_ref,i0_35 +R 4500,3500,ref_ref,i3_35 +S 4000,2800,4000,4200,300,*,DOWN,PDIF +S 700,2000,1500,2000,300,*,LEFT,POLY +S 3500,2000,3700,2000,300,*,RIGHT,POLY +S 2500,1500,2500,3500,200,i1,DOWN,CALU1 +S 3000,2000,3000,3500,200,i2,DOWN,CALU1 +S 3500,2000,3500,3500,200,i6,DOWN,CALU1 +S 5000,1500,5000,3500,200,i4,DOWN,CALU1 +S 5500,1500,5500,3500,200,i5,DOWN,CALU1 +S 1000,1000,1000,4000,200,q,DOWN,CALU1 +S 2000,1500,2000,3500,200,i0,DOWN,CALU1 +S 4500,1500,4500,3500,200,i3,DOWN,CALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 5000,1500,5000,3500,100,*,UP,ALU1 +S 3500,2000,3500,3500,100,*,UP,ALU1 +S 5700,300,5700,1000,200,*,DOWN,ALU1 +S 5500,1500,5500,3500,100,*,DOWN,ALU1 +S 2200,4000,5700,4000,100,*,RIGHT,ALU1 +S 1500,1000,1500,2000,100,*,UP,ALU1 +S 3900,1000,5100,1000,100,*,RIGHT,ALU1 +S 4500,1500,4500,3500,100,*,UP,ALU1 +S 4000,1500,4000,3500,100,*,DOWN,ALU1 +S 1500,1000,3300,1000,100,*,LEFT,ALU1 +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 1600,4000,1600,4700,200,*,UP,ALU1 +S 3300,1500,4000,1500,100,*,RIGHT,ALU1 +S 3300,1000,3300,1500,100,*,UP,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 400,400,400,1500,200,*,DOWN,ALU1 +S 400,3000,400,4500,200,*,UP,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 1300,1900,1300,2600,100,*,DOWN,POLY +S 5400,1900,5400,2600,100,i5,DOWN,POLY +S 4900,1900,4900,2600,100,i4,UP,POLY +S 1900,1900,1900,3000,100,*,DOWN,POLY +S 4800,1900,4900,1900,100,*,RIGHT,POLY +S 2500,1800,2500,2000,100,*,UP,POLY +S 5400,1400,5400,2000,100,*,UP,POLY +S 3700,1900,3700,2900,100,i6,UP,POLY +S 4400,1900,4400,2600,100,*,UP,POLY +S 4200,1900,4400,1900,100,*,RIGHT,POLY +S 3100,1900,3100,3000,100,i2,UP,POLY +S 3000,1800,3000,2000,100,*,UP,POLY +S 4200,1400,4200,1900,100,*,UP,POLY +S 3600,1900,3700,1900,100,*,LEFT,POLY +S 1900,1900,2000,1900,100,*,RIGHT,POLY +S 2500,1900,2500,3000,100,*,DOWN,POLY +S 2000,1800,2000,2000,100,*,DOWN,POLY +S 4800,1400,4800,1900,100,*,UP,POLY +S 3600,1600,3600,1900,100,*,UP,POLY +S 700,1900,700,2600,100,*,DOWN,POLY +S 2300,400,3800,400,300,*,RIGHT,PTIE +S 5200,400,5600,400,300,*,RIGHT,PTIE +S 2500,700,2500,1800,100,*,UP,NTRANS +S 5100,900,5100,1200,300,*,UP,NDIF +S 4500,400,4500,1200,300,*,DOWN,NDIF +S 3600,700,3600,1600,100,*,UP,NTRANS +S 1700,500,1700,1700,300,*,UP,NDIF +S 3900,900,3900,1400,200,*,UP,NDIF +S 4200,700,4200,1400,100,*,UP,NTRANS +S 2000,700,2000,1800,100,*,UP,NTRANS +S 3000,700,3000,1800,100,*,UP,NTRANS +S 1000,800,1000,1700,300,*,UP,NDIF +S 1300,600,1300,1900,100,*,DOWN,NTRANS +S 4800,700,4800,1400,100,*,UP,NTRANS +S 3300,900,3300,1400,200,*,UP,NDIF +S 5400,700,5400,1400,100,*,UP,NTRANS +S 5700,900,5700,1200,300,*,UP,NDIF +S 400,800,400,1700,300,*,DOWN,NDIF +S 700,600,700,1900,100,*,DOWN,NTRANS +S 5700,2800,5700,4200,300,*,UP,PDIF +S 3100,3000,3100,4400,100,*,UP,PTRANS +S 3700,2900,3700,4400,100,*,UP,PTRANS +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 1600,2800,1600,4200,200,*,DOWN,PDIF +S 2200,3200,2200,4200,300,*,UP,PDIF +S 4400,2600,4400,4400,100,*,UP,PTRANS +S 2500,3000,2500,4400,100,*,UP,PTRANS +S 2800,3200,2800,4500,300,*,DOWN,PDIF +S 3400,3100,3400,4200,200,*,UP,PDIF +S 5400,2600,5400,4400,100,*,UP,PTRANS +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 1900,3000,1900,4400,100,*,UP,PTRANS +S 400,2800,400,4700,300,*,UP,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +V 1500,2000,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 5000,2500,CONT_POLY,* +V 5500,2000,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2300,400,CONT_BODY_P,* +V 3850,400,CONT_BODY_P,* +V 2800,400,CONT_BODY_P,* +V 3300,400,CONT_BODY_P,* +V 5600,400,CONT_BODY_P,* +V 5200,400,CONT_BODY_P,* +V 5700,1000,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 1700,500,CONT_DIF_N,* +V 1000,1500,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 400,1500,CONT_DIF_N,* +V 400,1000,CONT_DIF_N,* +V 3400,4000,CONT_DIF_P,* +V 4600,4700,CONT_BODY_N,* +V 1000,3500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 4000,4700,CONT_BODY_N,* +V 3400,4700,CONT_BODY_N,* +V 1600,4000,CONT_DIF_P,* +V 5200,4700,CONT_BODY_N,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 2800,4500,CONT_DIF_P,* +V 2100,4700,CONT_BODY_N,* +V 5700,4000,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 2200,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 400,4000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x4.sym b/alliance/src/cells/src/sxlib/oa3ao322_x4.sym new file mode 100644 index 00000000..a6afb472 Binary files /dev/null and b/alliance/src/cells/src/sxlib/oa3ao322_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x4.vbe b/alliance/src/cells/src/sxlib/oa3ao322_x4.vbe new file mode 100644 index 00000000..6f1ad976 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT tpll_i6_q : NATURAL := 651; + CONSTANT tphh_i3_q : NATURAL := 673; + CONSTANT tphh_i6_q : NATURAL := 684; + CONSTANT tphh_i0_q : NATURAL := 717; + CONSTANT tphh_i4_q : NATURAL := 758; + CONSTANT tphh_i1_q : NATURAL := 818; + CONSTANT tpll_i2_q : NATURAL := 834; + CONSTANT tphh_i5_q : NATURAL := 839; + CONSTANT tpll_i5_q : NATURAL := 865; + CONSTANT tpll_i1_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 894; + CONSTANT tpll_i4_q : NATURAL := 896; + CONSTANT tpll_i3_q : NATURAL := 898; + CONSTANT tpll_i0_q : NATURAL := 946; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1500 ps; +END; diff --git a/alliance/src/cells/src/sxlib/oa3ao322_x4.vhd b/alliance/src/cells/src/sxlib/oa3ao322_x4.vhd new file mode 100644 index 00000000..24b29df7 --- /dev/null +++ b/alliance/src/cells/src/sxlib/oa3ao322_x4.vhd @@ -0,0 +1,25 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa3ao322_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa3ao322_x4; + +ARCHITECTURE RTL OF oa3ao322_x4 IS +BEGIN + q <= (((i0 AND i1) AND i2) OR (i6 AND ((i3 OR i4) OR i5))); +END RTL; diff --git a/alliance/src/cells/src/sxlib/on12_x1.al b/alliance/src/cells/src/sxlib/on12_x1.al new file mode 100644 index 00000000..209fc17f --- /dev/null +++ b/alliance/src/cells/src/sxlib/on12_x1.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H on12_x1,L,30/10/99 +C i0,IN,EXTERNAL,5 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,7,5,1,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006 +T P,0.35,2.9,1,2,7,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00005 +T P,0.35,2.9,7,6,2,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00004 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,4.5,tr_00003 +T N,0.35,2.9,4,5,1,0,0.75,0.75,7.3,7.3,4.8,3.75,tr_00002 +T N,0.35,2.9,3,2,4,0,0.75,0.75,7.3,7.3,3.6,3.75,tr_00001 +S 7,EXTERNAL,vdd +Q 0.0033382 +S 6,EXTERNAL,i1 +Q 0.00373582 +S 5,EXTERNAL,i0 +Q 0.00368237 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00316194 +S 2,INTERNAL +Q 0.00412385 +S 1,EXTERNAL,q +Q 0.00279086 +EOF diff --git a/alliance/src/cells/src/sxlib/on12_x1.ap b/alliance/src/cells/src/sxlib/on12_x1.ap new file mode 100644 index 00000000..a25d84a3 --- /dev/null +++ b/alliance/src/cells/src/sxlib/on12_x1.ap @@ -0,0 +1,74 @@ +V ALLIANCE : 6 +H on12_x1,P,30/ 8/2000,100 +A 0,0,2500,5000 +R 1500,1000,ref_ref,q_10 +R 1000,1000,ref_ref,i1_10 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 2000,3500,ref_ref,i0_35 +R 2000,3000,ref_ref,i0_30 +R 2000,2500,ref_ref,i0_25 +R 2000,2000,ref_ref,i0_20 +R 2000,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,q_15 +R 1500,2000,ref_ref,q_20 +R 1500,2500,ref_ref,q_25 +R 1500,3000,ref_ref,q_30 +R 1500,3500,ref_ref,q_35 +R 1500,4000,ref_ref,q_40 +R 2000,4000,ref_ref,i0_40 +S 300,3300,300,4200,300,*,UP,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 900,3300,900,4600,300,*,DOWN,PDIF +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 900,400,900,1700,300,*,UP,NDIF +S 1200,600,1200,1900,100,*,DOWN,NTRANS +S 1600,600,1600,1900,100,*,DOWN,NTRANS +S 1900,800,1900,1700,300,*,UP,NDIF +S 300,1300,300,1700,300,*,DOWN,NDIF +S 600,1100,600,1900,100,*,DOWN,NTRANS +S 300,2500,1200,2500,100,*,RIGHT,POLY +S 600,2000,800,2000,300,*,LEFT,POLY +S 600,3000,800,3000,300,*,LEFT,POLY +S 1200,1900,1200,3100,100,*,UP,POLY +S 1600,1900,2100,1900,100,*,RIGHT,POLY +S 1800,2000,2100,2000,300,*,RIGHT,POLY +S 1800,1900,1800,3100,100,*,DOWN,POLY +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1500,1000,1900,1000,200,*,RIGHT,ALU1 +S 1500,950,1500,4000,200,*,UP,ALU1 +S 300,1500,300,4000,100,*,UP,ALU1 +S 800,3000,1000,3000,200,*,RIGHT,ALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 800,2000,1000,2000,200,*,RIGHT,ALU1 +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1500,2000,4000,200,i0,DOWN,CALU1 +V 300,4700,CONT_BODY_N,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 2100,4500,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 1900,1000,CONT_DIF_N,* +V 300,1500,CONT_DIF_N,* +V 300,300,CONT_BODY_P,* +V 1750,300,CONT_BODY_P,* +V 300,2500,CONT_POLY,* +V 800,2000,CONT_POLY,* +V 800,3000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/on12_x1.sym b/alliance/src/cells/src/sxlib/on12_x1.sym new file mode 100644 index 00000000..6b8b5019 Binary files /dev/null and b/alliance/src/cells/src/sxlib/on12_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/on12_x1.vbe b/alliance/src/cells/src/sxlib/on12_x1.vbe new file mode 100644 index 00000000..32688f42 --- /dev/null +++ b/alliance/src/cells/src/sxlib/on12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3720; + CONSTANT rup_i1_q : NATURAL := 3720; + CONSTANT tphl_i0_q : NATURAL := 111; + CONSTANT tplh_i0_q : NATURAL := 234; + CONSTANT tpll_i1_q : NATURAL := 291; + CONSTANT tphh_i1_q : NATURAL := 314; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x1; + +ARCHITECTURE behaviour_data_flow OF on12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x1" + SEVERITY WARNING; + q <= (not (i0) or i1) after 900 ps; +END; diff --git a/alliance/src/cells/src/sxlib/on12_x1.vhd b/alliance/src/cells/src/sxlib/on12_x1.vhd new file mode 100644 index 00000000..8e0928f3 --- /dev/null +++ b/alliance/src/cells/src/sxlib/on12_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY on12_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END on12_x1; + +ARCHITECTURE RTL OF on12_x1 IS +BEGIN + q <= (NOT(i0) OR i1); +END RTL; diff --git a/alliance/src/cells/src/sxlib/on12_x4.al b/alliance/src/cells/src/sxlib/on12_x4.al new file mode 100644 index 00000000..3f58d0ad --- /dev/null +++ b/alliance/src/cells/src/sxlib/on12_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H on12_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,4,7,1,0,0.75,0.75,7.3,7.3,1.8,12.75,tr_00010 +T P,0.35,4.4,5,1,2,0,0.75,0.75,10.3,10.3,5.4,10.5,tr_00009 +T P,0.35,5.9,4,2,8,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00008 +T P,0.35,5.9,8,2,4,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00007 +T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,6.6,10.5,tr_00006 +T N,0.35,1.4,3,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005 +T N,0.35,2.9,8,2,3,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00004 +T N,0.35,2.9,3,2,8,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00003 +T N,0.35,1.4,3,1,2,0,0.75,0.75,4.3,4.3,4.8,3,tr_00002 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,6.6,3,tr_00001 +S 8,EXTERNAL,q +Q 0.00264397 +S 7,EXTERNAL,i0 +Q 0.00406025 +S 6,EXTERNAL,i1 +Q 0.00344095 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00589026 +S 3,EXTERNAL,vss +Q 0.00547897 +S 2,INTERNAL +Q 0.00629378 +S 1,INTERNAL +Q 0.00472684 +EOF diff --git a/alliance/src/cells/src/sxlib/on12_x4.ap b/alliance/src/cells/src/sxlib/on12_x4.ap new file mode 100644 index 00000000..916e1f56 --- /dev/null +++ b/alliance/src/cells/src/sxlib/on12_x4.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H on12_x4,P,30/ 8/2000,100 +A 0,0,4000,5000 +R 2500,2000,ref_ref,i1_20 +R 3000,1500,ref_ref,q_15 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 2500,2500,ref_ref,i1_25 +R 2500,3000,ref_ref,i1_30 +R 2500,3500,ref_ref,i1_35 +R 2500,4000,ref_ref,i1_40 +R 2500,1500,ref_ref,i1_15 +R 2500,1000,ref_ref,i1_10 +R 3000,1000,ref_ref,q_10 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,4000,ref_ref,i0_40 +R 1000,1000,ref_ref,i0_10 +S 1500,2900,1500,4000,100,*,DOWN,ALU1 +S 1900,1000,1900,2900,100,*,DOWN,ALU1 +S 1500,2900,1900,2900,100,*,RIGHT,ALU1 +S 3700,3000,3700,4500,200,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 2500,1000,2500,4000,100,*,UP,ALU1 +S 3700,500,3700,1000,200,*,DOWN,ALU1 +S 3000,950,3000,4050,200,*,UP,ALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 1600,1400,1600,2600,100,*,DOWN,POLY +S 1600,2600,1800,2600,100,*,RIGHT,POLY +S 2800,1400,2800,2600,100,*,DOWN,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2000,2000,3400,2000,100,*,RIGHT,POLY +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2200,600,2200,1400,100,*,DOWN,NTRANS +S 1900,800,1900,1200,300,*,UP,NDIF +S 1600,600,1600,1400,100,*,DOWN,NTRANS +S 3400,100,3400,1400,100,*,UP,NTRANS +S 3700,300,3700,1200,300,*,UP,NDIF +S 3100,300,3100,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 2200,2600,2200,4400,100,*,UP,PTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,UP,PDIF +S 2500,2800,2500,4700,300,*,UP,PDIF +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1500,2800,1500,4200,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1100,400,1100,1200,700,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,1400,600,1600,100,*,UP,POLY +S 600,1500,800,1500,100,*,RIGHT,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 300,2000,1600,2000,100,*,RIGHT,POLY +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 800,3500,1000,3500,200,*,RIGHT,ALU1 +S 600,3500,800,3500,100,*,RIGHT,POLY +S 600,3400,600,3600,100,*,DOWN,POLY +S 900,3800,900,4700,300,*,UP,PDIF +S 600,3600,600,4900,100,*,UP,PTRANS +S 300,3800,300,4700,300,*,UP,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 2500,1000,2500,4000,200,i1,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +V 300,300,CONT_BODY_P,* +V 2400,1500,CONT_POLY,* +V 2400,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 1900,300,CONT_BODY_P,* +V 2500,500,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 3700,500,CONT_DIF_N,* +V 3100,1000,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 1900,1000,CONT_DIF_N,* +V 1300,500,CONT_DIF_N,* +V 3100,3500,CONT_DIF_P,* +V 3100,4000,CONT_DIF_P,* +V 3700,4500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 2500,4500,CONT_DIF_P,* +V 3100,3000,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 1500,4000,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 800,3500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 1700,4700,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/on12_x4.sym b/alliance/src/cells/src/sxlib/on12_x4.sym new file mode 100644 index 00000000..6142c6ce Binary files /dev/null and b/alliance/src/cells/src/sxlib/on12_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/on12_x4.vbe b/alliance/src/cells/src/sxlib/on12_x4.vbe new file mode 100644 index 00000000..c5f990c6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/on12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 394; + CONSTANT tphl_i0_q : NATURAL := 474; + CONSTANT tphh_i1_q : NATURAL := 491; + CONSTANT tplh_i0_q : NATURAL := 499; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x4; + +ARCHITECTURE behaviour_data_flow OF on12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x4" + SEVERITY WARNING; + q <= (not (i0) or i1) after 1100 ps; +END; diff --git a/alliance/src/cells/src/sxlib/on12_x4.vhd b/alliance/src/cells/src/sxlib/on12_x4.vhd new file mode 100644 index 00000000..2e6b4193 --- /dev/null +++ b/alliance/src/cells/src/sxlib/on12_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY on12_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END on12_x4; + +ARCHITECTURE RTL OF on12_x4 IS +BEGIN + q <= (NOT(i0) OR i1); +END RTL; diff --git a/alliance/src/cells/src/sxlib/one_x0.al b/alliance/src/cells/src/sxlib/one_x0.al new file mode 100644 index 00000000..b41db892 --- /dev/null +++ b/alliance/src/cells/src/sxlib/one_x0.al @@ -0,0 +1,13 @@ +V ALLIANCE : 6 +H one_x0,L,30/10/99 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,1 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,2.1,9.75,tr_00001 +S 3,EXTERNAL,vss +Q 0.00473877 +S 2,EXTERNAL,q +Q 0.00223269 +S 1,EXTERNAL,vdd +Q 0.0037716 +EOF diff --git a/alliance/src/cells/src/sxlib/one_x0.ap b/alliance/src/cells/src/sxlib/one_x0.ap new file mode 100644 index 00000000..c5943501 --- /dev/null +++ b/alliance/src/cells/src/sxlib/one_x0.ap @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H one_x0,P, 6/ 9/2000,100 +A 0,0,1500,5000 +R 1000,1000,ref_ref,q_10 +R 1000,1500,ref_ref,q_15 +R 1000,2000,ref_ref,q_20 +R 1000,2500,ref_ref,q_25 +R 1000,3000,ref_ref,q_30 +R 1000,3500,ref_ref,q_35 +R 1000,4000,ref_ref,q_40 +S 500,2500,700,2500,300,*,RIGHT,POLY +S 500,500,1000,500,300,*,RIGHT,PTIE +S 500,500,500,1500,300,*,DOWN,PTIE +S 400,4500,1000,4500,300,*,RIGHT,NTIE +S 500,300,500,2500,200,*,DOWN,ALU1 +S 700,2400,700,2600,100,*,DOWN,POLY +S 400,3000,400,4700,200,*,UP,ALU1 +S 350,2800,350,3700,400,*,DOWN,PDIF +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 700,2600,700,3900,100,*,UP,PTRANS +S 1000,2800,1000,3700,300,*,DOWN,PDIF +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,q,DOWN,CALU1 +V 400,4500,CONT_BODY_N,* +V 1000,4500,CONT_BODY_N,* +V 1000,500,CONT_BODY_P,* +V 500,1500,CONT_BODY_P,* +V 500,1000,CONT_BODY_P,* +V 500,500,CONT_BODY_P,* +V 500,2500,CONT_POLY,* +V 400,3000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/one_x0.sym b/alliance/src/cells/src/sxlib/one_x0.sym new file mode 100644 index 00000000..9f9e2854 Binary files /dev/null and b/alliance/src/cells/src/sxlib/one_x0.sym differ diff --git a/alliance/src/cells/src/sxlib/one_x0.vbe b/alliance/src/cells/src/sxlib/one_x0.vbe new file mode 100644 index 00000000..e7439c59 --- /dev/null +++ b/alliance/src/cells/src/sxlib/one_x0.vbe @@ -0,0 +1,20 @@ +ENTITY one_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END one_x0; + +ARCHITECTURE behaviour_data_flow OF one_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on one_x0" + SEVERITY WARNING; + q <= '1'; +END; diff --git a/alliance/src/cells/src/sxlib/one_x0.vhd b/alliance/src/cells/src/sxlib/one_x0.vhd new file mode 100644 index 00000000..492070cb --- /dev/null +++ b/alliance/src/cells/src/sxlib/one_x0.vhd @@ -0,0 +1,18 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY one_x0 IS +PORT( + q : OUT STD_LOGIC +); +END one_x0; + +ARCHITECTURE RTL OF one_x0 IS +BEGIN + q <= '1'; +END RTL; diff --git a/alliance/src/cells/src/sxlib/powmid_x0.ap b/alliance/src/cells/src/sxlib/powmid_x0.ap new file mode 100644 index 00000000..5f076308 --- /dev/null +++ b/alliance/src/cells/src/sxlib/powmid_x0.ap @@ -0,0 +1,12 @@ +V ALLIANCE : 6 +H powmid_x0,P,18/ 9/2000,100 +A 0,0,3500,5000 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 1000,0,1000,5000,1200,vdd,DOWN,CALU3 +S 2500,0,2500,5000,1200,vss,DOWN,CALU3 +B 2500,0,1200,200,CONT_VIA,* +B 2500,0,1200,200,CONT_VIA2,* +B 1000,5000,1200,200,CONT_VIA,* +B 1000,5000,1200,200,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/sxlib/powmid_x0.vbe b/alliance/src/cells/src/sxlib/powmid_x0.vbe new file mode 100644 index 00000000..03293e5d --- /dev/null +++ b/alliance/src/cells/src/sxlib/powmid_x0.vbe @@ -0,0 +1,14 @@ +ENTITY powmid_x0 IS +PORT ( + vdd : in BIT; + vss : in BIT +); +END powmid_x0; + +ARCHITECTURE behaviour_data_flow OF powmid_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on powmid_x0" + SEVERITY WARNING; +END; diff --git a/alliance/src/cells/src/sxlib/powmid_x0.vhd b/alliance/src/cells/src/sxlib/powmid_x0.vhd new file mode 100644 index 00000000..e6b0b9d0 --- /dev/null +++ b/alliance/src/cells/src/sxlib/powmid_x0.vhd @@ -0,0 +1,16 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY powmid_x0 IS +PORT( +); +END powmid_x0; + +ARCHITECTURE RTL OF powmid_x0 IS +BEGIN +END RTL; diff --git a/alliance/src/cells/src/sxlib/rowend_x0.al b/alliance/src/cells/src/sxlib/rowend_x0.al new file mode 100644 index 00000000..a54f5a21 --- /dev/null +++ b/alliance/src/cells/src/sxlib/rowend_x0.al @@ -0,0 +1,9 @@ +V ALLIANCE : 6 +H rowend_x0,L,30/10/99 +C vdd,IN,EXTERNAL,2 +C vss,IN,EXTERNAL,1 +S 2,EXTERNAL,vdd +Q 0.00126725 +S 1,EXTERNAL,vss +Q 0.00126725 +EOF diff --git a/alliance/src/cells/src/sxlib/rowend_x0.ap b/alliance/src/cells/src/sxlib/rowend_x0.ap new file mode 100644 index 00000000..5674d949 --- /dev/null +++ b/alliance/src/cells/src/sxlib/rowend_x0.ap @@ -0,0 +1,7 @@ +V ALLIANCE : 6 +H rowend_x0,P,30/ 8/2000,100 +A 0,0,500,5000 +S 0,4700,500,4700,600,vdd,RIGHT,CALU1 +S 0,300,500,300,600,vss,RIGHT,CALU1 +S 0,3900,500,3900,2400,*,RIGHT,NWELL +EOF diff --git a/alliance/src/cells/src/sxlib/rowend_x0.vbe b/alliance/src/cells/src/sxlib/rowend_x0.vbe new file mode 100644 index 00000000..a6aa24ba --- /dev/null +++ b/alliance/src/cells/src/sxlib/rowend_x0.vbe @@ -0,0 +1,14 @@ +ENTITY rowend_x0 IS +PORT ( + vdd : in BIT; + vss : in BIT +); +END rowend_x0; + +ARCHITECTURE behaviour_data_flow OF rowend_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rowend_x0" + SEVERITY WARNING; +END; diff --git a/alliance/src/cells/src/sxlib/rowend_x0.vhd b/alliance/src/cells/src/sxlib/rowend_x0.vhd new file mode 100644 index 00000000..b21c2701 --- /dev/null +++ b/alliance/src/cells/src/sxlib/rowend_x0.vhd @@ -0,0 +1,16 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY rowend_x0 IS +PORT( +); +END rowend_x0; + +ARCHITECTURE RTL OF rowend_x0 IS +BEGIN +END RTL; diff --git a/alliance/src/cells/src/sxlib/sff1_x4.al b/alliance/src/cells/src/sxlib/sff1_x4.al new file mode 100644 index 00000000..ea46bf2a --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff1_x4.al @@ -0,0 +1,68 @@ +V ALLIANCE : 6 +H sff1_x4,L,30/10/99 +C ck,IN,EXTERNAL,5 +C i,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,17,13,14,0,0.75,0.75,7.3,7.3,21.6,12.75,tr_00026 +T P,0.35,2.9,12,3,17,0,0.75,0.75,7.3,7.3,19.8,12.75,tr_00025 +T P,0.35,2.9,9,2,12,0,0.75,0.75,7.3,7.3,18,12.75,tr_00024 +T P,0.35,2.9,7,2,15,0,0.75,0.75,7.3,7.3,12.6,11.25,tr_00023 +T P,0.35,2.9,15,9,14,0,0.75,0.75,7.3,7.3,14.4,12.75,tr_00022 +T P,0.35,2.9,16,3,7,0,0.75,0.75,7.3,7.3,10.8,11.25,tr_00021 +T P,0.35,2.9,2,5,14,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00020 +T P,0.35,2.9,14,2,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00019 +T P,0.35,2.9,4,6,14,0,0.75,0.75,7.3,7.3,7.2,12.75,tr_00018 +T P,0.35,2.9,14,4,16,0,0.75,0.75,7.3,7.3,9,12.75,tr_00017 +T P,0.35,5.9,14,12,13,0,0.75,0.75,13.3,13.3,23.4,11.25,tr_00016 +T P,0.35,5.9,13,12,14,0,0.75,0.75,13.3,13.3,25.2,11.25,tr_00015 +T P,0.35,2.9,9,7,14,0,0.75,0.75,7.3,7.3,16.2,12.75,tr_00014 +T N,0.35,1.4,11,2,12,0,0.75,0.75,4.3,4.3,19.8,3,tr_00013 +T N,0.35,1.4,1,13,11,0,0.75,0.75,4.3,4.3,21.6,3,tr_00012 +T N,0.35,1.4,12,3,9,0,0.75,0.75,4.3,4.3,18,3,tr_00011 +T N,0.35,1.4,1,9,8,0,0.75,0.75,4.3,4.3,14.4,1.5,tr_00010 +T N,0.35,1.4,8,3,7,0,0.75,0.75,4.3,4.3,12.6,3,tr_00009 +T N,0.35,1.4,7,2,10,0,0.75,0.75,4.3,4.3,10.8,3,tr_00008 +T N,0.35,1.4,3,2,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00007 +T N,0.35,1.4,1,5,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006 +T N,0.35,1.4,10,4,1,0,0.75,0.75,4.3,4.3,9,3,tr_00005 +T N,0.35,1.4,1,6,4,0,0.75,0.75,4.3,4.3,7.2,3,tr_00004 +T N,0.35,2.9,13,12,1,0,0.75,0.75,7.3,7.3,23.4,2.25,tr_00003 +T N,0.35,2.9,1,12,13,0,0.75,0.75,7.3,7.3,25.2,2.25,tr_00002 +T N,0.35,1.4,9,7,1,0,0.75,0.75,4.3,4.3,16.2,1.5,tr_00001 +S 17,INTERNAL +Q 0 +S 16,INTERNAL +Q 0 +S 15,INTERNAL +Q 0 +S 14,EXTERNAL,vdd +Q 0.0115377 +S 13,EXTERNAL,q +Q 0.00615082 +S 12,INTERNAL,sff_s +Q 0.00679978 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,INTERNAL,y +Q 0.00480814 +S 8,INTERNAL +Q 0 +S 7,INTERNAL,sff_m +Q 0.00642301 +S 6,EXTERNAL,i +Q 0.00344388 +S 5,EXTERNAL,ck +Q 0.00344095 +S 4,INTERNAL,u +Q 0.00567853 +S 3,INTERNAL,ckr +Q 0.0113963 +S 2,INTERNAL,nckr +Q 0.0123833 +S 1,EXTERNAL,vss +Q 0.0103626 +EOF diff --git a/alliance/src/cells/src/sxlib/sff1_x4.ap b/alliance/src/cells/src/sxlib/sff1_x4.ap new file mode 100644 index 00000000..e8251622 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff1_x4.ap @@ -0,0 +1,221 @@ +V ALLIANCE : 6 +H sff1_x4,P,30/ 8/2000,100 +A 0,0,9000,5000 +R 8000,2000,ref_ref,q_20 +R 1000,4000,ref_ref,ck_40 +R 1000,3500,ref_ref,ck_35 +R 1000,3000,ref_ref,ck_30 +R 1000,2500,ref_ref,ck_25 +R 1000,2000,ref_ref,ck_20 +R 1000,1500,ref_ref,ck_15 +R 1000,1000,ref_ref,ck_10 +R 2500,3500,ref_ref,i_35 +R 2500,3000,ref_ref,i_30 +R 2500,2500,ref_ref,i_25 +R 2500,2000,ref_ref,i_20 +R 2500,1500,ref_ref,i_15 +R 3000,1000,ref_ref,i_10 +R 8000,4000,ref_ref,q_40 +R 8000,3500,ref_ref,q_35 +R 8000,3000,ref_ref,q_30 +R 8000,2500,ref_ref,q_25 +R 8000,1500,ref_ref,q_15 +R 8000,1000,ref_ref,q_10 +R 3000,4000,ref_ref,i_40 +S 7300,2000,8400,2000,300,sff_s,RIGHT,POLY +S 6900,2000,7400,2000,100,*,RIGHT,ALU1 +S 7200,2400,7200,3600,100,*,UP,POLY +S 2050,1000,2050,4000,100,*,DOWN,ALU1 +S 2550,4000,3000,4000,100,*,RIGHT,ALU1 +S 2550,1000,3000,1000,100,*,RIGHT,ALU1 +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 6300,300,6900,300,300,*,RIGHT,PTIE +S 3300,300,3900,300,300,*,RIGHT,PTIE +S 1500,300,2100,300,300,*,RIGHT,PTIE +S 300,3500,300,4000,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 5000,3500,5700,3500,100,*,LEFT,ALU1 +S 5700,1000,5700,4000,100,y,DOWN,ALU1 +S 7400,1500,8100,1500,100,*,RIGHT,ALU1 +S 7400,2500,8100,2500,100,*,RIGHT,ALU1 +S 7500,500,7500,1000,200,*,DOWN,ALU1 +S 8700,500,8700,1000,200,*,DOWN,ALU1 +S 7500,3000,7500,4500,200,*,DOWN,ALU1 +S 8700,3000,8700,4500,200,*,DOWN,ALU1 +S 4500,1500,5200,1500,100,*,LEFT,ALU1 +S 3900,1000,4500,1000,100,*,RIGHT,ALU1 +S 5000,1000,5700,1000,100,*,RIGHT,ALU1 +S 6300,2000,6300,3500,100,*,DOWN,ALU1 +S 4500,3000,5200,3000,100,*,RIGHT,ALU1 +S 0,4700,9000,4700,600,vdd,RIGHT,CALU1 +S 0,300,9000,300,600,vss,RIGHT,CALU1 +S 6600,1400,6600,2500,100,*,DOWN,POLY +S 7800,1400,7800,2600,100,*,DOWN,POLY +S 7200,1500,7500,1500,300,*,RIGHT,POLY +S 7200,2500,7500,2500,300,*,RIGHT,POLY +S 8400,1400,8400,2600,100,*,DOWN,POLY +S 6000,1400,6000,2000,100,*,DOWN,POLY +S 5400,900,5400,1500,100,*,UP,POLY +S 5400,3000,5400,3600,100,*,DOWN,POLY +S 6000,2500,6000,3600,100,*,DOWN,POLY +S 4200,1400,4200,2000,100,*,DOWN,POLY +S 5600,3800,5600,4700,300,*,DOWN,PDIF +S 5000,3800,5000,4700,300,*,DOWN,PDIF +S 5400,3600,5400,4900,100,*,UP,PTRANS +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 8400,2600,8400,4900,100,*,DOWN,PTRANS +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 7800,2600,7800,4900,100,*,DOWN,PTRANS +S 7500,2800,7500,4700,300,*,DOWN,PDIF +S 3000,3600,3000,4900,100,*,DOWN,PTRANS +S 6900,3800,6900,4700,300,*,UP,PDIF +S 2400,3600,2400,4900,100,*,DOWN,PTRANS +S 2700,3800,2700,4700,300,*,UP,PDIF +S 2100,3800,2100,4700,300,*,UP,PDIF +S 5400,100,5400,900,100,*,UP,NTRANS +S 5700,300,5700,700,300,*,DOWN,NDIF +S 5100,300,5100,700,300,*,DOWN,NDIF +S 5700,300,5700,1200,300,*,DOWN,NDIF +S 7500,300,7500,1200,300,*,DOWN,NDIF +S 8100,300,8100,1200,300,*,DOWN,NDIF +S 8400,100,8400,1400,100,*,UP,NTRANS +S 8700,300,8700,1200,300,*,DOWN,NDIF +S 6900,800,6900,1200,300,*,DOWN,NDIF +S 7800,100,7800,1400,100,*,UP,NTRANS +S 3900,800,3900,1200,300,*,DOWN,NDIF +S 4500,300,4500,1200,300,*,DOWN,NDIF +S 2100,800,2100,1200,300,*,DOWN,NDIF +S 2400,600,2400,1400,100,*,UP,NTRANS +S 3000,600,3000,1400,100,*,UP,NTRANS +S 2700,400,2700,1200,300,*,DOWN,NDIF +S 0,3900,9000,3900,2400,*,RIGHT,NWELL +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 900,3300,900,4600,300,*,UP,PDIF +S 3500,1500,3500,2500,100,*,DOWN,ALU1 +S 600,3000,900,3000,300,*,RIGHT,POLY +S 6000,2000,6300,2000,300,*,RIGHT,POLY +S 3900,2000,4200,2000,300,*,RIGHT,POLY +S 5100,3000,5400,3000,300,*,RIGHT,POLY +S 6300,3500,6600,3500,300,*,RIGHT,POLY +S 4800,3500,5100,3500,300,*,RIGHT,POLY +S 5100,1500,5400,1500,300,*,RIGHT,POLY +S 4800,1000,5100,1000,300,*,RIGHT,POLY +S 2000,3000,3000,3000,100,*,RIGHT,POLY +S 300,800,300,1200,300,*,DOWN,NDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 900,400,900,1200,300,*,DOWN,NDIF +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1500,900,1500,300,*,RIGHT,POLY +S 1500,3300,1500,4200,300,*,UP,PDIF +S 300,2500,6600,2500,100,nckr,RIGHT,POLY +S 1600,2000,6000,2000,100,ckr,RIGHT,POLY +S 3500,3000,4000,3000,100,*,RIGHT,ALU1 +S 3900,3300,3900,4200,300,*,UP,PDIF +S 4200,2500,4200,3100,100,*,DOWN,POLY +S 4000,2000,4000,3000,100,*,UP,ALU1 +S 4500,3300,4500,4700,300,*,UP,PDIF +S 3000,3100,3000,3600,100,*,UP,POLY +S 3000,1500,3000,3000,100,u,DOWN,ALU1 +S 3900,3500,4500,3500,100,*,RIGHT,ALU1 +S 6900,1000,6900,4000,100,*,DOWN,ALU1 +S 4500,1000,4500,3500,100,sff_m,DOWN,ALU1 +S 3300,3300,3300,4700,300,*,UP,PDIF +S 3300,800,3300,1200,300,*,DOWN,NDIF +S 3600,600,3600,1400,100,*,UP,NTRANS +S 3600,3100,3600,4400,100,*,DOWN,PTRANS +S 4800,3600,4800,4900,100,*,DOWN,PTRANS +S 4200,3100,4200,4400,100,*,DOWN,PTRANS +S 4200,600,4200,1400,100,*,UP,NTRANS +S 4800,100,4800,900,100,*,UP,NTRANS +S 6000,600,6000,1400,100,*,UP,NTRANS +S 6000,3600,6000,4900,100,*,DOWN,PTRANS +S 6600,3600,6600,4900,100,*,DOWN,PTRANS +S 7200,3600,7200,4900,100,*,DOWN,PTRANS +S 7200,600,7200,1400,100,*,UP,NTRANS +S 6600,600,6600,1400,100,*,UP,NTRANS +S 6300,3800,6300,4700,300,*,DOWN,PDIF +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 6300,1000,6900,1000,100,*,RIGHT,ALU1 +S 6300,4000,6900,4000,100,*,RIGHT,ALU1 +S 8000,1000,8000,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,ck,DOWN,CALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 800,3000,1000,3000,200,*,RIGHT,ALU1 +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 2500,1500,2500,3500,200,i,DOWN,CALU1 +S 3000,4000,3000,4000,200,i,LEFT,CALU1 +S 3000,1000,3000,1000,200,i,LEFT,CALU1 +S 8000,1000,8000,4000,200,*,DOWN,ALU1 +V 7400,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 5000,3500,CONT_POLY,* +V 7400,2500,CONT_POLY,* +V 7400,1500,CONT_POLY,* +V 5200,1500,CONT_POLY,* +V 6200,2000,CONT_POLY,* +V 5200,3000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 5000,1000,CONT_POLY,* +V 6400,3500,CONT_POLY,* +V 6300,4000,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 8700,3000,CONT_DIF_P,* +V 8100,3000,CONT_DIF_P,* +V 7500,3000,CONT_DIF_P,* +V 7500,3500,CONT_DIF_P,* +V 7500,4000,CONT_DIF_P,* +V 8700,4500,CONT_DIF_P,* +V 7500,4500,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 8700,3500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 6300,1000,CONT_DIF_N,* +V 5100,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 5700,1000,CONT_DIF_N,* +V 8700,500,CONT_DIF_N,* +V 7500,500,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 7500,1000,CONT_DIF_N,* +V 8100,1000,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,3500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 800,3000,CONT_POLY,* +V 300,2500,CONT_POLY,* +V 1600,2000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 300,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 300,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 3300,300,CONT_BODY_P,* +V 3900,300,CONT_BODY_P,* +V 2500,3500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 800,1500,CONT_POLY,* +V 8100,4000,CONT_DIF_P,* +V 8100,3500,CONT_DIF_P,* +V 6300,300,CONT_BODY_P,* +V 6900,300,CONT_BODY_P,* +V 2100,4000,CONT_DIF_P,* +V 3500,3000,CONT_POLY,* +V 3900,4700,CONT_BODY_N,* +V 3900,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/sff1_x4.sym b/alliance/src/cells/src/sxlib/sff1_x4.sym new file mode 100644 index 00000000..6702478b Binary files /dev/null and b/alliance/src/cells/src/sxlib/sff1_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/sff1_x4.vbe b/alliance/src/cells/src/sxlib/sff1_x4.vbe new file mode 100644 index 00000000..4756bfdd --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff1_x4.vbe @@ -0,0 +1,39 @@ +ENTITY sff1_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476; + CONSTANT transistors : NATURAL := 26 +); +PORT ( + ck : in BIT; + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff1_x4; + +ARCHITECTURE VBE OF sff1_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED i; + END BLOCK label0; + + q <= sff_m after 1700 ps; +END; diff --git a/alliance/src/cells/src/sxlib/sff1_x4.vhd b/alliance/src/cells/src/sxlib/sff1_x4.vhd new file mode 100644 index 00000000..b274aa53 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff1_x4.vhd @@ -0,0 +1,27 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY sff1_x4 IS +PORT( + ck : IN STD_LOGIC; + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END sff1_x4; + +ARCHITECTURE RTL OF sff1_x4 IS + SIGNAL sff_m : STD_LOGIC; +BEGIN + q <= sff_m; + PROCESS ( ck ) + BEGIN + IF ((ck = '1') AND ck'EVENT) + THEN sff_m <= i; + END IF; + END PROCESS; +END RTL; diff --git a/alliance/src/cells/src/sxlib/sff2_x4.al b/alliance/src/cells/src/sxlib/sff2_x4.al new file mode 100644 index 00000000..fe6cd3d3 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff2_x4.al @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H sff2_x4,L,30/10/99 +C ck,IN,EXTERNAL,11 +C cmd,IN,EXTERNAL,6 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,17 +C vdd,IN,EXTERNAL,19 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,19,16,17,0,0.75,0.75,13.3,13.3,32.4,11.25,tr_00034 +T P,0.35,2.9,19,3,23,0,0.75,0.75,7.3,7.3,18,12.75,tr_00033 +T P,0.35,2.9,15,14,19,0,0.75,0.75,7.3,7.3,25.2,12.75,tr_00032 +T P,0.35,5.9,17,16,19,0,0.75,0.75,13.3,13.3,34.2,11.25,tr_00031 +T P,0.35,2.9,10,11,19,0,0.75,0.75,7.3,7.3,12.6,11.25,tr_00030 +T P,0.35,2.9,19,10,9,0,0.75,0.75,7.3,7.3,14.4,11.25,tr_00029 +T P,0.35,2.9,3,5,20,0,0.75,0.75,7.3,7.3,7.5,11.25,tr_00028 +T P,0.35,2.9,21,6,3,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00027 +T P,0.35,2.9,20,8,19,0,0.75,0.75,7.3,7.3,8.7,11.25,tr_00026 +T P,0.35,2.9,5,6,19,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00025 +T P,0.35,2.9,19,7,21,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00024 +T P,0.35,2.9,23,9,14,0,0.75,0.75,7.3,7.3,19.8,11.25,tr_00023 +T P,0.35,2.9,14,10,22,0,0.75,0.75,7.3,7.3,21.6,11.25,tr_00022 +T P,0.35,2.9,22,15,19,0,0.75,0.75,7.3,7.3,23.4,12.75,tr_00021 +T P,0.35,2.9,15,10,16,0,0.75,0.75,7.3,7.3,27,12.75,tr_00020 +T P,0.35,2.9,16,9,24,0,0.75,0.75,7.3,7.3,28.8,12.75,tr_00019 +T P,0.35,2.9,24,17,19,0,0.75,0.75,7.3,7.3,30.6,12.75,tr_00018 +T N,0.35,1.4,12,3,1,0,0.75,0.75,4.3,4.3,18,3,tr_00017 +T N,0.35,2.9,17,16,1,0,0.75,0.75,7.3,7.3,32.4,2.25,tr_00016 +T N,0.35,2.9,1,16,17,0,0.75,0.75,7.3,7.3,34.2,2.25,tr_00015 +T N,0.35,1.4,15,14,1,0,0.75,0.75,4.3,4.3,25.2,1.5,tr_00014 +T N,0.35,1.4,1,11,10,0,0.75,0.75,4.3,4.3,12.6,3,tr_00013 +T N,0.35,1.4,9,10,1,0,0.75,0.75,4.3,4.3,14.4,3,tr_00012 +T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,8.7,3,tr_00011 +T N,0.35,1.4,3,5,4,0,0.75,0.75,4.3,4.3,4.8,3,tr_00010 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,7.5,3,tr_00009 +T N,0.35,1.4,4,7,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00008 +T N,0.35,1.4,1,6,5,0,0.75,0.75,4.3,4.3,1.8,3,tr_00007 +T N,0.35,1.4,14,10,12,0,0.75,0.75,4.3,4.3,19.8,3,tr_00006 +T N,0.35,1.4,13,9,14,0,0.75,0.75,4.3,4.3,21.6,3,tr_00005 +T N,0.35,1.4,1,15,13,0,0.75,0.75,4.3,4.3,23.4,1.5,tr_00004 +T N,0.35,1.4,16,9,15,0,0.75,0.75,4.3,4.3,27,3,tr_00003 +T N,0.35,1.4,18,10,16,0,0.75,0.75,4.3,4.3,28.8,3,tr_00002 +T N,0.35,1.4,1,17,18,0,0.75,0.75,4.3,4.3,30.6,3,tr_00001 +S 24,INTERNAL +Q 0 +S 23,INTERNAL +Q 0 +S 22,INTERNAL +Q 0 +S 21,INTERNAL +Q 0 +S 20,INTERNAL +Q 0 +S 19,EXTERNAL,vdd +Q 0.0144679 +S 18,INTERNAL +Q 0 +S 17,EXTERNAL,q +Q 0.00615082 +S 16,INTERNAL,sff_s +Q 0.0067122 +S 15,INTERNAL,y +Q 0.00480814 +S 14,INTERNAL,sff_m +Q 0.00642301 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0 +S 11,EXTERNAL,ck +Q 0.0031591 +S 10,INTERNAL,nckr +Q 0.011396 +S 9,INTERNAL,ckr +Q 0.0110493 +S 8,EXTERNAL,i1 +Q 0.00242923 +S 7,EXTERNAL,i0 +Q 0.0031591 +S 6,EXTERNAL,cmd +Q 0.00541426 +S 5,INTERNAL +Q 0.00654862 +S 4,INTERNAL +Q 0 +S 3,INTERNAL,u +Q 0.00667128 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.0131165 +EOF diff --git a/alliance/src/cells/src/sxlib/sff2_x4.ap b/alliance/src/cells/src/sxlib/sff2_x4.ap new file mode 100644 index 00000000..a9e3766c --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff2_x4.ap @@ -0,0 +1,266 @@ +V ALLIANCE : 6 +H sff2_x4,P,30/ 8/2000,100 +A 0,0,12000,5000 +R 4500,1000,ref_ref,ck_10 +R 4500,3500,ref_ref,ck_35 +R 4500,3000,ref_ref,ck_30 +R 4500,2500,ref_ref,ck_25 +R 4500,2000,ref_ref,ck_20 +R 4500,1500,ref_ref,ck_15 +R 1000,1500,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,4000,ref_ref,i0_40 +R 3000,1000,ref_ref,i1_10 +R 3000,1500,ref_ref,i1_15 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 1500,2500,ref_ref,cmd_25 +R 1500,3000,ref_ref,cmd_30 +R 1500,3500,ref_ref,cmd_35 +R 1500,4000,ref_ref,cmd_40 +R 11000,1000,ref_ref,q_10 +R 11000,1500,ref_ref,q_15 +R 11000,2500,ref_ref,q_25 +R 11000,3000,ref_ref,q_30 +R 11000,3500,ref_ref,q_35 +R 11000,4000,ref_ref,q_40 +R 11000,2000,ref_ref,q_20 +S 11000,1000,11000,4000,200,*,DOWN,ALU1 +S 10200,600,10200,1400,100,*,UP,NTRANS +S 9600,600,9600,1400,100,*,UP,NTRANS +S 10200,3600,10200,4900,100,*,DOWN,PTRANS +S 9600,3600,9600,4900,100,*,DOWN,PTRANS +S 9000,3600,9000,4900,100,*,DOWN,PTRANS +S 9000,600,9000,1400,100,*,UP,NTRANS +S 7800,100,7800,900,100,*,UP,NTRANS +S 7200,600,7200,1400,100,*,UP,NTRANS +S 7800,3600,7800,4900,100,*,DOWN,PTRANS +S 7200,3100,7200,4400,100,*,DOWN,PTRANS +S 6600,3100,6600,4400,100,*,DOWN,PTRANS +S 6600,600,6600,1400,100,*,UP,NTRANS +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 9300,300,9900,300,300,*,RIGHT,PTIE +S 6300,300,6900,300,300,*,RIGHT,PTIE +S 1500,300,2500,300,300,*,RIGHT,PTIE +S 0,3900,12000,3900,2400,*,RIGHT,NWELL +S 900,400,900,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1200,600,1200,1400,100,*,UP,NTRANS +S 2500,600,2500,1400,100,*,UP,NTRANS +S 1900,800,1900,1200,300,*,UP,NDIF +S 1600,600,1600,1400,100,*,UP,NTRANS +S 3200,400,3200,1200,300,*,UP,NDIF +S 2900,600,2900,1400,100,*,UP,NTRANS +S 2100,800,2100,1600,500,*,DOWN,NDIF +S 4800,600,4800,1400,100,*,UP,NTRANS +S 4500,400,4500,1200,300,*,DOWN,NDIF +S 3900,800,3900,1200,300,*,DOWN,NDIF +S 4200,600,4200,1400,100,*,UP,NTRANS +S 5100,800,5100,1200,300,*,DOWN,NDIF +S 8100,300,8100,700,300,*,DOWN,NDIF +S 8700,300,8700,700,300,*,DOWN,NDIF +S 8400,100,8400,900,100,*,UP,NTRANS +S 11700,300,11700,1200,300,*,DOWN,NDIF +S 11400,100,11400,1400,100,*,UP,NTRANS +S 11100,300,11100,1200,300,*,DOWN,NDIF +S 10500,300,10500,1200,300,*,DOWN,NDIF +S 8700,300,8700,1200,300,*,DOWN,NDIF +S 9300,800,9300,1200,300,*,DOWN,NDIF +S 10800,100,10800,1400,100,*,UP,NTRANS +S 9900,800,9900,1200,300,*,DOWN,NDIF +S 5700,400,5700,1200,300,*,DOWN,NDIF +S 6000,600,6000,1400,100,*,UP,NTRANS +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 7500,300,7500,1200,300,*,DOWN,NDIF +S 6900,800,6900,1200,300,*,DOWN,NDIF +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 2900,3100,2900,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 3200,3300,3200,4600,300,*,DOWN,PDIF +S 2500,3100,2500,4400,100,*,DOWN,PTRANS +S 5100,3300,5100,4200,300,*,UP,PDIF +S 4800,3100,4800,4400,100,*,DOWN,PTRANS +S 4200,3100,4200,4400,100,*,DOWN,PTRANS +S 3900,3300,3900,4200,300,*,UP,PDIF +S 8000,3800,8000,4700,300,*,DOWN,PDIF +S 9300,3800,9300,4700,300,*,DOWN,PDIF +S 8600,3800,8600,4700,300,*,DOWN,PDIF +S 4500,3300,4500,4600,300,*,UP,PDIF +S 11700,2800,11700,4700,300,*,DOWN,PDIF +S 11400,2600,11400,4900,100,*,DOWN,PTRANS +S 11100,2800,11100,4700,300,*,DOWN,PDIF +S 8400,3600,8400,4900,100,*,UP,PTRANS +S 9900,3800,9900,4700,300,*,UP,PDIF +S 6000,3600,6000,4900,100,*,DOWN,PTRANS +S 10500,2800,10500,4700,300,*,DOWN,PDIF +S 10800,2600,10800,4900,100,*,DOWN,PTRANS +S 7500,3300,7500,4700,300,*,UP,PDIF +S 6900,3300,6900,4200,300,*,UP,PDIF +S 6300,3300,6300,4700,300,*,UP,PDIF +S 5700,3800,5700,4700,300,*,UP,PDIF +S 7800,1000,8100,1000,300,*,RIGHT,POLY +S 8400,900,8400,1500,100,*,UP,POLY +S 600,2500,2500,2500,100,*,RIGHT,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 900,1500,1200,1500,300,*,RIGHT,POLY +S 900,3000,1200,3000,300,*,RIGHT,POLY +S 2500,1400,2500,2500,100,*,DOWN,POLY +S 1600,1400,1600,2000,100,*,DOWN,POLY +S 1600,2500,1600,3100,100,*,DOWN,POLY +S 4200,3000,4500,3000,300,*,RIGHT,POLY +S 5100,2000,9000,2000,100,ckr,RIGHT,POLY +S 3900,2500,9600,2500,100,nckr,RIGHT,POLY +S 10200,2500,10500,2500,300,*,RIGHT,POLY +S 10200,1500,10500,1500,300,*,RIGHT,POLY +S 10800,1400,10800,2600,100,*,DOWN,POLY +S 9600,1400,9600,2500,100,*,DOWN,POLY +S 4800,1400,4800,3100,100,*,DOWN,POLY +S 4200,1500,4500,1500,300,*,RIGHT,POLY +S 6900,2000,7200,2000,300,*,RIGHT,POLY +S 9000,2000,9300,2000,300,*,RIGHT,POLY +S 7200,1400,7200,2000,100,*,DOWN,POLY +S 9000,2500,9000,3600,100,*,DOWN,POLY +S 8400,3000,8400,3600,100,*,DOWN,POLY +S 9000,1400,9000,2000,100,*,DOWN,POLY +S 11400,1400,11400,2600,100,*,DOWN,POLY +S 7200,2500,7200,3100,100,*,DOWN,POLY +S 8100,1500,8400,1500,300,*,RIGHT,POLY +S 7800,3500,8100,3500,300,*,RIGHT,POLY +S 9300,3500,9600,3500,300,*,RIGHT,POLY +S 8100,3000,8400,3000,300,*,RIGHT,POLY +S 0,300,12000,300,600,vss,RIGHT,CALU1 +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 4500,1000,4500,3500,100,*,DOWN,ALU1 +S 5100,1000,5100,3500,100,*,DOWN,ALU1 +S 2500,1000,2500,3000,100,*,DOWN,ALU1 +S 1500,1000,1500,2000,100,*,UP,ALU1 +S 8700,1000,8700,4000,100,y,DOWN,ALU1 +S 3000,1000,3000,3500,100,*,DOWN,ALU1 +S 3900,1000,3900,3500,100,*,DOWN,ALU1 +S 8000,1000,8700,1000,100,*,RIGHT,ALU1 +S 6900,1000,7500,1000,100,*,RIGHT,ALU1 +S 9300,1000,9900,1000,100,*,RIGHT,ALU1 +S 11700,500,11700,1000,200,*,DOWN,ALU1 +S 10500,500,10500,1000,200,*,DOWN,ALU1 +S 0,4700,12000,4700,600,vdd,RIGHT,CALU1 +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 2000,4000,6000,4000,100,*,RIGHT,ALU1 +S 1500,2500,1500,4000,100,*,DOWN,ALU1 +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 8000,3500,8700,3500,100,*,LEFT,ALU1 +S 11700,3000,11700,4500,200,*,DOWN,ALU1 +S 10500,3000,10500,4500,200,*,DOWN,ALU1 +S 10400,2500,11100,2500,100,*,RIGHT,ALU1 +S 10400,1500,11100,1500,100,*,RIGHT,ALU1 +S 7500,3000,8200,3000,100,*,RIGHT,ALU1 +S 9300,2000,9300,3500,100,*,DOWN,ALU1 +S 7500,1500,8200,1500,100,*,LEFT,ALU1 +S 9300,4000,9900,4000,100,*,RIGHT,ALU1 +S 6900,3500,7500,3500,100,*,RIGHT,ALU1 +S 6000,1500,6000,4000,100,u,DOWN,ALU1 +S 7000,2000,7000,3000,100,*,UP,ALU1 +S 6500,3000,7000,3000,100,*,RIGHT,ALU1 +S 6500,1500,6500,2500,100,*,DOWN,ALU1 +S 7500,1000,7500,3500,100,sff_m,DOWN,ALU1 +S 9900,1000,9900,4000,100,sff_s,DOWN,ALU1 +S 10200,2400,10200,3600,100,*,DOWN,POLY +S 9900,2000,10400,2000,100,*,RIGHT,ALU1 +S 10400,2000,11400,2000,300,*,RIGHT,POLY +S 4500,1000,4500,3500,200,ck,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 3000,1000,3000,3500,200,i1,DOWN,CALU1 +S 1500,2500,1500,4000,200,cmd,DOWN,CALU1 +S 11000,1000,11000,4000,200,q,DOWN,CALU1 +V 4000,2500,CONT_POLY,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 3200,500,CONT_DIF_N,* +V 9300,1000,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 11100,1000,CONT_DIF_N,* +V 10500,1000,CONT_DIF_N,* +V 11700,1000,CONT_DIF_N,* +V 10500,500,CONT_DIF_N,* +V 11700,500,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 6900,1000,CONT_DIF_N,* +V 8100,500,CONT_DIF_N,* +V 5700,500,CONT_DIF_N,* +V 2000,1500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 3200,4500,CONT_DIF_P,* +V 10500,3000,CONT_DIF_P,* +V 11100,3000,CONT_DIF_P,* +V 11700,3000,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 8100,4500,CONT_DIF_P,* +V 9300,4000,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 2000,3500,CONT_DIF_P,* +V 11100,4000,CONT_DIF_P,* +V 5700,4500,CONT_DIF_P,* +V 11700,3500,CONT_DIF_P,* +V 11700,4000,CONT_DIF_P,* +V 10500,4500,CONT_DIF_P,* +V 11700,4500,CONT_DIF_P,* +V 10500,4000,CONT_DIF_P,* +V 10500,3500,CONT_DIF_P,* +V 6900,3500,CONT_DIF_P,* +V 11100,3500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 6900,4700,CONT_BODY_N,* +V 3900,4700,CONT_BODY_N,* +V 5100,4700,CONT_BODY_N,* +V 2500,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 300,300,CONT_BODY_P,* +V 9900,300,CONT_BODY_P,* +V 9300,300,CONT_BODY_P,* +V 6900,300,CONT_BODY_P,* +V 6300,300,CONT_BODY_P,* +V 5100,300,CONT_BODY_P,* +V 3900,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 2500,300,CONT_BODY_P,* +V 8000,1000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 8000,3500,CONT_POLY,* +V 4400,1500,CONT_POLY,* +V 4400,3000,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 5200,2000,CONT_POLY,* +V 5900,3500,CONT_POLY,* +V 9400,3500,CONT_POLY,* +V 7000,2000,CONT_POLY,* +V 8200,3000,CONT_POLY,* +V 9200,2000,CONT_POLY,* +V 8200,1500,CONT_POLY,* +V 10400,1500,CONT_POLY,* +V 10400,2500,CONT_POLY,* +V 6500,3000,CONT_POLY,* +V 6500,1500,CONT_POLY,* +V 6500,2500,CONT_POLY,* +V 6000,1500,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 10400,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/sff2_x4.sym b/alliance/src/cells/src/sxlib/sff2_x4.sym new file mode 100644 index 00000000..343c2625 Binary files /dev/null and b/alliance/src/cells/src/sxlib/sff2_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/sff2_x4.vbe b/alliance/src/cells/src/sxlib/sff2_x4.vbe new file mode 100644 index 00000000..59eaa644 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff2_x4.vbe @@ -0,0 +1,51 @@ +ENTITY sff2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd : NATURAL := 16; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 7; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_cmd_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thr_cmd_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT tsf_cmd_ck : NATURAL := 833; + CONSTANT tsf_i0_ck : NATURAL := 764; + CONSTANT tsf_i1_ck : NATURAL := 764; + CONSTANT tsr_cmd_ck : NATURAL := 770; + CONSTANT tsr_i0_ck : NATURAL := 666; + CONSTANT tsr_i1_ck : NATURAL := 666; + CONSTANT transistors : NATURAL := 34 +); +PORT ( + ck : in BIT; + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff2_x4; + +ARCHITECTURE VBE OF sff2_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff2_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd))); + END BLOCK label0; + + q <= sff_m after 2000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/sff2_x4.vhd b/alliance/src/cells/src/sxlib/sff2_x4.vhd new file mode 100644 index 00000000..f49ef60e --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff2_x4.vhd @@ -0,0 +1,29 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY sff2_x4 IS +PORT( + ck : IN STD_LOGIC; + cmd : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END sff2_x4; + +ARCHITECTURE RTL OF sff2_x4 IS + SIGNAL sff_m : STD_LOGIC; +BEGIN + q <= sff_m; + PROCESS ( ck ) + BEGIN + IF ((ck = '1') AND ck'EVENT) + THEN sff_m <= ((i1 AND cmd) OR (i0 AND NOT(cmd))); + END IF; + END PROCESS; +END RTL; diff --git a/alliance/src/cells/src/sxlib/sff3_x4.al b/alliance/src/cells/src/sxlib/sff3_x4.al new file mode 100644 index 00000000..fbf02fa2 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff3_x4.al @@ -0,0 +1,116 @@ +V ALLIANCE : 6 +H sff3_x4,L,30/10/99 +C ck,IN,EXTERNAL,15 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,8 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,24 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,6,13,28,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00042 +T P,0.35,2,7,14,12,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00041 +T P,0.35,2.9,28,14,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00040 +T P,0.35,2.9,7,12,27,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00039 +T P,0.35,2.9,27,9,25,0,0.75,0.75,7.3,7.3,9,12.75,tr_00038 +T P,0.35,2.9,25,2,6,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00037 +T P,0.35,2,2,8,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00036 +T P,0.35,2.9,6,8,26,0,0.75,0.75,7.3,7.3,6,12.75,tr_00035 +T P,0.35,2.9,26,10,27,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00034 +T P,0.35,2.9,22,19,21,0,0.75,0.75,7.3,7.3,33,12.75,tr_00033 +T P,0.35,2.9,31,22,7,0,0.75,0.75,7.3,7.3,29.4,12.75,tr_00032 +T P,0.35,2.9,16,19,31,0,0.75,0.75,7.3,7.3,27.6,11.25,tr_00031 +T P,0.35,2.9,30,24,7,0,0.75,0.75,7.3,7.3,36.6,12.75,tr_00030 +T P,0.35,2.9,21,18,30,0,0.75,0.75,7.3,7.3,34.8,12.75,tr_00029 +T P,0.35,5.9,24,21,7,0,0.75,0.75,13.3,13.3,40.2,11.25,tr_00028 +T P,0.35,2.9,22,16,7,0,0.75,0.75,7.3,7.3,31.2,12.75,tr_00027 +T P,0.35,2.9,29,18,16,0,0.75,0.75,7.3,7.3,25.8,11.25,tr_00026 +T P,0.35,5.9,7,21,24,0,0.75,0.75,13.3,13.3,38.4,11.25,tr_00025 +T P,0.35,2.9,7,6,29,0,0.75,0.75,7.3,7.3,24,11.25,tr_00024 +T P,0.35,2.9,18,19,7,0,0.75,0.75,7.3,7.3,22.2,11.25,tr_00023 +T P,0.35,2.9,7,15,19,0,0.75,0.75,7.3,7.3,18.3,11.25,tr_00022 +T N,0.35,1.1,12,14,1,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00021 +T N,0.35,1.1,1,8,2,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00020 +T N,0.35,1.7,6,13,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00019 +T N,0.35,1.7,1,14,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00018 +T N,0.35,1.7,11,12,1,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00017 +T N,0.35,1.7,6,2,3,0,0.75,0.75,4.9,4.9,6,2.55,tr_00016 +T N,0.35,1.7,5,8,6,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00015 +T N,0.35,1.7,4,9,5,0,0.75,0.75,4.9,4.9,9,2.55,tr_00014 +T N,0.35,1.7,3,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00013 +T N,0.35,1.4,16,19,17,0,0.75,0.75,4.3,4.3,25.8,3,tr_00012 +T N,0.35,1.4,1,24,20,0,0.75,0.75,4.3,4.3,36.6,3,tr_00011 +T N,0.35,1.4,20,19,21,0,0.75,0.75,4.3,4.3,34.8,3,tr_00010 +T N,0.35,1.4,21,18,22,0,0.75,0.75,4.3,4.3,33,3,tr_00009 +T N,0.35,1.4,1,22,23,0,0.75,0.75,4.3,4.3,29.4,1.5,tr_00008 +T N,0.35,1.4,23,18,16,0,0.75,0.75,4.3,4.3,27.6,3,tr_00007 +T N,0.35,1.4,22,16,1,0,0.75,0.75,4.3,4.3,31.2,1.5,tr_00006 +T N,0.35,2.9,24,21,1,0,0.75,0.75,7.3,7.3,38.4,2.25,tr_00005 +T N,0.35,2.9,1,21,24,0,0.75,0.75,7.3,7.3,40.2,2.25,tr_00004 +T N,0.35,1.4,17,6,1,0,0.75,0.75,4.3,4.3,24,3,tr_00003 +T N,0.35,1.4,1,19,18,0,0.75,0.75,4.3,4.3,22.2,3,tr_00002 +T N,0.35,1.4,19,15,1,0,0.75,0.75,4.3,4.3,18.3,3,tr_00001 +S 31,INTERNAL +Q 0 +S 30,INTERNAL +Q 0 +S 29,INTERNAL +Q 0 +S 28,INTERNAL +Q 0 +S 27,INTERNAL +Q 0.00170541 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0 +S 24,EXTERNAL,q +Q 0.00615082 +S 23,INTERNAL +Q 0 +S 22,INTERNAL,y +Q 0.00480814 +S 21,INTERNAL,sff_s +Q 0.00671219 +S 20,INTERNAL +Q 0 +S 19,INTERNAL,nckr +Q 0.0114885 +S 18,INTERNAL,ckr +Q 0.0113072 +S 17,INTERNAL +Q 0 +S 16,INTERNAL,sff_m +Q 0.00642301 +S 15,EXTERNAL,ck +Q 0.00323647 +S 14,EXTERNAL,cmd0 +Q 0.00553121 +S 13,EXTERNAL,i0 +Q 0.00386191 +S 12,INTERNAL +Q 0.0057783 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,i1 +Q 0.0025589 +S 8,EXTERNAL,cmd1 +Q 0.00604152 +S 7,EXTERNAL,vdd +Q 0.0159513 +S 6,INTERNAL,u +Q 0.0112516 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00547335 +S 1,EXTERNAL,vss +Q 0.0145999 +EOF diff --git a/alliance/src/cells/src/sxlib/sff3_x4.ap b/alliance/src/cells/src/sxlib/sff3_x4.ap new file mode 100644 index 00000000..347549d1 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff3_x4.ap @@ -0,0 +1,341 @@ +V ALLIANCE : 6 +H sff3_x4,P, 6/ 9/2000,100 +A 0,0,14000,5000 +R 4500,2500,ref_ref,i0_25 +R 4000,3000,ref_ref,i0_30 +R 4000,2000,ref_ref,i0_20 +R 3500,3000,ref_ref,cmd0_30 +R 3500,2500,ref_ref,cmd0_25 +R 3500,2000,ref_ref,cmd0_20 +R 2500,2500,ref_ref,i1_25 +R 1500,2500,ref_ref,i2_25 +R 500,3500,ref_ref,cmd1_35 +R 500,3000,ref_ref,cmd1_30 +R 500,2500,ref_ref,cmd1_25 +R 500,2000,ref_ref,cmd1_20 +R 500,1500,ref_ref,cmd1_15 +R 13000,3500,ref_ref,q_35 +R 13000,4000,ref_ref,q_40 +R 13000,2000,ref_ref,q_20 +R 13000,1500,ref_ref,q_15 +R 13000,2500,ref_ref,q_25 +R 13000,3000,ref_ref,q_30 +R 13000,1000,ref_ref,q_10 +R 6000,2000,ref_ref,ck_20 +R 6000,1500,ref_ref,ck_15 +R 6000,2500,ref_ref,ck_25 +R 6000,3000,ref_ref,ck_30 +R 6000,3500,ref_ref,ck_35 +R 6000,1000,ref_ref,ck_10 +S 4400,3000,4600,3000,300,*,RIGHT,POLY +S 4400,2000,4600,2000,300,*,RIGHT,POLY +S 1800,3500,2000,3500,300,*,RIGHT,POLY +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 13000,1000,13000,4000,200,*,DOWN,ALU1 +S 4000,2000,4000,2000,200,i0,LEFT,CALU1 +S 4000,3000,4000,3000,200,i0,LEFT,CALU1 +S 4500,2500,4500,2500,200,i0,LEFT,CALU1 +S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1 +S 2500,2500,2500,2500,200,i1,LEFT,CALU1 +S 1500,2500,1500,2500,200,i2,LEFT,CALU1 +S 500,1500,500,3500,200,cmd1,DOWN,CALU1 +S 13000,1000,13000,4000,200,q,DOWN,CALU1 +S 6000,1000,6000,3500,200,ck,DOWN,CALU1 +S 5000,1800,5000,3000,100,*,DOWN,ALU1 +S 4900,1700,5000,1700,100,*,LEFT,ALU1 +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 4900,1500,4900,1700,200,*,DOWN,ALU1 +S 4900,3500,4900,4000,100,*,DOWN,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 4900,3000,5000,3000,100,*,RIGHT,ALU1 +S 4400,2000,4400,3000,100,*,UP,ALU1 +S 3400,1500,4900,1500,100,*,RIGHT,ALU1 +S 1000,3000,1800,3000,100,*,LEFT,ALU1 +S 1100,4000,3300,4000,100,*,RIGHT,ALU1 +S 2300,1500,2800,1500,100,*,RIGHT,ALU1 +S 2800,1500,2800,2000,100,*,UP,ALU1 +S 500,3500,1800,3500,100,*,LEFT,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1800,1500,1800,2000,100,*,UP,ALU1 +S 1800,2000,1900,2000,100,*,RIGHT,ALU1 +S 2300,3500,5500,3500,100,*,RIGHT,ALU1 +S 2800,2000,3000,2000,100,*,RIGHT,ALU1 +S 1800,3000,2500,3000,100,*,LEFT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 4900,1000,5500,1000,100,*,RIGHT,ALU1 +S 500,400,500,1000,200,*,DOWN,ALU1 +S 1100,1000,3300,1000,100,*,RIGHT,ALU1 +S 3500,1500,3500,3600,100,*,UP,POLY +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 4200,1100,4200,1500,100,*,UP,POLY +S 5200,2000,5200,2600,100,*,DOWN,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 4000,3300,4000,3600,100,*,UP,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 500,2500,800,2500,300,*,RIGHT,POLY +S 800,2100,800,2600,100,*,DOWN,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 2600,3000,2600,3600,100,*,UP,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 5200,1300,5200,2000,100,*,DOWN,NTRANS +S 1100,1600,1100,1900,300,*,UP,NDIF +S 800,1400,800,2100,100,*,DOWN,NTRANS +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 4600,200,4600,1100,100,*,UP,NTRANS +S 4900,500,4900,1000,300,*,UP,NDIF +S 3600,200,3600,1100,100,*,UP,NTRANS +S 3900,400,3900,900,200,*,DOWN,NDIF +S 4200,200,4200,1100,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 3000,400,3000,1300,100,*,UP,NTRANS +S 500,1000,500,1900,300,*,DOWN,NDIF +S 1400,400,1400,1300,100,*,UP,NTRANS +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 4900,3800,4900,4700,300,*,UP,PDIF +S 3900,3800,3900,4700,200,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 3300,3800,3300,4700,200,*,UP,PDIF +S 4900,2800,4900,3400,300,*,UP,PDIF +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 800,2600,800,3600,100,*,UP,PTRANS +S 500,2800,500,4000,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 2300,3500,2300,4700,300,*,UP,PDIF +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1100,3800,1100,4700,300,*,UP,PDIF +S 10000,3500,10700,3500,100,*,LEFT,ALU1 +S 13700,3000,13700,4500,200,*,DOWN,ALU1 +S 12500,3000,12500,4500,200,*,DOWN,ALU1 +S 12400,2500,13100,2500,100,*,RIGHT,ALU1 +S 12400,1500,13100,1500,100,*,RIGHT,ALU1 +S 9500,3000,10200,3000,100,*,RIGHT,ALU1 +S 11300,2000,11300,3500,100,*,DOWN,ALU1 +S 9500,1500,10200,1500,100,*,LEFT,ALU1 +S 11300,4000,11900,4000,100,*,RIGHT,ALU1 +S 8900,3500,9500,3500,100,*,RIGHT,ALU1 +S 8000,1500,8000,4000,100,u,DOWN,ALU1 +S 8500,1500,8500,2500,100,*,DOWN,ALU1 +S 11900,2000,12400,2000,100,*,RIGHT,ALU1 +S 10700,1000,10700,4000,100,y,DOWN,ALU1 +S 8900,1000,9500,1000,100,*,RIGHT,ALU1 +S 11300,1000,11900,1000,100,*,RIGHT,ALU1 +S 13700,500,13700,1000,200,*,DOWN,ALU1 +S 12500,500,12500,1000,200,*,DOWN,ALU1 +S 9500,1000,9500,3500,100,sff_m,DOWN,ALU1 +S 11900,1000,11900,4000,100,sff_s,DOWN,ALU1 +S 10000,1000,10700,1000,100,*,RIGHT,ALU1 +S 12200,2500,12500,2500,300,*,RIGHT,POLY +S 12200,1500,12500,1500,300,*,RIGHT,POLY +S 12800,1400,12800,2600,100,*,DOWN,POLY +S 11600,1400,11600,2500,100,*,DOWN,POLY +S 8900,2000,9200,2000,300,*,RIGHT,POLY +S 11000,2000,11300,2000,300,*,RIGHT,POLY +S 9200,1400,9200,2000,100,*,DOWN,POLY +S 11000,2500,11000,3600,100,*,DOWN,POLY +S 10400,3000,10400,3600,100,*,DOWN,POLY +S 11000,1400,11000,2000,100,*,DOWN,POLY +S 10100,1500,10400,1500,300,*,RIGHT,POLY +S 9800,3500,10100,3500,300,*,RIGHT,POLY +S 11300,3500,11600,3500,300,*,RIGHT,POLY +S 10100,3000,10400,3000,300,*,RIGHT,POLY +S 12200,2400,12200,3600,100,*,DOWN,POLY +S 12400,2000,13400,2000,300,*,RIGHT,POLY +S 13400,1400,13400,2600,100,*,DOWN,POLY +S 9200,2500,9200,3100,100,*,DOWN,POLY +S 7100,3100,7400,3100,100,*,RIGHT,POLY +S 7100,1400,7400,1400,100,*,RIGHT,POLY +S 7100,1400,7100,3100,100,*,DOWN,POLY +S 7500,2000,11000,2000,100,ckr,RIGHT,POLY +S 9800,1000,10100,1000,300,*,RIGHT,POLY +S 10400,900,10400,1500,100,*,UP,POLY +S 11300,300,11900,300,300,*,RIGHT,PTIE +S 8300,300,8900,300,300,*,RIGHT,PTIE +S 8600,600,8600,1400,100,*,UP,NTRANS +S 12200,600,12200,1400,100,*,UP,NTRANS +S 11600,600,11600,1400,100,*,UP,NTRANS +S 11000,600,11000,1400,100,*,UP,NTRANS +S 9800,100,9800,900,100,*,UP,NTRANS +S 9200,600,9200,1400,100,*,UP,NTRANS +S 10700,300,10700,700,300,*,DOWN,NDIF +S 10400,100,10400,900,100,*,UP,NTRANS +S 12500,300,12500,1200,300,*,DOWN,NDIF +S 10700,300,10700,1200,300,*,DOWN,NDIF +S 11300,800,11300,1200,300,*,DOWN,NDIF +S 12800,100,12800,1400,100,*,UP,NTRANS +S 7100,800,7100,1200,300,*,DOWN,NDIF +S 10100,300,10100,700,300,*,DOWN,NDIF +S 8300,800,8300,1200,300,*,DOWN,NDIF +S 9500,300,9500,1200,300,*,DOWN,NDIF +S 8900,800,8900,1200,300,*,DOWN,NDIF +S 13700,300,13700,1200,300,*,DOWN,NDIF +S 13400,100,13400,1400,100,*,UP,NTRANS +S 13100,300,13100,1200,300,*,DOWN,NDIF +S 11900,800,11900,1200,300,*,DOWN,NDIF +S 7700,400,7700,1200,300,*,DOWN,NDIF +S 8000,600,8000,1400,100,*,UP,NTRANS +S 7400,600,7400,1400,100,*,UP,NTRANS +S 11000,3600,11000,4900,100,*,DOWN,PTRANS +S 9800,3600,9800,4900,100,*,DOWN,PTRANS +S 9200,3100,9200,4400,100,*,DOWN,PTRANS +S 12200,3600,12200,4900,100,*,DOWN,PTRANS +S 11600,3600,11600,4900,100,*,DOWN,PTRANS +S 13700,2800,13700,4700,300,*,DOWN,PDIF +S 13400,2600,13400,4900,100,*,DOWN,PTRANS +S 13100,2800,13100,4700,300,*,DOWN,PDIF +S 10400,3600,10400,4900,100,*,UP,PTRANS +S 7100,3300,7100,4200,300,*,UP,PDIF +S 8600,3100,8600,4400,100,*,DOWN,PTRANS +S 9500,3300,9500,4700,300,*,UP,PDIF +S 8900,3300,8900,4200,300,*,UP,PDIF +S 10000,3800,10000,4700,300,*,DOWN,PDIF +S 11300,3800,11300,4700,300,*,DOWN,PDIF +S 10600,3800,10600,4700,300,*,DOWN,PDIF +S 11900,3800,11900,4700,300,*,UP,PDIF +S 12500,2800,12500,4700,300,*,DOWN,PDIF +S 12800,2600,12800,4900,100,*,DOWN,PTRANS +S 8300,3300,8300,4200,300,*,UP,PDIF +S 7700,3300,7700,4600,300,*,UP,PDIF +S 8000,3100,8000,4400,100,*,DOWN,PTRANS +S 7400,3100,7400,4400,100,*,DOWN,PTRANS +S 0,3900,14000,3900,2400,*,RIGHT,NWELL +S 0,4700,14000,4700,600,vdd,RIGHT,CALU1 +S 0,300,14000,300,600,vss,RIGHT,CALU1 +S 4900,4000,8000,4000,100,*,RIGHT,ALU1 +S 6000,1000,6000,3500,100,*,DOWN,ALU1 +S 6100,1400,6100,3100,100,*,DOWN,POLY +S 6100,3100,6100,4400,100,*,DOWN,PTRANS +S 6100,600,6100,1400,100,*,UP,NTRANS +S 6400,800,6400,1200,300,*,DOWN,NDIF +S 6400,3300,6400,4200,300,*,UP,PDIF +S 5600,2800,5600,4600,500,*,DOWN,PDIF +S 5600,400,5600,1800,500,*,DOWN,NDIF +S 6500,3300,6500,4200,300,*,UP,PDIF +S 6500,800,6500,1200,300,*,DOWN,NDIF +S 6500,1000,6500,3500,100,*,DOWN,ALU1 +S 8600,2950,9000,2950,100,*,RIGHT,ALU1 +S 7100,1050,7500,1050,100,*,RIGHT,ALU1 +S 9000,2000,9000,2950,100,*,UP,ALU1 +S 7100,3450,7500,3450,100,*,LEFT,ALU1 +S 7500,1050,7500,3450,100,*,UP,ALU1 +S 6600,2500,11600,2500,100,nckr,RIGHT,POLY +V 5500,4500,CONT_DIF_P,* +V 4400,3000,CONT_POLY,* +V 4400,2000,CONT_POLY,* +V 3900,2500,CONT_POLY,* +V 4200,1500,CONT_POLY,* +V 3400,1500,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 1800,1500,CONT_POLY,* +V 1800,3500,CONT_POLY,* +V 500,400,CONT_BODY_P,* +V 4900,1700,CONT_DIF_N,* +V 2300,1500,CONT_DIF_N,* +V 1100,1800,CONT_DIF_N,* +V 1100,1800,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 4900,1000,CONT_DIF_N,* +V 5500,500,CONT_DIF_N,* +V 500,1000,CONT_DIF_N,* +V 1100,1000,CONT_DIF_N,* +V 3300,4000,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 4900,3000,CONT_DIF_P,* +V 2300,3500,CONT_DIF_P,* +V 1100,4000,CONT_DIF_P,* +V 1100,3000,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 500,4600,CONT_BODY_N,* +V 10000,3500,CONT_POLY,* +V 11400,3500,CONT_POLY,* +V 9000,2000,CONT_POLY,* +V 10200,3000,CONT_POLY,* +V 11200,2000,CONT_POLY,* +V 10200,1500,CONT_POLY,* +V 12400,1500,CONT_POLY,* +V 12400,2500,CONT_POLY,* +V 8500,2500,CONT_POLY,* +V 12400,2000,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 8600,3000,CONT_POLY,* +V 8000,3000,CONT_POLY,* +V 8600,1500,CONT_POLY,* +V 8000,1500,CONT_POLY,* +V 10000,1000,CONT_POLY,* +V 7100,300,CONT_BODY_P,* +V 8900,300,CONT_BODY_P,* +V 11300,300,CONT_BODY_P,* +V 11900,300,CONT_BODY_P,* +V 8300,300,CONT_BODY_P,* +V 7100,1000,CONT_DIF_N,* +V 13100,1000,CONT_DIF_N,* +V 12500,1000,CONT_DIF_N,* +V 13700,1000,CONT_DIF_N,* +V 12500,500,CONT_DIF_N,* +V 13700,500,CONT_DIF_N,* +V 10700,1000,CONT_DIF_N,* +V 8900,1000,CONT_DIF_N,* +V 11300,1000,CONT_DIF_N,* +V 10100,500,CONT_DIF_N,* +V 7700,500,CONT_DIF_N,* +V 12500,3000,CONT_DIF_P,* +V 13100,3000,CONT_DIF_P,* +V 13700,3000,CONT_DIF_P,* +V 10700,4000,CONT_DIF_P,* +V 10100,4500,CONT_DIF_P,* +V 13100,4000,CONT_DIF_P,* +V 13700,3500,CONT_DIF_P,* +V 13700,4000,CONT_DIF_P,* +V 12500,4500,CONT_DIF_P,* +V 7100,3500,CONT_DIF_P,* +V 13700,4500,CONT_DIF_P,* +V 12500,4000,CONT_DIF_P,* +V 12500,3500,CONT_DIF_P,* +V 8900,3500,CONT_DIF_P,* +V 13100,3500,CONT_DIF_P,* +V 8900,4700,CONT_BODY_N,* +V 11300,4000,CONT_DIF_P,* +V 7100,4700,CONT_BODY_N,* +V 7700,4600,CONT_DIF_P,* +V 6000,2500,CONT_POLY,* +V 6600,2500,CONT_POLY,* +V 6500,1000,CONT_DIF_N,* +V 6500,3500,CONT_DIF_P,* +V 6400,4700,CONT_BODY_N,* +V 6400,300,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/sff3_x4.vbe b/alliance/src/cells/src/sxlib/sff3_x4.vbe new file mode 100644 index 00000000..a1953ab9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff3_x4.vbe @@ -0,0 +1,65 @@ +ENTITY sff3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 890; + CONSTANT rup_ck_q : NATURAL := 810; + CONSTANT taf_ck_q : NATURAL := 600; + CONSTANT tar_ck_q : NATURAL := 600; + CONSTANT thf_ck_q : NATURAL := 0; + CONSTANT thf_cmd0_ck : NATURAL := 0; + CONSTANT thf_cmd1_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thf_i2_ck : NATURAL := 0; + CONSTANT thr_ck_q : NATURAL := 0; + CONSTANT thr_cmd0_ck : NATURAL := 0; + CONSTANT thr_cmd1_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT thr_i2_ck : NATURAL := 0; + CONSTANT tsf_cmd0_ck : NATURAL := 1200; + CONSTANT tsf_cmd1_ck : NATURAL := 1200; + CONSTANT tsf_i0_ck : NATURAL := 1200; + CONSTANT tsf_i1_ck : NATURAL := 1200; + CONSTANT tsf_i2_ck : NATURAL := 1200; + CONSTANT tsr_cmd0_ck : NATURAL := 1100; + CONSTANT tsr_cmd1_ck : NATURAL := 1100; + CONSTANT tsr_i0_ck : NATURAL := 850; + CONSTANT tsr_i1_ck : NATURAL := 950; + CONSTANT tsr_i2_ck : NATURAL := 950; + CONSTANT transistors : NATURAL := 42 +); +PORT ( + ck : in BIT; + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff3_x4; + +ARCHITECTURE behaviour_data_flow OF sff3_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff3_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))); + END BLOCK label0; + + q <= sff_m after 2400 ps; +END; diff --git a/alliance/src/cells/src/sxlib/sff3_x4.vhd b/alliance/src/cells/src/sxlib/sff3_x4.vhd new file mode 100644 index 00000000..a99d02f2 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sff3_x4.vhd @@ -0,0 +1,31 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY sff3_x4 IS +PORT( + ck : IN STD_LOGIC; + cmd0 : IN STD_LOGIC; + cmd1 : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END sff3_x4; + +ARCHITECTURE RTL OF sff3_x4 IS + SIGNAL sff_m : STD_LOGIC; +BEGIN + q <= sff_m; + PROCESS ( ck ) + BEGIN + IF ((ck = '1') AND ck'EVENT) + THEN sff_m <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2)))); + END IF; + END PROCESS; +END RTL; diff --git a/alliance/src/cells/src/sxlib/sxlib.cct b/alliance/src/cells/src/sxlib/sxlib.cct new file mode 100644 index 00000000..c13bceff --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib.cct @@ -0,0 +1,1018 @@ +Circuit a2_x2 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 and i1) ; +EndCircuit +Circuit a2_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 and i1) ; +EndCircuit +Circuit a3_x2 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) and i2) ; +EndCircuit +Circuit a3_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) and i2) ; +EndCircuit +Circuit a4_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) and i3) ; +EndCircuit +Circuit a4_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) and i3) ; +EndCircuit +Circuit an12_x1 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 and i1) ; +EndCircuit +Circuit an12_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 and i1) ; +EndCircuit +Circuit ao22_x2 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) and i2) ; +EndCircuit +Circuit ao22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) and i2) ; +EndCircuit +Circuit ao2o22_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) and (i2 or i3)) ; +EndCircuit +Circuit ao2o22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) and (i2 or i3)) ; +EndCircuit +Circuit buf_x2 ( + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := i ; +EndCircuit +Circuit buf_x4 ( + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := i ; +EndCircuit +Circuit buf_x8 ( + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := i ; +EndCircuit +Circuit fulladder_x2 ( + Input a1 , + Input a2 , + Input a3 , + Input a4 , + Input b1 , + Input b2 , + Input b3 , + Input b4 , + Input cin1 , + Input cin2 , + Input cin3 , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE ncout := not ((a1 and b1) or ((a2 or b2) and cin1)) ; +WIRE sout := (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) ; +WIRE cout := not ncout ; +EndCircuit +Circuit fulladder_x4 ( + Input a1 , + Input a2 , + Input a3 , + Input a4 , + Input b1 , + Input b2 , + Input b3 , + Input b4 , + Input cin1 , + Input cin2 , + Input cin3 , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE ncout := not ((a1 and b1) or ((a2 or b2) and cin1)) ; +WIRE sout := (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) ; +WIRE cout := not ncout ; +EndCircuit +Circuit halfadder_x2 ( + Input a , + Input b , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE sout := (a xor b) ; +WIRE cout := (a and b) ; +EndCircuit +Circuit halfadder_x4 ( + Input a , + Input b , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE sout := (a xor b) ; +WIRE cout := (a and b) ; +EndCircuit +Circuit inv_x1 ( + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not i ; +EndCircuit +Circuit inv_x2 ( + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not i ; +EndCircuit +Circuit inv_x4 ( + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not i ; +EndCircuit +Circuit inv_x8 ( + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not i ; +EndCircuit +Circuit mx2_x2 ( + Input cmd , + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i1 and cmd) or (not cmd and i0)) ; +EndCircuit +Circuit mx2_x4 ( + Input cmd , + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i1 and cmd) or (not cmd and i0)) ; +EndCircuit +Circuit mx3_x2 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit mx3_x4 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit na2_x1 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 and i1) ; +EndCircuit +Circuit na2_x4 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 and i1) ; +EndCircuit +Circuit na3_x1 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) and i2) ; +EndCircuit +Circuit na3_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) and i2) ; +EndCircuit +Circuit na4_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) and i3) ; +EndCircuit +Circuit na4_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) and i3) ; +EndCircuit +Circuit nao22_x1 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) and i2) ; +EndCircuit +Circuit nao22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) and i2) ; +EndCircuit +Circuit nao2o22_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) and (i2 or i3)) ; +EndCircuit +Circuit nao2o22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) and (i2 or i3)) ; +EndCircuit +Circuit nmx2_x1 ( + Input cmd , + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and not cmd) or (i1 and cmd)) ; +EndCircuit +Circuit nmx2_x4 ( + Input cmd , + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and not cmd) or (i1 and cmd)) ; +EndCircuit +Circuit nmx3_x1 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit nmx3_x4 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit no2_x1 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 or i1) ; +EndCircuit +Circuit no2_x4 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 or i1) ; +EndCircuit +Circuit no3_x1 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) or i2) ; +EndCircuit +Circuit no3_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) or i2) ; +EndCircuit +Circuit no4_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 or i1) or i2) or i3) ; +EndCircuit +Circuit no4_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 or i1) or i2) or i3) ; +EndCircuit +Circuit noa22_x1 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or i2) ; +EndCircuit +Circuit noa22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or i2) ; +EndCircuit +Circuit noa2a22_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or (i2 and i3)) ; +EndCircuit +Circuit noa2a22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or (i2 and i3)) ; +EndCircuit +Circuit noa2a2a23_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit noa2a2a23_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit noa2a2a2a24_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit noa2a2a2a24_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit noa2ao222_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or ((i2 or i3) and i4)) ; +EndCircuit +Circuit noa2ao222_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or ((i2 or i3) and i4)) ; +EndCircuit +Circuit noa3ao322_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) or (((i3 or i4) or i5) and i6)) ; +EndCircuit +Circuit noa3ao322_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) or (((i3 or i4) or i5) and i6)) ; +EndCircuit +Circuit nts_x1 ( + Input cmd , + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE commande_0_nq := cmd ; +WIRE data_0_nq := not i ; +TRI1 nq ; + BUFIF1 tri_0_nq (nq,data_0_nq,commande_0_nq) ; +EndCircuit +Circuit nts_x2 ( + Input cmd , + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE commande_0_nq := cmd ; +WIRE data_0_nq := not i ; +TRI1 nq ; + BUFIF1 tri_0_nq (nq,data_0_nq,commande_0_nq) ; +EndCircuit +Circuit nxr2_x1 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 xor i1) ; +EndCircuit +Circuit nxr2_x4 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 xor i1) ; +EndCircuit +Circuit o2_x2 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 or i1) ; +EndCircuit +Circuit o2_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 or i1) ; +EndCircuit +Circuit o3_x2 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) or i2) ; +EndCircuit +Circuit o3_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) or i2) ; +EndCircuit +Circuit o4_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 or i1) or i2) or i3) ; +EndCircuit +Circuit o4_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 or i1) or i2) or i3) ; +EndCircuit +Circuit oa22_x2 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or i2) ; +EndCircuit +Circuit oa22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or i2) ; +EndCircuit +Circuit oa2a22_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i2 and i3)) ; +EndCircuit +Circuit oa2a22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i2 and i3)) ; +EndCircuit +Circuit oa2a2a23_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit oa2a2a23_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit oa2a2a2a24_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit oa2a2a2a24_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit oa2ao222_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i4 and (i2 or i3))) ; +EndCircuit +Circuit oa2ao222_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i4 and (i2 or i3))) ; +EndCircuit +Circuit oa3ao322_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) ; +EndCircuit +Circuit oa3ao322_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) ; +EndCircuit +Circuit on12_x1 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 or i1) ; +EndCircuit +Circuit on12_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 or i1) ; +EndCircuit +Circuit one_x0 ( + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := 1 ; +EndCircuit +Circuit rowend_x0 ( + Supply1 vdd , + Supply0 vss + ); +EndCircuit +Circuit sff1_x4 ( + Input ck , + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE sff_m_bcond_0 := ck ; +REGISTER (1,1) sff_m ; +WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := i ; +WIRE q := sff_m ; +EndCircuit +Circuit sff2_x4 ( + Input ck , + Input cmd , + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE sff_m_bcond_0 := ck ; +REGISTER (1,1) sff_m ; +WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((i1 and cmd) or (i0 and not cmd)) ; +WIRE q := sff_m ; +EndCircuit +Circuit sff3_x4 ( + Input ck , + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE sff_m_bcond_0 := ck ; +REGISTER (1,1) sff_m ; +WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +WIRE q := sff_m ; +EndCircuit +Circuit tie_x0 ( + Supply1 vdd , + Supply0 vss + ); +EndCircuit +Circuit ts_x4 ( + Input cmd , + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE commande_0_q := cmd ; +WIRE data_0_q := i ; +TRI1 q ; + BUFIF1 tri_0_q (q,data_0_q,commande_0_q) ; +EndCircuit +Circuit ts_x8 ( + Input cmd , + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE commande_0_q := cmd ; +WIRE data_0_q := i ; +TRI1 q ; + BUFIF1 tri_0_q (q,data_0_q,commande_0_q) ; +EndCircuit +Circuit xr2_x1 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 xor i1) ; +EndCircuit +Circuit xr2_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 xor i1) ; +EndCircuit +Circuit zero_x0 ( + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := 0 ; +EndCircuit diff --git a/alliance/src/cells/src/sxlib/sxlib.db b/alliance/src/cells/src/sxlib/sxlib.db new file mode 100644 index 00000000..c7915a1b Binary files /dev/null and b/alliance/src/cells/src/sxlib/sxlib.db differ diff --git a/alliance/src/cells/src/sxlib/sxlib.lef b/alliance/src/cells/src/sxlib/sxlib.lef new file mode 100644 index 00000000..cb2f2744 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib.lef @@ -0,0 +1,8073 @@ + +MACRO a2_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END a2_x2 + + +MACRO a2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END a2_x4 + + +MACRO a3_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END a3_x2 + + +MACRO a3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END a3_x4 + + +MACRO a4_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END a4_x2 + + +MACRO a4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END a4_x4 + + +MACRO an12_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END an12_x1 + + +MACRO an12_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END an12_x4 + + +MACRO ao22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END ao22_x2 + + +MACRO ao22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END ao22_x4 + + +MACRO ao2o22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END ao2o22_x2 + + +MACRO ao2o22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END ao2o22_x4 + + +MACRO buf_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END buf_x2 + + +MACRO buf_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END buf_x4 + + +MACRO buf_x8 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END buf_x8 + + +MACRO fulladder_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END sout + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END cout + PIN b4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + END + END b4 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + END + END a4 + PIN b1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END b1 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a1 + PIN cin3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 84.00 29.00 86.00 31.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 84.00 19.00 86.00 21.00 ; + RECT 84.00 14.00 86.00 16.00 ; + END + END cin3 + PIN cin2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END cin2 + PIN b3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END b3 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END a3 + PIN b2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END b2 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END a2 + PIN cin1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END cin1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 98.50 41.00 ; + END +END fulladder_x2 + + +MACRO fulladder_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 105.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END cout + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END sout + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + END + END a3 + PIN cin2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 74.00 14.00 76.00 16.00 ; + END + END cin2 + PIN b3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END b3 + PIN cin3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + END + END cin3 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + END + END a4 + PIN b4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + END + END b4 + PIN b2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END b2 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END a2 + PIN cin1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END cin1 + PIN b1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END b1 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 102.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 102.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 103.50 41.00 ; + END +END fulladder_x4 + + +MACRO halfadder_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 80.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 74.00 39.00 76.00 41.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 74.00 9.00 76.00 11.00 ; + END + END sout + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END cout + PIN b + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END b + PIN a + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END a + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 77.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 77.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 78.50 41.00 ; + END +END halfadder_x2 + + +MACRO halfadder_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 90.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END cout + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END sout + PIN a + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END a + PIN b + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END b + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 87.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 87.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 88.50 41.00 ; + END +END halfadder_x4 + + +MACRO inv_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END inv_x1 + + +MACRO inv_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END inv_x2 + + +MACRO inv_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END inv_x4 + + +MACRO inv_x8 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END inv_x8 + + +MACRO mx2_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END cmd + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END mx2_x2 + + +MACRO mx2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END cmd + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END mx2_x4 + + +MACRO mx3_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + LAYER L_ALU1 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER L_ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + LAYER L_ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i0 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END mx3_x2 + + +MACRO mx3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + LAYER L_ALU1 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + LAYER L_ALU1 ; + RECT 64.00 19.00 66.00 21.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER L_ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i0 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 68.50 41.00 ; + END +END mx3_x4 + + +MACRO na2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END na2_x1 + + +MACRO na2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END na2_x4 + + +MACRO na3_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END na3_x1 + + +MACRO na3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END na3_x4 + + +MACRO na4_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END nq + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END na4_x1 + + +MACRO na4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END na4_x4 + + +MACRO nao22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END nao22_x1 + + +MACRO nao22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 14.00 26.00 16.00 ; + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END nao22_x4 + + +MACRO nao2o22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END nao2o22_x1 + + +MACRO nao2o22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END nao2o22_x4 + + +MACRO nmx2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 14.00 26.00 16.00 ; + LAYER L_ALU1 ; + RECT 19.00 9.00 21.00 11.00 ; + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END nq + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END cmd + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END nmx2_x1 + + +MACRO nmx2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END cmd + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END nmx2_x4 + + +MACRO nmx3_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER L_ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + LAYER L_ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i0 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END nmx3_x1 + + +MACRO nmx3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 75.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER L_ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i0 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 72.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 72.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 73.50 41.00 ; + END +END nmx3_x4 + + +MACRO no2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END no2_x1 + + +MACRO no2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END no2_x4 + + +MACRO no3_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END no3_x1 + + +MACRO no3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END no3_x4 + + +MACRO no4_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END no4_x1 + + +MACRO no4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END no4_x4 + + +MACRO noa22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END noa22_x1 + + +MACRO noa22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END noa22_x4 + + +MACRO noa2a22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END noa2a22_x1 + + +MACRO noa2a22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END noa2a22_x4 + + +MACRO noa2a2a23_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END noa2a2a23_x1 + + +MACRO noa2a2a23_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END nq + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END noa2a2a23_x4 + + +MACRO noa2a2a2a24_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 68.50 41.00 ; + END +END noa2a2a2a24_x1 + + +MACRO noa2a2a2a24_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 85.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 82.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 82.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 83.50 41.00 ; + END +END noa2a2a2a24_x4 + + +MACRO noa2ao222_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + LAYER L_ALU1 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END noa2ao222_x1 + + +MACRO noa2ao222_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END noa2ao222_x4 + + +MACRO noa3ao322_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + LAYER L_ALU1 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i5 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i4 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i6 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END noa3ao322_x1 + + +MACRO noa3ao322_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i0 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END i3 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END i5 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END i2 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i6 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END noa3ao322_x4 + + +MACRO nts_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END cmd + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END nts_x1 + + +MACRO nts_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END cmd + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END nts_x2 + + +MACRO nxr2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END nxr2_x1 + + +MACRO nxr2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END nxr2_x4 + + +MACRO o2_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END o2_x2 + + +MACRO o2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END o2_x4 + + +MACRO o3_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END o3_x2 + + +MACRO o3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END o3_x4 + + +MACRO o4_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END o4_x2 + + +MACRO o4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END o4_x4 + + +MACRO oa22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END oa22_x2 + + +MACRO oa22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END oa22_x4 + + +MACRO oa2a22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END oa2a22_x2 + + +MACRO oa2a22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END oa2a22_x4 + + +MACRO oa2a2a23_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END oa2a2a23_x2 + + +MACRO oa2a2a23_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i0 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END oa2a2a23_x4 + + +MACRO oa2a2a2a24_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 75.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END i0 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 72.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 72.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 73.50 41.00 ; + END +END oa2a2a2a24_x2 + + +MACRO oa2a2a2a24_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 80.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 77.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 77.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 78.50 41.00 ; + END +END oa2a2a2a24_x4 + + +MACRO oa2ao222_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END oa2ao222_x2 + + +MACRO oa2ao222_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END oa2ao222_x4 + + +MACRO oa3ao322_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END i5 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i3 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END i6 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END oa3ao322_x2 + + +MACRO oa3ao322_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END i2 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END i6 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i5 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i0 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END oa3ao322_x4 + + +MACRO on12_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END on12_x1 + + +MACRO on12_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END on12_x4 + + +MACRO one_x0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END one_x0 + + +MACRO powmid_x0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 44.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END powmid_x0 + + +MACRO rowend_x0 + CLASS CORE FEEDTHRU ; + ORIGIN 0.00 0.00 ; + SIZE 5.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 2.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 2.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 3.50 41.00 ; + END +END rowend_x0 + + +MACRO sff1_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 90.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END q + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END ck + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 9.00 31.00 11.00 ; + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 87.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 87.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 88.50 41.00 ; + END +END sff1_x4 + + +MACRO sff2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + RECT 109.00 24.00 111.00 26.00 ; + RECT 109.00 19.00 111.00 21.00 ; + RECT 109.00 14.00 111.00 16.00 ; + RECT 109.00 9.00 111.00 11.00 ; + END + END q + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END ck + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END cmd + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 117.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 117.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 118.50 41.00 ; + END +END sff2_x4 + + +MACRO sff3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 140.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 129.00 39.00 131.00 41.00 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 129.00 29.00 131.00 31.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 129.00 19.00 131.00 21.00 ; + RECT 129.00 14.00 131.00 16.00 ; + RECT 129.00 9.00 131.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER L_ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i0 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END ck + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 137.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 137.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 138.50 41.00 ; + END +END sff3_x4 + + +MACRO tie_x0 + CLASS CORE FEEDTHRU ; + ORIGIN 0.00 0.00 ; + SIZE 10.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 7.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 7.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 8.50 41.00 ; + END +END tie_x0 + + +MACRO ts_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END cmd + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END ts_x4 + + +MACRO ts_x8 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END cmd + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END ts_x8 + + +MACRO xr2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 9.00 21.00 11.00 ; + LAYER L_ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END xr2_x1 + + +MACRO xr2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END xr2_x4 + + +MACRO zero_x0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END zero_x0 + + +END LIBRARY diff --git a/alliance/src/cells/src/sxlib/sxlib.lib b/alliance/src/cells/src/sxlib/sxlib.lib new file mode 100644 index 00000000..079af9c0 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib.lib @@ -0,0 +1,5019 @@ +/* --------------------------------------------- */ +/* written by Franck LE DU and Franck Wajsburt */ +/* */ +/* DEF_SXLIB modified : Sep 27, 1999 */ +/* */ +/* This file is obtained from */ +/* the technolocal parameters contained in the */ +/* VHDL generic data included in the .vbe files. */ +/* This file should not be edited directly. */ +/* */ +/* NOTE FOR NEW REVISION THAT ALL NON ZERO VALUE */ +/* MUST BE UPDATED TO THE NEW TECHNOLOGY AND ALL */ +/* ZERO VALUE SHOULD REMAIN ZERO (CHANGE */ +/* DEFAULT_WIRE_LOAD_RESISTANCE MAY HAVE NO */ +/* EFFECT SINCE ALL USEFUL PARAMETER REQUIRED TO */ +/* TAKE RESISTANCE INTO ACCOUNT ARE NOT DEFINED */ +/* IN THIS FILE */ +/* --------------------------------------------- */ + +library (sxlib) { + + date : "Thu Dec 21 11:24:55 MET 2000"; + revision : 1.2; + + /* --------------------------------------------- */ + /* Set of default values required for Synopsys */ + /* technology library generation */ + /* --------------------------------------------- */ + + /* --------------------------------------------- */ + /* default values intended to represent a */ + /* typical na2_x1 cell */ + /* --------------------------------------------- */ + + default_inout_pin_cap : 0.011; /* pf= + */ + default_inout_pin_fall_res : 2.850; /* kOhms */ + default_inout_pin_rise_res : 3.720; /* kOhms */ + default_input_pin_cap : 0.011; /* pf= + */ + default_intrinsic_fall : 0.059; /* ns */ + default_intrinsic_rise : 0.059; /* ns */ + default_output_pin_cap : 0; /* must be 0 */ + default_output_pin_fall_res : 2.850; /* kOhms */ + default_output_pin_rise_res : 3.720; /* kOhms */ + default_slope_fall : 0.1; /* worst case meaning propagation */ + /* time is delayed of .1 the */ + /* transition time of the previous*/ + /* gate */ + default_slope_rise : 0.1; /* idem */ + default_fanout_load : 0.011; /* max of input capacities in pF */ + default_max_fanout : 0.078; /* max output capacitance in pF */ + /* computed in order to a inv_x1 */ + /* be able to drive 10 inv_x1 */ + + /* --------------------------------------------- */ + /* default_wire_load_capacitance in pf/lambda */ + /* is capacitance-per-unit-length value of */ + /* the routing wire */ + /* --------------------------------------------- */ + + default_wire_load_capacitance : 0.00015;/* pf/lambda */ + default_wire_load_resistance : 0; /* must be 0 */ + default_wire_load_area : 0; /* must be 0 */ + default_wire_load_mode : enclosed;/* top/segmented/enclosed */ + + /* --------------------------------------------- */ + /* all these parameters are neglected since */ + /* we choose to only time design with worst case */ + /* operating conditions (must be 0) */ + /* --------------------------------------------- */ + + k_process_drive_fall : 0.0; + k_process_drive_rise : 0.0; + k_process_intrinsic_fall : 0.0; + k_process_intrinsic_rise : 0.0; + k_process_pin_cap : 0.0; + k_process_slope_fall : 0.0; + k_process_slope_rise : 0.0; + k_process_wire_cap : 0.0; + k_process_wire_res : 0.0; + k_temp_drive_fall : 0.0; + k_temp_drive_rise : 0.0; + k_temp_intrinsic_fall : 0.0; + k_temp_intrinsic_rise : 0.0; + k_temp_pin_cap : 0.0; + k_temp_slope_fall : 0.0; + k_temp_slope_rise : 0.0; + k_temp_wire_cap : 0.0; + k_temp_wire_res : 0.0; + k_volt_drive_fall : 0.0; + k_volt_drive_rise : 0.0; + k_volt_intrinsic_fall : 0.0; + k_volt_intrinsic_rise : 0.0; + k_volt_pin_cap : 0.0; + k_volt_slope_fall : 0.0; + k_volt_slope_rise : 0.0; + k_volt_wire_cap : 0.0; + k_volt_wire_res : 0.0; + + /* -------------------------------------------- */ + /* values given as information (unused for */ + /* timing design computation) */ + /* -------------------------------------------- */ + + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + pulling_resistance_unit : "1kohm"; + capacitive_load_unit (1,pf); + + /* -------------------------------------------- */ + /* Operating conditions */ + /* -------------------------------------------- */ + + nom_process : 1.5; + nom_temperature : 70.0; + nom_voltage : 3.0; + + in_place_swap_mode : match_footprint; + + /* -------------------------------------------- */ + /* slope and fanout_length are expressed */ + /* in lambda. it represents the average wire */ + /* length from the driver output to one of the */ + /* following input. It means it needs 50 */ + /* lambdas of wire to connect 2 cells whatever */ + /* in small case */ + /* -------------------------------------------- */ + + wire_load("small") { + resistance : 0 ; /* must be 0 */ + capacitance : 0.00015 ; /* pf/lambda */ + area : 0 ; /* must be 0 */ + slope : 100; /* lambda */ + fanout_length(1,100) ; /* first parameter must be 1, second in lambda */ + } + wire_load("medium") { + resistance : 0 ; /* must be 0 */ + capacitance : 0.00015 ; /* pf/lambda */ + area : 0 ; /* must be 0 */ + slope : 200; /* lambda */ + fanout_length(1,200) ; /* first parameter must be 1, second in lambda */ + } + wire_load("big") { + resistance : 0 ; /* must be 0 */ + capacitance : 0.00015 ; /* pf/lambda */ + area : 0 ; /* must be 0 */ + slope : 400; /* lambda */ + fanout_length(1,400) ; /* first parameter must be 1, second in lambda */ + } + + wire_load_selection(medium) { + wire_load_from_area(0,500,"small"); /* less about 200 gates */ + wire_load_from_area(500,1500,"medium"); /* less about 500 gates */ + wire_load_from_area(1500,3000,"big"); /* less about 1000 gates */ + } + default_wire_load_selection : medium + + /*---------------------------------------------- */ + /* Combinationnal cells part 1 */ + /*---------------------------------------------- */ + + cell (inv_x1) { + area : 1.0 /* pitchs */ + cell_footprint : "inv"; + pin(i) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(nq) { + direction : output; + max_fanout : 0.078; + function : "i'"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.101; + intrinsic_fall : 0.139; + rise_resistance : 3.720; + fall_resistance : 3.640; + related_pin : "i"; + } + } + } + cell (inv_x2) { + area : 1.0 /* pitchs */ + cell_footprint : "inv"; + pin(i) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(nq) { + direction : output; + max_fanout : 0.120; + function : "i'"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.069; + intrinsic_fall : 0.163; + rise_resistance : 2.420; + fall_resistance : 1.620; + related_pin : "i"; + } + } + } + cell (inv_x4) { + area : 1.3 /* pitchs */ + cell_footprint : "inv"; + pin(i) { + direction : input; + capacitance : 0.026; + fanout_load : 0.026; + } + pin(nq) { + direction : output; + max_fanout : 0.275; + function : "i'"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.071; + intrinsic_fall : 0.143; + rise_resistance : 1.060; + fall_resistance : 0.810; + related_pin : "i"; + } + } + } + cell (inv_x8) { + area : 2.3 /* pitchs */ + cell_footprint : "inv"; + pin(i) { + direction : input; + capacitance : 0.054; + fanout_load : 0.054; + } + pin(nq) { + direction : output; + max_fanout : 0.647; + function : "i'"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.086; + intrinsic_fall : 0.133; + rise_resistance : 0.450; + fall_resistance : 0.400; + related_pin : "i"; + } + } + } + cell (an12_x1) { + area : 1.7 /* pitchs */ + cell_footprint : "an12"; + pin(i0) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i1) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.080; + function : "i0' * i1"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.200; + intrinsic_fall : 0.168; + rise_resistance : 3.210; + fall_resistance : 3.640; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.285; + intrinsic_fall : 0.405; + rise_resistance : 3.210; + fall_resistance : 3.640; + related_pin : "i1"; + } + } + } + cell (an12_x4) { + area : 2.7 /* pitchs */ + cell_footprint : "an12"; + pin(i0) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "i0' * i1"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.461; + intrinsic_fall : 0.471; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.269; + intrinsic_fall : 0.518; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + } + } + cell (on12_x1) { + area : 1.7 /* pitchs */ + cell_footprint : "on12"; + pin(i0) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i1) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.078; + function : "i0' + i1"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.111; + intrinsic_fall : 0.234; + rise_resistance : 3.720; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.314; + intrinsic_fall : 0.291; + rise_resistance : 3.720; + fall_resistance : 2.850; + related_pin : "i1"; + } + } + } + cell (on12_x4) { + area : 2.7 /* pitchs */ + cell_footprint : "on12"; + pin(i0) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "i0' + i1"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.474; + intrinsic_fall : 0.499; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.491; + intrinsic_fall : 0.394; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + } + } + cell (na2_x1) { + area : 1.3 /* pitchs */ + cell_footprint : "na2"; + pin(i0) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(nq) { + direction : output; + max_fanout : 0.078; + function : "(i0' + i1')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.059; + intrinsic_fall : 0.288; + rise_resistance : 3.720; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.111; + intrinsic_fall : 0.234; + rise_resistance : 3.720; + fall_resistance : 2.850; + related_pin : "i1"; + } + } + } + cell (na2_x4) { + area : 2.3 /* pitchs */ + cell_footprint : "na2"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "(i0' + i1')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.412; + intrinsic_fall : 0.552; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.353; + intrinsic_fall : 0.601; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + } + } + cell (no2_x1) { + area : 1.3 /* pitchs */ + cell_footprint : "no2"; + pin(i0) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i1) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(nq) { + direction : output; + max_fanout : 0.080; + function : "(i0' * i1')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.298; + intrinsic_fall : 0.121; + rise_resistance : 3.210; + fall_resistance : 3.640; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.193; + intrinsic_fall : 0.161; + rise_resistance : 3.210; + fall_resistance : 3.640; + related_pin : "i1"; + } + } + } + cell (no2_x4) { + area : 2.3 /* pitchs */ + cell_footprint : "no2"; + pin(i0) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "(i0' * i1')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.618; + intrinsic_fall : 0.447; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.522; + intrinsic_fall : 0.504; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + } + } + cell (na3_x1) { + area : 1.7 /* pitchs */ + cell_footprint : "na3"; + pin(i0) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i2) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(nq) { + direction : output; + max_fanout : 0.071; + function : "(i0' + i1' + i2')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.119; + intrinsic_fall : 0.363; + rise_resistance : 3.720; + fall_resistance : 4.120; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.171; + intrinsic_fall : 0.316; + rise_resistance : 3.720; + fall_resistance : 4.120; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.193; + intrinsic_fall : 0.265; + rise_resistance : 3.720; + fall_resistance : 4.120; + related_pin : "i2"; + } + } + } + cell (na3_x4) { + area : 2.7 /* pitchs */ + cell_footprint : "na3"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i2) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "(i0' + i1' + i2')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.556; + intrinsic_fall : 0.601; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.460; + intrinsic_fall : 0.691; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.519; + intrinsic_fall : 0.647; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + } + } + cell (nao22_x1) { + area : 2.0 /* pitchs */ + cell_footprint : "nao22"; + pin(i0) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i2) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(nq) { + direction : output; + max_fanout : 0.091; + function : "((i0' * i1') + i2')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.294; + intrinsic_fall : 0.226; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.218; + intrinsic_fall : 0.287; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.165; + intrinsic_fall : 0.238; + rise_resistance : 1.790; + fall_resistance : 2.850; + related_pin : "i2"; + } + } + } + cell (nao22_x4) { + area : 3.3 /* pitchs */ + cell_footprint : "nao22"; + pin(i0) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "((i0' * i1') + i2')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.732; + intrinsic_fall : 0.650; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.664; + intrinsic_fall : 0.723; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.596; + intrinsic_fall : 0.636; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + } + } + cell (nmx2_x1) { + area : 2.3 /* pitchs */ + cell_footprint : "nmx2"; + pin(cmd) { + direction : input; + capacitance : 0.021; + fanout_load : 0.021; + } + pin(i0) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(nq) { + direction : output; + max_fanout : 0.091; + function : "((cmd + i0') * (cmd' + i1'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.218; + intrinsic_fall : 0.287; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "cmd"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.217; + intrinsic_fall : 0.256; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.217; + intrinsic_fall : 0.256; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i1"; + } + } + } + cell (nmx2_x4) { + area : 4.0 /* pitchs */ + cell_footprint : "nmx2"; + pin(cmd) { + direction : input; + capacitance : 0.017; + fanout_load : 0.017; + } + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "((cmd + i0') * (cmd' + i1'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.632; + intrinsic_fall : 0.708; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "cmd"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.610; + intrinsic_fall : 0.653; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.610; + intrinsic_fall : 0.653; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + } + } + cell (no3_x1) { + area : 1.7 /* pitchs */ + cell_footprint : "no3"; + pin(i0) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i1) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i2) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(nq) { + direction : output; + max_fanout : 0.062; + function : "(i0' * i1' * i2')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.318; + intrinsic_fall : 0.246; + rise_resistance : 4.690; + fall_resistance : 3.640; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.215; + intrinsic_fall : 0.243; + rise_resistance : 4.690; + fall_resistance : 3.640; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.407; + intrinsic_fall : 0.192; + rise_resistance : 4.690; + fall_resistance : 3.640; + related_pin : "i2"; + } + } + } + cell (no3_x4) { + area : 2.7 /* pitchs */ + cell_footprint : "no3"; + pin(i0) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i1) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i2) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "(i0' * i1' * i2')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.722; + intrinsic_fall : 0.561; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.638; + intrinsic_fall : 0.623; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.545; + intrinsic_fall : 0.640; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + } + } + cell (noa22_x1) { + area : 2.0 /* pitchs */ + cell_footprint : "noa22"; + pin(i0) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i2) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(nq) { + direction : output; + max_fanout : 0.091; + function : "((i0' + i1') * i2')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.151; + intrinsic_fall : 0.327; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.218; + intrinsic_fall : 0.287; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.218; + intrinsic_fall : 0.241; + rise_resistance : 3.210; + fall_resistance : 1.620; + related_pin : "i2"; + } + } + } + cell (noa22_x4) { + area : 3.3 /* pitchs */ + cell_footprint : "noa22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "((i0' + i1') * i2')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.550; + intrinsic_fall : 0.740; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.643; + intrinsic_fall : 0.709; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.610; + intrinsic_fall : 0.646; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + } + } + cell (na4_x1) { + area : 2.0 /* pitchs */ + cell_footprint : "na4"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i2) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i3) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(nq) { + direction : output; + max_fanout : 0.054; + function : "(i0' + i1' + i2' + i3')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.179; + intrinsic_fall : 0.438; + rise_resistance : 3.720; + fall_resistance : 5.400; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.237; + intrinsic_fall : 0.395; + rise_resistance : 3.720; + fall_resistance : 5.400; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.269; + intrinsic_fall : 0.350; + rise_resistance : 3.720; + fall_resistance : 5.400; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.282; + intrinsic_fall : 0.302; + rise_resistance : 3.720; + fall_resistance : 5.400; + related_pin : "i3"; + } + } + } + cell (na4_x4) { + area : 3.3 /* pitchs */ + cell_footprint : "na4"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i2) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i3) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "(i0' + i1' + i2' + i3')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.578; + intrinsic_fall : 0.771; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.643; + intrinsic_fall : 0.731; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.681; + intrinsic_fall : 0.689; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.703; + intrinsic_fall : 0.644; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + } + } + cell (nao2o22_x1) { + area : 2.3 /* pitchs */ + cell_footprint : "nao2o22"; + pin(i0) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i2) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i3) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(nq) { + direction : output; + max_fanout : 0.091; + function : "((i0' * i1') + (i2' * i3'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.294; + intrinsic_fall : 0.226; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.218; + intrinsic_fall : 0.287; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.237; + intrinsic_fall : 0.307; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.174; + intrinsic_fall : 0.382; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i3"; + } + } + } + cell (nao2o22_x4) { + area : 3.7 /* pitchs */ + cell_footprint : "nao2o22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i3) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "((i0' * i1') + (i2' * i3'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.734; + intrinsic_fall : 0.644; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.666; + intrinsic_fall : 0.717; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.664; + intrinsic_fall : 0.721; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.607; + intrinsic_fall : 0.807; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + } + } + cell (no4_x1) { + area : 2.0 /* pitchs */ + cell_footprint : "no4"; + pin(i0) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i1) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i2) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i3) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(nq) { + direction : output; + max_fanout : 0.047; + function : "(i0' * i1' * i2' * i3')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.330; + intrinsic_fall : 0.340; + rise_resistance : 6.190; + fall_resistance : 3.640; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.230; + intrinsic_fall : 0.320; + rise_resistance : 6.190; + fall_resistance : 3.640; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.419; + intrinsic_fall : 0.333; + rise_resistance : 6.190; + fall_resistance : 3.640; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.499; + intrinsic_fall : 0.271; + rise_resistance : 6.190; + fall_resistance : 3.640; + related_pin : "i3"; + } + } + } + cell (no4_x4) { + area : 3.3 /* pitchs */ + cell_footprint : "no4"; + pin(i0) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i1) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i2) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i3) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "(i0' * i1' * i2' * i3')"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.656; + intrinsic_fall : 0.777; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.564; + intrinsic_fall : 0.768; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.739; + intrinsic_fall : 0.761; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.816; + intrinsic_fall : 0.693; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + } + } + cell (noa2a22_x1) { + area : 2.3 /* pitchs */ + cell_footprint : "noa2a22"; + pin(i0) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i2) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i3) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(nq) { + direction : output; + max_fanout : 0.091; + function : "((i0' + i1') * (i2' + i3'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.151; + intrinsic_fall : 0.327; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.218; + intrinsic_fall : 0.287; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.284; + intrinsic_fall : 0.289; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.372; + intrinsic_fall : 0.256; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i3"; + } + } + } + cell (noa2a22_x4) { + area : 3.7 /* pitchs */ + cell_footprint : "noa2a22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i3) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "((i0' + i1') * (i2' + i3'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.562; + intrinsic_fall : 0.745; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.646; + intrinsic_fall : 0.714; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.701; + intrinsic_fall : 0.703; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.805; + intrinsic_fall : 0.677; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + } + } + cell (nmx3_x1) { + area : 4.0 /* pitchs */ + cell_footprint : "nmx3"; + pin(cmd0) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(cmd1) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(i0) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(nq) { + direction : output; + max_fanout : 0.030; + function : "((cmd0+i0')*(cmd0'+((cmd1'+i1')*(cmd1+i2'))))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.356; + intrinsic_fall : 0.495; + rise_resistance : 9.760; + fall_resistance : 7.420; + related_pin : "cmd0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.414; + intrinsic_fall : 0.566; + rise_resistance : 9.760; + fall_resistance : 7.420; + related_pin : "cmd1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.315; + intrinsic_fall : 0.441; + rise_resistance : 6.680; + fall_resistance : 5.140; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.429; + intrinsic_fall : 0.582; + rise_resistance : 9.760; + fall_resistance : 7.420; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.429; + intrinsic_fall : 0.582; + rise_resistance : 9.760; + fall_resistance : 7.420; + related_pin : "i2"; + } + } + } + cell (nmx3_x4) { + area : 5.0 /* pitchs */ + cell_footprint : "nmx3"; + pin(cmd0) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(cmd1) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(i0) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "((cmd0+i0')*(cmd0'+((cmd1'+i1')*(cmd1+i2'))))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.790; + intrinsic_fall : 0.936; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "cmd0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.866; + intrinsic_fall : 1.048; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "cmd1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.748; + intrinsic_fall : 0.900; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.869; + intrinsic_fall : 1.053; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.869; + intrinsic_fall : 1.053; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + } + } + cell (noa2ao222_x1) { + area : 2.3 /* pitchs */ + cell_footprint : "noa2ao222"; + pin(i0) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i2) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i3) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i4) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(nq) { + direction : output; + max_fanout : 0.055; + function : "((i0'+i1')*((i2'*i3')+i4'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.348; + intrinsic_fall : 0.422; + rise_resistance : 5.260; + fall_resistance : 3.210; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.440; + intrinsic_fall : 0.378; + rise_resistance : 5.260; + fall_resistance : 3.210; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.186; + intrinsic_fall : 0.473; + rise_resistance : 5.260; + fall_resistance : 3.210; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.256; + intrinsic_fall : 0.459; + rise_resistance : 5.260; + fall_resistance : 3.210; + related_pin : "i3"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.240; + intrinsic_fall : 0.309; + rise_resistance : 3.750; + fall_resistance : 3.210; + related_pin : "i4"; + } + } + } + cell (noa2ao222_x4) { + area : 4.0 /* pitchs */ + cell_footprint : "noa2ao222"; + pin(i0) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i2) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i3) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i4) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "((i0'+i1')*((i2'*i3')+i4'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.684; + intrinsic_fall : 0.801; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.780; + intrinsic_fall : 0.758; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.638; + intrinsic_fall : 0.809; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.732; + intrinsic_fall : 0.795; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.718; + intrinsic_fall : 0.664; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i4"; + } + } + } + cell (noa2a2a23_x1) { + area : 3.3 /* pitchs */ + cell_footprint : "noa2a2a23"; + pin(i0) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i2) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i3) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i4) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i5) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(nq) { + direction : output; + max_fanout : 0.062; + function : "((i0'+i1')*(i2'+i3')*(i4'+i5'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.525; + intrinsic_fall : 0.425; + rise_resistance : 4.690; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.643; + intrinsic_fall : 0.388; + rise_resistance : 4.690; + fall_resistance : 2.850; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.307; + intrinsic_fall : 0.479; + rise_resistance : 4.690; + fall_resistance : 2.850; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.398; + intrinsic_fall : 0.438; + rise_resistance : 4.690; + fall_resistance : 2.850; + related_pin : "i3"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.250; + intrinsic_fall : 0.416; + rise_resistance : 4.690; + fall_resistance : 2.850; + related_pin : "i4"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.178; + intrinsic_fall : 0.464; + rise_resistance : 4.690; + fall_resistance : 2.850; + related_pin : "i5"; + } + } + } + cell (noa2a2a23_x4) { + area : 4.3 /* pitchs */ + cell_footprint : "noa2a2a23"; + pin(i0) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i2) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i3) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i4) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i5) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "((i0'+i1')*(i2'+i3')*(i4'+i5'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.834; + intrinsic_fall : 0.814; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.955; + intrinsic_fall : 0.778; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.620; + intrinsic_fall : 0.873; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.716; + intrinsic_fall : 0.833; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.574; + intrinsic_fall : 0.819; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i4"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.496; + intrinsic_fall : 0.865; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i5"; + } + } + } + cell (noa3ao322_x1) { + area : 3.0 /* pitchs */ + cell_footprint : "noa3ao322"; + pin(i0) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i1) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i2) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i3) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i4) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i5) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i6) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(nq) { + direction : output; + max_fanout : 0.043; + function : "((i0'+i1'+i2')*(((i3'*i4')*i5')+i6'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.396; + intrinsic_fall : 0.616; + rise_resistance : 6.700; + fall_resistance : 3.370; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.486; + intrinsic_fall : 0.552; + rise_resistance : 6.700; + fall_resistance : 3.370; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.546; + intrinsic_fall : 0.488; + rise_resistance : 6.700; + fall_resistance : 3.370; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.196; + intrinsic_fall : 0.599; + rise_resistance : 6.700; + fall_resistance : 3.210; + related_pin : "i3"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.264; + intrinsic_fall : 0.608; + rise_resistance : 6.700; + fall_resistance : 3.210; + related_pin : "i4"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.328; + intrinsic_fall : 0.581; + rise_resistance : 6.700; + fall_resistance : 3.210; + related_pin : "i5"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.246; + intrinsic_fall : 0.311; + rise_resistance : 3.690; + fall_resistance : 3.210; + related_pin : "i6"; + } + } + } + cell (noa3ao322_x4) { + area : 4.3 /* pitchs */ + cell_footprint : "noa3ao322"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i3) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i4) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i5) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i6) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "((i0'+i1'+i2')*(((i3'*i4')*i5')+i6'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.819; + intrinsic_fall : 0.987; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.914; + intrinsic_fall : 0.931; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.990; + intrinsic_fall : 0.874; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.729; + intrinsic_fall : 0.926; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.821; + intrinsic_fall : 0.924; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i4"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.907; + intrinsic_fall : 0.900; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i5"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.738; + intrinsic_fall : 0.718; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i6"; + } + } + } + cell (noa2a2a2a24_x1) { + area : 4.7 /* pitchs */ + cell_footprint : "noa2a2a2a24"; + pin(i0) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i2) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i3) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i4) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i5) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i6) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i7) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(nq) { + direction : output; + max_fanout : 0.047; + function : "((i0'+i1')*(i2'+i3')*(i4'+i5')*(i6'+i7'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.649; + intrinsic_fall : 0.606; + rise_resistance : 6.190; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.775; + intrinsic_fall : 0.562; + rise_resistance : 6.190; + fall_resistance : 2.850; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.550; + intrinsic_fall : 0.662; + rise_resistance : 6.190; + fall_resistance : 2.850; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.667; + intrinsic_fall : 0.616; + rise_resistance : 6.190; + fall_resistance : 2.850; + related_pin : "i3"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.419; + intrinsic_fall : 0.613; + rise_resistance : 6.190; + fall_resistance : 2.850; + related_pin : "i4"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.329; + intrinsic_fall : 0.662; + rise_resistance : 6.190; + fall_resistance : 2.850; + related_pin : "i5"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.270; + intrinsic_fall : 0.535; + rise_resistance : 6.190; + fall_resistance : 2.850; + related_pin : "i6"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.200; + intrinsic_fall : 0.591; + rise_resistance : 6.190; + fall_resistance : 2.850; + related_pin : "i7"; + } + } + } + cell (noa2a2a2a24_x4) { + area : 5.7 /* pitchs */ + cell_footprint : "noa2a2a2a24"; + pin(i0) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i2) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i3) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i4) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i5) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i6) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i7) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "((i0'+i1')*(i2'+i3')*(i4'+i5')*(i6'+i7'))"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.966; + intrinsic_fall : 1.049; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 1.097; + intrinsic_fall : 1.005; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.867; + intrinsic_fall : 1.106; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.990; + intrinsic_fall : 1.061; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.748; + intrinsic_fall : 1.061; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i4"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.649; + intrinsic_fall : 1.109; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i5"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.606; + intrinsic_fall : 0.999; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i6"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.525; + intrinsic_fall : 1.052; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i7"; + } + } + } + cell (buf_x2) { + area : 1.3 /* pitchs */ + cell_footprint : "buf"; + pin(i) { + direction : input; + capacitance : 0.006; + fanout_load : 0.006; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "i"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.409; + intrinsic_fall : 0.391; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i"; + } + } + } + cell (buf_x4) { + area : 1.7 /* pitchs */ + cell_footprint : "buf"; + pin(i) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "i"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.379; + intrinsic_fall : 0.409; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i"; + } + } + } + cell (buf_x8) { + area : 2.7 /* pitchs */ + cell_footprint : "buf"; + pin(i) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(q) { + direction : output; + max_fanout : 0.647; + function : "i"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.343; + intrinsic_fall : 0.396; + rise_resistance : 0.450; + fall_resistance : 0.400; + related_pin : "i"; + } + } + } + cell (a2_x2) { + area : 1.7 /* pitchs */ + cell_footprint : "a2"; + pin(i0) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(i0 * i1)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.261; + intrinsic_fall : 0.388; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.203; + intrinsic_fall : 0.434; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + } + } + cell (a2_x4) { + area : 2.0 /* pitchs */ + cell_footprint : "a2"; + pin(i0) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(i0 * i1)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.338; + intrinsic_fall : 0.476; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.269; + intrinsic_fall : 0.518; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + } + } + cell (o2_x2) { + area : 1.7 /* pitchs */ + cell_footprint : "o2"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(i0 + i1)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.406; + intrinsic_fall : 0.310; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.335; + intrinsic_fall : 0.364; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + } + } + cell (o2_x4) { + area : 2.0 /* pitchs */ + cell_footprint : "o2"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(i0 + i1)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.491; + intrinsic_fall : 0.394; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.427; + intrinsic_fall : 0.464; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + } + } + cell (a3_x2) { + area : 2.0 /* pitchs */ + cell_footprint : "a3"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i2) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(i0 * i1 * i2)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.395; + intrinsic_fall : 0.435; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.353; + intrinsic_fall : 0.479; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.290; + intrinsic_fall : 0.521; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + } + } + cell (a3_x4) { + area : 2.3 /* pitchs */ + cell_footprint : "a3"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i2) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(i0 * i1 * i2)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.478; + intrinsic_fall : 0.514; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.428; + intrinsic_fall : 0.554; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.356; + intrinsic_fall : 0.592; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + } + } + cell (ao22_x2) { + area : 2.0 /* pitchs */ + cell_footprint : "ao22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "((i0 + i1) * i2)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.558; + intrinsic_fall : 0.447; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.493; + intrinsic_fall : 0.526; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.420; + intrinsic_fall : 0.425; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + } + } + cell (ao22_x4) { + area : 2.7 /* pitchs */ + cell_footprint : "ao22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "((i0 + i1) * i2)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.674; + intrinsic_fall : 0.552; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.615; + intrinsic_fall : 0.647; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.526; + intrinsic_fall : 0.505; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + } + } + cell (mx2_x2) { + area : 3.0 /* pitchs */ + cell_footprint : "mx2"; + pin(cmd) { + direction : input; + capacitance : 0.017; + fanout_load : 0.017; + } + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(cmd' * i0)+(cmd * i1)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.484; + intrinsic_fall : 0.522; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "cmd"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.451; + intrinsic_fall : 0.469; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.451; + intrinsic_fall : 0.469; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + } + } + cell (mx2_x4) { + area : 3.3 /* pitchs */ + cell_footprint : "mx2"; + pin(cmd) { + direction : input; + capacitance : 0.017; + fanout_load : 0.017; + } + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(cmd' * i0)+(cmd * i1)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.615; + intrinsic_fall : 0.647; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "cmd"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.564; + intrinsic_fall : 0.576; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.564; + intrinsic_fall : 0.576; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + } + } + cell (o3_x2) { + area : 2.0 /* pitchs */ + cell_footprint : "o3"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(i0 + i1 + i2)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.494; + intrinsic_fall : 0.407; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.430; + intrinsic_fall : 0.482; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.360; + intrinsic_fall : 0.506; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + } + } + cell (o3_x4) { + area : 2.3 /* pitchs */ + cell_footprint : "o3"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(i0 + i1 + i2)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.569; + intrinsic_fall : 0.501; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.510; + intrinsic_fall : 0.585; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.447; + intrinsic_fall : 0.622; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + } + } + cell (oa22_x2) { + area : 2.0 /* pitchs */ + cell_footprint : "oa22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "((i0 * i1) + i2)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.390; + intrinsic_fall : 0.555; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.488; + intrinsic_fall : 0.525; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.438; + intrinsic_fall : 0.454; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + } + } + cell (oa22_x4) { + area : 2.7 /* pitchs */ + cell_footprint : "oa22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "((i0 * i1) + i2)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.511; + intrinsic_fall : 0.677; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.615; + intrinsic_fall : 0.650; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.523; + intrinsic_fall : 0.571; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + } + } + cell (a4_x2) { + area : 2.3 /* pitchs */ + cell_footprint : "a4"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i2) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i3) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(i0 * i1 * i2 * i3)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.374; + intrinsic_fall : 0.578; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.441; + intrinsic_fall : 0.539; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.482; + intrinsic_fall : 0.498; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.506; + intrinsic_fall : 0.455; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i3"; + } + } + } + cell (a4_x4) { + area : 2.7 /* pitchs */ + cell_footprint : "a4"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i2) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i3) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(i0 * i1 * i2 * i3)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.505; + intrinsic_fall : 0.650; + rise_resistance : 0.890; + fall_resistance : 0.540; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.578; + intrinsic_fall : 0.614; + rise_resistance : 0.890; + fall_resistance : 0.540; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.627; + intrinsic_fall : 0.576; + rise_resistance : 0.890; + fall_resistance : 0.540; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.661; + intrinsic_fall : 0.538; + rise_resistance : 0.890; + fall_resistance : 0.540; + related_pin : "i3"; + } + } + } + cell (ao2o22_x2) { + area : 3.0 /* pitchs */ + cell_footprint : "ao2o22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i3) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "((i0 + i1) * (i2 + i3))"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.572; + intrinsic_fall : 0.451; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.508; + intrinsic_fall : 0.542; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.432; + intrinsic_fall : 0.627; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.488; + intrinsic_fall : 0.526; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i3"; + } + } + } + cell (ao2o22_x4) { + area : 3.3 /* pitchs */ + cell_footprint : "ao2o22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i3) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "((i0 + i1) * (i2 + i3))"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.696; + intrinsic_fall : 0.569; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.637; + intrinsic_fall : 0.666; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.554; + intrinsic_fall : 0.744; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.606; + intrinsic_fall : 0.639; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + } + } + cell (o4_x2) { + area : 2.3 /* pitchs */ + cell_footprint : "o4"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i2) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i3) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(i0 + i1 + i2 + i3)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.508; + intrinsic_fall : 0.601; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.446; + intrinsic_fall : 0.631; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.567; + intrinsic_fall : 0.531; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.378; + intrinsic_fall : 0.626; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i3"; + } + } + } + cell (o4_x4) { + area : 2.7 /* pitchs */ + cell_footprint : "o4"; + pin(i0) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i1) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i2) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(i3) { + direction : input; + capacitance : 0.012; + fanout_load : 0.012; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(i0 + i1 + i2 + i3)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.574; + intrinsic_fall : 0.638; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.492; + intrinsic_fall : 0.650; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.649; + intrinsic_fall : 0.611; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.721; + intrinsic_fall : 0.536; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + } + } + cell (oa2a22_x2) { + area : 3.0 /* pitchs */ + cell_footprint : "oa2a22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i3) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "((i0 * i1) + (i2 * i3))"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.403; + intrinsic_fall : 0.564; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.495; + intrinsic_fall : 0.534; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.646; + intrinsic_fall : 0.487; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.537; + intrinsic_fall : 0.512; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i3"; + } + } + } + cell (oa2a22_x4) { + area : 3.3 /* pitchs */ + cell_footprint : "oa2a22"; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i3) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "((i0 * i1) + (i2 * i3))"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.519; + intrinsic_fall : 0.696; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.624; + intrinsic_fall : 0.669; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.763; + intrinsic_fall : 0.596; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.644; + intrinsic_fall : 0.619; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + } + } + cell (mx3_x2) { + area : 4.3 /* pitchs */ + cell_footprint : "mx3"; + pin(cmd0) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(cmd1) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(i0) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(cmd0'*i0)+(cmd0*((cmd1*i1)+(cmd1'*i2)))"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.573; + intrinsic_fall : 0.680; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "cmd0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.664; + intrinsic_fall : 0.817; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "cmd1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.538; + intrinsic_fall : 0.658; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.654; + intrinsic_fall : 0.808; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.654; + intrinsic_fall : 0.808; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + } + } + cell (mx3_x4) { + area : 4.7 /* pitchs */ + cell_footprint : "mx3"; + pin(cmd0) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(cmd1) { + direction : input; + capacitance : 0.015; + fanout_load : 0.015; + } + pin(i0) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i1) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(i2) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(cmd0'*i0)+(cmd0*((cmd1*i1)+(cmd1'*i2)))"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.683; + intrinsic_fall : 0.779; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "cmd0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.792; + intrinsic_fall : 0.967; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "cmd1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.640; + intrinsic_fall : 0.774; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.770; + intrinsic_fall : 0.948; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.770; + intrinsic_fall : 0.948; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + } + } + cell (oa2ao222_x2) { + area : 3.3 /* pitchs */ + cell_footprint : "oa2ao222"; + pin(i0) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i2) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i3) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i4) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(i0*i1)+(i4*(i2+i3))"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.495; + intrinsic_fall : 0.581; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.598; + intrinsic_fall : 0.539; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.464; + intrinsic_fall : 0.604; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.556; + intrinsic_fall : 0.578; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i3"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.558; + intrinsic_fall : 0.453; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i4"; + } + } + } + cell (oa2ao222_x4) { + area : 3.7 /* pitchs */ + cell_footprint : "oa2ao222"; + pin(i0) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i1) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i2) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i3) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(i4) { + direction : input; + capacitance : 0.011; + fanout_load : 0.011; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(i0*i1)+(i4*(i2+i3))"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.553; + intrinsic_fall : 0.657; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.662; + intrinsic_fall : 0.616; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.552; + intrinsic_fall : 0.693; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.640; + intrinsic_fall : 0.660; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.656; + intrinsic_fall : 0.529; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i4"; + } + } + } + cell (oa2a2a23_x2) { + area : 4.0 /* pitchs */ + cell_footprint : "oa2a2a23"; + pin(i0) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i2) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i3) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i4) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i5) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "((i0*i1)+(i2*i3))+(i4*i5)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.653; + intrinsic_fall : 0.578; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.775; + intrinsic_fall : 0.542; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.441; + intrinsic_fall : 0.639; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.540; + intrinsic_fall : 0.600; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i3"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.402; + intrinsic_fall : 0.591; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i4"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.321; + intrinsic_fall : 0.636; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i5"; + } + } + } + cell (oa2a2a23_x4) { + area : 4.3 /* pitchs */ + cell_footprint : "oa2a2a23"; + pin(i0) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i1) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i2) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i3) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i4) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i5) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "((i0*i1)+(i2*i3))+(i4*i5)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.699; + intrinsic_fall : 0.648; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.822; + intrinsic_fall : 0.613; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.493; + intrinsic_fall : 0.715; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.594; + intrinsic_fall : 0.677; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.464; + intrinsic_fall : 0.673; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i4"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.379; + intrinsic_fall : 0.714; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i5"; + } + } + } + cell (oa3ao322_x2) { + area : 3.7 /* pitchs */ + cell_footprint : "oa3ao322"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i3) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i4) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i5) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i6) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(i0*i1*i2)+(i6*((i3+i4)+i5))"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.638; + intrinsic_fall : 0.820; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.735; + intrinsic_fall : 0.764; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.806; + intrinsic_fall : 0.707; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.560; + intrinsic_fall : 0.765; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i3"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.649; + intrinsic_fall : 0.760; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i4"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.734; + intrinsic_fall : 0.734; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i5"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.563; + intrinsic_fall : 0.540; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i6"; + } + } + } + cell (oa3ao322_x4) { + area : 4.0 /* pitchs */ + cell_footprint : "oa3ao322"; + pin(i0) { + direction : input; + capacitance : 0.010; + fanout_load : 0.010; + } + pin(i1) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i2) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i3) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i4) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i5) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(i6) { + direction : input; + capacitance : 0.009; + fanout_load : 0.009; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(i0*i1*i2)+(i6*((i3+i4)+i5))"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.717; + intrinsic_fall : 0.946; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.818; + intrinsic_fall : 0.890; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.894; + intrinsic_fall : 0.834; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.673; + intrinsic_fall : 0.898; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.758; + intrinsic_fall : 0.896; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i4"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.839; + intrinsic_fall : 0.865; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i5"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.684; + intrinsic_fall : 0.651; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i6"; + } + } + } + cell (oa2a2a2a24_x2) { + area : 5.0 /* pitchs */ + cell_footprint : "oa2a2a2a24"; + pin(i0) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i1) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i2) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i3) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i4) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i5) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i6) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i7) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(q) { + direction : output; + max_fanout : 0.163; + function : "(i0*i1)+(i2*i3)+(i4*i5)+(i6*i7)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.780; + intrinsic_fall : 0.797; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.909; + intrinsic_fall : 0.753; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.682; + intrinsic_fall : 0.856; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.803; + intrinsic_fall : 0.810; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i3"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.565; + intrinsic_fall : 0.813; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i4"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.467; + intrinsic_fall : 0.861; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i5"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.426; + intrinsic_fall : 0.748; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i6"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.346; + intrinsic_fall : 0.800; + rise_resistance : 1.790; + fall_resistance : 1.620; + related_pin : "i7"; + } + } + } + cell (oa2a2a2a24_x4) { + area : 5.3 /* pitchs */ + cell_footprint : "oa2a2a2a24"; + pin(i0) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i1) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i2) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i3) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i4) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i5) { + direction : input; + capacitance : 0.013; + fanout_load : 0.013; + } + pin(i6) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(i7) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(i0*i1)+(i2*i3)+(i4*i5)+(i6*i7)"; + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.823; + intrinsic_fall : 0.879; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.955; + intrinsic_fall : 0.835; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.726; + intrinsic_fall : 0.940; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i2"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.851; + intrinsic_fall : 0.895; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i3"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.619; + intrinsic_fall : 0.902; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i4"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.515; + intrinsic_fall : 0.949; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i5"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.487; + intrinsic_fall : 0.845; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i6"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.399; + intrinsic_fall : 0.895; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i7"; + } + } + } + cell (nxr2_x1) { + area : 3.0 /* pitchs */ + cell_footprint : "nxr2"; + pin(i0) { + direction : input; + capacitance : 0.021; + fanout_load : 0.021; + } + pin(i1) { + direction : input; + capacitance : 0.022; + fanout_load : 0.022; + } + pin(nq) { + direction : output; + max_fanout : 0.091; + function : "(i0' ^ i1)"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.288; + intrinsic_fall : 0.293; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.156; + intrinsic_fall : 0.327; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.366; + intrinsic_fall : 0.389; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.395; + intrinsic_fall : 0.503; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i1"; + } + } + } + cell (nxr2_x4) { + area : 4.0 /* pitchs */ + cell_footprint : "nxr2"; + pin(i0) { + direction : input; + capacitance : 0.020; + fanout_load : 0.020; + } + pin(i1) { + direction : input; + capacitance : 0.021; + fanout_load : 0.021; + } + pin(nq) { + direction : output; + max_fanout : 0.327; + function : "(i0' ^ i1)"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.522; + intrinsic_fall : 0.553; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.553; + intrinsic_fall : 0.542; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.469; + intrinsic_fall : 0.481; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.568; + intrinsic_fall : 0.453; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + } + } + cell (xr2_x1) { + area : 3.0 /* pitchs */ + cell_footprint : "xr2"; + pin(i0) { + direction : input; + capacitance : 0.021; + fanout_load : 0.021; + } + pin(i1) { + direction : input; + capacitance : 0.022; + fanout_load : 0.022; + } + pin(q) { + direction : output; + max_fanout : 0.091; + function : "(i0 ^ i1)"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.292; + intrinsic_fall : 0.293; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.377; + intrinsic_fall : 0.261; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.366; + intrinsic_fall : 0.389; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.405; + intrinsic_fall : 0.388; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i1"; + } + } + } + cell (xr2_x4) { + area : 4.0 /* pitchs */ + cell_footprint : "xr2"; + pin(i0) { + direction : input; + capacitance : 0.020; + fanout_load : 0.020; + } + pin(i1) { + direction : input; + capacitance : 0.021; + fanout_load : 0.021; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "(i0 ^ i1)"; + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.521; + intrinsic_fall : 0.560; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.541; + intrinsic_fall : 0.657; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.476; + intrinsic_fall : 0.480; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i0"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.357; + intrinsic_fall : 0.539; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i1"; + } + } + } + /* --------------------------------------------- */ + /* combinationnal cells part 2: Three-State */ + /* --------------------------------------------- */ + + cell (nts_x1) { + area : 2.0 /* pitchs */ + cell_footprint : "nts"; + pin(i) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(cmd) { + direction : input; + capacitance : 0.014; + fanout_load : 0.014; + } + pin(nq) { + direction : output; + max_fanout : 0.091; + function : "i'"; + three_state : "cmd'"; + timing() { + intrinsic_rise : 0.249; + intrinsic_fall : 0.041; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "cmd"; + } + timing() { + timing_type : three_state_disable; + intrinsic_rise : 0.249; + intrinsic_fall : 0.041; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "cmd"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.169; + intrinsic_fall : 0.201; + rise_resistance : 3.210; + fall_resistance : 2.850; + related_pin : "i"; + } + } + } + cell (nts_x2) { + area : 2.7 /* pitchs */ + cell_footprint : "nts"; + pin(i) { + direction : input; + capacitance : 0.028; + fanout_load : 0.028; + } + pin(cmd) { + direction : input; + capacitance : 0.018; + fanout_load : 0.018; + } + pin(nq) { + direction : output; + max_fanout : 0.182; + function : "i'"; + three_state : "cmd'"; + timing() { + intrinsic_rise : 0.330; + intrinsic_fall : 0.033; + rise_resistance : 1.600; + fall_resistance : 1.430; + related_pin : "cmd"; + } + timing() { + timing_type : three_state_disable; + intrinsic_rise : 0.330; + intrinsic_fall : 0.033; + rise_resistance : 1.600; + fall_resistance : 1.430; + related_pin : "cmd"; + } + timing() { + timing_sense : negative_unate; + intrinsic_rise : 0.167; + intrinsic_fall : 0.201; + rise_resistance : 1.600; + fall_resistance : 1.430; + related_pin : "i"; + } + } + } + cell (ts_x4) { + area : 3.3 /* pitchs */ + cell_footprint : "ts"; + pin(i) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(cmd) { + direction : input; + capacitance : 0.019; + fanout_load : 0.019; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "i"; + three_state : "cmd'"; + timing() { + intrinsic_rise : 0.492; + intrinsic_fall : 0.409; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "cmd"; + } + timing() { + timing_type : three_state_disable; + intrinsic_rise : 0.492; + intrinsic_fall : 0.409; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "cmd"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.475; + intrinsic_fall : 0.444; + rise_resistance : 0.890; + fall_resistance : 0.810; + related_pin : "i"; + } + } + } + cell (ts_x8) { + area : 4.3 /* pitchs */ + cell_footprint : "ts"; + pin(i) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + pin(cmd) { + direction : input; + capacitance : 0.019; + fanout_load : 0.019; + } + pin(q) { + direction : output; + max_fanout : 0.647; + function : "i"; + three_state : "cmd'"; + timing() { + intrinsic_rise : 0.626; + intrinsic_fall : 0.466; + rise_resistance : 0.450; + fall_resistance : 0.400; + related_pin : "cmd"; + } + timing() { + timing_type : three_state_disable; + intrinsic_rise : 0.626; + intrinsic_fall : 0.466; + rise_resistance : 0.450; + fall_resistance : 0.400; + related_pin : "cmd"; + } + timing() { + timing_sense : positive_unate; + intrinsic_rise : 0.613; + intrinsic_fall : 0.569; + rise_resistance : 0.450; + fall_resistance : 0.400; + related_pin : "i"; + } + } + } + + + /* --------------------------------------------- */ + /* Pull-Up, Pull-Down Cells */ + /* --------------------------------------------- */ + + cell (one_x0) { + area : 1.0 /* pitchs */ + cell_footprint : "one"; + pin(q) { + direction : output ; + max_fanout : 7.82796; + function : "1"; + driver_type : pull_up ; + } + } + + cell (zero_x0) { + area : 1.0 /* pitchs */ + cell_footprint : "zero"; + pin(nq) { + direction : output ; + max_fanout : 7.82796; + function : "0"; + driver_type : pull_down ; + } + } + + /* --------------------------------------------- */ + /* Sequential cells part 1 : Flip-Flops */ + /* --------------------------------------------- */ + + cell (sff1_x4) { + area : 6.0 /* pitchs */ + cell_footprint : "sff1"; + pin(i) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + timing() { + timing_type : setup_rising; + intrinsic_rise : 0.476; + intrinsic_fall : 0.585; + related_pin : "ck"; + } + timing() { + timing_type : hold_rising; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + related_pin : "ck"; + } + } + pin(ck) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + ff("IQ","IQN") { + next_state : "i"; + clocked_on : "ck"; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "IQ"; + timing() { + timing_type : rising_edge; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + rise_resistance : 0.890; + fall_resistance : 0.890; + related_pin : "ck"; + } + } + } + cell (sff2_x4) { + area : 8.0 /* pitchs */ + cell_footprint : "sff2"; + dont_use : false; + pin(i0) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + timing() { + timing_type : setup_rising; + intrinsic_rise : 0.666; + intrinsic_fall : 0.764; + related_pin : "ck"; + } + timing() { + timing_type : hold_rising; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + related_pin : "ck"; + } + } + pin(i1) { + direction : input; + capacitance : 0.007; + fanout_load : 0.007; + timing() { + timing_type : setup_rising; + intrinsic_rise : 0.666; + intrinsic_fall : 0.764; + related_pin : "ck"; + } + timing() { + timing_type : hold_rising; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + related_pin : "ck"; + } + } + pin(cmd) { + direction : input; + capacitance : 0.016; + fanout_load : 0.016; + timing() { + timing_type : setup_rising; + intrinsic_rise : 0.770; + intrinsic_fall : 0.833; + related_pin : "ck"; + } + timing() { + timing_type : hold_rising; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + related_pin : "ck"; + } + } + pin(ck) { + direction : input; + capacitance : 0.008; + fanout_load : 0.008; + } + ff("IQ","IQN") { + next_state : "(cmd * i1) + (cmd' * i0)"; + clocked_on : "ck"; + } + pin(q) { + direction : output; + max_fanout : 0.327; + function : "IQ"; + timing() { + timing_type : rising_edge; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + rise_resistance : 0.890; + fall_resistance : 0.890; + related_pin : "ck"; + } + } + test_cell() { + ff("IQ","IQN") { + next_state : "i0"; + clocked_on : "ck"; + } + pin(i0,ck) { + direction : input; + } + pin(i1) { + direction : input; + signal_type : test_scan_in; + } + pin(cmd) { + direction : input; + signal_type : test_scan_enable; + } + pin(q) { + direction : output; + function : "IQ"; + signal_type : test_scan_out; + } + } + } +} diff --git a/alliance/src/cells/src/sxlib/sxlib.sdb b/alliance/src/cells/src/sxlib/sxlib.sdb new file mode 100644 index 00000000..86798ed2 Binary files /dev/null and b/alliance/src/cells/src/sxlib/sxlib.sdb differ diff --git a/alliance/src/cells/src/sxlib/sxlib.slib b/alliance/src/cells/src/sxlib/sxlib.slib new file mode 100644 index 00000000..6f4d0f4a --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib.slib @@ -0,0 +1,472 @@ +/****************************************************************************** + ** + ** FILE NAME: sclib.slib + ** + ** Created by Mokhtar HIRECH (MASI laboratory) on 26 October 1995 + ** from $SYNOPSYS/libraries/syn/class.slib + ** + ** Modified September 1, 1999 Franck + ** + ***************************************************************************** +*/ + + +TRUE = 1; +FALSE = 0; + + +library("sxlib.sdb") { + + ROUTE_GRID = 1024; + INCHES_PER_GRID = .1; + DB_PER_GRID = ROUTE_GRID; + + CENTEMETERS_PER_GRID = INCHES_PER_GRID * 2.54; + METERS_PER_GRID = CENTEMETERS_PER_GRID / 100; + METERS_PER_DB = METERS_PER_GRID / DB_PER_GRID; + + set_route_grid(ROUTE_GRID); + set_external_scale(METERS_PER_DB); + set_meter_scale(METERS_PER_DB); + + grid_pins : TRUE ; + + + + /* note: One ROUTE_GRID is equivalent to 13 / 2 "units" of the IEEE / ANSI symbol + * standard (Std 91 - 1984). One ROUTE_GRID is equivalent to .2 MIL standard + * units (inches) (MIL - STD - 8086) + * Dimensions were derrived from these standards. + * + * - *************************** + * | * **** + * | *** - ** + * | * **** | * + * | ******* *** DYNAMIC HEIGHT * **** -------- + * * **** | * * * | + * AND_HEIGHT *** - ** * BUBBLE_DIAMETER + * * ** * | + * | <-------> *. **** -------- + * | * DYNAMIC WIDTH *. + * | ******* * . + * | * ** . + * | * *** . + * - *************************** . + * . . + * . . + * . . + * <-------------- AND_WIDTH ---------> + * + * + * + * XOR_GAP + * <-------> + * . . + * . . + * . . + * . . + * * *********************** - + * * * ******** | + * * * **** | + * * * ** | + * * * ** | + * * * * + * -.............*.......*..........+ * OR_HEIGHT + * | * * * + * | * *. . *. | + * OR_Y_ORIGIN * *. . ** . | + * | * * . . ** . | + * | * * . . **** . | + * | * * . . ******** . | + * -........*.......*********************** . - + * . . + * <- OR_X_ORIGIN -> . + * . . + * . . + * <---------- OR_WIDTH --------------> + * + * + * + * NOTE: + * + * Both OR_HEIGHT and AND_HEIGHT are defined to be four. + * The rest of the parameters are under "user" control. + * + * The radius of the arcs in an OR gate are defined to be equal to the + * height of the OR gate (this seems to be an industry standard). Thus, + * The radius of all three arcs are defined to be four. + * + * Both the MIL standard and the ANSI / IEEE standard have slightly different + * ideas on these dimensions, so choose the dimensions you like best: + * + */ + +/* REQUIRED SIZES: */ + +AND_HEIGHT = 4; +OR_HEIGHT = 4; + +grid_pins : TRUE ; + +/* ANSI Dimensions: + * The ANSI dimensions have been commented out in favor of the MIL dimensions: + * + * ANSI_AND_HEIGHT = 26.0; + * SCALE = AND_HEIGHT / ANSI_AND_HEIGHT; + * + * AND_WIDTH = 32 * SCALE; + * OR_WIDTH = 32 * SCALE; + * INVERTER_HEIGHT = 22.5 * SCALE; + * XOR_GAP = 5 * SCALE; + * BUBBLE_DIAMETER = 4 * SCALE; + * DYNAMIC_HEIGHT = 4 * SCALE; + * DYNAMIC_WIDTH = 6 * SCALE; + * OFF_SHEET_HEIGHT = 8 * SCALE; Not specified by ANSI, + * this value from MIL + * + */ + + +/* MIL Dimensions: */ + +GRIDS_PER_INCH = 1 / INCHES_PER_GRID; +MIL_AND_HEIGHT = .8; +SCALE = AND_HEIGHT / MIL_AND_HEIGHT; + +AND_WIDTH = 1.00 * SCALE; +OR_WIDTH = 1.00 * SCALE; +OR_INTERNAL_WIDTH = 0.50 * GRIDS_PER_INCH; +INVERTER_HEIGHT = .70 * SCALE; +XOR_GAP = (2.0 / 13.0) * SCALE; /* Not specifed by MIL, this value from ANSI */ +BUBBLE_DIAMETER = .16 * SCALE; +DYNAMIC_HEIGHT = .15 * SCALE; +DYNAMIC_WIDTH = .30 * SCALE; +OFF_SHEET_HEIGHT = .25 * SCALE; + + +/* The following values are not specified by MIL or ANSI: */ + +/* Origins are defined as offset from the lower left corner */ +OR_X_ORIGIN = 3; +OR_Y_ORIGIN = 2; +AND_X_ORIGIN = 3; +AND_Y_ORIGIN = 2; +INVERTER_X_ORIGIN = 1; +INVERTER_Y_ORIGIN = INVERTER_HEIGHT / 2.0; + +EXTRA_WING_SPAN = .5; /* ON 3 + GATES, CONTROLS WING SIZE */ +GATE_GAP = 0; /* CONTROLS VERTICAL GAP ON STACKED GATES */ + +/* The following values are deduced from the above values: */ + +BUBBLE_RADIUS = BUBBLE_DIAMETER / 2.0; +DYNAMIC_RADIUS = DYNAMIC_HEIGHT / 2.0; + + + symbol(and_outline) { + AND_LEFT_X = - AND_X_ORIGIN; + AND_BOTTOM_Y = - AND_Y_ORIGIN; + + AND_TOP_Y = AND_BOTTOM_Y + AND_HEIGHT; + X_START_OF_ARC = AND_LEFT_X + AND_WIDTH - AND_HEIGHT / 2.0; + AND_MIDDLE_Y = AND_BOTTOM_Y + AND_HEIGHT / 2.0; + AND_RIGHT_X = AND_LEFT_X + AND_WIDTH; + + line(AND_LEFT_X, AND_TOP_Y, X_START_OF_ARC, AND_TOP_Y); + line(AND_LEFT_X, AND_BOTTOM_Y, X_START_OF_ARC, AND_BOTTOM_Y); + arc(X_START_OF_ARC, AND_TOP_Y, X_START_OF_ARC, AND_BOTTOM_Y, \ + X_START_OF_ARC, AND_MIDDLE_Y); + } + + + symbol(inverter_triangle) { + + /* The origins are defined to be the offset from the lower left corner */ + INVERTER_LEFT_X = - INVERTER_X_ORIGIN; + INVERTER_BOTTOM_Y = - INVERTER_Y_ORIGIN; + + INVERTER_RIGHT_X = INVERTER_LEFT_X + INVERTER_HEIGHT * SQRT(3) / 2.0; + INVERTER_TOP_Y = INVERTER_BOTTOM_Y + INVERTER_HEIGHT; + INVERTER_MIDDLE_Y = INVERTER_BOTTOM_Y + INVERTER_HEIGHT / 2.0; + + line(INVERTER_LEFT_X, INVERTER_TOP_Y, INVERTER_RIGHT_X, INVERTER_MIDDLE_Y); + line(INVERTER_RIGHT_X, INVERTER_MIDDLE_Y, \ + INVERTER_LEFT_X, INVERTER_BOTTOM_Y); + line(INVERTER_LEFT_X, INVERTER_BOTTOM_Y, INVERTER_LEFT_X, INVERTER_TOP_Y); + } + + symbol(solder_dot) { + line( -.25,-.25,.25,-.25); + line(.25,.25,.25,-.25); + line(.25,.25,-.25,.25); + line( -.25,.25,-.25,-.25); + line( -.25,-.25,.25,.25); + line(.25,-.25,-.25,.25); + } + +/****************************************************************************** +** +** New symbols added for SCLIB cells +** +******************************************************************************/ + + symbol(inv_x1) { + sub_symbol(inverter_triangle, 0,0,0); + + circle(INVERTER_RIGHT_X + BUBBLE_RADIUS, INVERTER_MIDDLE_Y, BUBBLE_RADIUS); + pin(nq, INVERTER_RIGHT_X + BUBBLE_DIAMETER, INVERTER_MIDDLE_Y, RIGHT); + pin(i, INVERTER_LEFT_X, INVERTER_MIDDLE_Y, LEFT); + } + + symbol(a2_x1) { + sub_symbol(and_outline, 0,0,0); + + line(AND_LEFT_X, AND_BOTTOM_Y, AND_LEFT_X, AND_TOP_Y); + + pin(i0, AND_LEFT_X, AND_BOTTOM_Y + 3, LEFT); + pin(i1, AND_LEFT_X, AND_BOTTOM_Y + 1, LEFT); + pin(q, AND_RIGHT_X, AND_MIDDLE_Y, RIGHT); + } + + symbol(na2_x1) { + sub_symbol(and_outline, 0,0,0); + + line(AND_LEFT_X, AND_BOTTOM_Y, AND_LEFT_X, AND_TOP_Y); + circle(AND_LEFT_X - BUBBLE_RADIUS, AND_BOTTOM_Y + 1, BUBBLE_RADIUS); + + pin(i0, AND_LEFT_X, AND_BOTTOM_Y + 3, LEFT); + pin(i1, (AND_LEFT_X - BUBBLE_DIAMETER), AND_BOTTOM_Y + 1, LEFT); + pin(nq, AND_RIGHT_X, AND_MIDDLE_Y, RIGHT); + } + + + OR_LEFT_X = - OR_X_ORIGIN; + OR_BOTTOM_Y = - OR_Y_ORIGIN; + + OR_TOP_Y = OR_BOTTOM_Y + OR_HEIGHT; + OR_LEFT_ARC_CENTER_X = OR_LEFT_X - sqrt(.75 * OR_HEIGHT * OR_HEIGHT); + OR_MIDDLE_Y = OR_BOTTOM_Y + OR_HEIGHT / 2.0; + OR_RIGHT_X = OR_LEFT_ARC_CENTER_X + OR_HEIGHT + OR_INTERNAL_WIDTH; + OR_RIGHT_ARCS_X_START = OR_RIGHT_X - sqrt(.75 * OR_HEIGHT * OR_HEIGHT); +/* + OR_WIDTH = OR_RIGHT_X - OR_LEFT_X; +*/ + symbol(left_side_of_or) { + arc(OR_LEFT_X,OR_TOP_Y,OR_LEFT_X, OR_BOTTOM_Y, \ + OR_LEFT_ARC_CENTER_X, OR_MIDDLE_Y); + } + + + symbol(or_outline) { + sub_symbol(left_side_of_or, 0,0,0); + + + arc(OR_RIGHT_ARCS_X_START, OR_TOP_Y, OR_RIGHT_X, OR_MIDDLE_Y, \ + OR_RIGHT_ARCS_X_START, OR_BOTTOM_Y); + arc(OR_RIGHT_X, OR_MIDDLE_Y, OR_RIGHT_ARCS_X_START, OR_BOTTOM_Y, \ + OR_RIGHT_ARCS_X_START, OR_TOP_Y); + + line(OR_LEFT_X, OR_TOP_Y, OR_RIGHT_ARCS_X_START, OR_TOP_Y); + line(OR_LEFT_X, OR_BOTTOM_Y, OR_RIGHT_ARCS_X_START, OR_BOTTOM_Y); + } + + OR_EVEN_LEFT_PIN_X = OR_LEFT_ARC_CENTER_X + sqrt((15.0 / 16.0) * \ + OR_HEIGHT * OR_HEIGHT); + OR_ODD_LEFT_PIN_X = OR_LEFT_ARC_CENTER_X + OR_HEIGHT; + + symbol(o2_x1) { + sub_symbol(or_outline,0,0,0); + + pin(i0, OR_EVEN_LEFT_PIN_X, OR_BOTTOM_Y + 3, LEFT); + pin(i1, OR_EVEN_LEFT_PIN_X, OR_BOTTOM_Y + 1, LEFT); + pin(q, OR_RIGHT_X, 0, RIGHT); + } + + /* height assumed to be radius of or arc */ + OR_NOT_CIRCLE_X = OR_LEFT_ARC_CENTER_X + sqrt(((OR_HEIGHT - BUBBLE_RADIUS) * \ + (OR_HEIGHT - BUBBLE_RADIUS)) - 1); + symbol(no2_x1) { + sub_symbol(or_outline, 0,0,0); + + circle(OR_NOT_CIRCLE_X, OR_BOTTOM_Y + 1, BUBBLE_RADIUS); + + pin(i0, OR_EVEN_LEFT_PIN_X, OR_BOTTOM_Y + 3, LEFT); + pin(i1, OR_NOT_CIRCLE_X - BUBBLE_RADIUS, OR_BOTTOM_Y + 1, LEFT); + pin(nq, OR_RIGHT_X, 0, RIGHT); + } + + + symbol(B2I) { + LEFT_INVERTER_ORIGIN_X = - INVERTER_X_ORIGIN - 2; + sub_symbol(inverter_triangle, LEFT_INVERTER_ORIGIN_X,0,0); + circle(LEFT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_RADIUS, \ + INVERTER_MIDDLE_Y, BUBBLE_RADIUS); + + RIGHT_INVERTER_ORIGIN_X = INVERTER_X_ORIGIN + 2; + sub_symbol(inverter_triangle, RIGHT_INVERTER_ORIGIN_X,0,0); + circle(RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_RADIUS, \ + INVERTER_MIDDLE_Y, BUBBLE_RADIUS); + + line(LEFT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER, \ + INVERTER_MIDDLE_Y, \ + RIGHT_INVERTER_ORIGIN_X + INVERTER_LEFT_X, INVERTER_MIDDLE_Y); + sub_symbol(solder_dot, INVERTER_X_ORIGIN,0,0); + line(INVERTER_X_ORIGIN, INVERTER_MIDDLE_Y, \ + INVERTER_X_ORIGIN, ceil(INVERTER_TOP_Y) + 1); + line(INVERTER_X_ORIGIN, ceil(INVERTER_TOP_Y) + 1, \ + RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER, \ + ceil(INVERTER_TOP_Y) + 1); + pin(Z1, RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER, \ + ceil(INVERTER_TOP_Y) + 1, RIGHT); + pin(Z2, RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER, \ + INVERTER_MIDDLE_Y, RIGHT); + pin(A, LEFT_INVERTER_ORIGIN_X + INVERTER_LEFT_X, INVERTER_MIDDLE_Y, LEFT); + } + symbol(B2IP) { + sub_symbol(B2I, 0,0,0); + } + symbol(B3I) { + sub_symbol(B2I, 0,0,0); + } + symbol(B3IP) { + sub_symbol(B2I, 0,0,0); + } + symbol(mux2) { + MUX_WIDTH = 2.0; + MUX_X_ORIGIN = MUX_WIDTH / 2.0; + MUX_HEIGHT = 4.0; + MUX_Y_ORIGIN = MUX_HEIGHT / 2.0; + + MUX_LEFT = MUX_X_ORIGIN - (MUX_WIDTH / 2.0); + MUX_RIGHT = MUX_X_ORIGIN + (MUX_WIDTH / 2.0); + MUX_TOP = MUX_Y_ORIGIN + (MUX_HEIGHT / 2.0); + MUX_BOTTOM = MUX_Y_ORIGIN - (MUX_HEIGHT / 2.0); + line(MUX_LEFT, MUX_BOTTOM, MUX_RIGHT, MUX_BOTTOM); + line(MUX_LEFT, MUX_BOTTOM, MUX_LEFT, MUX_TOP); + line(MUX_RIGHT, MUX_TOP, MUX_RIGHT, MUX_BOTTOM); + line(MUX_RIGHT, MUX_TOP, MUX_LEFT, MUX_TOP); + pin(A, MUX_LEFT, MUX_Y_ORIGIN + 1, LEFT); + pin(B, MUX_LEFT, MUX_Y_ORIGIN - 1, LEFT); + pin(S, MUX_X_ORIGIN, MUX_BOTTOM , DOWN); + } + symbol(MUX21H) { + sub_symbol(mux2, 0,0,0); + pin(Z, MUX_RIGHT, MUX_Y_ORIGIN, RIGHT); + } + symbol(MUX21HP) { + sub_symbol(MUX21H, 0,0,0); + } + symbol(MUX21L) { + sub_symbol(mux2, 0,0,0); + pin(Z, MUX_RIGHT + BUBBLE_DIAMETER, MUX_Y_ORIGIN, RIGHT); + circle(MUX_RIGHT + BUBBLE_RADIUS, MUX_Y_ORIGIN, BUBBLE_RADIUS); + } + symbol(MUX21LP) { + sub_symbol(MUX21L, 0,0,0); + } + symbol(mux2sel) { + MUX_WIDTH = 3.0; + MUX_X_ORIGIN = MUX_WIDTH / 2.0; + MUX_HEIGHT = 4.0; + MUX_Y_ORIGIN = MUX_HEIGHT / 2.0; + + MUX_LEFT = MUX_X_ORIGIN - (MUX_WIDTH / 2.0); + MUX_RIGHT = MUX_X_ORIGIN + (MUX_WIDTH / 2.0); + MUX_TOP = MUX_Y_ORIGIN + (MUX_HEIGHT / 2.0); + MUX_BOTTOM = MUX_Y_ORIGIN - (MUX_HEIGHT / 2.0); + line(MUX_LEFT, MUX_BOTTOM, MUX_RIGHT, MUX_BOTTOM); + line(MUX_LEFT, MUX_BOTTOM, MUX_LEFT, MUX_TOP); + line(MUX_RIGHT, MUX_TOP, MUX_RIGHT, MUX_BOTTOM); + line(MUX_RIGHT, MUX_TOP, MUX_LEFT, MUX_TOP); + } + symbol(MUX21LA) { + sub_symbol(mux2sel, 0,0,0); + pin(A, MUX_LEFT, MUX_Y_ORIGIN + 1, LEFT); + pin(B, MUX_LEFT, MUX_Y_ORIGIN - 1, LEFT); + pin(SN, MUX_X_ORIGIN - 0.5, MUX_BOTTOM - BUBBLE_DIAMETER , DOWN); + circle(MUX_X_ORIGIN - 0.5, MUX_BOTTOM - BUBBLE_RADIUS, BUBBLE_RADIUS); + pin(S, MUX_X_ORIGIN + 0.5, MUX_BOTTOM , DOWN); + circle(MUX_RIGHT + BUBBLE_RADIUS, MUX_Y_ORIGIN, BUBBLE_RADIUS); + pin(Z, MUX_RIGHT + BUBBLE_DIAMETER, MUX_Y_ORIGIN, RIGHT); + } + symbol(MUX21LAP) { + sub_symbol(MUX21LA, 0,0,0); + } + symbol(MUX31L) { + sub_symbol(mux2sel, 0,0,0); + pin(D0, MUX_LEFT, MUX_Y_ORIGIN + 1, LEFT); + pin(D1, MUX_LEFT, MUX_Y_ORIGIN , LEFT); + pin(D2, MUX_LEFT, MUX_Y_ORIGIN - 1, LEFT); + pin(A, MUX_X_ORIGIN - 0.5, MUX_BOTTOM , DOWN); + pin(B, MUX_X_ORIGIN + 0.5, MUX_BOTTOM , DOWN); + circle(MUX_RIGHT + BUBBLE_RADIUS, MUX_Y_ORIGIN, BUBBLE_RADIUS); + pin(Z, MUX_RIGHT + BUBBLE_DIAMETER, MUX_Y_ORIGIN, RIGHT); + } + symbol(MUX31LP) { + sub_symbol(MUX31L, 0,0,0); + } + +FFBOX_WIDTH = 6.0; +FFBOX_X_ORIGIN = FFBOX_WIDTH / 2.0; +FFBOX_HEIGHT = 10.0; +FFBOX_Y_ORIGIN = FFBOX_HEIGHT / 2.0; + +FFBOX_LEFT = FFBOX_X_ORIGIN - (FFBOX_WIDTH / 2.0); +FFBOX_RIGHT = FFBOX_X_ORIGIN + (FFBOX_WIDTH / 2.0); + + symbol(ff_box) { + FFBOX_TOP = FFBOX_Y_ORIGIN + (FFBOX_HEIGHT / 2.0); + FFBOX_BOTTOM = FFBOX_Y_ORIGIN - (FFBOX_HEIGHT / 2.0); + line(FFBOX_LEFT, FFBOX_BOTTOM, FFBOX_RIGHT, FFBOX_BOTTOM); + line(FFBOX_LEFT, FFBOX_BOTTOM, FFBOX_LEFT, FFBOX_TOP); + line(FFBOX_RIGHT, FFBOX_TOP, FFBOX_RIGHT, FFBOX_BOTTOM); + line(FFBOX_RIGHT, FFBOX_TOP, FFBOX_LEFT, FFBOX_TOP); + pin(Q, FFBOX_RIGHT, FFBOX_Y_ORIGIN + 4 , RIGHT); + pin(QN, FFBOX_RIGHT + BUBBLE_DIAMETER, FFBOX_Y_ORIGIN - 4 , RIGHT); + circle(FFBOX_RIGHT + BUBBLE_RADIUS, FFBOX_Y_ORIGIN - 4, BUBBLE_RADIUS); + } + + symbol(FD1) { + sub_symbol(ff_box, 0,0,0); + pin(D, FFBOX_LEFT, FFBOX_Y_ORIGIN + 4, LEFT); + + CLOCK_Y = FFBOX_Y_ORIGIN - 4; + pin(CP, FFBOX_LEFT, CLOCK_Y , LEFT); + line(FFBOX_LEFT, CLOCK_Y - 0.5, FFBOX_LEFT + 1, CLOCK_Y); + line(FFBOX_LEFT, CLOCK_Y + 0.5, FFBOX_LEFT + 1, CLOCK_Y); + } + + symbol(FD1P) { + sub_symbol(FD1, 0,0,0); + } + symbol(FDW) { + sub_symbol(FD1, 0,0,0); + pin(CD, FFBOX_X_ORIGIN, FFBOX_BOTTOM - BUBBLE_DIAMETER, DOWN); + circle(FFBOX_X_ORIGIN,FFBOX_BOTTOM - BUBBLE_RADIUS, BUBBLE_RADIUS); + } + + symbol(FD4) { + sub_symbol(FD1, 0,0,0); + pin(SD, FFBOX_X_ORIGIN, FFBOX_TOP + BUBBLE_DIAMETER, UP); + circle(FFBOX_X_ORIGIN,FFBOX_TOP + BUBBLE_RADIUS, BUBBLE_RADIUS); + } + symbol(box_3x6) { + BOX_3X6_WIDTH = 3.0; + BOX_3X6_X_ORIGIN = BOX_3X6_WIDTH / 2.0; + BOX_3X6_HEIGHT = 6.0; + BOX_3X6_Y_ORIGIN = BOX_3X6_HEIGHT / 2.0; + + BOX_3X6_LEFT = BOX_3X6_X_ORIGIN - (BOX_3X6_WIDTH / 2.0); + BOX_3X6_RIGHT = BOX_3X6_X_ORIGIN + (BOX_3X6_WIDTH / 2.0); + BOX_3X6_TOP = BOX_3X6_Y_ORIGIN + (BOX_3X6_HEIGHT / 2.0); + BOX_3X6_BOTTOM = BOX_3X6_Y_ORIGIN - (BOX_3X6_HEIGHT / 2.0); + line(BOX_3X6_LEFT, BOX_3X6_BOTTOM, BOX_3X6_RIGHT, BOX_3X6_BOTTOM); + line(BOX_3X6_LEFT, BOX_3X6_BOTTOM, BOX_3X6_LEFT, BOX_3X6_TOP); + line(BOX_3X6_RIGHT, BOX_3X6_TOP, BOX_3X6_RIGHT, BOX_3X6_BOTTOM); + line(BOX_3X6_RIGHT, BOX_3X6_TOP, BOX_3X6_LEFT, BOX_3X6_TOP); + } +} + + + +/*****************************************************************************/ diff --git a/alliance/src/cells/src/sxlib/sxlib_FTGS.vhd b/alliance/src/cells/src/sxlib/sxlib_FTGS.vhd new file mode 100644 index 00000000..6bc6ab6f --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib_FTGS.vhd @@ -0,0 +1,12219 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_FTGS.vhd +-- FILE CONTENTS: Entity, Structural Architecture(FTGS), +-- and Configuration +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : FTGS, Timing_mesg(TRUE), Timing_xgen(FALSE), GLITCH_HANDLE +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a2_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_a2_x2_FTGS of a2_x2 is + for FTGS + end for; +end CFG_a2_x2_FTGS; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_a2_x4_FTGS of a2_x4 is + for FTGS + end for; +end CFG_a2_x4_FTGS; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a3_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_a3_x2_FTGS of a3_x2 is + for FTGS + end for; +end CFG_a3_x2_FTGS; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_a3_x4_FTGS of a3_x4 is + for FTGS + end for; +end CFG_a3_x4_FTGS; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a4_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000000000000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_a4_x2_FTGS of a4_x2 is + for FTGS + end for; +end CFG_a4_x2_FTGS; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000000000000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_a4_x4_FTGS of a4_x4 is + for FTGS + end for; +end CFG_a4_x4_FTGS; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of an12_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_an12_x1_FTGS of an12_x1 is + for FTGS + end for; +end CFG_an12_x1_FTGS; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of an12_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_an12_x4_FTGS of an12_x4 is + for FTGS + end for; +end CFG_an12_x4_FTGS; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao2o22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000011101110111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_ao2o22_x2_FTGS of ao2o22_x2 is + for FTGS + end for; +end CFG_ao2o22_x2_FTGS; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao2o22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000011101110111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_ao2o22_x4_FTGS of ao2o22_x4 is + for FTGS + end for; +end CFG_ao2o22_x4_FTGS; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00010101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_ao22_x2_FTGS of ao22_x2 is + for FTGS + end for; +end CFG_ao22_x2_FTGS; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00010101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_ao22_x4_FTGS of ao22_x4 is + for FTGS + end for; +end CFG_ao22_x4_FTGS; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of buf_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "01", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i q", + delay_param => + ( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_buf_x2_FTGS of buf_x2 is + for FTGS + end for; +end CFG_buf_x2_FTGS; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of buf_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "01", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i q", + delay_param => + ( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_buf_x4_FTGS of buf_x4 is + for FTGS + end for; +end CFG_buf_x4_FTGS; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of buf_x8 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "01", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i q", + delay_param => + ( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_buf_x8_FTGS of buf_x8 is + for FTGS + end for; +end CFG_buf_x8_FTGS; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x1_FTGS of inv_x1 is + for FTGS + end for; +end CFG_inv_x1_FTGS; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x2_FTGS of inv_x2 is + for FTGS + end for; +end CFG_inv_x2_FTGS; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x4_FTGS of inv_x4 is + for FTGS + end for; +end CFG_inv_x4_FTGS; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x8 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x8_FTGS of inv_x8 is + for FTGS + end for; +end CFG_inv_x8_FTGS; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx2_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00110101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 q", + delay_param => + ((tpdcmd_q_R, tpdcmd_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_mx2_x2_FTGS of mx2_x2 is + for FTGS + end for; +end CFG_mx2_x2_FTGS; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00110101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 q", + delay_param => + ((tpdcmd_q_R, tpdcmd_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_mx2_x4_FTGS of mx2_x4 is + for FTGS + end for; +end CFG_mx2_x4_FTGS; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx3_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00001111000011110101010100110011", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 q", + delay_param => + ((tpdcmd0_q_R, tpdcmd0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_q_R, tpdcmd1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_mx3_x2_FTGS of mx3_x2 is + for FTGS + end for; +end CFG_mx3_x2_FTGS; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00001111000011110101010100110011", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 q", + delay_param => + ((tpdcmd0_q_R, tpdcmd0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_q_R, tpdcmd1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_mx3_x4_FTGS of mx3_x4 is + for FTGS + end for; +end CFG_mx3_x4_FTGS; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_na2_x1_FTGS of na2_x1 is + for FTGS + end for; +end CFG_na2_x1_FTGS; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_na2_x4_FTGS of na2_x4 is + for FTGS + end for; +end CFG_na2_x4_FTGS; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na3_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_na3_x1_FTGS of na3_x1 is + for FTGS + end for; +end CFG_na3_x1_FTGS; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_na3_x4_FTGS of na3_x4 is + for FTGS + end for; +end CFG_na3_x4_FTGS; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na4_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111111111111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_na4_x1_FTGS of na4_x1 is + for FTGS + end for; +end CFG_na4_x1_FTGS; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111111111111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_na4_x4_FTGS of na4_x4 is + for FTGS + end for; +end CFG_na4_x4_FTGS; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao2o22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111100010001000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_nao2o22_x1_FTGS of nao2o22_x1 is + for FTGS + end for; +end CFG_nao2o22_x1_FTGS; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao2o22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111100010001000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_nao2o22_x4_FTGS of nao2o22_x4 is + for FTGS + end for; +end CFG_nao2o22_x4_FTGS; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11101010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nao22_x1_FTGS of nao22_x1 is + for FTGS + end for; +end CFG_nao22_x1_FTGS; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11101010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nao22_x4_FTGS of nao22_x4 is + for FTGS + end for; +end CFG_nao22_x4_FTGS; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11001010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 nq", + delay_param => + ((tpdcmd_nq_R, tpdcmd_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nmx2_x1_FTGS of nmx2_x1 is + for FTGS + end for; +end CFG_nmx2_x1_FTGS; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11001010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 nq", + delay_param => + ((tpdcmd_nq_R, tpdcmd_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nmx2_x4_FTGS of nmx2_x4 is + for FTGS + end for; +end CFG_nmx2_x4_FTGS; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx3_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11110000111100001010101011001100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 nq", + delay_param => + ((tpdcmd0_nq_R, tpdcmd0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_nq_R, tpdcmd1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_nmx3_x1_FTGS of nmx3_x1 is + for FTGS + end for; +end CFG_nmx3_x1_FTGS; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11110000111100001010101011001100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 nq", + delay_param => + ((tpdcmd0_nq_R, tpdcmd0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_nq_R, tpdcmd1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_nmx3_x4_FTGS of nmx3_x4 is + for FTGS + end for; +end CFG_nmx3_x4_FTGS; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_no2_x1_FTGS of no2_x1 is + for FTGS + end for; +end CFG_no2_x1_FTGS; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_no2_x4_FTGS of no2_x4 is + for FTGS + end for; +end CFG_no2_x4_FTGS; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no3_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_no3_x1_FTGS of no3_x1 is + for FTGS + end for; +end CFG_no3_x1_FTGS; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_no3_x4_FTGS of no3_x4 is + for FTGS + end for; +end CFG_no3_x4_FTGS; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no4_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1000000000000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_no4_x1_FTGS of no4_x1 is + for FTGS + end for; +end CFG_no4_x1_FTGS; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1000000000000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_no4_x4_FTGS of no4_x4 is + for FTGS + end for; +end CFG_no4_x4_FTGS; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a2a24_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "10101000101010001010100000000000", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i2 i3 i4 i5 i0 i1 i6 i7 nq", + delay_param => + ((tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_nq_R, tpdi7_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(6), + Input(7) => connect(7), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a2a24_x1_FTGS of noa2a2a2a24_x1 is + for FTGS + end for; +end CFG_noa2a2a2a24_x1_FTGS; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a2a24_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "10101000101010001010100000000000", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i2 i3 i4 i5 i0 i1 i6 i7 nq", + delay_param => + ((tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_nq_R, tpdi7_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(6), + Input(7) => connect(7), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a2a24_x4_FTGS of noa2a2a2a24_x4 is + for FTGS + end for; +end CFG_noa2a2a2a24_x4_FTGS; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a23_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "10101000", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i0 i1 i4 i5 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(2), + Input(5) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a23_x1_FTGS of noa2a2a23_x1 is + for FTGS + end for; +end CFG_noa2a2a23_x1_FTGS; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a23_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "10101000", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i0 i1 i4 i5 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(2), + Input(5) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a23_x4_FTGS of noa2a2a23_x4 is + for FTGS + end for; +end CFG_noa2a2a23_x4_FTGS; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1110111011100000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a22_x1_FTGS of noa2a22_x1 is + for FTGS + end for; +end CFG_noa2a22_x1_FTGS; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1110111011100000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a22_x4_FTGS of noa2a22_x4 is + for FTGS + end for; +end CFG_noa2a22_x4_FTGS; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2ao222_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11101010111010101110101000000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_noa2ao222_x1_FTGS of noa2ao222_x1 is + for FTGS + end for; +end CFG_noa2ao222_x1_FTGS; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2ao222_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11101010111010101110101000000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_noa2ao222_x4_FTGS of noa2ao222_x4 is + for FTGS + end for; +end CFG_noa2ao222_x4_FTGS; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa3ao322_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "0001010101010101" & + "1010101010101000", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 nq", + delay_param => + ((tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa3ao322_x1_FTGS of noa3ao322_x1 is + for FTGS + end for; +end CFG_noa3ao322_x1_FTGS; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa3ao322_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "0001010101010101" & + "1010101010101000", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 nq", + delay_param => + ((tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa3ao322_x4_FTGS of noa3ao322_x4 is + for FTGS + end for; +end CFG_noa3ao322_x4_FTGS; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10101000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa22_x1_FTGS of noa22_x1 is + for FTGS + end for; +end CFG_noa22_x1_FTGS; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10101000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa22_x4_FTGS of noa22_x4 is + for FTGS + end for; +end CFG_noa22_x4_FTGS; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nts_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z1Z0", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd nq", + delay_param => + ((tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_nq_R, tpdcmd_nq_F, tpdcmd_nq_LZ, tpdcmd_nq_R, tpdcmd_nq_HZ, tpdcmd_nq_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_nts_x1_FTGS of nts_x1 is + for FTGS + end for; +end CFG_nts_x1_FTGS; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nts_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z1Z0", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd nq", + delay_param => + ((tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_nq_R, tpdcmd_nq_F, tpdcmd_nq_LZ, tpdcmd_nq_R, tpdcmd_nq_HZ, tpdcmd_nq_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_nts_x2_FTGS of nts_x2 is + for FTGS + end for; +end CFG_nts_x2_FTGS; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nxr2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_nxr2_x1_FTGS of nxr2_x1 is + for FTGS + end for; +end CFG_nxr2_x1_FTGS; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nxr2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_nxr2_x4_FTGS of nxr2_x4 is + for FTGS + end for; +end CFG_nxr2_x4_FTGS; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o2_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_o2_x2_FTGS of o2_x2 is + for FTGS + end for; +end CFG_o2_x2_FTGS; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_o2_x4_FTGS of o2_x4 is + for FTGS + end for; +end CFG_o2_x4_FTGS; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o3_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_o3_x2_FTGS of o3_x2 is + for FTGS + end for; +end CFG_o3_x2_FTGS; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_o3_x4_FTGS of o3_x4 is + for FTGS + end for; +end CFG_o3_x4_FTGS; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o4_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0111111111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_o4_x2_FTGS of o4_x2 is + for FTGS + end for; +end CFG_o4_x2_FTGS; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0111111111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_o4_x4_FTGS of o4_x4 is + for FTGS + end for; +end CFG_o4_x4_FTGS; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a2a24_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "01010111010101110101011111111111", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i4 i5 i6 i7 i0 i1 i2 i3 q", + delay_param => + ((tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_q_R, tpdi7_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(4), + Input(1) => connect(5), + Input(2) => connect(6), + Input(3) => connect(7), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Input(7) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a2a24_x2_FTGS of oa2a2a2a24_x2 is + for FTGS + end for; +end CFG_oa2a2a2a24_x2_FTGS; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a2a24_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "01010111010101110101011111111111", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i4 i5 i6 i7 i0 i1 i2 i3 q", + delay_param => + ((tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_q_R, tpdi7_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(4), + Input(1) => connect(5), + Input(2) => connect(6), + Input(3) => connect(7), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Input(7) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a2a24_x4_FTGS of oa2a2a2a24_x4 is + for FTGS + end for; +end CFG_oa2a2a2a24_x4_FTGS; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a23_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "01010111", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i2 i3 i4 i5 i0 i1 q", + delay_param => + ((tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a23_x2_FTGS of oa2a2a23_x2 is + for FTGS + end for; +end CFG_oa2a2a23_x2_FTGS; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a23_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "01010111", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i2 i3 i4 i5 i0 i1 q", + delay_param => + ((tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a23_x4_FTGS of oa2a2a23_x4 is + for FTGS + end for; +end CFG_oa2a2a23_x4_FTGS; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0001000100011111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a22_x2_FTGS of oa2a22_x2 is + for FTGS + end for; +end CFG_oa2a22_x2_FTGS; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0001000100011111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a22_x4_FTGS of oa2a22_x4 is + for FTGS + end for; +end CFG_oa2a22_x4_FTGS; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2ao222_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00010101000101010001010111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_oa2ao222_x2_FTGS of oa2ao222_x2 is + for FTGS + end for; +end CFG_oa2ao222_x2_FTGS; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2ao222_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00010101000101010001010111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_oa2ao222_x4_FTGS of oa2ao222_x4 is + for FTGS + end for; +end CFG_oa2ao222_x4_FTGS; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa3ao322_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "0001010101010101" & + "0101010101010111", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 q", + delay_param => + ((tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa3ao322_x2_FTGS of oa3ao322_x2 is + for FTGS + end for; +end CFG_oa3ao322_x2_FTGS; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa3ao322_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "0001010101010101" & + "0101010101010111", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 q", + delay_param => + ((tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa3ao322_x4_FTGS of oa3ao322_x4 is + for FTGS + end for; +end CFG_oa3ao322_x4_FTGS; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01010111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa22_x2_FTGS of oa22_x2 is + for FTGS + end for; +end CFG_oa22_x2_FTGS; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01010111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa22_x4_FTGS of oa22_x4 is + for FTGS + end for; +end CFG_oa22_x4_FTGS; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of on12_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_on12_x1_FTGS of on12_x1 is + for FTGS + end for; +end CFG_on12_x1_FTGS; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of on12_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_on12_x4_FTGS of on12_x4 is + for FTGS + end for; +end CFG_on12_x4_FTGS; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity one_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + q : out STD_LOGIC := '1'); +end one_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of one_x0 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + + + +begin + + -- Netlist + q <= '1'; + +end FTGS; + +configuration CFG_one_x0_FTGS of one_x0 is + for FTGS + end for; +end CFG_one_x0_FTGS; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff1_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff1_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of sff1_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_i: constant is + "U3/constraint_param(1).Check_time"; + attribute PROPAGATE_VALUE of tsui_ck: constant is + "U3/constraint_param(0).Check_time"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is + "U3/delay_param(0)(TRAN_10), " & + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is + "U3/delay_param(0)(TRAN_01), " & + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdck_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdck_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdck_R, twdck_F, twdck_R, twdck_R, twdck_F, twdck_F)) + port map( Input => ck, Output => connect(1)); + + -- Netlist + U3 : SEQGEN + generic map( + N_enable => 0, + N_clock => 1, + N_clear => 0, + N_preset => 0, + N_data => 1, + N_cond_signal => 0, + lut_enable => "", + lut_clock => "01", + lut_clear => "", + lut_preset => "", + lut_data => "01", + TT_size_data => nil_integer_vector, + Node_Index_data => nil_integer_vector, + lut_next => "NN01NN01", + pin_names => "ck i q", + delay_param => + ((tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + constraint_param => + ((1, 0, setup_rising_ff, tsui_ck), + (0, 1, hold_rising_ff, thck_i)), + InMapZ => "XX", + Q_feedback => FALSE, + Enable_feedback => FALSE, + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + Constraint_mesg => Timing_mesg, + Constraint_xgen => Timing_xgen, + strn => strn_X01) + port map( Input(0) => connect(1), + Input(1) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_sff1_x4_FTGS of sff1_x4 is + for FTGS + end for; +end CFG_sff1_x4_FTGS; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of sff2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_cmd: constant is + "U5/constraint_param(5).Check_time"; + attribute PROPAGATE_VALUE of tsucmd_ck: constant is + "U5/constraint_param(4).Check_time"; + attribute PROPAGATE_VALUE of thck_i1: constant is + "U5/constraint_param(3).Check_time"; + attribute PROPAGATE_VALUE of tsui1_ck: constant is + "U5/constraint_param(2).Check_time"; + attribute PROPAGATE_VALUE of thck_i0: constant is + "U5/constraint_param(1).Check_time"; + attribute PROPAGATE_VALUE of tsui0_ck: constant is + "U5/constraint_param(0).Check_time"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is + "U5/delay_param(0)(TRAN_10), " & + "U5/delay_param(1)(TRAN_10), U5/delay_param(2)(TRAN_10), " & + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is + "U5/delay_param(0)(TRAN_01), " & + "U5/delay_param(1)(TRAN_01), U5/delay_param(2)(TRAN_01), " & + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdck_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdck_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdck_R, twdck_F, twdck_R, twdck_R, twdck_F, twdck_F)) + port map( Input => ck, Output => connect(3)); + + -- Netlist + U5 : SEQGEN + generic map( + N_enable => 0, + N_clock => 1, + N_clear => 0, + N_preset => 0, + N_data => 3, + N_cond_signal => 0, + lut_enable => "", + lut_clock => "01", + lut_clear => "", + lut_preset => "", + lut_data => "00011011", + TT_size_data => nil_integer_vector, + Node_Index_data => nil_integer_vector, + lut_next => "NN01NN01", + pin_names => "ck i0 i1 cmd q", + delay_param => + ((tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + constraint_param => + ((1, 0, setup_rising_ff, tsui0_ck), + (0, 1, hold_rising_ff, thck_i0), + (2, 0, setup_rising_ff, tsui1_ck), + (0, 2, hold_rising_ff, thck_i1), + (3, 0, setup_rising_ff, tsucmd_ck), + (0, 3, hold_rising_ff, thck_cmd)), + InMapZ => "XXXX", + Q_feedback => FALSE, + Enable_feedback => FALSE, + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + Constraint_mesg => Timing_mesg, + Constraint_xgen => Timing_xgen, + strn => strn_X01) + port map( Input(0) => connect(3), + Input(1) => connect(0), + Input(2) => connect(1), + Input(3) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_sff2_x4_FTGS of sff2_x4 is + for FTGS + end for; +end CFG_sff2_x4_FTGS; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ts_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z0Z1", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd q", + delay_param => + ((tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_q_R, tpdcmd_q_F, tpdcmd_q_LZ, tpdcmd_q_R, tpdcmd_q_HZ, tpdcmd_q_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_ts_x4_FTGS of ts_x4 is + for FTGS + end for; +end CFG_ts_x4_FTGS; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ts_x8 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z0Z1", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd q", + delay_param => + ((tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_q_R, tpdcmd_q_F, tpdcmd_q_LZ, tpdcmd_q_R, tpdcmd_q_HZ, tpdcmd_q_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_ts_x8_FTGS of ts_x8 is + for FTGS + end for; +end CFG_ts_x8_FTGS; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of xr2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_xr2_x1_FTGS of xr2_x1 is + for FTGS + end for; +end CFG_xr2_x1_FTGS; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of xr2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_xr2_x4_FTGS of xr2_x4 is + for FTGS + end for; +end CFG_xr2_x4_FTGS; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity zero_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + nq : out STD_LOGIC := '0'); +end zero_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of zero_x0 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + + + +begin + + -- Netlist + nq <= '0'; + +end FTGS; + +configuration CFG_zero_x0_FTGS of zero_x0 is + for FTGS + end for; +end CFG_zero_x0_FTGS; + + +---- end of library ---- diff --git a/alliance/src/cells/src/sxlib/sxlib_FTSM.vhd b/alliance/src/cells/src/sxlib/sxlib_FTSM.vhd new file mode 100644 index 00000000..f19acf59 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib_FTSM.vhd @@ -0,0 +1,11368 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_FTSM.vhd +-- FILE CONTENTS: Entity, Structural Architecture(FTSM), +-- and Configuration +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : FTSM, Timing_mesg(TRUE) +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a2_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_a2_x2_FTSM of a2_x2 is + for FTSM + end for; +end CFG_a2_x2_FTSM; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_a2_x4_FTSM of a2_x4 is + for FTSM + end for; +end CFG_a2_x4_FTSM; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a3_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_a3_x2_FTSM of a3_x2 is + for FTSM + end for; +end CFG_a3_x2_FTSM; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_a3_x4_FTSM of a3_x4 is + for FTSM + end for; +end CFG_a3_x4_FTSM; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a4_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND4MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), I3 => + prop_q(3), Y => q); + + +end FTSM; + +configuration CFG_a4_x2_FTSM of a4_x2 is + for FTSM + end for; +end CFG_a4_x2_FTSM; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND4MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), I3 => + prop_q(3), Y => q); + + +end FTSM; + +configuration CFG_a4_x4_FTSM of a4_x4 is + for FTSM + end for; +end CFG_a4_x4_FTSM; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of an12_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(1), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_an12_x1_FTSM of an12_x1 is + for FTSM + end for; +end CFG_an12_x1_FTSM; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of an12_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(1), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_an12_x4_FTSM of an12_x4 is + for FTSM + end for; +end CFG_an12_x4_FTSM; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao2o22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao2o22_x2_FTSM of ao2o22_x2 is + for FTSM + end for; +end CFG_ao2o22_x2_FTSM; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao2o22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao2o22_x4_FTSM of ao2o22_x4 is + for FTSM + end for; +end CFG_ao2o22_x4_FTSM; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND2MAC + port map( I0 => prop_q(2), I1 => n1, Y => q); + + U8 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao22_x2_FTSM of ao22_x2 is + for FTSM + end for; +end CFG_ao22_x2_FTSM; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND2MAC + port map( I0 => prop_q(2), I1 => n1, Y => q); + + U8 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao22_x4_FTSM of ao22_x4 is + for FTSM + end for; +end CFG_ao22_x4_FTSM; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of buf_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Concurrent assignments + U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(0), Output => q); + + +end FTSM; + +configuration CFG_buf_x2_FTSM of buf_x2 is + for FTSM + end for; +end CFG_buf_x2_FTSM; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of buf_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Concurrent assignments + U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(0), Output => q); + + +end FTSM; + +configuration CFG_buf_x4_FTSM of buf_x4 is + for FTSM + end for; +end CFG_buf_x4_FTSM; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of buf_x8 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Concurrent assignments + U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(0), Output => q); + + +end FTSM; + +configuration CFG_buf_x8_FTSM of buf_x8 is + for FTSM + end for; +end CFG_buf_x8_FTSM; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x1_FTSM of inv_x1 is + for FTSM + end for; +end CFG_inv_x1_FTSM; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x2_FTSM of inv_x2 is + for FTSM + end for; +end CFG_inv_x2_FTSM; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x4_FTSM of inv_x4 is + for FTSM + end for; +end CFG_inv_x4_FTSM; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x8 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x8_FTSM of inv_x8 is + for FTSM + end for; +end CFG_inv_x8_FTSM; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx2_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_q(1), I1 => prop_q(2), S0 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_mx2_x2_FTSM of mx2_x2 is + for FTSM + end for; +end CFG_mx2_x2_FTSM; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_q(1), I1 => prop_q(2), S0 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_mx2_x4_FTSM of mx2_x4 is + for FTSM + end for; +end CFG_mx2_x4_FTSM; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx3_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_q_R, tHL => tpdcmd0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_q_R, tHL => tpdcmd1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_q(4), I1 => prop_q(3), S0 => prop_q(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_q(2), I1 => n1, S0 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_mx3_x2_FTSM of mx3_x2 is + for FTSM + end for; +end CFG_mx3_x2_FTSM; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_q_R, tHL => tpdcmd0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_q_R, tHL => tpdcmd1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_q(4), I1 => prop_q(3), S0 => prop_q(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_q(2), I1 => n1, S0 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_mx3_x4_FTSM of mx3_x4 is + for FTSM + end for; +end CFG_mx3_x4_FTSM; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_na2_x1_FTSM of na2_x1 is + for FTSM + end for; +end CFG_na2_x1_FTSM; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_na2_x4_FTSM of na2_x4 is + for FTSM + end for; +end CFG_na2_x4_FTSM; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na3_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND3MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => + nq); + + +end FTSM; + +configuration CFG_na3_x1_FTSM of na3_x1 is + for FTSM + end for; +end CFG_na3_x1_FTSM; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND3MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => + nq); + + +end FTSM; + +configuration CFG_na3_x4_FTSM of na3_x4 is + for FTSM + end for; +end CFG_na3_x4_FTSM; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na4_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_na4_x1_FTSM of na4_x1 is + for FTSM + end for; +end CFG_na4_x1_FTSM; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_na4_x4_FTSM of na4_x4 is + for FTSM + end for; +end CFG_na4_x4_FTSM; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao2o22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : OR2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao2o22_x1_FTSM of nao2o22_x1 is + for FTSM + end for; +end CFG_nao2o22_x1_FTSM; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao2o22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : OR2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao2o22_x4_FTSM of nao2o22_x4 is + for FTSM + end for; +end CFG_nao2o22_x4_FTSM; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao22_x1_FTSM of nao22_x1 is + for FTSM + end for; +end CFG_nao22_x1_FTSM; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao22_x4_FTSM of nao22_x4 is + for FTSM + end for; +end CFG_nao22_x4_FTSM; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_F, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), S0 => prop_nq(0), Y => + n1); + + U8 : INVMAC + port map( I0 => n1, Y => nq); + + +end FTSM; + +configuration CFG_nmx2_x1_FTSM of nmx2_x1 is + for FTSM + end for; +end CFG_nmx2_x1_FTSM; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_F, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), S0 => prop_nq(0), Y => + n1); + + U8 : INVMAC + port map( I0 => n1, Y => nq); + + +end FTSM; + +configuration CFG_nmx2_x4_FTSM of nmx2_x4 is + for FTSM + end for; +end CFG_nmx2_x4_FTSM; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx3_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_nq_F, tHL => tpdcmd0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_nq_F, tHL => tpdcmd1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(3), S0 => prop_nq(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_nq(2), I1 => n1, S0 => prop_nq(0), Y => n2); + + U13 : INVMAC + port map( I0 => n2, Y => nq); + + +end FTSM; + +configuration CFG_nmx3_x1_FTSM of nmx3_x1 is + for FTSM + end for; +end CFG_nmx3_x1_FTSM; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_nq_F, tHL => tpdcmd0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_nq_F, tHL => tpdcmd1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(3), S0 => prop_nq(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_nq(2), I1 => n1, S0 => prop_nq(0), Y => n2); + + U13 : INVMAC + port map( I0 => n2, Y => nq); + + +end FTSM; + +configuration CFG_nmx3_x4_FTSM of nmx3_x4 is + for FTSM + end for; +end CFG_nmx3_x4_FTSM; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NOR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_no2_x1_FTSM of no2_x1 is + for FTSM + end for; +end CFG_no2_x1_FTSM; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NOR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_no2_x4_FTSM of no2_x4 is + for FTSM + end for; +end CFG_no2_x4_FTSM; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no3_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR3MAC + port map( I0 => prop_nq(2), I1 => prop_nq(0), I2 => prop_nq(1), Y => + nq); + + +end FTSM; + +configuration CFG_no3_x1_FTSM of no3_x1 is + for FTSM + end for; +end CFG_no3_x1_FTSM; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR3MAC + port map( I0 => prop_nq(2), I1 => prop_nq(0), I2 => prop_nq(1), Y => + nq); + + +end FTSM; + +configuration CFG_no3_x4_FTSM of no3_x4 is + for FTSM + end for; +end CFG_no3_x4_FTSM; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no4_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NOR4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_no4_x1_FTSM of no4_x1 is + for FTSM + end for; +end CFG_no4_x1_FTSM; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NOR4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_no4_x4_FTSM of no4_x4 is + for FTSM + end for; +end CFG_no4_x4_FTSM; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a2a24_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_nq_F, tHL => tpdi7_nq_R) + port map( Input => connect(7), Output => prop_nq(7)); + + -- Netlist + U17 : AND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U18 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_nq(6), I1 => prop_nq(7), Y => n1); + + +end FTSM; + +configuration CFG_noa2a2a2a24_x1_FTSM of noa2a2a2a24_x1 is + for FTSM + end for; +end CFG_noa2a2a2a24_x1_FTSM; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a2a24_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_nq_F, tHL => tpdi7_nq_R) + port map( Input => connect(7), Output => prop_nq(7)); + + -- Netlist + U17 : AND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U18 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_nq(6), I1 => prop_nq(7), Y => n1); + + +end FTSM; + +configuration CFG_noa2a2a2a24_x4_FTSM of noa2a2a2a24_x4 is + for FTSM + end for; +end CFG_noa2a2a2a24_x4_FTSM; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a23_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + -- Netlist + U13 : AND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U14 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n3); + + +end FTSM; + +configuration CFG_noa2a2a23_x1_FTSM of noa2a2a23_x1 is + for FTSM + end for; +end CFG_noa2a2a23_x1_FTSM; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a23_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + -- Netlist + U13 : AND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U14 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n3); + + +end FTSM; + +configuration CFG_noa2a2a23_x4_FTSM of noa2a2a23_x4 is + for FTSM + end for; +end CFG_noa2a2a23_x4_FTSM; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2a22_x1_FTSM of noa2a22_x1 is + for FTSM + end for; +end CFG_noa2a22_x1_FTSM; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2a22_x4_FTSM of noa2a22_x4 is + for FTSM + end for; +end CFG_noa2a22_x4_FTSM; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2ao222_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U12 : OR2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U13 : NAND2MAC + port map( I0 => prop_nq(4), I1 => n3, Y => n2); + + U14 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2ao222_x1_FTSM of noa2ao222_x1 is + for FTSM + end for; +end CFG_noa2ao222_x1_FTSM; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2ao222_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U12 : OR2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U13 : NAND2MAC + port map( I0 => prop_nq(4), I1 => n3, Y => n2); + + U14 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2ao222_x4_FTSM of noa2ao222_x4 is + for FTSM + end for; +end CFG_noa2ao222_x4_FTSM; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa3ao322_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + -- Netlist + U15 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U16 : NAND3MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => + n2); + + U17 : OR3MAC + port map( I0 => prop_nq(3), I1 => prop_nq(4), I2 => prop_nq(5), Y => + n3); + + U18 : NAND2MAC + port map( I0 => prop_nq(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_noa3ao322_x1_FTSM of noa3ao322_x1 is + for FTSM + end for; +end CFG_noa3ao322_x1_FTSM; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa3ao322_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + -- Netlist + U15 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U16 : NAND3MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => + n2); + + U17 : OR3MAC + port map( I0 => prop_nq(3), I1 => prop_nq(4), I2 => prop_nq(5), Y => + n3); + + U18 : NAND2MAC + port map( I0 => prop_nq(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_noa3ao322_x4_FTSM of noa3ao322_x4 is + for FTSM + end for; +end CFG_noa3ao322_x4_FTSM; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : AND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa22_x1_FTSM of noa22_x1 is + for FTSM + end for; +end CFG_noa22_x1_FTSM; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : AND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa22_x4_FTSM of noa22_x4 is + for FTSM + end for; +end CFG_noa22_x4_FTSM; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nts_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_R, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_nq_F, tHL => tpdi_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : INV3SHEMAC + port map( I0 => prop_nq(1), OE => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nts_x1_FTSM of nts_x1 is + for FTSM + end for; +end CFG_nts_x1_FTSM; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nts_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_R, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_nq_F, tHL => tpdi_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : INV3SHEMAC + port map( I0 => prop_nq(1), OE => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nts_x2_FTSM of nts_x2 is + for FTSM + end for; +end CFG_nts_x2_FTSM; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nxr2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NXOR2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nxr2_x1_FTSM of nxr2_x1 is + for FTSM + end for; +end CFG_nxr2_x1_FTSM; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nxr2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NXOR2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nxr2_x4_FTSM of nxr2_x4 is + for FTSM + end for; +end CFG_nxr2_x4_FTSM; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o2_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_o2_x2_FTSM of o2_x2 is + for FTSM + end for; +end CFG_o2_x2_FTSM; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_o2_x4_FTSM of o2_x4 is + for FTSM + end for; +end CFG_o2_x4_FTSM; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o3_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR3MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), Y => + q); + + +end FTSM; + +configuration CFG_o3_x2_FTSM of o3_x2 is + for FTSM + end for; +end CFG_o3_x2_FTSM; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR3MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), Y => + q); + + +end FTSM; + +configuration CFG_o3_x4_FTSM of o3_x4 is + for FTSM + end for; +end CFG_o3_x4_FTSM; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o4_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : OR4MAC + port map( I0 => prop_q(2), I1 => prop_q(3), I2 => prop_q(0), I3 => + prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_o4_x2_FTSM of o4_x2 is + for FTSM + end for; +end CFG_o4_x2_FTSM; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : OR4MAC + port map( I0 => prop_q(2), I1 => prop_q(3), I2 => prop_q(0), I3 => + prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_o4_x4_FTSM of o4_x4 is + for FTSM + end for; +end CFG_o4_x4_FTSM; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a2a24_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_q_R, tHL => tpdi7_q_F) + port map( Input => connect(7), Output => prop_q(7)); + + -- Netlist + U17 : NAND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => prop_q(7), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a2a2a24_x2_FTSM of oa2a2a2a24_x2 is + for FTSM + end for; +end CFG_oa2a2a2a24_x2_FTSM; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a2a24_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_q_R, tHL => tpdi7_q_F) + port map( Input => connect(7), Output => prop_q(7)); + + -- Netlist + U17 : NAND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => prop_q(7), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a2a2a24_x4_FTSM of oa2a2a2a24_x4 is + for FTSM + end for; +end CFG_oa2a2a2a24_x4_FTSM; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a23_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + -- Netlist + U13 : NAND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U14 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n3); + + +end FTSM; + +configuration CFG_oa2a2a23_x2_FTSM of oa2a2a23_x2 is + for FTSM + end for; +end CFG_oa2a2a23_x2_FTSM; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a23_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + -- Netlist + U13 : NAND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U14 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n3); + + +end FTSM; + +configuration CFG_oa2a2a23_x4_FTSM of oa2a2a23_x4 is + for FTSM + end for; +end CFG_oa2a2a23_x4_FTSM; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a22_x2_FTSM of oa2a22_x2 is + for FTSM + end for; +end CFG_oa2a22_x2_FTSM; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a22_x4_FTSM of oa2a22_x4 is + for FTSM + end for; +end CFG_oa2a22_x4_FTSM; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2ao222_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U12 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n3); + + U13 : NAND2MAC + port map( I0 => prop_q(4), I1 => n3, Y => n2); + + U14 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2ao222_x2_FTSM of oa2ao222_x2 is + for FTSM + end for; +end CFG_oa2ao222_x2_FTSM; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2ao222_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U12 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n3); + + U13 : NAND2MAC + port map( I0 => prop_q(4), I1 => n3, Y => n2); + + U14 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2ao222_x4_FTSM of oa2ao222_x4 is + for FTSM + end for; +end CFG_oa2ao222_x4_FTSM; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa3ao322_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + -- Netlist + U15 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U16 : OR3MAC + port map( I0 => prop_q(3), I1 => prop_q(4), I2 => prop_q(5), Y => + n3); + + U17 : NAND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + n2); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_oa3ao322_x2_FTSM of oa3ao322_x2 is + for FTSM + end for; +end CFG_oa3ao322_x2_FTSM; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa3ao322_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + -- Netlist + U15 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U16 : OR3MAC + port map( I0 => prop_q(3), I1 => prop_q(4), I2 => prop_q(5), Y => + n3); + + U17 : NAND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + n2); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_oa3ao322_x4_FTSM of oa3ao322_x4 is + for FTSM + end for; +end CFG_oa3ao322_x4_FTSM; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR2MAC + port map( I0 => n1, I1 => prop_q(2), Y => q); + + U8 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa22_x2_FTSM of oa22_x2 is + for FTSM + end for; +end CFG_oa22_x2_FTSM; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR2MAC + port map( I0 => n1, I1 => prop_q(2), Y => q); + + U8 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa22_x4_FTSM of oa22_x4 is + for FTSM + end for; +end CFG_oa22_x4_FTSM; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of on12_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_q(0), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_on12_x1_FTSM of on12_x1 is + for FTSM + end for; +end CFG_on12_x1_FTSM; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of on12_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_q(0), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_on12_x4_FTSM of on12_x4 is + for FTSM + end for; +end CFG_on12_x4_FTSM; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity one_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + q : out STD_LOGIC := '1'); +end one_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of one_x0 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + + +begin + + -- Netlist + q <= '1'; + +end FTSM; + +configuration CFG_one_x0_FTSM of one_x0 is + for FTSM + end for; +end CFG_one_x0_FTSM; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff1_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff1_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of sff1_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_i: constant is "FEC/F2/tHold"; + attribute PROPAGATE_VALUE of tsui_ck: constant is "FEC/F1/tSetup"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is "U3/U1/tHL"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is "U3/U1/tLH"; + attribute PROPAGATE_VALUE of twdck_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdck_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdck_R, tHL => twdck_F) + port map( Input => ck, Output => connect(1)); + + -- Netlist + U3 : DFFLMAC + generic map( tpdY_R => tpdck_q_R, tpdY_F => tpdck_q_F ) + port map( D => connect(0), CLK => connect(1), CLR => n1, Q => q); + + n1 <= '1'; + + -- Forbidden Events + FEC : if Timing_mesg generate + + F1 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsui_ck) + port map( Data(1) => connect(0), Clock => connect(1)); + + F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_i) + port map( Data(1) => connect(0), Clock => connect(1)); + + end generate FEC; + +end FTSM; + +configuration CFG_sff1_x4_FTSM of sff1_x4 is + for FTSM + end for; +end CFG_sff1_x4_FTSM; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of sff2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_cmd: constant is "FEC/F6/tHold"; + attribute PROPAGATE_VALUE of tsucmd_ck: constant is "FEC/F5/tSetup"; + attribute PROPAGATE_VALUE of thck_i1: constant is "FEC/F4/tHold"; + attribute PROPAGATE_VALUE of tsui1_ck: constant is "FEC/F3/tSetup"; + attribute PROPAGATE_VALUE of thck_i0: constant is "FEC/F2/tHold"; + attribute PROPAGATE_VALUE of tsui0_ck: constant is "FEC/F1/tSetup"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is "U6/U1/tHL"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is "U6/U1/tLH"; + attribute PROPAGATE_VALUE of twdck_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdck_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdck_R, tHL => twdck_F) + port map( Input => ck, Output => connect(3)); + + -- Netlist + U5 : MUX2MAC + port map( I0 => connect(0), I1 => connect(1), S0 => connect(2), Y => + n1); + + U6 : DFFLMAC + generic map( tpdY_R => tpdck_q_R, tpdY_F => tpdck_q_F ) + port map( D => n1, CLK => connect(3), CLR => n2, Q => q); + + n2 <= '1'; + + -- Forbidden Events + FEC : if Timing_mesg generate + + F1 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsui0_ck) + port map( Data(1) => connect(0), Clock => connect(3)); + + F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_i0) + port map( Data(1) => connect(0), Clock => connect(3)); + + F3 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsui1_ck) + port map( Data(1) => connect(1), Clock => connect(3)); + + F4 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_i1) + port map( Data(1) => connect(1), Clock => connect(3)); + + F5 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsucmd_ck) + port map( Data(1) => connect(2), Clock => connect(3)); + + F6 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_cmd) + port map( Data(1) => connect(2), Clock => connect(3)); + + end generate FEC; + +end FTSM; + +configuration CFG_sff2_x4_FTSM of sff2_x4 is + for FTSM + end for; +end CFG_sff2_x4_FTSM; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ts_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : BUF3SHEMAC + port map( I0 => prop_q(1), OE => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_ts_x4_FTSM of ts_x4 is + for FTSM + end for; +end CFG_ts_x4_FTSM; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ts_x8 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : BUF3SHEMAC + port map( I0 => prop_q(1), OE => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_ts_x8_FTSM of ts_x8 is + for FTSM + end for; +end CFG_ts_x8_FTSM; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of xr2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_F, tHL => tpdi1_q_R) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : XOR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_xr2_x1_FTSM of xr2_x1 is + for FTSM + end for; +end CFG_xr2_x1_FTSM; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of xr2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_F, tHL => tpdi1_q_R) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : XOR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_xr2_x4_FTSM of xr2_x4 is + for FTSM + end for; +end CFG_xr2_x4_FTSM; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity zero_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + nq : out STD_LOGIC := '0'); +end zero_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of zero_x0 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + + +begin + + -- Netlist + nq <= '0'; + +end FTSM; + +configuration CFG_zero_x0_FTSM of zero_x0 is + for FTSM + end for; +end CFG_zero_x0_FTSM; + + +---- end of library ---- diff --git a/alliance/src/cells/src/sxlib/sxlib_UDSM.vhd b/alliance/src/cells/src/sxlib/sxlib_UDSM.vhd new file mode 100644 index 00000000..e54da28c --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib_UDSM.vhd @@ -0,0 +1,7175 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_UDSM.vhd +-- FILE CONTENTS: Entity, Structural Architecture(UDSM), +-- and Configuration +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : UDSM +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a2_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => q); + + +end UDSM; + +configuration CFG_a2_x2_UDSM of a2_x2 is + for UDSM + end for; +end CFG_a2_x2_UDSM; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => q); + + +end UDSM; + +configuration CFG_a2_x4_UDSM of a2_x4 is + for UDSM + end for; +end CFG_a2_x4_UDSM; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a3_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => q); + + +end UDSM; + +configuration CFG_a3_x2_UDSM of a3_x2 is + for UDSM + end for; +end CFG_a3_x2_UDSM; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => q); + + +end UDSM; + +configuration CFG_a3_x4_UDSM of a3_x4 is + for UDSM + end for; +end CFG_a3_x4_UDSM; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a4_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => q); + + +end UDSM; + +configuration CFG_a4_x2_UDSM of a4_x2 is + for UDSM + end for; +end CFG_a4_x2_UDSM; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => q); + + +end UDSM; + +configuration CFG_a4_x4_UDSM of a4_x4 is + for UDSM + end for; +end CFG_a4_x4_UDSM; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of an12_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i0, Y => n1); + + +end UDSM; + +configuration CFG_an12_x1_UDSM of an12_x1 is + for UDSM + end for; +end CFG_an12_x1_UDSM; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of an12_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i0, Y => n1); + + +end UDSM; + +configuration CFG_an12_x4_UDSM of an12_x4 is + for UDSM + end for; +end CFG_an12_x4_UDSM; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao2o22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n2); + + U3 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao2o22_x2_UDSM of ao2o22_x2 is + for UDSM + end for; +end CFG_ao2o22_x2_UDSM; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao2o22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n2); + + U3 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao2o22_x4_UDSM of ao2o22_x4 is + for UDSM + end for; +end CFG_ao2o22_x4_UDSM; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => q); + + U2 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao22_x2_UDSM of ao22_x2 is + for UDSM + end for; +end CFG_ao22_x2_UDSM; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => q); + + U2 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao22_x4_UDSM of ao22_x4 is + for UDSM + end for; +end CFG_ao22_x4_UDSM; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of buf_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Concurrent assignments + U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => 1 ns, tHL => 1 ns) + port map( Input => i, Output => q); + + +end UDSM; + +configuration CFG_buf_x2_UDSM of buf_x2 is + for UDSM + end for; +end CFG_buf_x2_UDSM; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of buf_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Concurrent assignments + U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => 1 ns, tHL => 1 ns) + port map( Input => i, Output => q); + + +end UDSM; + +configuration CFG_buf_x4_UDSM of buf_x4 is + for UDSM + end for; +end CFG_buf_x4_UDSM; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of buf_x8 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Concurrent assignments + U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => 1 ns, tHL => 1 ns) + port map( Input => i, Output => q); + + +end UDSM; + +configuration CFG_buf_x8_UDSM of buf_x8 is + for UDSM + end for; +end CFG_buf_x8_UDSM; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x1_UDSM of inv_x1 is + for UDSM + end for; +end CFG_inv_x1_UDSM; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x2_UDSM of inv_x2 is + for UDSM + end for; +end CFG_inv_x2_UDSM; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x4_UDSM of inv_x4 is + for UDSM + end for; +end CFG_inv_x4_UDSM; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x8 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x8_UDSM of inv_x8 is + for UDSM + end for; +end CFG_inv_x8_UDSM; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx2_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, S0 => cmd, Y => q); + + +end UDSM; + +configuration CFG_mx2_x2_UDSM of mx2_x2 is + for UDSM + end for; +end CFG_mx2_x2_UDSM; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, S0 => cmd, Y => q); + + +end UDSM; + +configuration CFG_mx2_x4_UDSM of mx2_x4 is + for UDSM + end for; +end CFG_mx2_x4_UDSM; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx3_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => q); + + +end UDSM; + +configuration CFG_mx3_x2_UDSM of mx3_x2 is + for UDSM + end for; +end CFG_mx3_x2_UDSM; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => q); + + +end UDSM; + +configuration CFG_mx3_x4_UDSM of mx3_x4 is + for UDSM + end for; +end CFG_mx3_x4_UDSM; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_na2_x1_UDSM of na2_x1 is + for UDSM + end for; +end CFG_na2_x1_UDSM; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_na2_x4_UDSM of na2_x4 is + for UDSM + end for; +end CFG_na2_x4_UDSM; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na3_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => nq); + + +end UDSM; + +configuration CFG_na3_x1_UDSM of na3_x1 is + for UDSM + end for; +end CFG_na3_x1_UDSM; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => nq); + + +end UDSM; + +configuration CFG_na3_x4_UDSM of na3_x4 is + for UDSM + end for; +end CFG_na3_x4_UDSM; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na4_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_na4_x1_UDSM of na4_x1 is + for UDSM + end for; +end CFG_na4_x1_UDSM; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_na4_x4_UDSM of na4_x4 is + for UDSM + end for; +end CFG_na4_x4_UDSM; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao2o22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : OR2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao2o22_x1_UDSM of nao2o22_x1 is + for UDSM + end for; +end CFG_nao2o22_x1_UDSM; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao2o22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : OR2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao2o22_x4_UDSM of nao2o22_x4 is + for UDSM + end for; +end CFG_nao2o22_x4_UDSM; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao22_x1_UDSM of nao22_x1 is + for UDSM + end for; +end CFG_nao22_x1_UDSM; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao22_x4_UDSM of nao22_x4 is + for UDSM + end for; +end CFG_nao22_x4_UDSM; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); + + U2 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, Y => nq); + + +end UDSM; + +configuration CFG_nmx2_x1_UDSM of nmx2_x1 is + for UDSM + end for; +end CFG_nmx2_x1_UDSM; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); + + U2 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, Y => nq); + + +end UDSM; + +configuration CFG_nmx2_x4_UDSM of nmx2_x4 is + for UDSM + end for; +end CFG_nmx2_x4_UDSM; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx3_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => n2); + + U3 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n2, Y => nq); + + +end UDSM; + +configuration CFG_nmx3_x1_UDSM of nmx3_x1 is + for UDSM + end for; +end CFG_nmx3_x1_UDSM; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => n2); + + U3 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n2, Y => nq); + + +end UDSM; + +configuration CFG_nmx3_x4_UDSM of nmx3_x4 is + for UDSM + end for; +end CFG_nmx3_x4_UDSM; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no2_x1_UDSM of no2_x1 is + for UDSM + end for; +end CFG_no2_x1_UDSM; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no2_x4_UDSM of no2_x4 is + for UDSM + end for; +end CFG_no2_x4_UDSM; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no3_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i0, I2 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no3_x1_UDSM of no3_x1 is + for UDSM + end for; +end CFG_no3_x1_UDSM; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i0, I2 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no3_x4_UDSM of no3_x4 is + for UDSM + end for; +end CFG_no3_x4_UDSM; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no4_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_no4_x1_UDSM of no4_x1 is + for UDSM + end for; +end CFG_no4_x1_UDSM; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_no4_x4_UDSM of no4_x4 is + for UDSM + end for; +end CFG_no4_x4_UDSM; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a2a24_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U2 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n4); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U5 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n1); + + +end UDSM; + +configuration CFG_noa2a2a2a24_x1_UDSM of noa2a2a2a24_x1 is + for UDSM + end for; +end CFG_noa2a2a2a24_x1_UDSM; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a2a24_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U2 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n4); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U5 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n1); + + +end UDSM; + +configuration CFG_noa2a2a2a24_x4_UDSM of noa2a2a2a24_x4 is + for UDSM + end for; +end CFG_noa2a2a2a24_x4_UDSM; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a23_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + +end UDSM; + +configuration CFG_noa2a2a23_x1_UDSM of noa2a2a23_x1 is + for UDSM + end for; +end CFG_noa2a2a23_x1_UDSM; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a23_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + +end UDSM; + +configuration CFG_noa2a2a23_x4_UDSM of noa2a2a23_x4 is + for UDSM + end for; +end CFG_noa2a2a23_x4_UDSM; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2a22_x1_UDSM of noa2a22_x1 is + for UDSM + end for; +end CFG_noa2a22_x1_UDSM; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2a22_x4_UDSM of noa2a22_x4 is + for UDSM + end for; +end CFG_noa2a22_x4_UDSM; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2ao222_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : OR2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U3 : NAND2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2ao222_x1_UDSM of noa2ao222_x1 is + for UDSM + end for; +end CFG_noa2ao222_x1_UDSM; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2ao222_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : OR2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U3 : NAND2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2ao222_x4_UDSM of noa2ao222_x4 is + for UDSM + end for; +end CFG_noa2ao222_x4_UDSM; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa3ao322_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : NAND3MAC + port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); + + U3 : OR3MAC + port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); + + U4 : NAND2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_noa3ao322_x1_UDSM of noa3ao322_x1 is + for UDSM + end for; +end CFG_noa3ao322_x1_UDSM; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa3ao322_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : NAND3MAC + port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); + + U3 : OR3MAC + port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); + + U4 : NAND2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_noa3ao322_x4_UDSM of noa3ao322_x4 is + for UDSM + end for; +end CFG_noa3ao322_x4_UDSM; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa22_x1_UDSM of noa22_x1 is + for UDSM + end for; +end CFG_noa22_x1_UDSM; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa22_x4_UDSM of noa22_x4 is + for UDSM + end for; +end CFG_noa22_x4_UDSM; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nts_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INV3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => nq); + + +end UDSM; + +configuration CFG_nts_x1_UDSM of nts_x1 is + for UDSM + end for; +end CFG_nts_x1_UDSM; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nts_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INV3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => nq); + + +end UDSM; + +configuration CFG_nts_x2_UDSM of nts_x2 is + for UDSM + end for; +end CFG_nts_x2_UDSM; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nxr2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NXOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => nq); + + +end UDSM; + +configuration CFG_nxr2_x1_UDSM of nxr2_x1 is + for UDSM + end for; +end CFG_nxr2_x1_UDSM; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nxr2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NXOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => nq); + + +end UDSM; + +configuration CFG_nxr2_x4_UDSM of nxr2_x4 is + for UDSM + end for; +end CFG_nxr2_x4_UDSM; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o2_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_o2_x2_UDSM of o2_x2 is + for UDSM + end for; +end CFG_o2_x2_UDSM; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_o2_x4_UDSM of o2_x4 is + for UDSM + end for; +end CFG_o2_x4_UDSM; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o3_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, Y => q); + + +end UDSM; + +configuration CFG_o3_x2_UDSM of o3_x2 is + for UDSM + end for; +end CFG_o3_x2_UDSM; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, Y => q); + + +end UDSM; + +configuration CFG_o3_x4_UDSM of o3_x4 is + for UDSM + end for; +end CFG_o3_x4_UDSM; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o4_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i3, I2 => i0, I3 => i1, Y => q); + + +end UDSM; + +configuration CFG_o4_x2_UDSM of o4_x2 is + for UDSM + end for; +end CFG_o4_x2_UDSM; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i3, I2 => i0, I3 => i1, Y => q); + + +end UDSM; + +configuration CFG_o4_x4_UDSM of o4_x4 is + for UDSM + end for; +end CFG_o4_x4_UDSM; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a2a24_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U2 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n4); + + U3 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + U4 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U5 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a2a2a24_x2_UDSM of oa2a2a2a24_x2 is + for UDSM + end for; +end CFG_oa2a2a2a24_x2_UDSM; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a2a24_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U2 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n4); + + U3 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + U4 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U5 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a2a2a24_x4_UDSM of oa2a2a2a24_x4 is + for UDSM + end for; +end CFG_oa2a2a2a24_x4_UDSM; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a23_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U2 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n1); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n3); + + +end UDSM; + +configuration CFG_oa2a2a23_x2_UDSM of oa2a2a23_x2 is + for UDSM + end for; +end CFG_oa2a2a23_x2_UDSM; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a23_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U2 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n1); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n3); + + +end UDSM; + +configuration CFG_oa2a2a23_x4_UDSM of oa2a2a23_x4 is + for UDSM + end for; +end CFG_oa2a2a23_x4_UDSM; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a22_x2_UDSM of oa2a22_x2 is + for UDSM + end for; +end CFG_oa2a22_x2_UDSM; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a22_x4_UDSM of oa2a22_x4 is + for UDSM + end for; +end CFG_oa2a22_x4_UDSM; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2ao222_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n3); + + U3 : NAND2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2ao222_x2_UDSM of oa2ao222_x2 is + for UDSM + end for; +end CFG_oa2ao222_x2_UDSM; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2ao222_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n3); + + U3 : NAND2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2ao222_x4_UDSM of oa2ao222_x4 is + for UDSM + end for; +end CFG_oa2ao222_x4_UDSM; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa3ao322_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR3MAC + port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); + + U3 : NAND3MAC + port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); + + U4 : NAND2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_oa3ao322_x2_UDSM of oa3ao322_x2 is + for UDSM + end for; +end CFG_oa3ao322_x2_UDSM; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa3ao322_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR3MAC + port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); + + U3 : NAND3MAC + port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); + + U4 : NAND2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_oa3ao322_x4_UDSM of oa3ao322_x4 is + for UDSM + end for; +end CFG_oa3ao322_x4_UDSM; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => i2, Y => q); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa22_x2_UDSM of oa22_x2 is + for UDSM + end for; +end CFG_oa22_x2_UDSM; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => i2, Y => q); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa22_x4_UDSM of oa22_x4 is + for UDSM + end for; +end CFG_oa22_x4_UDSM; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of on12_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i1, Y => n1); + + +end UDSM; + +configuration CFG_on12_x1_UDSM of on12_x1 is + for UDSM + end for; +end CFG_on12_x1_UDSM; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of on12_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i1, Y => n1); + + +end UDSM; + +configuration CFG_on12_x4_UDSM of on12_x4 is + for UDSM + end for; +end CFG_on12_x4_UDSM; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity one_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + q : out STD_LOGIC := '1'); +end one_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of one_x0 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Netlist + q <= '1'; + +end UDSM; + +configuration CFG_one_x0_UDSM of one_x0 is + for UDSM + end for; +end CFG_one_x0_UDSM; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff1_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff1_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of sff1_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : DFFLMAC + generic map( tpdY_R => 2 ns, tpdY_F => 2 ns) + port map( D => i, CLK => ck, CLR => n1, Q => q); + + n1 <= '1'; + +end UDSM; + +configuration CFG_sff1_x4_UDSM of sff1_x4 is + for UDSM + end for; +end CFG_sff1_x4_UDSM; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of sff2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); + + U2 : DFFLMAC + generic map( tpdY_R => 2 ns, tpdY_F => 2 ns) + port map( D => n1, CLK => ck, CLR => n2, Q => q); + + n2 <= '1'; + +end UDSM; + +configuration CFG_sff2_x4_UDSM of sff2_x4 is + for UDSM + end for; +end CFG_sff2_x4_UDSM; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ts_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : BUF3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => q); + + +end UDSM; + +configuration CFG_ts_x4_UDSM of ts_x4 is + for UDSM + end for; +end CFG_ts_x4_UDSM; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ts_x8 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : BUF3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => q); + + +end UDSM; + +configuration CFG_ts_x8_UDSM of ts_x8 is + for UDSM + end for; +end CFG_ts_x8_UDSM; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of xr2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : XOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_xr2_x1_UDSM of xr2_x1 is + for UDSM + end for; +end CFG_xr2_x1_UDSM; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of xr2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : XOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_xr2_x4_UDSM of xr2_x4 is + for UDSM + end for; +end CFG_xr2_x4_UDSM; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity zero_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + nq : out STD_LOGIC := '0'); +end zero_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of zero_x0 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Netlist + nq <= '0'; + +end UDSM; + +configuration CFG_zero_x0_UDSM of zero_x0 is + for UDSM + end for; +end CFG_zero_x0_UDSM; + + +---- end of library ---- diff --git a/alliance/src/cells/src/sxlib/sxlib_VITAL.vhd b/alliance/src/cells/src/sxlib/sxlib_VITAL.vhd new file mode 100644 index 00000000..c6203b0b --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib_VITAL.vhd @@ -0,0 +1,8941 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_VITAL.vhd +-- FILE CONTENTS: Entity, Structural Architecture(VITAL), +-- and Configuration +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : VITAL, TimingChecksOn(TRUE), XGenerationOn(FALSE), TimingMessage(TRUE), OnDetect +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a2_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.261 ns, 0.388 ns); + tpd_i1_q : VitalDelayType01 := (0.203 ns, 0.434 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a2_x2 : entity is TRUE; +end a2_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a2_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a2_x2_VITAL of a2_x2 is + for VITAL + end for; +end CFG_a2_x2_VITAL; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.338 ns, 0.476 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a2_x4 : entity is TRUE; +end a2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a2_x4_VITAL of a2_x4 is + for VITAL + end for; +end CFG_a2_x4_VITAL; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a3_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.395 ns, 0.435 ns); + tpd_i1_q : VitalDelayType01 := (0.353 ns, 0.479 ns); + tpd_i2_q : VitalDelayType01 := (0.290 ns, 0.521 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a3_x2 : entity is TRUE; +end a3_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a3_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a3_x2_VITAL of a3_x2 is + for VITAL + end for; +end CFG_a3_x2_VITAL; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.478 ns, 0.514 ns); + tpd_i1_q : VitalDelayType01 := (0.428 ns, 0.554 ns); + tpd_i2_q : VitalDelayType01 := (0.356 ns, 0.592 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a3_x4 : entity is TRUE; +end a3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a3_x4_VITAL of a3_x4 is + for VITAL + end for; +end CFG_a3_x4_VITAL; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a4_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.374 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.441 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.482 ns, 0.498 ns); + tpd_i3_q : VitalDelayType01 := (0.506 ns, 0.455 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a4_x2 : entity is TRUE; +end a4_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a4_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd) AND (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a4_x2_VITAL of a4_x2 is + for VITAL + end for; +end CFG_a4_x2_VITAL; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.505 ns, 0.650 ns); + tpd_i1_q : VitalDelayType01 := (0.578 ns, 0.614 ns); + tpd_i2_q : VitalDelayType01 := (0.627 ns, 0.576 ns); + tpd_i3_q : VitalDelayType01 := (0.661 ns, 0.538 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a4_x4 : entity is TRUE; +end a4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd) AND (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a4_x4_VITAL of a4_x4 is + for VITAL + end for; +end CFG_a4_x4_VITAL; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity an12_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.200 ns, 0.168 ns); + tpd_i1_q : VitalDelayType01 := (0.285 ns, 0.405 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of an12_x1 : entity is TRUE; +end an12_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of an12_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_an12_x1_VITAL of an12_x1 is + for VITAL + end for; +end CFG_an12_x1_VITAL; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity an12_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.461 ns, 0.471 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of an12_x4 : entity is TRUE; +end an12_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of an12_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_an12_x4_VITAL of an12_x4 is + for VITAL + end for; +end CFG_an12_x4_VITAL; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao2o22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.572 ns, 0.451 ns); + tpd_i1_q : VitalDelayType01 := (0.508 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.432 ns, 0.627 ns); + tpd_i3_q : VitalDelayType01 := (0.488 ns, 0.526 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao2o22_x2 : entity is TRUE; +end ao2o22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao2o22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) OR (i2_ipd)) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao2o22_x2_VITAL of ao2o22_x2 is + for VITAL + end for; +end CFG_ao2o22_x2_VITAL; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao2o22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.696 ns, 0.569 ns); + tpd_i1_q : VitalDelayType01 := (0.637 ns, 0.666 ns); + tpd_i2_q : VitalDelayType01 := (0.554 ns, 0.744 ns); + tpd_i3_q : VitalDelayType01 := (0.606 ns, 0.639 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao2o22_x4 : entity is TRUE; +end ao2o22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao2o22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) OR (i2_ipd)) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao2o22_x4_VITAL of ao2o22_x4 is + for VITAL + end for; +end CFG_ao2o22_x4_VITAL; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.558 ns, 0.447 ns); + tpd_i1_q : VitalDelayType01 := (0.493 ns, 0.526 ns); + tpd_i2_q : VitalDelayType01 := (0.420 ns, 0.425 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao22_x2 : entity is TRUE; +end ao22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao22_x2_VITAL of ao22_x2 is + for VITAL + end for; +end CFG_ao22_x2_VITAL; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.674 ns, 0.552 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i2_q : VitalDelayType01 := (0.526 ns, 0.505 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao22_x4 : entity is TRUE; +end ao22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao22_x4_VITAL of ao22_x4 is + for VITAL + end for; +end CFG_ao22_x4_VITAL; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity buf_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_q : VitalDelayType01 := (0.409 ns, 0.391 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of buf_x2 : entity is TRUE; +end buf_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of buf_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := TO_X01(i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_buf_x2_VITAL of buf_x2 is + for VITAL + end for; +end CFG_buf_x2_VITAL; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity buf_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_q : VitalDelayType01 := (0.379 ns, 0.409 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of buf_x4 : entity is TRUE; +end buf_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of buf_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := TO_X01(i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_buf_x4_VITAL of buf_x4 is + for VITAL + end for; +end CFG_buf_x4_VITAL; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity buf_x8 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_q : VitalDelayType01 := (0.343 ns, 0.396 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of buf_x8 : entity is TRUE; +end buf_x8; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of buf_x8 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := TO_X01(i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_buf_x8_VITAL of buf_x8 is + for VITAL + end for; +end CFG_buf_x8_VITAL; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.101 ns, 0.139 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x1 : entity is TRUE; +end inv_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x1_VITAL of inv_x1 is + for VITAL + end for; +end CFG_inv_x1_VITAL; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.069 ns, 0.163 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x2 : entity is TRUE; +end inv_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x2_VITAL of inv_x2 is + for VITAL + end for; +end CFG_inv_x2_VITAL; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.071 ns, 0.143 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x4 : entity is TRUE; +end inv_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x4_VITAL of inv_x4 is + for VITAL + end for; +end CFG_inv_x4_VITAL; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x8 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.086 ns, 0.133 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x8 : entity is TRUE; +end inv_x8; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x8 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x8_VITAL of inv_x8 is + for VITAL + end for; +end CFG_inv_x8_VITAL; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx2_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01 := (0.484 ns, 0.522 ns); + tpd_i0_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tpd_i1_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx2_x2 : entity is TRUE; +end mx2_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx2_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_q, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx2_x2_VITAL of mx2_x2 is + for VITAL + end for; +end CFG_mx2_x2_VITAL; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i0_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tpd_i1_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx2_x4 : entity is TRUE; +end mx2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_q, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx2_x4_VITAL of mx2_x4 is + for VITAL + end for; +end CFG_mx2_x4_VITAL; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx3_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_q : VitalDelayType01 := (0.573 ns, 0.680 ns); + tpd_cmd1_q : VitalDelayType01 := (0.664 ns, 0.817 ns); + tpd_i0_q : VitalDelayType01 := (0.538 ns, 0.658 ns); + tpd_i1_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tpd_i2_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx3_x2 : entity is TRUE; +end mx3_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx3_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_q, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_q, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx3_x2_VITAL of mx3_x2 is + for VITAL + end for; +end CFG_mx3_x2_VITAL; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_q : VitalDelayType01 := (0.683 ns, 0.779 ns); + tpd_cmd1_q : VitalDelayType01 := (0.792 ns, 0.967 ns); + tpd_i0_q : VitalDelayType01 := (0.640 ns, 0.774 ns); + tpd_i1_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tpd_i2_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx3_x4 : entity is TRUE; +end mx3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_q, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_q, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx3_x4_VITAL of mx3_x4 is + for VITAL + end for; +end CFG_mx3_x4_VITAL; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.059 ns, 0.288 ns); + tpd_i1_nq : VitalDelayType01 := (0.111 ns, 0.234 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na2_x1 : entity is TRUE; +end na2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na2_x1_VITAL of na2_x1 is + for VITAL + end for; +end CFG_na2_x1_VITAL; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.412 ns, 0.552 ns); + tpd_i1_nq : VitalDelayType01 := (0.353 ns, 0.601 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na2_x4 : entity is TRUE; +end na2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na2_x4_VITAL of na2_x4 is + for VITAL + end for; +end CFG_na2_x4_VITAL; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na3_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.119 ns, 0.363 ns); + tpd_i1_nq : VitalDelayType01 := (0.171 ns, 0.316 ns); + tpd_i2_nq : VitalDelayType01 := (0.193 ns, 0.265 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na3_x1 : entity is TRUE; +end na3_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na3_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na3_x1_VITAL of na3_x1 is + for VITAL + end for; +end CFG_na3_x1_VITAL; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.556 ns, 0.601 ns); + tpd_i1_nq : VitalDelayType01 := (0.460 ns, 0.691 ns); + tpd_i2_nq : VitalDelayType01 := (0.519 ns, 0.647 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na3_x4 : entity is TRUE; +end na3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na3_x4_VITAL of na3_x4 is + for VITAL + end for; +end CFG_na3_x4_VITAL; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na4_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.179 ns, 0.438 ns); + tpd_i1_nq : VitalDelayType01 := (0.237 ns, 0.395 ns); + tpd_i2_nq : VitalDelayType01 := (0.269 ns, 0.350 ns); + tpd_i3_nq : VitalDelayType01 := (0.282 ns, 0.302 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na4_x1 : entity is TRUE; +end na4_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na4_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)) OR ((NOT i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na4_x1_VITAL of na4_x1 is + for VITAL + end for; +end CFG_na4_x1_VITAL; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.578 ns, 0.771 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.731 ns); + tpd_i2_nq : VitalDelayType01 := (0.681 ns, 0.689 ns); + tpd_i3_nq : VitalDelayType01 := (0.703 ns, 0.644 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na4_x4 : entity is TRUE; +end na4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)) OR ((NOT i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na4_x4_VITAL of na4_x4 is + for VITAL + end for; +end CFG_na4_x4_VITAL; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao2o22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.237 ns, 0.307 ns); + tpd_i3_nq : VitalDelayType01 := (0.174 ns, 0.382 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao2o22_x1 : entity is TRUE; +end nao2o22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao2o22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) AND ((NOT i2_ipd))) OR (((NOT i1_ipd)) AND ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao2o22_x1_VITAL of nao2o22_x1 is + for VITAL + end for; +end CFG_nao2o22_x1_VITAL; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao2o22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.734 ns, 0.644 ns); + tpd_i1_nq : VitalDelayType01 := (0.666 ns, 0.717 ns); + tpd_i2_nq : VitalDelayType01 := (0.664 ns, 0.721 ns); + tpd_i3_nq : VitalDelayType01 := (0.607 ns, 0.807 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao2o22_x4 : entity is TRUE; +end nao2o22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao2o22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) AND ((NOT i2_ipd))) OR (((NOT i1_ipd)) AND ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao2o22_x4_VITAL of nao2o22_x4 is + for VITAL + end for; +end CFG_nao2o22_x4_VITAL; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.165 ns, 0.238 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao22_x1 : entity is TRUE; +end nao22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) OR (((NOT i1_ipd)) AND ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao22_x1_VITAL of nao22_x1 is + for VITAL + end for; +end CFG_nao22_x1_VITAL; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.732 ns, 0.650 ns); + tpd_i1_nq : VitalDelayType01 := (0.664 ns, 0.723 ns); + tpd_i2_nq : VitalDelayType01 := (0.596 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao22_x4 : entity is TRUE; +end nao22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) OR (((NOT i1_ipd)) AND ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao22_x4_VITAL of nao22_x4 is + for VITAL + end for; +end CFG_nao22_x4_VITAL; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i0_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tpd_i1_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx2_x1 : entity is TRUE; +end nmx2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_nq, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx2_x1_VITAL of nmx2_x1 is + for VITAL + end for; +end CFG_nmx2_x1_VITAL; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01 := (0.632 ns, 0.708 ns); + tpd_i0_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tpd_i1_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx2_x4 : entity is TRUE; +end nmx2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_nq, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx2_x4_VITAL of nmx2_x4 is + for VITAL + end for; +end CFG_nmx2_x4_VITAL; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx3_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_nq : VitalDelayType01 := (0.356 ns, 0.495 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.414 ns, 0.566 ns); + tpd_i0_nq : VitalDelayType01 := (0.315 ns, 0.441 ns); + tpd_i1_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tpd_i2_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx3_x1 : entity is TRUE; +end nmx3_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx3_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_nq, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_nq, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx3_x1_VITAL of nmx3_x1 is + for VITAL + end for; +end CFG_nmx3_x1_VITAL; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_nq : VitalDelayType01 := (0.790 ns, 0.936 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.866 ns, 1.048 ns); + tpd_i0_nq : VitalDelayType01 := (0.748 ns, 0.900 ns); + tpd_i1_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tpd_i2_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx3_x4 : entity is TRUE; +end nmx3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_nq, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_nq, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx3_x4_VITAL of nmx3_x4 is + for VITAL + end for; +end CFG_nmx3_x4_VITAL; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.298 ns, 0.121 ns); + tpd_i1_nq : VitalDelayType01 := (0.193 ns, 0.161 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no2_x1 : entity is TRUE; +end no2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no2_x1_VITAL of no2_x1 is + for VITAL + end for; +end CFG_no2_x1_VITAL; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.618 ns, 0.447 ns); + tpd_i1_nq : VitalDelayType01 := (0.522 ns, 0.504 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no2_x4 : entity is TRUE; +end no2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no2_x4_VITAL of no2_x4 is + for VITAL + end for; +end CFG_no2_x4_VITAL; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no3_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.318 ns, 0.246 ns); + tpd_i1_nq : VitalDelayType01 := (0.215 ns, 0.243 ns); + tpd_i2_nq : VitalDelayType01 := (0.407 ns, 0.192 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no3_x1 : entity is TRUE; +end no3_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no3_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no3_x1_VITAL of no3_x1 is + for VITAL + end for; +end CFG_no3_x1_VITAL; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.722 ns, 0.561 ns); + tpd_i1_nq : VitalDelayType01 := (0.638 ns, 0.623 ns); + tpd_i2_nq : VitalDelayType01 := (0.545 ns, 0.640 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no3_x4 : entity is TRUE; +end no3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no3_x4_VITAL of no3_x4 is + for VITAL + end for; +end CFG_no3_x4_VITAL; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no4_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.330 ns, 0.340 ns); + tpd_i1_nq : VitalDelayType01 := (0.230 ns, 0.320 ns); + tpd_i2_nq : VitalDelayType01 := (0.419 ns, 0.333 ns); + tpd_i3_nq : VitalDelayType01 := (0.499 ns, 0.271 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no4_x1 : entity is TRUE; +end no4_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no4_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)) AND ((NOT + i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no4_x1_VITAL of no4_x1 is + for VITAL + end for; +end CFG_no4_x1_VITAL; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.656 ns, 0.777 ns); + tpd_i1_nq : VitalDelayType01 := (0.564 ns, 0.768 ns); + tpd_i2_nq : VitalDelayType01 := (0.739 ns, 0.761 ns); + tpd_i3_nq : VitalDelayType01 := (0.816 ns, 0.693 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no4_x4 : entity is TRUE; +end no4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)) AND ((NOT + i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no4_x4_VITAL of no4_x4 is + for VITAL + end for; +end CFG_no4_x4_VITAL; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.649 ns, 0.606 ns); + tpd_i1_nq : VitalDelayType01 := (0.775 ns, 0.562 ns); + tpd_i2_nq : VitalDelayType01 := (0.550 ns, 0.662 ns); + tpd_i3_nq : VitalDelayType01 := (0.667 ns, 0.616 ns); + tpd_i4_nq : VitalDelayType01 := (0.419 ns, 0.613 ns); + tpd_i5_nq : VitalDelayType01 := (0.329 ns, 0.662 ns); + tpd_i6_nq : VitalDelayType01 := (0.270 ns, 0.535 ns); + tpd_i7_nq : VitalDelayType01 := (0.200 ns, 0.591 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a2a24_x1 : entity is TRUE; +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a2a24_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))) AND (((NOT i7_ipd)) + OR ((NOT i6_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a2a24_x1_VITAL of noa2a2a2a24_x1 is + for VITAL + end for; +end CFG_noa2a2a2a24_x1_VITAL; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.966 ns, 1.049 ns); + tpd_i1_nq : VitalDelayType01 := (1.097 ns, 1.005 ns); + tpd_i2_nq : VitalDelayType01 := (0.867 ns, 1.106 ns); + tpd_i3_nq : VitalDelayType01 := (0.990 ns, 1.061 ns); + tpd_i4_nq : VitalDelayType01 := (0.748 ns, 1.061 ns); + tpd_i5_nq : VitalDelayType01 := (0.649 ns, 1.109 ns); + tpd_i6_nq : VitalDelayType01 := (0.606 ns, 0.999 ns); + tpd_i7_nq : VitalDelayType01 := (0.525 ns, 1.052 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a2a24_x4 : entity is TRUE; +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a2a24_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))) AND (((NOT i7_ipd)) + OR ((NOT i6_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a2a24_x4_VITAL of noa2a2a2a24_x4 is + for VITAL + end for; +end CFG_noa2a2a2a24_x4_VITAL; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.525 ns, 0.425 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.388 ns); + tpd_i2_nq : VitalDelayType01 := (0.307 ns, 0.479 ns); + tpd_i3_nq : VitalDelayType01 := (0.398 ns, 0.438 ns); + tpd_i4_nq : VitalDelayType01 := (0.250 ns, 0.416 ns); + tpd_i5_nq : VitalDelayType01 := (0.178 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a23_x1 : entity is TRUE; +end noa2a2a23_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a23_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a23_x1_VITAL of noa2a2a23_x1 is + for VITAL + end for; +end CFG_noa2a2a23_x1_VITAL; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.834 ns, 0.814 ns); + tpd_i1_nq : VitalDelayType01 := (0.955 ns, 0.778 ns); + tpd_i2_nq : VitalDelayType01 := (0.620 ns, 0.873 ns); + tpd_i3_nq : VitalDelayType01 := (0.716 ns, 0.833 ns); + tpd_i4_nq : VitalDelayType01 := (0.574 ns, 0.819 ns); + tpd_i5_nq : VitalDelayType01 := (0.496 ns, 0.865 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a23_x4 : entity is TRUE; +end noa2a2a23_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a23_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a23_x4_VITAL of noa2a2a23_x4 is + for VITAL + end for; +end CFG_noa2a2a23_x4_VITAL; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.284 ns, 0.289 ns); + tpd_i3_nq : VitalDelayType01 := (0.372 ns, 0.256 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a22_x1 : entity is TRUE; +end noa2a22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a22_x1_VITAL of noa2a22_x1 is + for VITAL + end for; +end CFG_noa2a22_x1_VITAL; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.562 ns, 0.745 ns); + tpd_i1_nq : VitalDelayType01 := (0.646 ns, 0.714 ns); + tpd_i2_nq : VitalDelayType01 := (0.701 ns, 0.703 ns); + tpd_i3_nq : VitalDelayType01 := (0.805 ns, 0.677 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a22_x4 : entity is TRUE; +end noa2a22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a22_x4_VITAL of noa2a22_x4 is + for VITAL + end for; +end CFG_noa2a22_x4_VITAL; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.348 ns, 0.422 ns); + tpd_i1_nq : VitalDelayType01 := (0.440 ns, 0.378 ns); + tpd_i2_nq : VitalDelayType01 := (0.186 ns, 0.473 ns); + tpd_i3_nq : VitalDelayType01 := (0.256 ns, 0.459 ns); + tpd_i4_nq : VitalDelayType01 := (0.240 ns, 0.309 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2ao222_x1 : entity is TRUE; +end noa2ao222_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2ao222_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i4_ipd)) OR (((NOT i3_ipd)) AND ((NOT i2_ipd)))) AND (((NOT + i1_ipd)) OR ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2ao222_x1_VITAL of noa2ao222_x1 is + for VITAL + end for; +end CFG_noa2ao222_x1_VITAL; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.684 ns, 0.801 ns); + tpd_i1_nq : VitalDelayType01 := (0.780 ns, 0.758 ns); + tpd_i2_nq : VitalDelayType01 := (0.638 ns, 0.809 ns); + tpd_i3_nq : VitalDelayType01 := (0.732 ns, 0.795 ns); + tpd_i4_nq : VitalDelayType01 := (0.718 ns, 0.664 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2ao222_x4 : entity is TRUE; +end noa2ao222_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2ao222_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i4_ipd)) OR (((NOT i3_ipd)) AND ((NOT i2_ipd)))) AND (((NOT + i1_ipd)) OR ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2ao222_x4_VITAL of noa2ao222_x4 is + for VITAL + end for; +end CFG_noa2ao222_x4_VITAL; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.396 ns, 0.616 ns); + tpd_i1_nq : VitalDelayType01 := (0.486 ns, 0.552 ns); + tpd_i2_nq : VitalDelayType01 := (0.546 ns, 0.488 ns); + tpd_i3_nq : VitalDelayType01 := (0.196 ns, 0.599 ns); + tpd_i4_nq : VitalDelayType01 := (0.264 ns, 0.608 ns); + tpd_i5_nq : VitalDelayType01 := (0.328 ns, 0.581 ns); + tpd_i6_nq : VitalDelayType01 := (0.246 ns, 0.311 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa3ao322_x1 : entity is TRUE; +end noa3ao322_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa3ao322_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i6_ipd)) OR (((NOT i4_ipd)) AND ((NOT i3_ipd)) AND ((NOT + i5_ipd)))) AND (((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa3ao322_x1_VITAL of noa3ao322_x1 is + for VITAL + end for; +end CFG_noa3ao322_x1_VITAL; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.819 ns, 0.987 ns); + tpd_i1_nq : VitalDelayType01 := (0.914 ns, 0.931 ns); + tpd_i2_nq : VitalDelayType01 := (0.990 ns, 0.874 ns); + tpd_i3_nq : VitalDelayType01 := (0.729 ns, 0.926 ns); + tpd_i4_nq : VitalDelayType01 := (0.821 ns, 0.924 ns); + tpd_i5_nq : VitalDelayType01 := (0.907 ns, 0.900 ns); + tpd_i6_nq : VitalDelayType01 := (0.738 ns, 0.718 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa3ao322_x4 : entity is TRUE; +end noa3ao322_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa3ao322_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i6_ipd)) OR (((NOT i4_ipd)) AND ((NOT i3_ipd)) AND ((NOT + i5_ipd)))) AND (((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa3ao322_x4_VITAL of noa3ao322_x4 is + for VITAL + end for; +end CFG_noa3ao322_x4_VITAL; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.218 ns, 0.241 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa22_x1 : entity is TRUE; +end noa22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) AND (((NOT i1_ipd)) OR ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa22_x1_VITAL of noa22_x1 is + for VITAL + end for; +end CFG_noa22_x1_VITAL; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.550 ns, 0.740 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.709 ns); + tpd_i2_nq : VitalDelayType01 := (0.610 ns, 0.646 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa22_x4 : entity is TRUE; +end noa22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) AND (((NOT i1_ipd)) OR ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa22_x4_VITAL of noa22_x4 is + for VITAL + end for; +end CFG_noa22_x4_VITAL; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nts_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01z := + (0.249 ns, 0.041 ns, 0.249 ns, 0.249 ns, 0.041 ns, 0.041 ns); + tpd_i_nq : VitalDelayType01 := (0.169 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nts_x1 : entity is TRUE; +end nts_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nts_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalBUFIF0 (data => (NOT i_ipd), + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_nq), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_nq), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_nts_x1_VITAL of nts_x1 is + for VITAL + end for; +end CFG_nts_x1_VITAL; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nts_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01z := + (0.330 ns, 0.033 ns, 0.330 ns, 0.330 ns, 0.033 ns, 0.033 ns); + tpd_i_nq : VitalDelayType01 := (0.167 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nts_x2 : entity is TRUE; +end nts_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nts_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalBUFIF0 (data => (NOT i_ipd), + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_nq), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_nq), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_nts_x2_VITAL of nts_x2 is + for VITAL + end for; +end CFG_nts_x2_VITAL; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nxr2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.288 ns, 0.293 ns); + tpd_i1_nq : VitalDelayType01 := (0.156 ns, 0.327 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nxr2_x1 : entity is TRUE; +end nxr2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nxr2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (i1_ipd) XOR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nxr2_x1_VITAL of nxr2_x1 is + for VITAL + end for; +end CFG_nxr2_x1_VITAL; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nxr2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.522 ns, 0.553 ns); + tpd_i1_nq : VitalDelayType01 := (0.553 ns, 0.542 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nxr2_x4 : entity is TRUE; +end nxr2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nxr2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (i1_ipd) XOR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nxr2_x4_VITAL of nxr2_x4 is + for VITAL + end for; +end CFG_nxr2_x4_VITAL; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o2_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.406 ns, 0.310 ns); + tpd_i1_q : VitalDelayType01 := (0.335 ns, 0.364 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o2_x2 : entity is TRUE; +end o2_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o2_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o2_x2_VITAL of o2_x2 is + for VITAL + end for; +end CFG_o2_x2_VITAL; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tpd_i1_q : VitalDelayType01 := (0.427 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o2_x4 : entity is TRUE; +end o2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o2_x4_VITAL of o2_x4 is + for VITAL + end for; +end CFG_o2_x4_VITAL; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o3_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.494 ns, 0.407 ns); + tpd_i1_q : VitalDelayType01 := (0.430 ns, 0.482 ns); + tpd_i2_q : VitalDelayType01 := (0.360 ns, 0.506 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o3_x2 : entity is TRUE; +end o3_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o3_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o3_x2_VITAL of o3_x2 is + for VITAL + end for; +end CFG_o3_x2_VITAL; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.569 ns, 0.501 ns); + tpd_i1_q : VitalDelayType01 := (0.510 ns, 0.585 ns); + tpd_i2_q : VitalDelayType01 := (0.447 ns, 0.622 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o3_x4 : entity is TRUE; +end o3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o3_x4_VITAL of o3_x4 is + for VITAL + end for; +end CFG_o3_x4_VITAL; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o4_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.508 ns, 0.601 ns); + tpd_i1_q : VitalDelayType01 := (0.446 ns, 0.631 ns); + tpd_i2_q : VitalDelayType01 := (0.567 ns, 0.531 ns); + tpd_i3_q : VitalDelayType01 := (0.378 ns, 0.626 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o4_x2 : entity is TRUE; +end o4_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o4_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd) OR (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o4_x2_VITAL of o4_x2 is + for VITAL + end for; +end CFG_o4_x2_VITAL; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.574 ns, 0.638 ns); + tpd_i1_q : VitalDelayType01 := (0.492 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.649 ns, 0.611 ns); + tpd_i3_q : VitalDelayType01 := (0.721 ns, 0.536 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o4_x4 : entity is TRUE; +end o4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd) OR (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o4_x4_VITAL of o4_x4 is + for VITAL + end for; +end CFG_o4_x4_VITAL; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.780 ns, 0.797 ns); + tpd_i1_q : VitalDelayType01 := (0.909 ns, 0.753 ns); + tpd_i2_q : VitalDelayType01 := (0.682 ns, 0.856 ns); + tpd_i3_q : VitalDelayType01 := (0.803 ns, 0.810 ns); + tpd_i4_q : VitalDelayType01 := (0.565 ns, 0.813 ns); + tpd_i5_q : VitalDelayType01 := (0.467 ns, 0.861 ns); + tpd_i6_q : VitalDelayType01 := (0.426 ns, 0.748 ns); + tpd_i7_q : VitalDelayType01 := (0.346 ns, 0.800 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a2a24_x2 : entity is TRUE; +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a2a24_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)) OR ((i7_ipd) AND (i6_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a2a24_x2_VITAL of oa2a2a2a24_x2 is + for VITAL + end for; +end CFG_oa2a2a2a24_x2_VITAL; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.823 ns, 0.879 ns); + tpd_i1_q : VitalDelayType01 := (0.955 ns, 0.835 ns); + tpd_i2_q : VitalDelayType01 := (0.726 ns, 0.940 ns); + tpd_i3_q : VitalDelayType01 := (0.851 ns, 0.895 ns); + tpd_i4_q : VitalDelayType01 := (0.619 ns, 0.902 ns); + tpd_i5_q : VitalDelayType01 := (0.515 ns, 0.949 ns); + tpd_i6_q : VitalDelayType01 := (0.487 ns, 0.845 ns); + tpd_i7_q : VitalDelayType01 := (0.399 ns, 0.895 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a2a24_x4 : entity is TRUE; +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a2a24_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)) OR ((i7_ipd) AND (i6_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a2a24_x4_VITAL of oa2a2a2a24_x4 is + for VITAL + end for; +end CFG_oa2a2a2a24_x4_VITAL; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.653 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.775 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.441 ns, 0.639 ns); + tpd_i3_q : VitalDelayType01 := (0.540 ns, 0.600 ns); + tpd_i4_q : VitalDelayType01 := (0.402 ns, 0.591 ns); + tpd_i5_q : VitalDelayType01 := (0.321 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a23_x2 : entity is TRUE; +end oa2a2a23_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a23_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a23_x2_VITAL of oa2a2a23_x2 is + for VITAL + end for; +end CFG_oa2a2a23_x2_VITAL; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.699 ns, 0.648 ns); + tpd_i1_q : VitalDelayType01 := (0.822 ns, 0.613 ns); + tpd_i2_q : VitalDelayType01 := (0.493 ns, 0.715 ns); + tpd_i3_q : VitalDelayType01 := (0.594 ns, 0.677 ns); + tpd_i4_q : VitalDelayType01 := (0.464 ns, 0.673 ns); + tpd_i5_q : VitalDelayType01 := (0.379 ns, 0.714 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a23_x4 : entity is TRUE; +end oa2a2a23_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a23_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a23_x4_VITAL of oa2a2a23_x4 is + for VITAL + end for; +end CFG_oa2a2a23_x4_VITAL; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.403 ns, 0.564 ns); + tpd_i1_q : VitalDelayType01 := (0.495 ns, 0.534 ns); + tpd_i2_q : VitalDelayType01 := (0.646 ns, 0.487 ns); + tpd_i3_q : VitalDelayType01 := (0.537 ns, 0.512 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a22_x2 : entity is TRUE; +end oa2a22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a22_x2_VITAL of oa2a22_x2 is + for VITAL + end for; +end CFG_oa2a22_x2_VITAL; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.519 ns, 0.696 ns); + tpd_i1_q : VitalDelayType01 := (0.624 ns, 0.669 ns); + tpd_i2_q : VitalDelayType01 := (0.763 ns, 0.596 ns); + tpd_i3_q : VitalDelayType01 := (0.644 ns, 0.619 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a22_x4 : entity is TRUE; +end oa2a22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a22_x4_VITAL of oa2a22_x4 is + for VITAL + end for; +end CFG_oa2a22_x4_VITAL; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.495 ns, 0.581 ns); + tpd_i1_q : VitalDelayType01 := (0.598 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.464 ns, 0.604 ns); + tpd_i3_q : VitalDelayType01 := (0.556 ns, 0.578 ns); + tpd_i4_q : VitalDelayType01 := (0.558 ns, 0.453 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2ao222_x2 : entity is TRUE; +end oa2ao222_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2ao222_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i3_ipd) OR (i2_ipd)) AND (i4_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2ao222_x2_VITAL of oa2ao222_x2 is + for VITAL + end for; +end CFG_oa2ao222_x2_VITAL; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.553 ns, 0.657 ns); + tpd_i1_q : VitalDelayType01 := (0.662 ns, 0.616 ns); + tpd_i2_q : VitalDelayType01 := (0.552 ns, 0.693 ns); + tpd_i3_q : VitalDelayType01 := (0.640 ns, 0.660 ns); + tpd_i4_q : VitalDelayType01 := (0.656 ns, 0.529 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2ao222_x4 : entity is TRUE; +end oa2ao222_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2ao222_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i3_ipd) OR (i2_ipd)) AND (i4_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2ao222_x4_VITAL of oa2ao222_x4 is + for VITAL + end for; +end CFG_oa2ao222_x4_VITAL; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.638 ns, 0.820 ns); + tpd_i1_q : VitalDelayType01 := (0.735 ns, 0.764 ns); + tpd_i2_q : VitalDelayType01 := (0.806 ns, 0.707 ns); + tpd_i3_q : VitalDelayType01 := (0.560 ns, 0.765 ns); + tpd_i4_q : VitalDelayType01 := (0.649 ns, 0.760 ns); + tpd_i5_q : VitalDelayType01 := (0.734 ns, 0.734 ns); + tpd_i6_q : VitalDelayType01 := (0.563 ns, 0.540 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa3ao322_x2 : entity is TRUE; +end oa3ao322_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa3ao322_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i4_ipd) OR (i3_ipd) OR (i5_ipd)) AND (i6_ipd)) OR ((i1_ipd) AND + (i0_ipd) AND (i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa3ao322_x2_VITAL of oa3ao322_x2 is + for VITAL + end for; +end CFG_oa3ao322_x2_VITAL; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.717 ns, 0.946 ns); + tpd_i1_q : VitalDelayType01 := (0.818 ns, 0.890 ns); + tpd_i2_q : VitalDelayType01 := (0.894 ns, 0.834 ns); + tpd_i3_q : VitalDelayType01 := (0.673 ns, 0.898 ns); + tpd_i4_q : VitalDelayType01 := (0.758 ns, 0.896 ns); + tpd_i5_q : VitalDelayType01 := (0.839 ns, 0.865 ns); + tpd_i6_q : VitalDelayType01 := (0.684 ns, 0.651 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa3ao322_x4 : entity is TRUE; +end oa3ao322_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa3ao322_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i4_ipd) OR (i3_ipd) OR (i5_ipd)) AND (i6_ipd)) OR ((i1_ipd) AND + (i0_ipd) AND (i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa3ao322_x4_VITAL of oa3ao322_x4 is + for VITAL + end for; +end CFG_oa3ao322_x4_VITAL; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.390 ns, 0.555 ns); + tpd_i1_q : VitalDelayType01 := (0.488 ns, 0.525 ns); + tpd_i2_q : VitalDelayType01 := (0.438 ns, 0.454 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa22_x2 : entity is TRUE; +end oa22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa22_x2_VITAL of oa22_x2 is + for VITAL + end for; +end CFG_oa22_x2_VITAL; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.511 ns, 0.677 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.523 ns, 0.571 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa22_x4 : entity is TRUE; +end oa22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa22_x4_VITAL of oa22_x4 is + for VITAL + end for; +end CFG_oa22_x4_VITAL; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity on12_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.111 ns, 0.234 ns); + tpd_i1_q : VitalDelayType01 := (0.314 ns, 0.291 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of on12_x1 : entity is TRUE; +end on12_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of on12_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_on12_x1_VITAL of on12_x1 is + for VITAL + end for; +end CFG_on12_x1_VITAL; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity on12_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.474 ns, 0.499 ns); + tpd_i1_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of on12_x4 : entity is TRUE; +end on12_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of on12_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_on12_x4_VITAL of on12_x4 is + for VITAL + end for; +end CFG_on12_x4_VITAL; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity one_x0 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True); + + port( + q : out STD_ULOGIC := '1'); +attribute VITAL_LEVEL0 of one_x0 : entity is TRUE; +end one_x0; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of one_x0 is + attribute VITAL_LEVEL0 of VITAL : architecture is TRUE; + + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + -- empty + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + q <= '1'; + + +end VITAL; + +configuration CFG_one_x0_VITAL of one_x0 is + for VITAL + end for; +end CFG_one_x0_VITAL; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity sff1_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i_ck : VitalDelayType := 0.585 ns; + thold_i_ck : VitalDelayType := 0.000 ns; + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of sff1_x4 : entity is TRUE; +end sff1_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of sff1_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL ck_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (ck_ipd, ck, tipd_ck); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, ck_ipd) + + -- timing check results + VARIABLE Tviol_i_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_i_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_q : STD_LOGIC_VECTOR(0 to 2); + VARIABLE i_delayed : STD_ULOGIC := 'X'; + VARIABLE ck_delayed : STD_ULOGIC := 'X'; + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_i_ck_posedge, + TimingData => Tmkr_i_ck_posedge, + TestSignal => i_ipd, + TestSignalName => "i", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_i_ck, + SetupLow => tsetup_i_ck, + HoldHigh => thold_i_ck, + HoldLow => thold_i_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff1_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_i_ck_posedge; + VitalStateTable( + Result => q_zd, + PreviousDataIn => PrevData_q, + StateTable => sff1_x4_q_tab, + DataIn => ( + ck_delayed, i_delayed, ck_ipd)); + q_zd := Violation XOR q_zd; + i_delayed := i_ipd; + ck_delayed := ck_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (ck_ipd'last_event, tpd_ck_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_sff1_x4_VITAL of sff1_x4 is + for VITAL + end for; +end CFG_sff1_x4_VITAL; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity sff2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i0_ck : VitalDelayType := 0.764 ns; + thold_i0_ck : VitalDelayType := 0.000 ns; + tsetup_i1_ck : VitalDelayType := 0.764 ns; + thold_i1_ck : VitalDelayType := 0.000 ns; + tsetup_cmd_ck : VitalDelayType := 0.833 ns; + thold_cmd_ck : VitalDelayType := 0.000 ns; + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + cmd : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of sff2_x4 : entity is TRUE; +end sff2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of sff2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL ck_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (ck_ipd, ck, tipd_ck); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, cmd_ipd, ck_ipd) + + -- timing check results + VARIABLE Tviol_i0_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_i0_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_i1_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_i1_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_cmd_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_cmd_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_q : STD_LOGIC_VECTOR(0 to 4); + VARIABLE i0_delayed : STD_ULOGIC := 'X'; + VARIABLE i1_delayed : STD_ULOGIC := 'X'; + VARIABLE cmd_delayed : STD_ULOGIC := 'X'; + VARIABLE ck_delayed : STD_ULOGIC := 'X'; + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_i0_ck_posedge, + TimingData => Tmkr_i0_ck_posedge, + TestSignal => i0_ipd, + TestSignalName => "i0", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_i0_ck, + SetupLow => tsetup_i0_ck, + HoldHigh => thold_i0_ck, + HoldLow => thold_i0_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff2_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalSetupHoldCheck ( + Violation => Tviol_i1_ck_posedge, + TimingData => Tmkr_i1_ck_posedge, + TestSignal => i1_ipd, + TestSignalName => "i1", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_i1_ck, + SetupLow => tsetup_i1_ck, + HoldHigh => thold_i1_ck, + HoldLow => thold_i1_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff2_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalSetupHoldCheck ( + Violation => Tviol_cmd_ck_posedge, + TimingData => Tmkr_cmd_ck_posedge, + TestSignal => cmd_ipd, + TestSignalName => "cmd", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_cmd_ck, + SetupLow => tsetup_cmd_ck, + HoldHigh => thold_cmd_ck, + HoldLow => thold_cmd_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff2_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_i0_ck_posedge or Tviol_i1_ck_posedge or Tviol_cmd_ck_posedge; + VitalStateTable( + Result => q_zd, + PreviousDataIn => PrevData_q, + StateTable => sff2_x4_q_tab, + DataIn => ( + ck_delayed, i1_delayed, i0_delayed, cmd_delayed, ck_ipd)); + q_zd := Violation XOR q_zd; + i0_delayed := i0_ipd; + i1_delayed := i1_ipd; + cmd_delayed := cmd_ipd; + ck_delayed := ck_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (ck_ipd'last_event, tpd_ck_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_sff2_x4_VITAL of sff2_x4 is + for VITAL + end for; +end CFG_sff2_x4_VITAL; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ts_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01z := + (0.492 ns, 0.409 ns, 0.492 ns, 0.492 ns, 0.409 ns, 0.409 ns); + tpd_i_q : VitalDelayType01 := (0.475 ns, 0.444 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ts_x4 : entity is TRUE; +end ts_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ts_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalBUFIF0 (data => i_ipd, + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_q), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_q), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_ts_x4_VITAL of ts_x4 is + for VITAL + end for; +end CFG_ts_x4_VITAL; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ts_x8 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01z := + (0.626 ns, 0.466 ns, 0.626 ns, 0.626 ns, 0.466 ns, 0.466 ns); + tpd_i_q : VitalDelayType01 := (0.613 ns, 0.569 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ts_x8 : entity is TRUE; +end ts_x8; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ts_x8 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalBUFIF0 (data => i_ipd, + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_q), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_q), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_ts_x8_VITAL of ts_x8 is + for VITAL + end for; +end CFG_ts_x8_VITAL; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity xr2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.292 ns, 0.293 ns); + tpd_i1_q : VitalDelayType01 := (0.377 ns, 0.261 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of xr2_x1 : entity is TRUE; +end xr2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of xr2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) XOR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_xr2_x1_VITAL of xr2_x1 is + for VITAL + end for; +end CFG_xr2_x1_VITAL; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity xr2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.521 ns, 0.560 ns); + tpd_i1_q : VitalDelayType01 := (0.541 ns, 0.657 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of xr2_x4 : entity is TRUE; +end xr2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of xr2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) XOR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_xr2_x4_VITAL of xr2_x4 is + for VITAL + end for; +end CFG_xr2_x4_VITAL; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity zero_x0 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True); + + port( + nq : out STD_ULOGIC := '0'); +attribute VITAL_LEVEL0 of zero_x0 : entity is TRUE; +end zero_x0; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of zero_x0 is + attribute VITAL_LEVEL0 of VITAL : architecture is TRUE; + + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + -- empty + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + nq <= '0'; + + +end VITAL; + +configuration CFG_zero_x0_VITAL of zero_x0 is + for VITAL + end for; +end CFG_zero_x0_VITAL; + + +---- end of library ---- diff --git a/alliance/src/cells/src/sxlib/sxlib_Vcomponents.vhd b/alliance/src/cells/src/sxlib/sxlib_Vcomponents.vhd new file mode 100644 index 00000000..5844b9e3 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib_Vcomponents.vhd @@ -0,0 +1,2252 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_Vcomponents.vhd +-- FILE CONTENTS: VITAL Component Package +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : +-- HISTORY : +-- +---------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +-- synopsys translate_off + +library IEEE; +use IEEE.VITAL_Timing.all; +-- synopsys translate_on + +package VCOMPONENTS is + +constant DefaultTimingChecksOn : Boolean := True; +constant DefaultXon : Boolean := False; +constant DefaultMsgOn : Boolean := True; + +----- Component a2_x2 ----- +component a2_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.261 ns, 0.388 ns); + tpd_i1_q : VitalDelayType01 := (0.203 ns, 0.434 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a2_x4 ----- +component a2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.338 ns, 0.476 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a3_x2 ----- +component a3_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.395 ns, 0.435 ns); + tpd_i1_q : VitalDelayType01 := (0.353 ns, 0.479 ns); + tpd_i2_q : VitalDelayType01 := (0.290 ns, 0.521 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a3_x4 ----- +component a3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.478 ns, 0.514 ns); + tpd_i1_q : VitalDelayType01 := (0.428 ns, 0.554 ns); + tpd_i2_q : VitalDelayType01 := (0.356 ns, 0.592 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a4_x2 ----- +component a4_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.374 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.441 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.482 ns, 0.498 ns); + tpd_i3_q : VitalDelayType01 := (0.506 ns, 0.455 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a4_x4 ----- +component a4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.505 ns, 0.650 ns); + tpd_i1_q : VitalDelayType01 := (0.578 ns, 0.614 ns); + tpd_i2_q : VitalDelayType01 := (0.627 ns, 0.576 ns); + tpd_i3_q : VitalDelayType01 := (0.661 ns, 0.538 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component an12_x1 ----- +component an12_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.200 ns, 0.168 ns); + tpd_i1_q : VitalDelayType01 := (0.285 ns, 0.405 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component an12_x4 ----- +component an12_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.461 ns, 0.471 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao2o22_x2 ----- +component ao2o22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.572 ns, 0.451 ns); + tpd_i1_q : VitalDelayType01 := (0.508 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.432 ns, 0.627 ns); + tpd_i3_q : VitalDelayType01 := (0.488 ns, 0.526 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao2o22_x4 ----- +component ao2o22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.696 ns, 0.569 ns); + tpd_i1_q : VitalDelayType01 := (0.637 ns, 0.666 ns); + tpd_i2_q : VitalDelayType01 := (0.554 ns, 0.744 ns); + tpd_i3_q : VitalDelayType01 := (0.606 ns, 0.639 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao22_x2 ----- +component ao22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.558 ns, 0.447 ns); + tpd_i1_q : VitalDelayType01 := (0.493 ns, 0.526 ns); + tpd_i2_q : VitalDelayType01 := (0.420 ns, 0.425 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao22_x4 ----- +component ao22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.674 ns, 0.552 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i2_q : VitalDelayType01 := (0.526 ns, 0.505 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component buf_x2 ----- +component buf_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_q : VitalDelayType01 := (0.409 ns, 0.391 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component buf_x4 ----- +component buf_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_q : VitalDelayType01 := (0.379 ns, 0.409 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component buf_x8 ----- +component buf_x8 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_q : VitalDelayType01 := (0.343 ns, 0.396 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component inv_x1 ----- +component inv_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.101 ns, 0.139 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component inv_x2 ----- +component inv_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.069 ns, 0.163 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component inv_x4 ----- +component inv_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.071 ns, 0.143 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component inv_x8 ----- +component inv_x8 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.086 ns, 0.133 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component mx2_x2 ----- +component mx2_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01 := (0.484 ns, 0.522 ns); + tpd_i0_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tpd_i1_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component mx2_x4 ----- +component mx2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i0_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tpd_i1_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component mx3_x2 ----- +component mx3_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_q : VitalDelayType01 := (0.573 ns, 0.680 ns); + tpd_cmd1_q : VitalDelayType01 := (0.664 ns, 0.817 ns); + tpd_i0_q : VitalDelayType01 := (0.538 ns, 0.658 ns); + tpd_i1_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tpd_i2_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component mx3_x4 ----- +component mx3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_q : VitalDelayType01 := (0.683 ns, 0.779 ns); + tpd_cmd1_q : VitalDelayType01 := (0.792 ns, 0.967 ns); + tpd_i0_q : VitalDelayType01 := (0.640 ns, 0.774 ns); + tpd_i1_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tpd_i2_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component na2_x1 ----- +component na2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.059 ns, 0.288 ns); + tpd_i1_nq : VitalDelayType01 := (0.111 ns, 0.234 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na2_x4 ----- +component na2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.412 ns, 0.552 ns); + tpd_i1_nq : VitalDelayType01 := (0.353 ns, 0.601 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na3_x1 ----- +component na3_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.119 ns, 0.363 ns); + tpd_i1_nq : VitalDelayType01 := (0.171 ns, 0.316 ns); + tpd_i2_nq : VitalDelayType01 := (0.193 ns, 0.265 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na3_x4 ----- +component na3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.556 ns, 0.601 ns); + tpd_i1_nq : VitalDelayType01 := (0.460 ns, 0.691 ns); + tpd_i2_nq : VitalDelayType01 := (0.519 ns, 0.647 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na4_x1 ----- +component na4_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.179 ns, 0.438 ns); + tpd_i1_nq : VitalDelayType01 := (0.237 ns, 0.395 ns); + tpd_i2_nq : VitalDelayType01 := (0.269 ns, 0.350 ns); + tpd_i3_nq : VitalDelayType01 := (0.282 ns, 0.302 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na4_x4 ----- +component na4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.578 ns, 0.771 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.731 ns); + tpd_i2_nq : VitalDelayType01 := (0.681 ns, 0.689 ns); + tpd_i3_nq : VitalDelayType01 := (0.703 ns, 0.644 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao2o22_x1 ----- +component nao2o22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.237 ns, 0.307 ns); + tpd_i3_nq : VitalDelayType01 := (0.174 ns, 0.382 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao2o22_x4 ----- +component nao2o22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.734 ns, 0.644 ns); + tpd_i1_nq : VitalDelayType01 := (0.666 ns, 0.717 ns); + tpd_i2_nq : VitalDelayType01 := (0.664 ns, 0.721 ns); + tpd_i3_nq : VitalDelayType01 := (0.607 ns, 0.807 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao22_x1 ----- +component nao22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.165 ns, 0.238 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao22_x4 ----- +component nao22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.732 ns, 0.650 ns); + tpd_i1_nq : VitalDelayType01 := (0.664 ns, 0.723 ns); + tpd_i2_nq : VitalDelayType01 := (0.596 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx2_x1 ----- +component nmx2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i0_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tpd_i1_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx2_x4 ----- +component nmx2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01 := (0.632 ns, 0.708 ns); + tpd_i0_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tpd_i1_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx3_x1 ----- +component nmx3_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_nq : VitalDelayType01 := (0.356 ns, 0.495 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.414 ns, 0.566 ns); + tpd_i0_nq : VitalDelayType01 := (0.315 ns, 0.441 ns); + tpd_i1_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tpd_i2_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx3_x4 ----- +component nmx3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_nq : VitalDelayType01 := (0.790 ns, 0.936 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.866 ns, 1.048 ns); + tpd_i0_nq : VitalDelayType01 := (0.748 ns, 0.900 ns); + tpd_i1_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tpd_i2_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no2_x1 ----- +component no2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.298 ns, 0.121 ns); + tpd_i1_nq : VitalDelayType01 := (0.193 ns, 0.161 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no2_x4 ----- +component no2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.618 ns, 0.447 ns); + tpd_i1_nq : VitalDelayType01 := (0.522 ns, 0.504 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no3_x1 ----- +component no3_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.318 ns, 0.246 ns); + tpd_i1_nq : VitalDelayType01 := (0.215 ns, 0.243 ns); + tpd_i2_nq : VitalDelayType01 := (0.407 ns, 0.192 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no3_x4 ----- +component no3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.722 ns, 0.561 ns); + tpd_i1_nq : VitalDelayType01 := (0.638 ns, 0.623 ns); + tpd_i2_nq : VitalDelayType01 := (0.545 ns, 0.640 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no4_x1 ----- +component no4_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.330 ns, 0.340 ns); + tpd_i1_nq : VitalDelayType01 := (0.230 ns, 0.320 ns); + tpd_i2_nq : VitalDelayType01 := (0.419 ns, 0.333 ns); + tpd_i3_nq : VitalDelayType01 := (0.499 ns, 0.271 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no4_x4 ----- +component no4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.656 ns, 0.777 ns); + tpd_i1_nq : VitalDelayType01 := (0.564 ns, 0.768 ns); + tpd_i2_nq : VitalDelayType01 := (0.739 ns, 0.761 ns); + tpd_i3_nq : VitalDelayType01 := (0.816 ns, 0.693 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a2a24_x1 ----- +component noa2a2a2a24_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.649 ns, 0.606 ns); + tpd_i1_nq : VitalDelayType01 := (0.775 ns, 0.562 ns); + tpd_i2_nq : VitalDelayType01 := (0.550 ns, 0.662 ns); + tpd_i3_nq : VitalDelayType01 := (0.667 ns, 0.616 ns); + tpd_i4_nq : VitalDelayType01 := (0.419 ns, 0.613 ns); + tpd_i5_nq : VitalDelayType01 := (0.329 ns, 0.662 ns); + tpd_i6_nq : VitalDelayType01 := (0.270 ns, 0.535 ns); + tpd_i7_nq : VitalDelayType01 := (0.200 ns, 0.591 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a2a24_x4 ----- +component noa2a2a2a24_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.966 ns, 1.049 ns); + tpd_i1_nq : VitalDelayType01 := (1.097 ns, 1.005 ns); + tpd_i2_nq : VitalDelayType01 := (0.867 ns, 1.106 ns); + tpd_i3_nq : VitalDelayType01 := (0.990 ns, 1.061 ns); + tpd_i4_nq : VitalDelayType01 := (0.748 ns, 1.061 ns); + tpd_i5_nq : VitalDelayType01 := (0.649 ns, 1.109 ns); + tpd_i6_nq : VitalDelayType01 := (0.606 ns, 0.999 ns); + tpd_i7_nq : VitalDelayType01 := (0.525 ns, 1.052 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a23_x1 ----- +component noa2a2a23_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.525 ns, 0.425 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.388 ns); + tpd_i2_nq : VitalDelayType01 := (0.307 ns, 0.479 ns); + tpd_i3_nq : VitalDelayType01 := (0.398 ns, 0.438 ns); + tpd_i4_nq : VitalDelayType01 := (0.250 ns, 0.416 ns); + tpd_i5_nq : VitalDelayType01 := (0.178 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a23_x4 ----- +component noa2a2a23_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.834 ns, 0.814 ns); + tpd_i1_nq : VitalDelayType01 := (0.955 ns, 0.778 ns); + tpd_i2_nq : VitalDelayType01 := (0.620 ns, 0.873 ns); + tpd_i3_nq : VitalDelayType01 := (0.716 ns, 0.833 ns); + tpd_i4_nq : VitalDelayType01 := (0.574 ns, 0.819 ns); + tpd_i5_nq : VitalDelayType01 := (0.496 ns, 0.865 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a22_x1 ----- +component noa2a22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.284 ns, 0.289 ns); + tpd_i3_nq : VitalDelayType01 := (0.372 ns, 0.256 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a22_x4 ----- +component noa2a22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.562 ns, 0.745 ns); + tpd_i1_nq : VitalDelayType01 := (0.646 ns, 0.714 ns); + tpd_i2_nq : VitalDelayType01 := (0.701 ns, 0.703 ns); + tpd_i3_nq : VitalDelayType01 := (0.805 ns, 0.677 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2ao222_x1 ----- +component noa2ao222_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.348 ns, 0.422 ns); + tpd_i1_nq : VitalDelayType01 := (0.440 ns, 0.378 ns); + tpd_i2_nq : VitalDelayType01 := (0.186 ns, 0.473 ns); + tpd_i3_nq : VitalDelayType01 := (0.256 ns, 0.459 ns); + tpd_i4_nq : VitalDelayType01 := (0.240 ns, 0.309 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2ao222_x4 ----- +component noa2ao222_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.684 ns, 0.801 ns); + tpd_i1_nq : VitalDelayType01 := (0.780 ns, 0.758 ns); + tpd_i2_nq : VitalDelayType01 := (0.638 ns, 0.809 ns); + tpd_i3_nq : VitalDelayType01 := (0.732 ns, 0.795 ns); + tpd_i4_nq : VitalDelayType01 := (0.718 ns, 0.664 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa3ao322_x1 ----- +component noa3ao322_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.396 ns, 0.616 ns); + tpd_i1_nq : VitalDelayType01 := (0.486 ns, 0.552 ns); + tpd_i2_nq : VitalDelayType01 := (0.546 ns, 0.488 ns); + tpd_i3_nq : VitalDelayType01 := (0.196 ns, 0.599 ns); + tpd_i4_nq : VitalDelayType01 := (0.264 ns, 0.608 ns); + tpd_i5_nq : VitalDelayType01 := (0.328 ns, 0.581 ns); + tpd_i6_nq : VitalDelayType01 := (0.246 ns, 0.311 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa3ao322_x4 ----- +component noa3ao322_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.819 ns, 0.987 ns); + tpd_i1_nq : VitalDelayType01 := (0.914 ns, 0.931 ns); + tpd_i2_nq : VitalDelayType01 := (0.990 ns, 0.874 ns); + tpd_i3_nq : VitalDelayType01 := (0.729 ns, 0.926 ns); + tpd_i4_nq : VitalDelayType01 := (0.821 ns, 0.924 ns); + tpd_i5_nq : VitalDelayType01 := (0.907 ns, 0.900 ns); + tpd_i6_nq : VitalDelayType01 := (0.738 ns, 0.718 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa22_x1 ----- +component noa22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.218 ns, 0.241 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa22_x4 ----- +component noa22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.550 ns, 0.740 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.709 ns); + tpd_i2_nq : VitalDelayType01 := (0.610 ns, 0.646 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nts_x1 ----- +component nts_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01z := + (0.249 ns, 0.041 ns, 0.249 ns, 0.249 ns, 0.041 ns, 0.041 ns); + tpd_i_nq : VitalDelayType01 := (0.169 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nts_x2 ----- +component nts_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01z := + (0.330 ns, 0.033 ns, 0.330 ns, 0.330 ns, 0.033 ns, 0.033 ns); + tpd_i_nq : VitalDelayType01 := (0.167 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nxr2_x1 ----- +component nxr2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.288 ns, 0.293 ns); + tpd_i1_nq : VitalDelayType01 := (0.156 ns, 0.327 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nxr2_x4 ----- +component nxr2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.522 ns, 0.553 ns); + tpd_i1_nq : VitalDelayType01 := (0.553 ns, 0.542 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component o2_x2 ----- +component o2_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.406 ns, 0.310 ns); + tpd_i1_q : VitalDelayType01 := (0.335 ns, 0.364 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o2_x4 ----- +component o2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tpd_i1_q : VitalDelayType01 := (0.427 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o3_x2 ----- +component o3_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.494 ns, 0.407 ns); + tpd_i1_q : VitalDelayType01 := (0.430 ns, 0.482 ns); + tpd_i2_q : VitalDelayType01 := (0.360 ns, 0.506 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o3_x4 ----- +component o3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.569 ns, 0.501 ns); + tpd_i1_q : VitalDelayType01 := (0.510 ns, 0.585 ns); + tpd_i2_q : VitalDelayType01 := (0.447 ns, 0.622 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o4_x2 ----- +component o4_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.508 ns, 0.601 ns); + tpd_i1_q : VitalDelayType01 := (0.446 ns, 0.631 ns); + tpd_i2_q : VitalDelayType01 := (0.567 ns, 0.531 ns); + tpd_i3_q : VitalDelayType01 := (0.378 ns, 0.626 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o4_x4 ----- +component o4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.574 ns, 0.638 ns); + tpd_i1_q : VitalDelayType01 := (0.492 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.649 ns, 0.611 ns); + tpd_i3_q : VitalDelayType01 := (0.721 ns, 0.536 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a2a24_x2 ----- +component oa2a2a2a24_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.780 ns, 0.797 ns); + tpd_i1_q : VitalDelayType01 := (0.909 ns, 0.753 ns); + tpd_i2_q : VitalDelayType01 := (0.682 ns, 0.856 ns); + tpd_i3_q : VitalDelayType01 := (0.803 ns, 0.810 ns); + tpd_i4_q : VitalDelayType01 := (0.565 ns, 0.813 ns); + tpd_i5_q : VitalDelayType01 := (0.467 ns, 0.861 ns); + tpd_i6_q : VitalDelayType01 := (0.426 ns, 0.748 ns); + tpd_i7_q : VitalDelayType01 := (0.346 ns, 0.800 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a2a24_x4 ----- +component oa2a2a2a24_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.823 ns, 0.879 ns); + tpd_i1_q : VitalDelayType01 := (0.955 ns, 0.835 ns); + tpd_i2_q : VitalDelayType01 := (0.726 ns, 0.940 ns); + tpd_i3_q : VitalDelayType01 := (0.851 ns, 0.895 ns); + tpd_i4_q : VitalDelayType01 := (0.619 ns, 0.902 ns); + tpd_i5_q : VitalDelayType01 := (0.515 ns, 0.949 ns); + tpd_i6_q : VitalDelayType01 := (0.487 ns, 0.845 ns); + tpd_i7_q : VitalDelayType01 := (0.399 ns, 0.895 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a23_x2 ----- +component oa2a2a23_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.653 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.775 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.441 ns, 0.639 ns); + tpd_i3_q : VitalDelayType01 := (0.540 ns, 0.600 ns); + tpd_i4_q : VitalDelayType01 := (0.402 ns, 0.591 ns); + tpd_i5_q : VitalDelayType01 := (0.321 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a23_x4 ----- +component oa2a2a23_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.699 ns, 0.648 ns); + tpd_i1_q : VitalDelayType01 := (0.822 ns, 0.613 ns); + tpd_i2_q : VitalDelayType01 := (0.493 ns, 0.715 ns); + tpd_i3_q : VitalDelayType01 := (0.594 ns, 0.677 ns); + tpd_i4_q : VitalDelayType01 := (0.464 ns, 0.673 ns); + tpd_i5_q : VitalDelayType01 := (0.379 ns, 0.714 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a22_x2 ----- +component oa2a22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.403 ns, 0.564 ns); + tpd_i1_q : VitalDelayType01 := (0.495 ns, 0.534 ns); + tpd_i2_q : VitalDelayType01 := (0.646 ns, 0.487 ns); + tpd_i3_q : VitalDelayType01 := (0.537 ns, 0.512 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a22_x4 ----- +component oa2a22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.519 ns, 0.696 ns); + tpd_i1_q : VitalDelayType01 := (0.624 ns, 0.669 ns); + tpd_i2_q : VitalDelayType01 := (0.763 ns, 0.596 ns); + tpd_i3_q : VitalDelayType01 := (0.644 ns, 0.619 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2ao222_x2 ----- +component oa2ao222_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.495 ns, 0.581 ns); + tpd_i1_q : VitalDelayType01 := (0.598 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.464 ns, 0.604 ns); + tpd_i3_q : VitalDelayType01 := (0.556 ns, 0.578 ns); + tpd_i4_q : VitalDelayType01 := (0.558 ns, 0.453 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2ao222_x4 ----- +component oa2ao222_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.553 ns, 0.657 ns); + tpd_i1_q : VitalDelayType01 := (0.662 ns, 0.616 ns); + tpd_i2_q : VitalDelayType01 := (0.552 ns, 0.693 ns); + tpd_i3_q : VitalDelayType01 := (0.640 ns, 0.660 ns); + tpd_i4_q : VitalDelayType01 := (0.656 ns, 0.529 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa3ao322_x2 ----- +component oa3ao322_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.638 ns, 0.820 ns); + tpd_i1_q : VitalDelayType01 := (0.735 ns, 0.764 ns); + tpd_i2_q : VitalDelayType01 := (0.806 ns, 0.707 ns); + tpd_i3_q : VitalDelayType01 := (0.560 ns, 0.765 ns); + tpd_i4_q : VitalDelayType01 := (0.649 ns, 0.760 ns); + tpd_i5_q : VitalDelayType01 := (0.734 ns, 0.734 ns); + tpd_i6_q : VitalDelayType01 := (0.563 ns, 0.540 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa3ao322_x4 ----- +component oa3ao322_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.717 ns, 0.946 ns); + tpd_i1_q : VitalDelayType01 := (0.818 ns, 0.890 ns); + tpd_i2_q : VitalDelayType01 := (0.894 ns, 0.834 ns); + tpd_i3_q : VitalDelayType01 := (0.673 ns, 0.898 ns); + tpd_i4_q : VitalDelayType01 := (0.758 ns, 0.896 ns); + tpd_i5_q : VitalDelayType01 := (0.839 ns, 0.865 ns); + tpd_i6_q : VitalDelayType01 := (0.684 ns, 0.651 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa22_x2 ----- +component oa22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.390 ns, 0.555 ns); + tpd_i1_q : VitalDelayType01 := (0.488 ns, 0.525 ns); + tpd_i2_q : VitalDelayType01 := (0.438 ns, 0.454 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa22_x4 ----- +component oa22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.511 ns, 0.677 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.523 ns, 0.571 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component on12_x1 ----- +component on12_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.111 ns, 0.234 ns); + tpd_i1_q : VitalDelayType01 := (0.314 ns, 0.291 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component on12_x4 ----- +component on12_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.474 ns, 0.499 ns); + tpd_i1_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component one_x0 ----- +component one_x0 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn); + +-- synopsys translate_on + port( + q : out STD_ULOGIC := '1'); +end component; + + +----- Component sff1_x4 ----- +component sff1_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i_ck : VitalDelayType := 0.585 ns; + thold_i_ck : VitalDelayType := 0.000 ns; + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component sff2_x4 ----- +component sff2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i0_ck : VitalDelayType := 0.764 ns; + thold_i0_ck : VitalDelayType := 0.000 ns; + tsetup_i1_ck : VitalDelayType := 0.764 ns; + thold_i1_ck : VitalDelayType := 0.000 ns; + tsetup_cmd_ck : VitalDelayType := 0.833 ns; + thold_cmd_ck : VitalDelayType := 0.000 ns; + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + cmd : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ts_x4 ----- +component ts_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01z := + (0.492 ns, 0.409 ns, 0.492 ns, 0.492 ns, 0.409 ns, 0.409 ns); + tpd_i_q : VitalDelayType01 := (0.475 ns, 0.444 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ts_x8 ----- +component ts_x8 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01z := + (0.626 ns, 0.466 ns, 0.626 ns, 0.626 ns, 0.466 ns, 0.466 ns); + tpd_i_q : VitalDelayType01 := (0.613 ns, 0.569 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component xr2_x1 ----- +component xr2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.292 ns, 0.293 ns); + tpd_i1_q : VitalDelayType01 := (0.377 ns, 0.261 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component xr2_x4 ----- +component xr2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.521 ns, 0.560 ns); + tpd_i1_q : VitalDelayType01 := (0.541 ns, 0.657 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component zero_x0 ----- +component zero_x0 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn); + +-- synopsys translate_on + port( + nq : out STD_ULOGIC := '0'); +end component; + + +end VCOMPONENTS; + +---- end of VITAL components library ---- diff --git a/alliance/src/cells/src/sxlib/sxlib_Vtables.vhd b/alliance/src/cells/src/sxlib/sxlib_Vtables.vhd new file mode 100644 index 00000000..85db0e88 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib_Vtables.vhd @@ -0,0 +1,58 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_Vtables.vhd +-- FILE CONTENTS: VITAL Table Package +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : +-- HISTORY : +-- +---------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +-- synopsys translate_off + +library IEEE; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +-- synopsys translate_on + +package VTABLES is + + CONSTANT L : VitalTableSymbolType := '0'; + CONSTANT H : VitalTableSymbolType := '1'; + CONSTANT x : VitalTableSymbolType := '-'; + CONSTANT S : VitalTableSymbolType := 'S'; + CONSTANT R : VitalTableSymbolType := '/'; + CONSTANT U : VitalTableSymbolType := 'X'; + CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) + + CONSTANT sff1_x4_q_tab : VitalStateTableType := ( + ( L, L, H, x, L ), + ( L, H, H, x, H ), + ( H, x, x, x, S ), + ( x, x, L, x, S )); + + CONSTANT sff2_x4_q_tab : VitalStateTableType := ( + ( L, L, L, x, H, x, L ), + ( L, L, x, H, H, x, L ), + ( L, H, H, x, H, x, H ), + ( L, H, x, H, H, x, H ), + ( L, x, L, L, H, x, L ), + ( L, x, H, L, H, x, H ), + ( H, x, x, x, x, x, S ), + ( x, x, x, x, L, x, S )); + + +end VTABLES; + +---- end of VITAL tables library ---- diff --git a/alliance/src/cells/src/sxlib/sxlib_components.vhd b/alliance/src/cells/src/sxlib/sxlib_components.vhd new file mode 100644 index 00000000..0978efc2 --- /dev/null +++ b/alliance/src/cells/src/sxlib/sxlib_components.vhd @@ -0,0 +1,2677 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_components.vhd +-- FILE CONTENTS: Component Package +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : +-- HISTORY : +-- +---------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +-- synopsys translate_off +use IEEE.GS_TYPES.sdt_values_t; +-- synopsys translate_on + +package COMPONENTS is + +constant Default_Timing_mesg : Boolean := True; +constant Default_Timing_xgen : Boolean := False; + +----- Component a2_x2 ----- +component a2_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a2_x4 ----- +component a2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a3_x2 ----- +component a3_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a3_x4 ----- +component a3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a4_x2 ----- +component a4_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a4_x4 ----- +component a4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component an12_x1 ----- +component an12_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component an12_x4 ----- +component an12_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao2o22_x2 ----- +component ao2o22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao2o22_x4 ----- +component ao2o22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao22_x2 ----- +component ao22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao22_x4 ----- +component ao22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component buf_x2 ----- +component buf_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component buf_x4 ----- +component buf_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component buf_x8 ----- +component buf_x8 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component inv_x1 ----- +component inv_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component inv_x2 ----- +component inv_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component inv_x4 ----- +component inv_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component inv_x8 ----- +component inv_x8 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component mx2_x2 ----- +component mx2_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component mx2_x4 ----- +component mx2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component mx3_x2 ----- +component mx3_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component mx3_x4 ----- +component mx3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component na2_x1 ----- +component na2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na2_x4 ----- +component na2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na3_x1 ----- +component na3_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na3_x4 ----- +component na3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na4_x1 ----- +component na4_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na4_x4 ----- +component na4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao2o22_x1 ----- +component nao2o22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao2o22_x4 ----- +component nao2o22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao22_x1 ----- +component nao22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao22_x4 ----- +component nao22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx2_x1 ----- +component nmx2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx2_x4 ----- +component nmx2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx3_x1 ----- +component nmx3_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx3_x4 ----- +component nmx3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no2_x1 ----- +component no2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no2_x4 ----- +component no2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no3_x1 ----- +component no3_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no3_x4 ----- +component no3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no4_x1 ----- +component no4_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no4_x4 ----- +component no4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a2a24_x1 ----- +component noa2a2a2a24_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a2a24_x4 ----- +component noa2a2a2a24_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a23_x1 ----- +component noa2a2a23_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a23_x4 ----- +component noa2a2a23_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a22_x1 ----- +component noa2a22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a22_x4 ----- +component noa2a22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2ao222_x1 ----- +component noa2ao222_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2ao222_x4 ----- +component noa2ao222_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa3ao322_x1 ----- +component noa3ao322_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa3ao322_x4 ----- +component noa3ao322_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa22_x1 ----- +component noa22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa22_x4 ----- +component noa22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nts_x1 ----- +component nts_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nts_x2 ----- +component nts_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nxr2_x1 ----- +component nxr2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nxr2_x4 ----- +component nxr2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component o2_x2 ----- +component o2_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o2_x4 ----- +component o2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o3_x2 ----- +component o3_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o3_x4 ----- +component o3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o4_x2 ----- +component o4_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o4_x4 ----- +component o4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a2a24_x2 ----- +component oa2a2a2a24_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a2a24_x4 ----- +component oa2a2a2a24_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a23_x2 ----- +component oa2a2a23_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a23_x4 ----- +component oa2a2a23_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a22_x2 ----- +component oa2a22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a22_x4 ----- +component oa2a22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2ao222_x2 ----- +component oa2ao222_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2ao222_x4 ----- +component oa2ao222_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa3ao322_x2 ----- +component oa3ao322_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa3ao322_x4 ----- +component oa3ao322_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa22_x2 ----- +component oa22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa22_x4 ----- +component oa22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component on12_x1 ----- +component on12_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component on12_x4 ----- +component on12_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component one_x0 ----- +component one_x0 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen); + +-- synopsys translate_on + port( + q : out STD_LOGIC := '1'); +end component; + + +----- Component sff1_x4 ----- +component sff1_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component sff2_x4 ----- +component sff2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ts_x4 ----- +component ts_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ts_x8 ----- +component ts_x8 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component xr2_x1 ----- +component xr2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component xr2_x4 ----- +component xr2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component zero_x0 ----- +component zero_x0 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen); + +-- synopsys translate_on + port( + nq : out STD_LOGIC := '0'); +end component; + + +end COMPONENTS; + +---- end of components library ---- diff --git a/alliance/src/cells/src/sxlib/tie_x0.al b/alliance/src/cells/src/sxlib/tie_x0.al new file mode 100644 index 00000000..49929218 --- /dev/null +++ b/alliance/src/cells/src/sxlib/tie_x0.al @@ -0,0 +1,19 @@ +V ALLIANCE : 6 +H tie_x0,L,30/10/99 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +S 7,INTERNAL +Q 0.000176265 +S 6,INTERNAL +Q 0.000176265 +S 5,EXTERNAL,vdd +Q 0.00178498 +S 4,INTERNAL +Q 0.000176265 +S 3,INTERNAL +Q 0.000176265 +S 2,EXTERNAL,vss +Q 0.00178498 +S 1,INTERNAL +Q 0.000176265 +EOF diff --git a/alliance/src/cells/src/sxlib/tie_x0.ap b/alliance/src/cells/src/sxlib/tie_x0.ap new file mode 100644 index 00000000..725bab2b --- /dev/null +++ b/alliance/src/cells/src/sxlib/tie_x0.ap @@ -0,0 +1,16 @@ +V ALLIANCE : 6 +H tie_x0,P,30/ 8/2000,100 +A 0,0,1000,5000 +S 500,3000,500,4500,300,*,UP,NTIE +S 500,500,500,1500,300,*,DOWN,PTIE +S 0,4700,1000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,1000,3900,2400,*,RIGHT,NWELL +S 0,300,1000,300,600,vss,RIGHT,CALU1 +V 500,1500,CONT_BODY_P,* +V 500,1000,CONT_BODY_P,* +V 500,500,CONT_BODY_P,* +V 500,3000,CONT_BODY_N,* +V 500,3500,CONT_BODY_N,* +V 500,4000,CONT_BODY_N,* +V 500,4500,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/sxlib/tie_x0.vbe b/alliance/src/cells/src/sxlib/tie_x0.vbe new file mode 100644 index 00000000..133f4326 --- /dev/null +++ b/alliance/src/cells/src/sxlib/tie_x0.vbe @@ -0,0 +1,14 @@ +ENTITY tie_x0 IS +PORT ( + vdd : in BIT; + vss : in BIT +); +END tie_x0; + +ARCHITECTURE behaviour_data_flow OF tie_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on tie_x0" + SEVERITY WARNING; +END; diff --git a/alliance/src/cells/src/sxlib/tie_x0.vhd b/alliance/src/cells/src/sxlib/tie_x0.vhd new file mode 100644 index 00000000..0049a9c6 --- /dev/null +++ b/alliance/src/cells/src/sxlib/tie_x0.vhd @@ -0,0 +1,16 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY tie_x0 IS +PORT( +); +END tie_x0; + +ARCHITECTURE RTL OF tie_x0 IS +BEGIN +END RTL; diff --git a/alliance/src/cells/src/sxlib/ts_x4.al b/alliance/src/cells/src/sxlib/ts_x4.al new file mode 100644 index 00000000..a0d92c79 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ts_x4.al @@ -0,0 +1,36 @@ +V ALLIANCE : 6 +H ts_x4,L,30/10/99 +C cmd,IN,EXTERNAL,7 +C i,IN,EXTERNAL,8 +C q,TRISTATE,EXTERNAL,1 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,2,7,5,0,0.75,0.75,7.3,7.3,5.4,12.75,tr_00012 +T P,0.35,5.9,1,6,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011 +T P,0.35,2.9,6,8,5,0,0.75,0.75,7.3,7.3,13.2,11.25,tr_00010 +T P,0.35,2.9,6,2,4,0,0.75,0.75,7.3,7.3,9.6,11.25,tr_00009 +T P,0.35,2.9,5,7,6,0,0.75,0.75,7.3,7.3,11.4,11.25,tr_00008 +T P,0.35,5.9,5,6,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00007 +T N,0.35,2.9,1,4,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00006 +T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004 +T N,0.35,1.4,6,7,4,0,0.75,0.75,4.3,4.3,13.2,3,tr_00003 +T N,0.35,1.4,3,2,4,0,0.75,0.75,4.3,4.3,9.6,3,tr_00002 +T N,0.35,1.4,4,8,3,0,0.75,0.75,4.3,4.3,11.4,3,tr_00001 +S 8,EXTERNAL,i +Q 0.0029371 +S 7,EXTERNAL,cmd +Q 0.00891222 +S 6,INTERNAL +Q 0.00768869 +S 5,EXTERNAL,vdd +Q 0.00692574 +S 4,INTERNAL +Q 0.00628498 +S 3,EXTERNAL,vss +Q 0.00616192 +S 2,INTERNAL +Q 0.00506239 +S 1,EXTERNAL,q +Q 0.00264397 +EOF diff --git a/alliance/src/cells/src/sxlib/ts_x4.ap b/alliance/src/cells/src/sxlib/ts_x4.ap new file mode 100644 index 00000000..7420d780 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ts_x4.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H ts_x4,P, 6/ 9/2000,100 +A 0,0,5000,5000 +R 1000,1000,ref_ref,q_10 +R 1000,1500,ref_ref,q_15 +R 1000,2000,ref_ref,q_20 +R 1000,2500,ref_ref,q_25 +R 1000,3000,ref_ref,q_30 +R 1000,3500,ref_ref,q_35 +R 1000,4000,ref_ref,q_40 +R 4000,2000,ref_ref,i_20 +R 4000,2500,ref_ref,i_25 +R 4000,3000,ref_ref,i_30 +R 4000,3500,ref_ref,i_35 +R 4000,1500,ref_ref,i_15 +R 1500,1000,ref_ref,cmd_10 +R 1500,3000,ref_ref,cmd_30 +R 1500,3500,ref_ref,cmd_35 +R 1500,4000,ref_ref,cmd_40 +R 1500,1500,ref_ref,cmd_15 +R 1500,2000,ref_ref,cmd_20 +R 1500,2500,ref_ref,cmd_25 +S 600,2300,4700,2300,100,*,RIGHT,POLY +S 2300,3100,3200,3100,100,*,RIGHT,POLY +S 3500,3500,3500,4000,100,*,UP,ALU1 +S 1000,950,1000,4050,200,*,UP,ALU1 +S 2100,4000,2400,4000,200,*,RIGHT,ALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2300,1200,2600,100,*,DOWN,POLY +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1900,2800,1900,3000,300,*,UP,POLY +S 1500,3000,1900,3000,200,*,RIGHT,ALU1 +S 600,2300,600,2600,100,*,UP,POLY +S 1800,2800,3800,2800,100,*,RIGHT,POLY +S 3800,2800,3800,3100,100,*,DOWN,POLY +S 1800,2800,1800,3600,100,*,DOWN,POLY +S 3400,1800,3400,2700,100,*,DOWN,ALU1 +S 4200,3000,4400,3000,300,*,RIGHT,POLY +S 4000,3000,4200,3000,200,*,LEFT,ALU1 +S 2700,4700,3500,4700,300,*,RIGHT,NTIE +S 0,3900,5000,3900,2400,*,LEFT,NWELL +S 3500,3300,3500,4200,300,*,UP,PDIF +S 3800,3100,3800,4400,100,*,UP,PTRANS +S 2900,3300,2900,4200,300,*,UP,PDIF +S 3200,3100,3200,4400,100,*,UP,PTRANS +S 4400,1400,4400,1900,100,*,DOWN,POLY +S 3400,1900,4400,1900,100,*,RIGHT,POLY +S 600,1900,2900,1900,100,*,RIGHT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 600,1400,600,1900,100,*,DOWN,POLY +S 4100,3300,4100,4700,300,*,UP,PDIF +S 4700,3300,4700,4200,300,*,UP,PDIF +S 4400,3100,4400,4400,100,*,UP,PTRANS +S 4100,300,4700,300,300,*,RIGHT,PTIE +S 2100,300,2900,300,300,*,RIGHT,PTIE +S 4000,1500,4000,3500,100,*,DOWN,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 3500,400,3500,1200,300,*,UP,NDIF +S 2900,1000,2900,4000,100,*,DOWN,ALU1 +S 2900,1000,4100,1000,100,*,RIGHT,ALU1 +S 3800,600,3800,1400,100,*,UP,NTRANS +S 3200,600,3200,1400,100,*,UP,NTRANS +S 4700,800,4700,1200,300,*,UP,NDIF +S 4400,600,4400,1400,100,*,UP,NTRANS +S 2900,800,2900,1200,300,*,UP,NDIF +S 4100,800,4100,1200,300,*,UP,NDIF +S 4700,1000,4700,4000,100,*,DOWN,ALU1 +S 3800,1500,4000,1500,300,*,RIGHT,POLY +S 3500,4000,4700,4000,100,*,RIGHT,ALU1 +S 2100,3800,2100,4700,300,*,UP,PDIF +S 1800,3600,1800,4900,100,*,UP,PTRANS +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 600,100,600,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 1600,1500,1800,1500,300,*,RIGHT,POLY +S 1500,1500,1600,1500,100,*,RIGHT,ALU1 +S 2400,1000,2400,4000,100,*,DOWN,ALU1 +S 2300,1400,3200,1400,100,*,RIGHT,POLY +S 2100,1000,2400,1000,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,200,q,DOWN,CALU1 +S 4000,1500,4000,3500,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,cmd,DOWN,CALU1 +V 2400,3200,CONT_POLY,* +V 2900,3500,CONT_DIF_P,* +V 4700,3500,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 1900,3000,CONT_POLY,* +V 4200,3000,CONT_POLY,* +V 3500,4700,CONT_BODY_N,* +V 2700,4700,CONT_BODY_N,* +V 4700,2300,CONT_POLY,* +V 3400,2700,CONT_POLY,* +V 900,3000,CONT_DIF_P,* +V 3400,1800,CONT_POLY,* +V 4700,4700,CONT_BODY_N,* +V 2100,300,CONT_BODY_P,* +V 4100,300,CONT_BODY_P,* +V 4700,300,CONT_BODY_P,* +V 2900,300,CONT_BODY_P,* +V 300,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 3500,4000,CONT_DIF_P,* +V 4100,1000,CONT_DIF_N,* +V 3500,500,CONT_DIF_N,* +V 4700,1000,CONT_DIF_N,* +V 2900,1000,CONT_DIF_N,* +V 4000,1500,CONT_POLY,* +V 4100,4500,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 4700,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1600,1500,CONT_POLY,* +V 2900,1800,CONT_POLY,* +V 2400,1500,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/ts_x4.sym b/alliance/src/cells/src/sxlib/ts_x4.sym new file mode 100644 index 00000000..a013224e Binary files /dev/null and b/alliance/src/cells/src/sxlib/ts_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/ts_x4.vbe b/alliance/src/cells/src/sxlib/ts_x4.vbe new file mode 100644 index 00000000..25d28a49 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ts_x4.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphl_cmd_q : NATURAL := 409; + CONSTANT tpll_i_q : NATURAL := 444; + CONSTANT tphh_i_q : NATURAL := 475; + CONSTANT tphh_cmd_q : NATURAL := 492; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x4; + +ARCHITECTURE behaviour_data_flow OF ts_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x4" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1100 ps; + END BLOCK label0; + +END; diff --git a/alliance/src/cells/src/sxlib/ts_x4.vhd b/alliance/src/cells/src/sxlib/ts_x4.vhd new file mode 100644 index 00000000..c5c71db9 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ts_x4.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ts_x4 IS +PORT( + cmd : IN STD_LOGIC; + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ts_x4; + +ARCHITECTURE RTL OF ts_x4 IS +BEGIN + PROCESS ( i, cmd ) + BEGIN + IF (cmd = '1') + THEN q <= i; + ELSE q <= 'Z'; + END IF; + END PROCESS; +END RTL; diff --git a/alliance/src/cells/src/sxlib/ts_x8.al b/alliance/src/cells/src/sxlib/ts_x8.al new file mode 100644 index 00000000..6dbe0365 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ts_x8.al @@ -0,0 +1,40 @@ +V ALLIANCE : 6 +H ts_x8,L,30/10/99 +C cmd,IN,EXTERNAL,7 +C i,IN,EXTERNAL,8 +C q,TRISTATE,EXTERNAL,2 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,3,5,2,0,0.75,0.75,13.3,13.3,4.5,11.25,tr_00016 +T P,0.35,5.9,2,5,3,0,0.75,0.75,13.3,13.3,2.7,11.25,tr_00015 +T P,0.35,5.9,3,5,2,0,0.75,0.75,13.3,13.3,8.1,11.25,tr_00014 +T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,14.1,11.25,tr_00013 +T P,0.35,2.9,3,7,5,0,0.75,0.75,7.3,7.3,15.9,11.25,tr_00012 +T P,0.35,2.9,6,7,3,0,0.75,0.75,7.3,7.3,9.9,12.75,tr_00011 +T P,0.35,5.9,2,5,3,0,0.75,0.75,13.3,13.3,6.3,11.25,tr_00010 +T P,0.35,2.9,5,8,3,0,0.75,0.75,7.3,7.3,17.7,11.25,tr_00009 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,4.5,2.25,tr_00008 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.7,2.25,tr_00007 +T N,0.35,1.4,1,6,4,0,0.75,0.75,4.3,4.3,14.1,3,tr_00006 +T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,15.9,3,tr_00005 +T N,0.35,1.4,6,7,1,0,0.75,0.75,4.3,4.3,9.9,3,tr_00004 +T N,0.35,1.4,5,7,4,0,0.75,0.75,4.3,4.3,17.7,3,tr_00003 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,6.3,2.25,tr_00002 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,8.1,2.25,tr_00001 +S 8,EXTERNAL,i +Q 0.0029371 +S 7,EXTERNAL,cmd +Q 0.00891222 +S 6,INTERNAL +Q 0.00502769 +S 5,INTERNAL +Q 0.00909993 +S 4,INTERNAL +Q 0.00797383 +S 3,EXTERNAL,vdd +Q 0.00965406 +S 2,EXTERNAL,q +Q 0.00611052 +S 1,EXTERNAL,vss +Q 0.00795016 +EOF diff --git a/alliance/src/cells/src/sxlib/ts_x8.ap b/alliance/src/cells/src/sxlib/ts_x8.ap new file mode 100644 index 00000000..ea489a48 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ts_x8.ap @@ -0,0 +1,162 @@ +V ALLIANCE : 6 +H ts_x8,P, 6/ 9/2000,100 +A 0,0,6500,5000 +R 5500,1500,ref_ref,i_15 +R 3000,1000,ref_ref,cmd_10 +R 3000,3000,ref_ref,cmd_30 +R 3000,3500,ref_ref,cmd_35 +R 3000,4000,ref_ref,cmd_40 +R 3000,1500,ref_ref,cmd_15 +R 3000,2000,ref_ref,cmd_20 +R 3000,2500,ref_ref,cmd_25 +R 2500,2500,ref_ref,q_25 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +R 5500,2000,ref_ref,i_20 +R 5500,2500,ref_ref,i_25 +R 5500,3000,ref_ref,i_30 +R 5500,3500,ref_ref,i_35 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,2000,ref_ref,q_20 +S 900,2300,6200,2300,100,*,RIGHT,POLY +S 1200,2100,2500,2100,200,*,RIGHT,ALU1 +S 1200,1000,1200,4000,200,*,DOWN,ALU1 +S 4400,1000,5600,1000,100,*,RIGHT,ALU1 +S 6200,1000,6200,4000,100,*,DOWN,ALU1 +S 5000,4000,6200,4000,100,*,RIGHT,ALU1 +S 3000,1000,3000,4000,100,*,UP,ALU1 +S 3000,1500,3100,1500,100,*,RIGHT,ALU1 +S 3000,3000,3400,3000,200,*,RIGHT,ALU1 +S 3900,1000,3900,4000,100,*,DOWN,ALU1 +S 4900,1800,4900,2700,100,*,DOWN,ALU1 +S 5500,3000,5700,3000,200,*,LEFT,ALU1 +S 5500,1500,5500,3500,100,*,DOWN,ALU1 +S 4400,1000,4400,4000,100,*,DOWN,ALU1 +S 3600,4000,3900,4000,200,*,RIGHT,ALU1 +S 1800,500,1800,1000,200,*,DOWN,ALU1 +S 1800,3000,1800,4500,200,*,DOWN,ALU1 +S 3600,1000,3900,1000,200,*,RIGHT,ALU1 +S 600,3000,600,4500,200,*,DOWN,ALU1 +S 600,500,600,1000,200,*,DOWN,ALU1 +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 5900,1400,5900,1900,100,*,DOWN,POLY +S 4900,1900,5900,1900,100,*,RIGHT,POLY +S 2700,1400,2700,1900,100,*,DOWN,POLY +S 2100,1400,2100,1900,100,*,DOWN,POLY +S 5300,1500,5500,1500,300,*,RIGHT,POLY +S 3100,1500,3300,1500,300,*,RIGHT,POLY +S 3400,2800,3400,3000,300,*,UP,POLY +S 2100,2300,2100,2600,100,*,UP,POLY +S 3300,2800,5300,2800,100,*,RIGHT,POLY +S 5300,2800,5300,3100,100,*,DOWN,POLY +S 3300,2800,3300,3600,100,*,DOWN,POLY +S 5700,3000,5900,3000,300,*,RIGHT,POLY +S 2700,2300,2700,2600,100,*,DOWN,POLY +S 3800,1400,4700,1400,100,*,RIGHT,POLY +S 900,1900,4400,1900,100,*,RIGHT,POLY +S 900,2300,900,2600,100,*,DOWN,POLY +S 1500,2300,1500,2600,100,*,UP,POLY +S 900,1400,900,1900,100,*,DOWN,POLY +S 1500,1400,1500,1900,100,*,DOWN,POLY +S 5600,300,6200,300,300,*,RIGHT,PTIE +S 3600,300,4400,300,300,*,RIGHT,PTIE +S 4200,4700,5000,4700,300,*,RIGHT,NTIE +S 5900,3100,5900,4400,100,*,UP,PTRANS +S 1800,2800,1800,4700,300,*,UP,PDIF +S 2100,2600,2100,4900,100,*,UP,PTRANS +S 3600,3800,3600,4700,300,*,UP,PDIF +S 3300,3600,3300,4900,100,*,UP,PTRANS +S 5000,3300,5000,4200,300,*,UP,PDIF +S 5300,3100,5300,4400,100,*,UP,PTRANS +S 4400,3300,4400,4200,300,*,UP,PDIF +S 4700,3100,4700,4400,100,*,UP,PTRANS +S 6200,3300,6200,4200,300,*,UP,PDIF +S 2400,2800,2400,4700,300,*,UP,PDIF +S 3000,2800,3000,4700,300,*,UP,PDIF +S 2700,2600,2700,4900,100,*,UP,PTRANS +S 1200,2800,1200,4700,300,*,UP,PDIF +S 900,2600,900,4900,100,*,UP,PTRANS +S 1500,2600,1500,4900,100,*,UP,PTRANS +S 600,2800,600,4700,300,*,UP,PDIF +S 1800,300,1800,1200,300,*,UP,NDIF +S 2700,100,2700,1400,100,*,UP,NTRANS +S 2100,100,2100,1400,100,*,UP,NTRANS +S 3000,300,3000,1200,300,*,UP,NDIF +S 2400,300,2400,1200,300,*,UP,NDIF +S 6200,800,6200,1200,300,*,UP,NDIF +S 5900,600,5900,1400,100,*,UP,NTRANS +S 4400,800,4400,1200,300,*,UP,NDIF +S 5600,800,5600,1200,300,*,UP,NDIF +S 3600,800,3600,1200,300,*,UP,NDIF +S 3300,600,3300,1400,100,*,UP,NTRANS +S 5000,400,5000,1200,300,*,UP,NDIF +S 5300,600,5300,1400,100,*,UP,NTRANS +S 4700,600,4700,1400,100,*,UP,NTRANS +S 600,300,600,1200,300,*,UP,NDIF +S 1200,300,1200,1200,300,*,UP,NDIF +S 900,100,900,1400,100,*,UP,NTRANS +S 1500,100,1500,1400,100,*,UP,NTRANS +S 0,3900,6500,3900,2400,*,LEFT,NWELL +S 2500,950,2500,4050,200,*,UP,ALU1 +S 5000,3500,5000,4000,100,*,UP,ALU1 +S 3850,3100,4700,3100,100,*,RIGHT,POLY +S 5600,3300,5600,4550,300,*,UP,PDIF +S 5500,1500,5500,3500,200,i,DOWN,CALU1 +S 3000,1000,3000,4000,200,cmd,DOWN,CALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +V 3400,3000,CONT_POLY,* +V 6200,2300,CONT_POLY,* +V 4900,2700,CONT_POLY,* +V 4900,1800,CONT_POLY,* +V 5700,3000,CONT_POLY,* +V 5500,1500,CONT_POLY,* +V 3100,1500,CONT_POLY,* +V 3900,1500,CONT_POLY,* +V 4400,1800,CONT_POLY,* +V 3600,300,CONT_BODY_P,* +V 5600,300,CONT_BODY_P,* +V 6200,300,CONT_BODY_P,* +V 4400,300,CONT_BODY_P,* +V 5000,4700,CONT_BODY_N,* +V 4200,4700,CONT_BODY_N,* +V 6200,4700,CONT_BODY_N,* +V 3600,4000,CONT_DIF_P,* +V 1800,4500,CONT_DIF_P,* +V 1800,3500,CONT_DIF_P,* +V 1800,4000,CONT_DIF_P,* +V 2400,3500,CONT_DIF_P,* +V 2400,4000,CONT_DIF_P,* +V 1800,3000,CONT_DIF_P,* +V 3000,4500,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 6200,4000,CONT_DIF_P,* +V 2400,3000,CONT_DIF_P,* +V 600,4000,CONT_DIF_P,* +V 600,3500,CONT_DIF_P,* +V 600,3000,CONT_DIF_P,* +V 600,4500,CONT_DIF_P,* +V 1200,3000,CONT_DIF_P,* +V 1200,3500,CONT_DIF_P,* +V 1200,4000,CONT_DIF_P,* +V 4400,1000,CONT_DIF_N,* +V 3600,1000,CONT_DIF_N,* +V 1800,500,CONT_DIF_N,* +V 3000,500,CONT_DIF_N,* +V 1800,1000,CONT_DIF_N,* +V 2400,1000,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 5000,500,CONT_DIF_N,* +V 6200,1000,CONT_DIF_N,* +V 1200,1000,CONT_DIF_N,* +V 600,1000,CONT_DIF_N,* +V 600,500,CONT_DIF_N,* +V 5000,3500,CONT_DIF_P,* +V 6200,3500,CONT_DIF_P,* +V 3900,3200,CONT_POLY,* +V 4400,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/ts_x8.sym b/alliance/src/cells/src/sxlib/ts_x8.sym new file mode 100644 index 00000000..4f9e57eb Binary files /dev/null and b/alliance/src/cells/src/sxlib/ts_x8.sym differ diff --git a/alliance/src/cells/src/sxlib/ts_x8.vbe b/alliance/src/cells/src/sxlib/ts_x8.vbe new file mode 100644 index 00000000..c92f94f5 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ts_x8.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 400; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_cmd_q : NATURAL := 450; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphl_cmd_q : NATURAL := 466; + CONSTANT tpll_i_q : NATURAL := 569; + CONSTANT tphh_i_q : NATURAL := 613; + CONSTANT tphh_cmd_q : NATURAL := 626; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x8; + +ARCHITECTURE behaviour_data_flow OF ts_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x8" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1200 ps; + END BLOCK label0; + +END; diff --git a/alliance/src/cells/src/sxlib/ts_x8.vhd b/alliance/src/cells/src/sxlib/ts_x8.vhd new file mode 100644 index 00000000..464e2931 --- /dev/null +++ b/alliance/src/cells/src/sxlib/ts_x8.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ts_x8 IS +PORT( + cmd : IN STD_LOGIC; + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ts_x8; + +ARCHITECTURE RTL OF ts_x8 IS +BEGIN + PROCESS ( i, cmd ) + BEGIN + IF (cmd = '1') + THEN q <= i; + ELSE q <= 'Z'; + END IF; + END PROCESS; +END RTL; diff --git a/alliance/src/cells/src/sxlib/xr2_x1.al b/alliance/src/cells/src/sxlib/xr2_x1.al new file mode 100644 index 00000000..dbd8a28b --- /dev/null +++ b/alliance/src/cells/src/sxlib/xr2_x1.al @@ -0,0 +1,40 @@ +V ALLIANCE : 6 +H xr2_x1,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,7,10,6,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012 +T P,0.35,5.9,6,5,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,6,8,7,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T P,0.35,5.9,2,9,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,2.9,7,8,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00008 +T P,0.35,2.9,9,10,7,0,0.75,0.75,7.3,7.3,10.8,11.25,tr_00007 +T N,0.35,2.9,4,8,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005 +T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003 +T N,0.35,1.4,4,10,9,0,0.75,0.75,4.3,4.3,10.8,3,tr_00002 +T N,0.35,1.4,5,8,4,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 10,EXTERNAL,i1 +Q 0.00533757 +S 9,INTERNAL +Q 0.00655161 +S 8,EXTERNAL,i0 +Q 0.00413388 +S 7,EXTERNAL,vdd +Q 0.0047041 +S 6,INTERNAL +Q 0.00274153 +S 5,INTERNAL +Q 0.0053513 +S 4,EXTERNAL,vss +Q 0.0047041 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,q +Q 0.0029965 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/src/cells/src/sxlib/xr2_x1.ap b/alliance/src/cells/src/sxlib/xr2_x1.ap new file mode 100644 index 00000000..80714b10 --- /dev/null +++ b/alliance/src/cells/src/sxlib/xr2_x1.ap @@ -0,0 +1,116 @@ +V ALLIANCE : 6 +H xr2_x1,P,30/ 8/2000,100 +A 0,0,4500,5000 +R 2000,3000,ref_ref,q_30 +R 2000,3500,ref_ref,q_35 +R 3500,4000,ref_ref,i1_40 +R 3500,3500,ref_ref,i1_35 +R 3500,3000,ref_ref,i1_30 +R 3500,2500,ref_ref,i1_25 +R 3500,2000,ref_ref,i1_20 +R 3500,1500,ref_ref,i1_15 +R 3500,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,1500,ref_ref,i0_15 +R 1000,1000,ref_ref,i0_10 +R 1500,1000,ref_ref,q_10 +R 1500,1500,ref_ref,q_15 +R 1500,2000,ref_ref,q_20 +R 1500,2500,ref_ref,q_25 +S 1500,3500,1500,4000,100,*,UP,ALU1 +S 4000,3500,4000,4000,100,*,DOWN,ALU1 +S 1500,950,1500,3050,200,*,UP,ALU1 +S 1500,3000,2000,3000,200,*,LEFT,ALU1 +S 2000,3000,2000,3500,200,*,DOWN,ALU1 +S 2700,3000,2700,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,DOWN,ALU1 +S 4000,800,4000,1200,300,*,UP,NDIF +S 4000,3300,4000,4200,300,*,DOWN,PDIF +S 4000,1000,4000,3500,100,*,DOWN,ALU1 +S 2000,2500,2500,2500,100,*,RIGHT,ALU1 +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 2500,2000,2500,2500,100,*,DOWN,ALU1 +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 3000,1400,3000,2000,100,*,DOWN,POLY +S 3000,2600,3600,2600,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 2000,1500,3500,1500,100,*,RIGHT,ALU1 +S 3500,1000,3500,4000,100,*,DOWN,ALU1 +S 3600,2600,3600,3100,100,*,DOWN,POLY +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3600,3100,3600,4400,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,600,3100,100,*,DOWN,POLY +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 1500,1000,2100,1000,200,*,RIGHT,ALU1 +S 3500,1000,3500,4000,200,i1,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 2000,3000,2000,3500,200,q,DOWN,CALU1 +S 1500,1000,1500,3000,200,q,DOWN,CALU1 +S 2000,1000,2000,1000,200,q,LEFT,CALU1 +V 1500,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 4000,1000,CONT_DIF_N,* +V 4000,3500,CONT_DIF_P,* +V 4000,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 3900,4700,CONT_BODY_N,* +V 300,300,CONT_BODY_P,* +V 3900,300,CONT_BODY_P,* +V 1000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/sxlib/xr2_x1.sym b/alliance/src/cells/src/sxlib/xr2_x1.sym new file mode 100644 index 00000000..2e21e7d4 Binary files /dev/null and b/alliance/src/cells/src/sxlib/xr2_x1.sym differ diff --git a/alliance/src/cells/src/sxlib/xr2_x1.vbe b/alliance/src/cells/src/sxlib/xr2_x1.vbe new file mode 100644 index 00000000..aef426b0 --- /dev/null +++ b/alliance/src/cells/src/sxlib/xr2_x1.vbe @@ -0,0 +1,40 @@ +ENTITY xr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i1_q : NATURAL := 261; + CONSTANT tphl_i0_q : NATURAL := 292; + CONSTANT tplh_i0_q : NATURAL := 293; + CONSTANT tphh_i0_q : NATURAL := 366; + CONSTANT tphl_i1_q : NATURAL := 377; + CONSTANT tpll_i1_q : NATURAL := 388; + CONSTANT tpll_i0_q : NATURAL := 389; + CONSTANT tphh_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x1; + +ARCHITECTURE behaviour_data_flow OF xr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x1" + SEVERITY WARNING; + q <= (i0 xor i1) after 1000 ps; +END; diff --git a/alliance/src/cells/src/sxlib/xr2_x1.vhd b/alliance/src/cells/src/sxlib/xr2_x1.vhd new file mode 100644 index 00000000..dca01149 --- /dev/null +++ b/alliance/src/cells/src/sxlib/xr2_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY xr2_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END xr2_x1; + +ARCHITECTURE RTL OF xr2_x1 IS +BEGIN + q <= (i0 XOR i1); +END RTL; diff --git a/alliance/src/cells/src/sxlib/xr2_x4.al b/alliance/src/cells/src/sxlib/xr2_x4.al new file mode 100644 index 00000000..c2255927 --- /dev/null +++ b/alliance/src/cells/src/sxlib/xr2_x4.al @@ -0,0 +1,46 @@ +V ALLIANCE : 6 +H xr2_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,9 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,10,9,7,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00016 +T P,0.35,2.9,7,8,4,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00015 +T P,0.35,5.9,11,2,7,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00014 +T P,0.35,5.9,7,2,11,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00013 +T P,0.35,5.9,2,9,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012 +T P,0.35,5.9,6,8,7,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00011 +T P,0.35,5.9,6,4,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,7,10,6,0,0.75,0.75,13.3,13.3,9,11.25,tr_00009 +T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00008 +T N,0.35,2.9,1,2,11,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00007 +T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006 +T N,0.35,1.4,1,9,10,0,0.75,0.75,4.3,4.3,10.8,3,tr_00005 +T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004 +T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,5,10,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00002 +T N,0.35,2.9,1,8,5,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00001 +S 11,EXTERNAL,q +Q 0.00258522 +S 10,INTERNAL +Q 0.00536068 +S 9,EXTERNAL,i1 +Q 0.00462772 +S 8,EXTERNAL,i0 +Q 0.00370588 +S 7,EXTERNAL,vdd +Q 0.00866628 +S 6,INTERNAL +Q 0.00274153 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00506945 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00791506 +S 1,EXTERNAL,vss +Q 0.00737367 +EOF diff --git a/alliance/src/cells/src/sxlib/xr2_x4.ap b/alliance/src/cells/src/sxlib/xr2_x4.ap new file mode 100644 index 00000000..25fa815e --- /dev/null +++ b/alliance/src/cells/src/sxlib/xr2_x4.ap @@ -0,0 +1,145 @@ +V ALLIANCE : 6 +H xr2_x4,P, 6/ 9/2000,100 +A 0,0,6000,5000 +R 5000,4000,ref_ref,q_40 +R 5000,1000,ref_ref,q_10 +R 5000,3000,ref_ref,q_30 +R 5000,3500,ref_ref,q_35 +R 5000,2500,ref_ref,q_25 +R 5000,2000,ref_ref,q_20 +R 5000,1500,ref_ref,q_15 +R 3500,4000,ref_ref,i1_40 +R 3500,3500,ref_ref,i1_35 +R 3500,3000,ref_ref,i1_30 +R 3500,2500,ref_ref,i1_25 +R 3500,2000,ref_ref,i1_20 +R 3500,1500,ref_ref,i1_15 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,1500,ref_ref,i0_15 +R 1000,1000,ref_ref,i0_10 +S 4500,2000,5400,2000,300,*,RIGHT,POLY +S 5000,1000,5000,4000,200,q,DOWN,CALU1 +S 3500,1500,3500,4000,200,i1,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 0,3900,6000,3900,2400,*,LEFT,NWELL +S 4500,300,4500,1000,300,*,UP,NDIF +S 3900,800,3900,1600,300,*,UP,NDIF +S 1500,1000,4500,1000,100,*,RIGHT,ALU1 +S 4500,1000,4500,2000,100,*,DOWN,ALU1 +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 5700,500,5700,1000,200,*,DOWN,ALU1 +S 5700,3000,5700,4500,200,*,DOWN,ALU1 +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 3500,1500,3500,4000,100,*,DOWN,ALU1 +S 4000,1500,4000,2900,100,*,DOWN,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 5700,300,5700,1200,300,*,UP,NDIF +S 5100,300,5100,1200,300,*,UP,NDIF +S 5400,100,5400,1400,100,*,DOWN,NTRANS +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 3900,2800,3900,3700,300,*,DOWN,PDIF +S 4500,3400,4500,4700,300,*,DOWN,PDIF +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 600,2600,600,3900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,UP,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,DOWN,PDIF +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 2500,1500,2500,2000,100,*,DOWN,ALU1 +S 2000,1500,2500,1500,100,*,RIGHT,ALU1 +S 3000,1400,3600,1400,100,*,RIGHT,POLY +S 2000,2500,3500,2500,100,*,RIGHT,ALU1 +S 3000,2000,3000,2600,100,*,DOWN,POLY +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 300,1000,300,3000,100,*,DOWN,ALU1 +S 2100,3000,2100,3500,100,*,DOWN,ALU1 +S 1500,3000,2100,3000,100,*,LEFT,ALU1 +S 1500,1000,1500,3000,100,*,UP,ALU1 +S 1500,3500,1500,4000,100,*,UP,ALU1 +S 2700,3000,2700,4000,100,*,DOWN,ALU1 +S 300,3000,300,3500,100,*,UP,ALU1 +S 5700,1000,5700,1700,200,*,UP,ALU1 +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +V 4500,2000,CONT_POLY,* +V 4000,2900,CONT_DIF_P,* +V 4000,1500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 5100,3000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 5700,3000,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5700,4500,CONT_DIF_P,* +V 5700,1000,CONT_DIF_N,* +V 5700,500,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 300,3000,CONT_DIF_P,* +V 3000,2000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 3900,4700,CONT_BODY_N,* +V 300,300,CONT_BODY_P,* +V 3900,300,CONT_BODY_P,* +V 1000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 1500,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 5700,1700,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/xr2_x4.sym b/alliance/src/cells/src/sxlib/xr2_x4.sym new file mode 100644 index 00000000..8198a29b Binary files /dev/null and b/alliance/src/cells/src/sxlib/xr2_x4.sym differ diff --git a/alliance/src/cells/src/sxlib/xr2_x4.vbe b/alliance/src/cells/src/sxlib/xr2_x4.vbe new file mode 100644 index 00000000..047882b4 --- /dev/null +++ b/alliance/src/cells/src/sxlib/xr2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY xr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 357; + CONSTANT tphh_i0_q : NATURAL := 476; + CONSTANT tpll_i0_q : NATURAL := 480; + CONSTANT tphl_i0_q : NATURAL := 521; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphl_i1_q : NATURAL := 541; + CONSTANT tplh_i0_q : NATURAL := 560; + CONSTANT tplh_i1_q : NATURAL := 657; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x4; + +ARCHITECTURE behaviour_data_flow OF xr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x4" + SEVERITY WARNING; + q <= (i0 xor i1) after 1300 ps; +END; diff --git a/alliance/src/cells/src/sxlib/xr2_x4.vhd b/alliance/src/cells/src/sxlib/xr2_x4.vhd new file mode 100644 index 00000000..404a3949 --- /dev/null +++ b/alliance/src/cells/src/sxlib/xr2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY xr2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END xr2_x4; + +ARCHITECTURE RTL OF xr2_x4 IS +BEGIN + q <= (i0 XOR i1); +END RTL; diff --git a/alliance/src/cells/src/sxlib/zero_x0.al b/alliance/src/cells/src/sxlib/zero_x0.al new file mode 100644 index 00000000..aafb6a73 --- /dev/null +++ b/alliance/src/cells/src/sxlib/zero_x0.al @@ -0,0 +1,13 @@ +V ALLIANCE : 6 +H zero_x0,L,30/10/99 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,2 +T N,0.35,1.4,2,3,1,0,0.75,0.75,4.3,4.3,2.1,4.5,tr_00001 +S 3,EXTERNAL,vdd +Q 0.00535397 +S 2,EXTERNAL,vss +Q 0.00330156 +S 1,EXTERNAL,nq +Q 0.00205642 +EOF diff --git a/alliance/src/cells/src/sxlib/zero_x0.ap b/alliance/src/cells/src/sxlib/zero_x0.ap new file mode 100644 index 00000000..92c72144 --- /dev/null +++ b/alliance/src/cells/src/sxlib/zero_x0.ap @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H zero_x0,P,30/ 8/2000,100 +A 0,0,1500,5000 +R 1000,4000,ref_ref,nq_40 +R 1000,3500,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_30 +R 1000,2500,ref_ref,nq_25 +R 1000,2000,ref_ref,nq_20 +R 1000,1500,ref_ref,nq_15 +R 1000,1000,ref_ref,nq_10 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 500,3000,500,4600,300,*,UP,NTIE +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 500,4500,1000,4500,300,*,LEFT,NTIE +S 400,2000,700,2000,300,*,RIGHT,POLY +S 350,1300,350,1700,400,*,UP,NDIF +S 1000,1300,1000,1700,300,*,UP,NDIF +S 700,1100,700,1900,100,*,DOWN,NTRANS +S 500,2000,500,4700,200,*,DOWN,ALU1 +S 400,300,400,1500,200,*,DOWN,ALU1 +S 400,500,1000,500,300,*,RIGHT,PTIE +V 500,4000,CONT_BODY_N,* +V 500,3500,CONT_BODY_N,* +V 500,3000,CONT_BODY_N,* +V 1000,4500,CONT_BODY_N,* +V 500,4500,CONT_BODY_N,* +V 500,2000,CONT_POLY,* +V 400,1500,CONT_DIF_N,* +V 1000,1500,CONT_DIF_N,* +V 1000,500,CONT_BODY_P,* +V 400,500,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/sxlib/zero_x0.sym b/alliance/src/cells/src/sxlib/zero_x0.sym new file mode 100644 index 00000000..5452045b Binary files /dev/null and b/alliance/src/cells/src/sxlib/zero_x0.sym differ diff --git a/alliance/src/cells/src/sxlib/zero_x0.vbe b/alliance/src/cells/src/sxlib/zero_x0.vbe new file mode 100644 index 00000000..535efebc --- /dev/null +++ b/alliance/src/cells/src/sxlib/zero_x0.vbe @@ -0,0 +1,20 @@ +ENTITY zero_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END zero_x0; + +ARCHITECTURE behaviour_data_flow OF zero_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on zero_x0" + SEVERITY WARNING; + nq <= '0'; +END; diff --git a/alliance/src/cells/src/sxlib/zero_x0.vhd b/alliance/src/cells/src/sxlib/zero_x0.vhd new file mode 100644 index 00000000..c662155c --- /dev/null +++ b/alliance/src/cells/src/sxlib/zero_x0.vhd @@ -0,0 +1,18 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY zero_x0 IS +PORT( + nq : OUT STD_LOGIC +); +END zero_x0; + +ARCHITECTURE RTL OF zero_x0 IS +BEGIN + nq <= '0'; +END RTL;